a 4-Channel, 1 MSPS, 8-/10-/12-Bit ADCs with Sequencer in 16-Lead TSSOP AD7904/AD7914/AD7924 FEATURES Fast Throughput Rate: 1 MSPS Specified for VDD of 2.7 V to 5.25 V Low Power: 6 mW max at 1 MSPS with 3 V Supplies 13.5 mW max at 1 MSPS with 5 V Supplies 4 (Single-Ended) Inputs with Sequencer Wide Input Bandwidth: AD7924, 70 dB SNR at 50 kHz Input Frequency Flexible Power/Serial Clock Speed Management No Pipeline Delays High Speed Serial Interface SPITM/QSPITM/ MICROWIRETM/DSP Compatible Shutdown Mode: 0.5 A Max 16-Lead TSSOP Package FUNCTIONAL BLOCK DIAGRAM VDD REFIN VIN0 • • • • • • • • • • • • • VIN3 T/H 8-/10-/12-BIT SUCCESSIVE APPROXIMATION ADC I/P MUX SCLK DOUT GENERAL DESCRIPTION The AD7904/AD7914/AD7924 are respectively, 8-bit, 10-bit, and 12-bit, high speed, low power, 4-channel, successive-approximation ADCs. The parts operate from a single 2.7 V to 5.25 V power supply and feature throughput rates up to 1 MSPS. The parts contain a low noise, wide bandwidth track/hold amplifier that can handle input frequencies in excess of 8 MHz. The conversion process and data acquisition are controlled using CS and the serial clock signal, allowing the device to easily interface with microprocessors or DSPs. The input signal is sampled on the falling edge of CS and conversion is also initiated at this point. There are no pipeline delays associated with the part. The AD7904/AD7914/AD7924 use advanced design techniques to achieve very low power dissipation at maximum throughput rates. At maximum throughput rates, the AD7904/AD7914/AD7924 consume 2 mA maximum with 3 V supplies; with 5 V supplies, the current consumption is 2.7 mA maximum. Through the configuration of the Control Register, the analog input range for the part can be selected as 0 V to REFIN or 0 V to 2 × REFIN, with either straight binary or twos complement output coding. The AD7904/AD7914/AD7924 each feature four single-ended analog inputs with a channel sequencer to allow a preprogrammed selection of channels to be converted sequentially. The conversion time for the AD7904/AD7914/AD7924 is determined by the SCLK frequency, as this is also used as the master clock to control the conversion. SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corporation. CONTROL LOGIC SEQUENCER DIN CS AD7904/AD7914/AD7924 VDRIVE GND PRODUCT HIGHLIGHTS 1. High Throughput with Low Power Consumption. The AD7904/AD7914/AD7924 offer up to 1 MSPS throughput rates. At the maximum throughput rate with 3 V sup`plies, the AD7904/AD7914/AD7924 dissipate just 6 mW of power maximum. 2. Four Single-Ended Inputs with a Channel Sequencer. A consecutive sequence of channels can be selected, through which the ADC will cycle and convert on. 3. Single-Supply Operation with VDRIVE Function. The AD7904/AD7914/AD7924 operate from a single 2.7 V to 5.25 V supply. The VDRIVE function allows the serial interface to connect directly to either 3 V or 5 V processor systems independent of VDD. 4. Flexible Power/Serial Clock Speed Management. The conversion rate is determined by the serial clock, allowing the conversion time to be reduced through the serial clock speed increase. The parts also feature various shutdown modes to maximize power efficiency at lower throughput rates. Current consumption is 0.5 µA max when in full shutdown. 5. No Pipeline Delay. The parts feature a standard successive-approximation ADC with accurate control of the sampling instant via a CS input and once off conversion control. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 AD7904–SPECIFICATIONS (AVDD = VDRIVE = 2.7 V to 5.25 V, REFIN = 2.5 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted.) B Version1 Unit 49 49 –66 dB min dB min dB max –64 dB max –90 –90 10 50 –85 8.2 1.6 dB typ dB typ ns typ ps typ dB typ MHz typ MHz typ 8 ± 0.2 ± 0.2 Bits LSB max LSB max ± 0.5 ± 0.05 ± 0.2 ± 0.05 LSB max LSB max LSB max LSB max ± 0.2 ± 0.05 ± 0.5 ± 0.1 ± 0.2 ± 0.05 LSB max LSB max LSB max LSB max LSB max LSB max 0 to REFIN 0 to 2 × REFIN ±1 20 V V µA max pF typ RANGE Bit Set to 1 RANGE Bit Set to 0, VDD/VDRIVE = 4.75 V to 5.25 V REFERENCE INPUT REFIN Input Voltage DC Leakage Current REFIN Input Impedance 2.5 ±1 36 V µA max kΩ typ ± 1% Specified Performance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN3 0.7 × VDRIVE 0.3 × VDRIVE ±1 10 V min V max µA max pF max Parameter DYNAMIC PERFORMANCE Signal-to-Noise + Distortion (SINAD)2 Signal-to-Noise Ratio (SNR)2 Total Harmonic Distortion (THD)2 Peak Harmonic or Spurious Noise (SFDR)2 Intermodulation Distortion (IMD)2 Second Order Terms Third Order Terms Aperture Delay Aperture Jitter Channel-to-Channel Isolation2 Full Power Bandwidth DC ACCURACY2 Resolution Integral Nonlinearity Differential Nonlinearity 0 V to REFIN Input Range Offset Error Offset Error Match Gain Error Gain Error Match 0 V to 2 × REFIN Input Range Positive Gain Error Positive Gain Error Match Zero Code Error Zero Code Error Match Negative Gain Error Negative Gain Error Match ANALOG INPUT Input Voltage Range DC Leakage Current Input Capacitance LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance3 Output Coding CONVERSION RATE Conversion Time Track/Hold Acquisition Time Throughput Rate Test Conditions/Comments fIN = 50 kHz Sine Wave, fSCLK = 20 MHz fa = 40.1 kHz, fb = 41.5 kHz fIN = 400 kHz @ 3 dB @ 0.1 dB Guaranteed No Missed Codes to 8 Bits Straight Binary Output Coding –REFIN to +REFIN Biased about REFIN with Twos Complement Output Coding fSAMPLE = 1 MSPS Typically 10 nA, VIN = 0 V or VDRIVE VDRIVE – 0.2 V min 0.4 V max ±1 µA max 10 pF max Straight (Natural) Binary Twos Complement ISOURCE = 200 µA, VDD = 2.7 V to 5.25 V ISINK = 200 µA 800 300 300 1 16 SCLK Cycles with SCLK at 20 MHz Sine Wave Input Full-Scale Step Input See Serial Interface Section ns max ns max ns max MSPS max –2– Coding Bit Set to 1 Coding Bit Set to 0 REV. 0 AD7904/AD7914/AD7924 Parameter POWER REQUIREMENTS VDD VDRIVE IDD4 Normal Mode (Static) Normal Mode (Operational) Using Auto Shutdown Mode Full Shutdown Mode Power Dissipation4 Normal Mode (Operational) Auto Shutdown Mode (Static) Full Shutdown Mode B Version1 Unit 2.7/5.25 2.7/5.25 V min/max V min/max 600 2.7 2 960 0.5 0.5 µA typ mA max mA max µA typ µA max µA max Digital I/Ps = 0 V or VDRIVE VDD = 2.7 V to 5.25 V, SCLK On or Off VDD = 4.75 V to 5.25 V, fSCLK = 20 MHz VDD = 2.7 V to 3.6 V, fSCLK = 20 MHz fSAMPLE = 250 kSPS (Static) SCLK On or Off (20 nA typ) 13.5 6 2.5 1.5 2.5 1.5 mW max mW max µW max µW max µW max µW max VDD = 5 V, fSCLK = 20 MHz VDD = 3 V, fSCLK = 20 MHz VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V NOTES 1 Temperature ranges as follows: B Version: –40°C to +85°C. 2 See Terminology section. 3 Sample tested @ 25°C to ensure compliance. 4 See Power Versus Throughput Rate section. Specifications subject to change without notice. REV. 0 –3– Test Conditions/Comments AD7914–SPECIFICATIONS (AVDD = VDRIVE = 2.7 V to 5.25 V, REFIN = 2.5 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted.) B Version1 Unit 61 61 –72 dB min dB min dB max –74 dB max –90 –90 10 50 –85 8.2 1.6 dB typ dB typ ns typ ps typ dB typ MHz typ MHz typ 10 ± 0.5 ± 0.5 Bits LSB max LSB max ±2 ± 0.2 ± 0.5 ± 0.2 LSB max LSB max LSB max LSB max ± 0.5 ± 0.2 ±2 ± 0.2 ± 0.5 ± 0.2 LSB max LSB max LSB max LSB max LSB max LSB max 0 to REFIN 0 to 2 × REFIN ±1 20 V V µA max pF typ RANGE Bit Set to 1 RANGE Bit Set to 0, VDD/VDRIVE = 4.75 V to 5.25 V REFERENCE INPUT REFIN Input Voltage DC Leakage Current REFIN Input Impedance 2.5 ±1 36 V µA max kΩ typ ± 1% Specified Performance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN3 0.7 × VDRIVE 0.3 × VDRIVE ±1 10 V min V max µA max pF max Parameter DYNAMIC PERFORMANCE Signal-to-Noise + Distortion (SINAD)2 Signal-to-Noise Ratio (SNR)2 Total Harmonic Distortion (THD)2 Peak Harmonic or Spurious Noise (SFDR)2 Intermodulation Distortion (IMD)2 Second Order Terms Third Order Terms Aperture Delay Aperture Jitter Channel-to-Channel Isolation2 Full Power Bandwidth DC ACCURACY2 Resolution Integral Nonlinearity Differential Nonlinearity 0 V to REFIN Input Range Offset Error Offset Error Match Gain Error Gain Error Match 0 V to 2 × REFIN Input Range Positive Gain Error Positive Gain Error Match Zero Code Error Zero Code Error Match Negative Gain Error Negative Gain Error Match ANALOG INPUT Input Voltage Range DC Leakage Current Input Capacitance LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance3 Output Coding CONVERSION RATE Conversion Time Track/Hold Acquisition Time Throughput Rate Test Conditions/Comments fIN = 50 kHz Sine Wave, fSCLK = 20 MHz fa = 40.1 kHz, fb = 41.5 kHz fIN = 400 kHz @ 3 dB @ 0.1 dB Guaranteed No Missed Codes to 10 Bits Straight Binary Output Coding –REFIN to +REFIN Biased about REFIN with Twos Complement Output Coding fSAMPLE = 1 MSPS Typically 10 nA, VIN = 0 V or VDRIVE VDRIVE – 0.2 V min 0.4 V max ±1 µA max 10 pF max Straight (Natural) Binary Twos Complement ISOURCE = 200 µA, VDD = 2.7 V to 5.25 V ISINK = 200 µA 800 300 300 1 16 SCLK Cycles with SCLK at 20 MHz Sine Wave Input Full-Scale Step Input See Serial Interface Section ns max ns max ns max MSPS max –4– Coding Bit Set to 1 Coding Bit Set to 0 REV. 0 AD7904/AD7914/AD7924 Parameter POWER REQUIREMENTS VDD VDRIVE IDD4 Normal Mode (Static) Normal Mode (Operational) Using Auto Shutdown Mode Full Shutdown Mode Power Dissipation4 Normal Mode (Operational) Auto Shutdown Mode (Static) Full Shutdown Mode B Version1 Unit 2.7/5.25 2.7/5.25 V min/max V min/max 600 2.7 2 960 0.5 0.5 µA typ mA max mA max µA typ µA max µA max Digital I/Ps = 0 V or VDRIVE VDD = 2.7 V to 5.25 V, SCLK On or Off VDD = 4.75 V to 5.25 V, fSCLK = 20 MHz VDD = 2.7 V to 3.6 V, fSCLK = 20 MHz fSAMPLE = 250 kSPS (Static) SCLK On or Off (20 nA typ) 13.5 6 2.5 1.5 2.5 1.5 mW max mW max µW max µW max µW max µW max VDD = 5 V, fSCLK = 20 MHz VDD = 3 V, fSCLK = 20 MHz VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V NOTES 1 Temperature ranges as follows: B Version: –40°C to +85°C. 2 See Terminology section. 3 Sample tested @ 25°C to ensure compliance. 4 See Power Versus Throughput Rate section. Specifications subject to change without notice. REV. 0 –5– Test Conditions/Comments AD7924–SPECIFICATIONS (AVDD = VDRIVE = 2.7 V to 5.25 V, REFIN = 2.5 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted.) B Version1 Unit 70 69 70 –77 –73 –78 –76 dB min dB min dB min dB max dB max dB max dB max –90 –90 10 50 –85 8.2 1.6 dB typ dB typ ns typ ps typ dB typ MHz typ MHz typ 12 ±1 –0.9/+1.5 Bits LSB max LSB max ±8 ± 0.5 ± 1.5 ± 0.5 LSB max LSB max LSB max LSB max ± 1.5 ± 0.5 ±8 ± 0.5 ±1 ± 0.5 LSB max LSB max LSB max LSB max LSB max LSB max 0 to REFIN 0 to 2 × REFIN ±1 20 V V µA max pF typ RANGE Bit Set to 1 RANGE Bit Set to 0, VDD/VDRIVE = 4.75 V to 5.25 V REFERENCE INPUT REFIN Input Voltage DC Leakage Current REFIN Input Impedance 2.5 ±1 36 V µA max kΩ typ ± 1% Specified Performance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN3 0.7 × VDRIVE 0.3 × VDRIVE ±1 10 V min V max µA max pF max Parameter DYNAMIC PERFORMANCE Signal to Noise + Distortion (SINAD)2 Signal to Noise Ratio (SNR)2 Total Harmonic Distortion (THD)2 Peak Harmonic or Spurious Noise (SFDR)2 Intermodulation Distortion (IMD)2 Second Order Terms Third Order Terms Aperture Delay Aperture Jitter Channel-to-Channel Isolation2 Full Power Bandwidth DC ACCURACY2 Resolution Integral Nonlinearity Differential Nonlinearity 0 V to REFIN Input Range Offset Error Offset Error Match Gain Error Gain Error Match 0 V to 2 × REFIN Input Range Positive Gain Error Positive Gain Error Match Zero Code Error Zero Code Error Match Negative Gain Error Negative Gain Error Match ANALOG INPUT Input Voltage Range DC Leakage Current Input Capacitance LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance3 Output Coding VDRIVE – 0.2 V min 0.4 V max ±1 µA max 10 pF max Straight (Natural) Binary Twos Complement –6– Test Conditions/Comments fIN = 50 kHz Sine Wave, fSCLK = 20 MHz @5V @ 3 V Typically 69.5 dB @ 5 V Typically –84 dB @ 3 V Typically –77 dB @ 5 V Typically –86 dB @ 3 V Typically –80 dB fa = 40.1 kHz, fb = 41.5 kHz fIN = 400 kHz @ 3 dB @ 0.1 dB Guaranteed No Missed Codes to 12 Bits Straight Binary Output Coding Typically ± 0.5 LSB –REFIN to +REFIN Biased about REFIN with Twos Complement Output Coding Typically ± 0.8 LSB fSAMPLE = 1 MSPS Typically 10 nA, VIN = 0 V or VDRIVE ISOURCE = 200 µA, VDD = 2.7 V to 5.25 V ISINK = 200 µA Coding Bit Set to 1 Coding Bit Set to 0 REV. 0 AD7904/AD7914/AD7924 Parameter CONVERSION RATE Conversion Time Track/Hold Acquisition Time Throughput Rate POWER REQUIREMENTS VDD VDRIVE IDD4 Normal Mode(Static) Normal Mode (Operational) Using Auto Shutdown Mode Full Shutdown Mode Power Dissipation4 Normal Mode (Operational) Auto Shutdown Mode (Static) Full Shutdown Mode B Version1 Unit Test Conditions/Comments 800 300 300 1 ns max ns max ns max MSPS max 16 SCLK Cycles with SCLK at 20 MHz Sine Wave Input Full-Scale Step Input See Serial Interface Section 2.7/5.25 2.7/5.25 V min/max V min/max 600 2.7 2 960 0.5 0.5 µA typ mA max mA max µA typ µA max µA max Digital I/Ps = 0 V or VDRIVE VDD = 2.7 V to 5.25 V, SCLK On or Off VDD = 4.75 V to 5.25 V, fSCLK = 20 MHz VDD = 2.7 V to 3.6 V, fSCLK = 20 MHz fSAMPLE = 250 kSPS (Static) SCLK On or Off (20 nA typ) 13.5 6 2.5 1.5 2.5 1.5 mW max mW max µW max µW max µW max µW max VDD = 5 V, fSCLK = 20 MHz VDD = 3 V, fSCLK = 20 MHz VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V NOTES 1 Temperature ranges as follows: B Versions: –40°C to +85°C. 2 See Terminology section. 3 Sample tested @ 25°C to ensure compliance. 4 See Power Versus Throughput Rate section. Specifications subject to change without notice. REV. 0 –7– AD7904/AD7914/AD7924 TIMING SPECIFICATIONS1 Parameter 2 (VDD = 2.7 V to 5.25 V, VDRIVE ⱕ VDD, REFIN = 2.5 V, TA = TMIN to TMAX, unless otherwise noted.) Limit at TMIN, TMAX AD7904/AD7914/AD7924 VDD = 3 V VDD = 5 V Unit 10 20 16 × tSCLK 50 kHz min MHz max tCONVERT tQUIET 10 20 16 × tSCLK 50 t2 t3 3 t4 3 t5 t6 t7 t8 4 t9 t10 t11 t12 10 35 40 0.4 × tSCLK 0.4 × tSCLK 10 15/45 10 5 20 1 10 30 40 0.4 × tSCLK 0.4 × tSCLK 10 15/35 10 5 20 1 ns min ns max ns max ns min ns min ns min ns min/max ns min ns min ns min µs max fSCLK ns min Description Minimum Quiet Time Required Between CS Rising Edge and Start of Next Conversion CS to SCLK Setup Time Delay from CS until DOUT Three-State Disabled Data Access Time after SCLK Falling Edge SCLK Low Pulsewidth SCLK High Pulsewidth SCLK to DOUT Valid Hold Time SCLK Falling Edge to DOUT High Impedance DIN Setup Time Prior to SCLK Falling Edge DIN Hold Time after SCLK Falling Edge Sixteenth SCLK Falling Edge to CS High Power-Up Time from Full Power-Down/Auto Shutdown Modes NOTES 1 Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V. See Figure 1. The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V. 2 Mark/Space ratio for the SCLK input is 40/60 to 60/40. 3 Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.4 V or 0.7 × VDRIVE. 4 t8 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 8, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. Specifications subject to change without notice. –8– REV. 0 AD7904/AD7914/AD7924 ABSOLUTE MAXIMUM RATINGS 1 TSSOP Package, Power Dissipation ........................... 450 mW θJA Thermal Impedance ......................... 150.4°C/W (TSSOP) θJC Thermal Impedance ........................... 27.6°C/W (TSSOP) Lead Temperature, Soldering Vapor Phase (60 secs) ................................................ 215°C Infrared (15 secs) ....................................................... 220°C ESD ................................................................................. 2 kV (TA = 25°C unless otherwise noted.) AVDD to AGND ............................................... –0.3 V to +7 V VDRIVE to AGND ................................ –0.3 V to AVDD + 0.3 V Analog Input Voltage to AGND ......... –0.3 V to AVDD + 0.3 V Digital Input Voltage to AGND ........................ –0.3 V to +7 V Digital Output Voltage to AGND ........... –0.3 V to AVDD + 0.3 V REFIN to AGND ................................ –0.3 V to AVDD + 0.3 V Input Current to Any Pin Except Supplies2 ................. ± 10 mA Operating Temperature Range Commercial (B Version) ............................. –40°C to +85°C Storage Temperature Range ...................... –65°C to +150°C Junction Temperature ................................................... 150°C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latch up. 200A TO OUTPUT PIN IOL 1.6V CL 50pF 200A IOH Figure 1. Load Circuit for Digital Output Timing Specifications ORDERING GUIDE Model Temperature Range Linearity Error (LSB)1 Package Option Package Description AD7904BRU AD7914BRU AD7924BRU EVAL-AD79x4CB2 EVAL-CONTROL BRD23 –40°C to +85°C –40°C to +85°C –40°C to +85°C Evaluation Board Controller Board ± 0.2 ± 0.5 ±1 RU-16 RU-16 RU-16 TSSOP TSSOP TSSOP NOTES 1 Linearity error here refers to integral linearity error. 2 This can be used as a stand alone evaluation board or in conjunction with the Evaluation Controller Board for evaluation/demonstration purposes. The board comes with one chip of each the AD7904, AD7914, and AD7924. 3 This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. To order a complete evaluation kit you will need to order the particular ADC evaluation board, e.g., EVAL-AD79x4CB, the EVAL-CONTROL BRD2, and a 12 V ac transformer. See relevant Evaluation Board Technical Note for more information. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7904/AD7914/AD7924 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –9– AD7904/AD7914/AD7924 PIN CONFIGURATION 16-Lead TSSOP SCLK 1 16 DIN 2 15 VDRIVE 14 DOUT 13 AGND CS 3 AGND 4 AD7904/ AD7914/ AD7924 AGND AVDD 5 12 VIN0 TOP VIEW AVDD 6 (Not to Scale) 11 VIN1 REFIN 7 10 VIN2 AGND 8 9 VIN3 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1 SCLK 2 DIN 3 CS 4, 8, 13, 16 AGND 5, 6 AVDD 7 REFIN 12–9 VIN0–VIN3 14 DOUT 15 VDRIVE Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the AD7904/AD7914/AD7924’s conversion process. Data In. Logic Input. Data to be written to the AD7904/AD7914/AD7924’s Control Register is provided on this input and is clocked into the register on the falling edge of SCLK (see Control Register section). Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7904/AD7914/AD7924 and also frames the serial data transfer. Analog Ground. Ground reference point for all analog circuitry on the AD7904/AD7914/AD7924. All analog input signals and any external reference signal should be referred to this AGND voltage. All AGND pins should be connected together. Analog Power Supply Input. The AVDD range for the AD7904/AD7914/AD7924 is from 2.7 V to 5.25 V. For the 0 V to 2 × REFIN range, AVDD should be from 4.75 V to 5.25 V. Reference Input for the AD7904/AD7914/AD7924. An external reference must be applied to this input. The voltage range for the external reference is 2.5 V ± 1% for specified performance. Analog Input 0 through Analog Input 3. Four single-ended analog input channels that are multiplexed into the on-chip track/hold. The analog input channel to be converted is selected by using the address bits ADD1 and ADD0 of the control register. The address bits, in conjunction with the SEQ1 and SEQ0 bits, allow the Sequencer to be programmed. The input range for all input channels can extend from 0 V to REFIN or 0 V to 2 × REFIN as selected via the RANGE bit in the control register. Any unused input channels should be connected to AGND to avoid noise pickup. Data Out. Logic Output. The conversion result from the AD7904/AD7914/AD7924 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7904 consists of two leading zeros, two address bits indicating which channel the conversion result corresponds to, followed by the eight bits of conversion data, followed by four trailing zeros, provided MSB first; the data stream from the AD7914 consists of two leading zeros, two address bits indicating which channel the conversion result corresponds to, followed by the 10 bits of conversion data, followed by two trailing zeros, also provided MSB first; the data stream from the AD7924 consists of two leading zeros, two address bits indicating which channel the conversion result corresponds to, followed by the 12 bits of conversion data provided MSB first. The output coding may be selected as straight binary or twos complement via the CODING bit in the control register. Logic Power Supply Input. The voltage supplied at this pin determines what voltage the serial interface of the AD7904/AD7914/AD7924 will operate at. –10– REV. 0 AD7904/AD7914/AD7924 Negative Gain Error Match This is the difference in Negative Gain Error between any two channels. TERMINOLOGY Integral Nonlinearity This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point 1 LSB below the first code transition, and full scale, a point 1 LSB above the last code transition. Channel-to-Channel Isolation This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Channel-to-Channel Isolation is a measure of the level of crosstalk between channels. It is measured by applying a full-scale 400 kHz sine wave signal to all three nonselected input channels and determining how much that signal is attenuated in the selected channel with a 50 kHz signal. The figure is given worst case across all four channels for the AD7904/AD7914/AD7924. Offset Error PSR (Power Supply Rejection) This is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, i.e., AGND + 1 LSB. Variations in power supply will affect the full scale transition, but not the converter’s linearity. Power supply rejection is the maximum change in full-scale transition point due to a change in power-supply voltage from the nominal value. See Typical Performance Curves. Differential Nonlinearity Offset Error Match This is the difference in offset error between any two channels. Gain Error Track/Hold Acquisition Time This is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal (i.e., REFIN – 1 LSB) after the offset error has been adjusted out. The track/hold amplifier returns into track mode at the end of conversion. Track/Hold acquisition time is the time required for the output of the track/hold amplifier to reach its final value, within ± 1 LSB, after the end of conversion. Gain Error Match This is the difference in Gain error between any two channels. Signal to (Noise + Distortion) Ratio Zero Code Error This is the measured ratio of signal to (noise + distortion) at the output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by: This applies when using the twos complement output coding option, in particular to the 2 × REFIN input range with –REFIN to +REFIN biased about the REFIN point. It is the deviation of the midscale transition (all 0s to all 1s) from the ideal VIN voltage, i.e., REFIN – 1 LSB. Zero Code Error Match This is the difference in Zero Code Error between any two channels. Signal to ( Noise + Distortion ) = (6.02N + 1.76) dB Positive Gain Error This applies when using the twos complement output coding option, in particular to the 2 × REFIN input range with –REFIN to +REFIN biased about the REFIN point. It is the deviation of the last code transition (011. . .110) to (011 . . . 111) from the ideal (i.e., +REFIN – 1 LSB) after the Zero Code Error has been adjusted out. Thus for a 12-bit converter, this is 74 dB, for a 10-bit converter this is 62 dB, and for an 8-bit converter this is 50 dB. Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7904/AD7914/AD7924, it is defined as: Positive Gain Error Match THD ( dB ) = 20 log This is the difference in Positive Gain Error between any two channels. Negative Gain Error This applies when using the twos complement output coding option, in particular to the 2 × REFIN input range with –REF IN to +REFIN biased about the REFIN point. It is the deviation of the first code transition (100 . . . 000) to (100 . . . 001) from the ideal (i.e., –REF IN + 1 LSB) after the Zero Code Error has been adjusted out. REV. 0 V22 + V32 + V42 + V52 + V62 V1 where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. –11– AD7904/AD7914/AD7924–Typical Performance Characteristics PERFORMANCE CURVES TPC 1 shows a typical FFT plot for the AD7924 at 1MSPS sample rate and 50 kHz input frequency. TPC 2 shows the signal-to-(noise + distortion) ratio performance versus input frequency for various supply voltages while sampling at 1 MSPS with an SCLK of 20 MHz. TPC 4 shows a graph of total harmonic distortion versus analog input frequency for various supply voltages, while TPC 5 shows a graph of total harmonic distortion versus analog input frequency for various source impedances. See the Analog Input section. TPC 6 and TPC 7 show typical INL and DNL plots for the AD7924. TPC 3 shows the power supply rejection ratio versus supply ripple frequency for the AD7924 when no decoupling is used. The power supply rejection ratio is defined as the ratio of the power in the ADC output at full-scale frequency f, to the power of a 200 mV p-p sine wave applied to the ADC AVDD supply of frequency fS: 0 VDD = 5V, 200mV p-p SINE WAVE ON V DD REFIN = 2.5V, 1F CAPACITOR TA = 25ⴗC –10 –20 –30 PSRR – dB PSRR( dB ) = 10 log( Pf / Pfs ) Pf is equal to the power at frequency f in ADC output; PfS is equal to the power at frequency fS coupled onto the ADC AVDD supply. Here a 200 mV p-p sine wave is coupled onto the AVDD supply. –40 –50 –60 –70 4096 POINT FFT VDD = 5V fSAMPLE = 1MSPS fIN = 50kHz SINAD = 71.147 THD = –87.229 SFDR = –90.744 –10 SNR – dB –30 –80 –90 0 100 200 300 400 500 600 700 800 SUPPLY RIPPLE FREQUENCY – kHz 900 1000 TPC 3. AD7924 PSRR vs. Supply Ripple Frequency –50 –50 –70 –55 fSAMPLE = 1MSPS TA = 25ⴗC RANGE = 0 TO REFIN VDD = V DRIVE = 2.7V –60 –90 –110 0 50 100 150 200 250 300 350 FREQUENCY – kHz 400 450 THD – dB –65 500 VDD = V DRIVE = 3.6V –70 –75 TPC 1. AD7924 Dynamic Performance at 1 MSPS –80 VDD = V DRIVE = 4.75V 75 –85 VDD = V DRIVE = 5.25V VDD = V DRIVE = 5.25V VDD = V DRIVE = 4.75V –90 10 SINAD – dB 70 1000 100 INPUT FREQUENCY – kHz TPC 4. AD7924 THD vs. Analog Input Frequency for Various Supply Voltages at 1 MSPS VDD = V DRIVE = 3.6V 65 –50 –55 60 55 10 –60 VDD = V DRIVE = 2.7V 100 INPUT FREQUENCY – kHz RIN = 1000⍀ –65 THD – dB fSAMPLE = 1MSPS TA = 25ⴗC RANGE = 0 TO REFIN fSAMPLE = 1MSPS TA = 25ⴗC RANGE = 0 TO REFIN VDD = 5.25V 1000 TPC 2. AD7924 SINAD vs. Analog Input Frequency for Various Supply Voltages at 1 MSPS –70 RIN = 100⍀ –75 RIN = 50⍀ –80 RIN = 10⍀ –85 –90 10 100 INPUT FREQUENCY – kHz 1000 TPC 5. AD7924 THD vs. Analog Input Frequency for Various Source Impedances –12– REV. 0 AD7904/AD7914/AD7924 1.0 1.0 VDD = V DRIVE = 5V TEMP = 25ⴗC 0.6 0.6 0.4 0.4 0.2 0 –0.2 0.2 0 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 0 512 1024 VDD = V DRIVE = 5V TEMP = 25ⴗC 0.8 DNL ERROR – LSB INL ERROR – LSB 0.8 1536 2048 2560 CODE 3072 3584 –1.0 4096 0 TPC 6. AD7924 Typical INL 512 1024 1536 2048 2560 CODE 3072 3584 4096 TPC 7. AD7924 Typical DNL CONTROL REGISTER The Control Register on the AD7904/AD7914/AD7924 is a 12-bit, write-only register. Data is loaded from the DIN pin of the AD7904/AD7914/AD7924 on the falling edge of SCLK. The data is transferred on the DIN line at the same time that the conversion result is read from the part. The data transferred on the DIN line corresponds to the AD7904/AD7914/AD7924 configuration for the next conversion. This requires 16 serial clocks for every data transfer. Only the information provided on the first 12 falling clock edges (after CS falling edge) is loaded to the Control Register. MSB denotes the first bit in the data stream. The bit functions are outlined in Table I. Table I. Control Register Bit Functions MSB WRITE SEQ1 DONTC DONTC ADD1 ADD0 PM1 PM0 SEQ0 DONTC RANGE LSB CODING Bit Mnemonic Comment 11 WRITE The value written to this bit of the Control Register determines whether the following 11 bits will be loaded to the control register or not. If this bit is a 1 then the following 11 bits will be written to the control register; if it is a 0 then the remaining 11 bits are not loaded to the control register and so it remains unchanged. 10 SEQ1 The SEQ1 bit in the control register is used in conjunction with the SEQ0 bit to control the use of the sequencer function. (See Table IV.) 9–8 DONTCARE 7–6 ADD1, ADD0 These two address bits are loaded at the end of the present conversion sequence and select which analog input channel is to be converted in the next serial transfer, or they may select the final channel in a consecutive sequence as described in Table IV. The selected input channel is decoded as shown in Table II. The address bits corresponding to the conversion result are also output on DOUT prior to the 12 bits of data, see the Serial Interface section. The next channel to be converted on will be selected by the mux on the fourteenth SCLK falling edge. 5, 4 PM1, PM0 Power Management Bits. These two bits decode the mode of operation of the AD7904/AD7914/AD7924 as shown in Table III. 3 SEQ0 The SEQ0 bit in the control register is used in conjunction with the SEQ1 bit to control the use of the sequencer function. (See Table IV.) 2 DONTCARE 1 RANGE This bit selects the analog input range to be used on the AD7904/AD7914/AD7924. If it is set to 0 then the analog input range will extend from 0 V to 2 × REFIN. If it is set to 1 then the analog input range will extend from 0 V to REFIN (for the next conversion). For 0 V to 2 × REFIN, VDD = 4.75 V to 5.25 V. 0 CODING This bit selects the type of output coding the AD7904/AD7914/AD7924 will use for the conversion result. If this bit is set to 0 the output coding for the part will be twos complement. If this bit is set to 1 then the output coding from the part will be straight binary (for the next conversion). REV. 0 –13– AD7904/AD7914/AD7924 Table II. Channel Selection ADD1 ADD0 Analog Input Channel 0 0 1 1 0 1 0 1 VIN0 VIN1 VIN2 VIN3 Table III. Power Mode Selection PM1 PM0 Mode 1 1 Normal Operation. In this mode, the AD7904/ AD7914/AD7924 remain in full power mode regardless of the status of any of the logicinputs. This mode allows the fastest possible throughput rate from the AD7904/AD7914/AD7924. 1 0 Full Shutdown. In this mode, the AD7904/ AD7914/AD7924 is in full shutdown mode with all circuitry on the AD7904/AD7914/AD7924 powering down. The AD7904/AD7914/AD7924 retains the information in the Control Register while in full shutdown. The part remains in full shutdown until these bits are changed. 0 0 1 0 Auto Shutdown. In this mode, the AD7904/ AD7914/AD7924/ automatically enters full shutdown mode at the end of each conversion when the control register is updated. Wake-up time from full shutdown is 1 µs and the user should ensure that 1 µs has elapsed before attempting to perform a valid conversion on the part in this mode. SEQUENCER OPERATION The configuration of the SEQ1 and SEQ0 bits in the control register allows the user to select a particular mode of operation of the sequencer function. Table IV outlines the three modes of operation of the Sequencer. Figure 2 reflects the traditional operation of a multichannel ADC, where each serial transfer selects the next channel for conversion. In this mode of operation the Sequencer function is not used. Figure 3 shows how to program the AD7904/AD7914/AD7924 to continuously convert on a sequence of consecutive channels from Channel 0 to a selected final channel. To exit this mode of operation and revert back to the traditional mode of operation of a multichannel ADC (as outlined in Figure 2), ensure that the WRITE bit = 1 and SEQ1 = SEQ0 = 0 on the next serial transfer. Table IV. Sequence Selection SEQ1 SEQ0 Sequence Type 0 X This configuration means that the sequence function is not used. The analog input channel selected for each individual conversion is determined by the contents of the channel address bits ADD1, ADD0 in each prior write operation. This mode of operation reflects the traditional operation of a multichannel ADC, without the Sequencer function being used, where each write to the AD7904/AD7914/AD7924 selects the next channel for conversion (see Figure 2). 1 0 If the SEQ1 and SEQ0 bits are set in this way then the sequence function will not be interrupted upon completion of the WRITE operation. This allows other bits in the Control Register to be altered between conversions while in a sequence without terminating the cycle. 1 1 This configuration is used in conjunction with the channel address bits ADD1, ADD0 to program continuous conversions on a consecutive sequence of channels from Channel 0 to a selected final channel as determined by the channel address bits in the Control Register (see Figure 3). Invalid Selection. This configuration is not allowed. –14– REV. 0 AD7904/AD7914/AD7924 CIRCUIT INFORMATION POWER ON The AD7904/AD7914/AD7924 are high speed, 4-channel, 8-bit, 10-bit, and 12-bit, single supply, A/D converters, respectively. The parts can be operated from a 2.7 V to 5.25 V supply. When operated from either a 5 V or 3 V supply, the AD7904/AD7914/ AD7924 are capable of throughput rates of 1 MSPS when provided with a 20 MHz clock. DUMMY CONVERSION DIN: WRITE TO CONTROL REGISTER, WRITE BIT = 1, SELECT CODING, RANGE, AND POWER MODE. SELECT CHANNEL A1, A0 FOR CONVERSION. SEQ1 = 0, SEQ0 = x CS DOUT: CONVERSION RESULT FROM PREVIOUSLY SELECTED CHANNEL A1, A0 DIN: WRITE TO CONTROL REGISTER, WRITE BIT = 1, SELECT CODING, RANGE, AND POWER MODE. SELECT A1, A0 FOR CONVERSION. SEQ1 = 0, SEQ0 = x CS WRITE BIT = 1, SEQ1 = 0, SEQ0 = x Figure 2. SEQ1 Bit = 0, SEQ0 Bit = x Flowchart POWER ON The AD7904/AD7914/AD7924 provide flexible power management options to allow the user to achieve the best power performance for a given throughput rate. These options are selected by programming the Power Management bits, PM1 and PM0, in the Control Register. DUMMY CONVERSION DIN: WRITE TO CONTROL REGISTER, WRITE BIT = 1, SELECT CODING, RANGE, AND POWER MODE. SELECT CHANNEL A1, A0 FOR CONVERSION. SEQ1 = 1, SEQ0 = 1 CS The AD7904/AD7914/AD7924 provide the user with an on-chip track/hold, A/D converter, and a serial interface housed in a 16-lead TSSOP package. The AD7904/AD7914/AD7924 each have four single-ended input channels with a channel sequencer, allowing the user to select a channel sequence through which the ADC can cycle with each consecutive CS falling edge. The serial clock input accesses data from the part, controls the transfer of data written to the ADC, and provides the clock source for the successive-approximation A/D converter. The analog input range for the AD7904/AD7914/AD7924 is 0 V to REFIN or 0 V to 2 × REFIN, depending on the status of Bit 1 in the Control Register. For the 0 to 2 × REFIN range, the part must be operated from a 4.75 V to 5.25 V supply. CONVERTER OPERATION DOUT: CONVERSION RESULT FROM CHANNEL 0 CS CONTINUOUSLY CONVERTS ON A CONSECUTIVE SEQUENCE OF CHANNELS FROM CHANNEL 0 UP TO AND INCLUDING THE PREVIOUSLY SELECTED A1, A0 IN THE CONTROL REGISTER CONTINUOUSLY CONVERTS ON THE SELECTED SEQUENCE OF CHANNELS BUT WILL ALLOW RANGE, CODING, AND SO FORTH, TO CHANGE IN THE CONTROL REGISTER WITHOUT INTERRUPTING THE SEQUENCE, PROVIDED SEQ1 = 1, SEQ0 = 0 CS WRITE BIT = 0 WRITE BIT = 1, SEQ1 = 1, SEQ0 = 0 The AD7904/AD7914/AD7924 are 8-, 10-, and 12-bit successive approximation analog-to-digital converters based around a capacitive DAC, respectively. The AD7904/AD7914/AD7924 can convert analog input signals in the range 0 V to REFIN or 0 V to 2 × REFIN. Figures 4 and 5 show simplified schematics of the ADC. The ADC is comprised of Control Logic, SAR, and a Capacitive DAC, which are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. Figure 4 shows the ADC during its acquisition phase. SW2 is closed and SW1 is in position A. The comparator is held in a balanced condition and the sampling capacitor acquires the signal on the selected VIN channel. CAPACITIVE DAC Figure 3. SEQ1 Bit = 1, SEQ0 Bit = 1 Flowchart VIN0 A SW1 VIN3 4k⍀ B CONTROL LOGIC SW2 COMPARATOR AGND Figure 4. ADC Acquisition Phase REV. 0 –15– AD7904/AD7914/AD7924 When the ADC starts a conversion (see Figure 5), SW2 will open and SW1 will move to position B, causing the comparator to become unbalanced. The Control Logic and the Capacitive DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The Control Logic generates the ADC output code. Figures 7 and 8 show the ADC transfer functions. CAPACITIVE DAC A VIN0 •. •. SW1 ADC TRANSFER FUNCTION The output coding of the AD7904/AD7914/AD7924 is either straight binary or twos complement, depending on the status of the LSB in the Control Register. The designed code transitions occur at successive LSB values (i.e., 1 LSB, 2 LSBs, and so on). The LSB size is REFIN/256 for the AD7904 , REFIN/1024 for the AD7914, and REFIN/4096 for the AD7924. The ideal transfer characteristic for the AD7904/AD7914/AD7924 when straight binary coding is selected is shown in Figure 7, and the ideal transfer characteristic for the AD7904/AD7914/AD7924 when twos complement coding is selected is shown in Figure 8. 4k⍀ B CONTROL LOGIC SW2 VIN3 111…111 111…110 • • 111…000 • 011…111 • • 000…010 000…001 000…000 COMPARATOR AGND Figure 5. ADC Conversion Phase Analog Input When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum source impedance will depend on the amount of total harmonic distortion (THD) that can be tolerated. The THD will increase as the source impedance increases and performance will degrade (see TPC 5). VDD D1 R1 D2 1 LSB +VREF ⴚ 1 LSB ANALOG INPUT NOTE: V REF IS EITHER REFIN OR 2 ⴛ REFIN Figure 7. Straight Binary Transfer Characteristic 011…111 011…110 • • 000…001 000…000 111…111 • • 100…010 100…001 100…000 1LSB = 2 ⴛ VREFⲐ256 AD7904 1LSB = 2 ⴛ VREFⲐ1024 AD7914 1LSB = 2 ⴛ VREFⲐ4096 AD7924 –VREF ⴙ 1LSB +VREF ⴚ 1LSB VREF ⴚ 1LSB ANALOG INPUT Figure 8. Twos Complement Transfer Characteristic with REFIN ± REFIN Input Range Handling Bipolar Input Signals Figure 9 shows how useful the combination of the 2 × REFIN input range and the twos complement output coding scheme is for handling bipolar input signals. If the bipolar input signal is biased about REFIN and twos complement output coding is selected, then REFIN becomes the zero code point, –REFIN is negative full scale and +REFIN becomes positive full scale, with a dynamic range of 2 × REFIN. TYPICAL CONNECTION DIAGRAM C2 30pF VIN C1 4pF 0V ADC CODE Figure 6 shows an equivalent circuit of the analog input structure of the AD7904/AD7914/AD7924. The two diodes D1 and D2 provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 200 mV. This will cause these diodes to become forward biased and start conducting current into the substrate. 10 mA is the maximum current these diodes can conduct without causing irreversible damage to the part. The capacitor C1 in Figure 6 is typically about 4 pF and can primarily be attributed to pin capacitance. The resistor R1 is a lumped component made up of the on resistance of a switch (track and hold switch) and also includes the on resistance of the input multiplexer. The total resistance is typically about 400 Ω. The capacitor C2 is the ADC sampling capacitor and has a capacitance of 30 pF typically. For ac applications, removing high frequency components from the analog input signal is recommended by use of an RC low-pass filter on the relevant analog input pin. In applications where harmonic distortion and signal to noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances will significantly affect the ac performance of the ADC. This may necessitate the use of an input buffer amplifier. The choice of the op amp will be a function of the particular application. 1LSB = V REF/256 AD7904 1LSB = V REF/1024 AD7914 1LSB = VREF/4096 AD7924 CONVERSION PHASE: SWITCH OPEN TRACK PHASE: SWITCH CLOSED Figure 6. Equivalent Analog Input Circuit Figure 10 shows a typical connection diagram for the AD7904/ AD7914/AD7924. In this setup the GND pin is connected to the analog ground plane of the system. In Figure 10, REFIN is connected to a decoupled 2.5 V supply from a reference source, the AD780, to provide an analog input range of 0 V to 2.5 V (if RANGE bit is 1) or 0 V to 5 V (if RANGE bit is 0). Although the AD7904/AD7914/AD7924 is connected to a VDD of 5 V, the serial interface is connected to a 3 V microprocessor. The VDRIVE pin of the AD7904/AD7914/AD7924 is connected to the same 3 V supply of the microprocessor to allow a 3 V logic interface (see the Digital Inputs section). The conversion result is output in a –16– REV. 0 AD7904/AD7914/AD7924 VDD VREF 0.1F REFIN VDD VDD VDRIVE AD7904/ AD7914/ AD7924 R4 V R3 V 0V VIN0 R2 R1 R1 ⴝ R2 ⴝ R3 ⴝ R4 VIN3 DSP/P TWOS COMPLEMENT DOUT +REFIN (= 2 ⴛ REFIN) 000…000 REFIN –REFIN 011…111 (= 0V) 100…000 Figure 9. Handling Bipolar Signals 16-bit word. This 16-bit data stream consists of two leading zeros, two address bits indicating which channel the conversion result corresponds to, followed by the 12 bits of conversion data for the AD7924 (10 bits of data for the AD7914 and 8 bits of data for the AD7904, each followed by 2 and 4 trailing zeros, respectively). For applications where power consumption is of concern, the power-down modes should be used between conversions or bursts of several conversions to improve power performance. See the Modes of Operation section of the data sheet. 0.1F 10F 5V SUPPLY SERIAL INTERFACE VIN 0 0V TO REFIN VIN3 AGND VDD SCLK AD7904/ AD7914/ AD7924 C/P CS VDRIVE DIN REFIN 0.1F DOUT 2.5V 0.1F 10F AD780 3V SUPPLY NOTE: ALL UNUSED INPUT CHANNELS SHOULD BE CONNECTED TO AGND Figure 10. Typical Connection Diagram It is not necessary to write to the Control Register again once a sequencer operation has been initiated. The WRITE bit must be set to zero or the DIN line tied low to ensure the Control Register is not accidently overwritten, or the sequence operation interrupted. If the Control Register is written to at any time during the sequence then it must be ensured that the SEQ1 and SEQ0 bits are set to 1,0 to avoid interrupting the automatic conversion sequence. This pattern will continue until such time as the AD7904/AD7914/AD7924 is written to and the SEQ1 and SEQ0 bits are configured with any bit combination except 1,0 resulting in the termination of the sequence. If uninterrupted, however (WRITE bit = 0, or WRITE bit = 1 and SEQ1 and SEQ0 bits are set to 1,0), then upon completion of the sequence, the AD7904/AD7914/AD7924 sequencer will return to the Channel 0 and commence the sequence again. Regardless of which channel selection method is used, the 16-bit word output from the AD7924 during each conversion will always contain two leading zeros, two channel address bits that the conversion result corresponds to, followed by the 12-bit conversion result; the AD7914 will output two leading zeros, two channel address bits that the conversion result corresponds to, followed by the 10-bit conversion result and two trailing zeros; the AD7904 will output two leading zeros, two channel address bits that the conversion result corresponds to, followed by the 8-bit conversion result and four trailing zeros. See the Serial Interface section. Analog Input Selection Digital Inputs Any one of four analog input channels may be selected for conversion by programming the multiplexer with the address bits ADD1 and ADD0 in the Control Register. The channel configurations are shown in Table II. The digital inputs applied to the AD7904/AD7914/AD7924 are not limited by the maximum ratings that limit the analog inputs. Instead, the digital inputs applied can go to 7 V and are not restricted by the VDD + 0.3 V limit as on the analog inputs. The AD7904/AD7914/AD7924 may also be configured to autoAnother advantage of SCLK, DIN, and CS not being restricted matically cycle through a number of channels as selected. The by the VDD + 0.3 V limit is the fact that power supply sequencsequencer feature is accessed via the SEQ1 and SEQ0 bits in the ing issues are avoided. If CS, DIN, or SCLK are applied before Control Register, see Table IV. The AD7904/AD7914/AD7924 VDD there is no risk of latch-up as there would be on the analog can be programmed to continuously convert on a number of inputs if a signal greater than 0.3 V was applied prior to VDD. consecutive channels in ascending order from Channel 0 to a VDRIVE selected final channel as determined by the channel address bits The AD7904/AD7914/AD7924 also have the VDRIVE feature. ADD1 and ADD0. This is possible if the SEQ1 and SEQ0 bits VDRIVE controls the voltage at which the serial interface operare set to 1,1. The next serial transfer will then act on the sequence ates. VDRIVE allows the ADC to easily interface to both 3 V and programmed by executing a conversion on Channel 0. The next 5 V processors. For example, if the AD7904/AD7914/AD7924 serial transfer will result in a conversion on Channel 1, and so were operated with a VDD of 5 V, the VDRIVE pin could be powon, until the channel selected via the address bits ADD1, ADD0 ered from a 3 V supply. The AD7904/AD7914/AD7924 have is reached. REV. 0 –17– AD7904/AD7914/AD7924 CS better dynamic performance with a VDD of 5 V while still being able to interface to 3 V processors. Care should be taken to ensure VDRIVE does not exceed VDD by more than 0.3 V. (See the Absolute Maximum Ratings section). SCLK DOUT Reference An external reference source should be used to supply the 2.5 V reference to the AD7904/AD7914/AD7924. Errors in the reference source will result in gain errors in the AD7904/AD7914/ AD7924 transfer function and will add to the specified full-scale errors of the part. A capacitor of at least 0.1 µF should be placed on the REFIN pin. Suitable reference sources for the AD7904/ AD7914/AD7924 include the AD780, REF 193, and the AD1582. If 2.5 V is applied to the REFIN pin, the analog input range can either be 0 V to 2.5 V or 0 V to 5 V, depending on the setting of the RANGE bit in the Control Register. MODES OF OPERATION The AD7904/AD7914/AD7924 have a number of different modes of operation. These modes are designed to provide flexible power management options. These options can be chosen to optimize the power dissipation/throughput rate ratio for differing application requirements. The mode of operation of the AD7904/AD7914/AD7924 is controlled by the power management bits, PM1 and PM0, in the Control Register, as detailed in Table III. When power supplies are first applied to the AD7904/ AD7914/AD7924, care should be taken to ensure that the part is placed in the required mode of operation (see the Powering Up the AD7904/AD7914/AD7924 section). Normal Mode (PM1 = PM0 = 1) This mode is intended for the fastest throughput rate performance as the user does not have to worry about any power-up times with the AD7904/AD7914/AD7924 remaining fully powered at all times. Figure 11 shows the general diagram of the operation of the AD7904/AD7914/AD7924 in this mode. The conversion is initiated on the falling edge of CS and the track and hold will enter hold mode as described in the Serial Interface section. The data presented to the AD7904/AD7914/AD7924 on the DIN line during the first 12 clock cycles of the data transfer are loaded into the Control Register (provided WRITE bit is set to 1). The part will remain fully powered up in normal mode at the end of the conversion as long as PM1 and PM0 are set to 1 in the write transfer during that same conversion. To ensure continued operation in Normal Mode, PM1 and PM0 must both be loaded with 1 on every data transfer, assuming a write operation is taking place. If the WRITE bit is set to 0, then the power management bits will be left unchanged and the part will remain in Normal Mode. Sixteen serial clock cycles are required to complete the conversion and access the conversion result. The track and hold will go back into track on the fourteenth SCLK falling edge. CS may then idle high until the next conversion or may idle low until sometime prior to the next conversion, (effectively idling CS low). DIN 1 12 16 2 LEADING ZEROS + 2 CHANNEL IDENTIFIER BITS + CONVERSION RESULT DATA IN TO CONTROL REGISTER NOTE: CONTROL REGISTER DATA IS LOADED ON FIRST 12 SCLK CYCLES Figure 11. Normal Mode Operation Full Shutdown (PM1 = 1, PM0 = 0) In this mode, all internal circuitry on the AD7904/AD7914/ AD7924 is powered down. The part retains information in the Control Register during full shutdown. The AD7904/AD7914/ AD7924 remains in full shutdown until the power management bits in the Control Register, PM1 and PM0, are changed. If a write to the Control Register occurs while the part is in Full Shutdown, with the power management bits changed to PM0 = PM1 = 1, Normal mode, the part will begin to power up on the CS rising edge. The track and hold that was in hold while the part was in Full Shutdown will return to track on the fourteenth SCLK falling edge. To ensure that the part is fully powered up, tPOWER UP (t12) should have elapsed before the next CS falling edge. Figure 12 shows the general diagram for this sequence. Auto Shutdown (PM1 = 0, PM0 = 1) In this mode, the AD7904/AD7914/AD7924 automatically enters shutdown at the end of each conversion when the control register is updated. When the part is in shutdown, the track and hold is in hold mode. Figure 13 shows the general diagram of the operation of the AD7904/AD7914/AD7924 in this mode. In shutdown mode all internal circuitry on the AD7904/AD7914/AD7924 is powered down. The part retains information in the Control Register during shutdown. The AD7904/AD7914/AD7924 remains in shutdown until the next CS falling edge it receives. On this CS falling edge the track and hold that was in hold while the part was in shutdown will return to track. Wake-up time from auto shutdown is 1 µs maximum, and the user should ensure that 1 µs has elapsed before attempting a valid conversion. When running the AD7904/AD7914/AD7924 with a 20 MHz clock, one 16 SCLK dummy cycle should be sufficient to ensure the part is fully powered up. During this dummy cycle the contents of the Control Register should remain unchanged, therefore the WRITE bit should be 0 on the DIN line. This dummy cycle effectively halves the throughput rate of the part, with every other conversion result being valid. In this mode the power consumption of the part is greatly reduced with the part entering shutdown at the end of each conversion. When the Control Register is programmed to move into auto shutdown, it does so at the end of the conversion. The user can move the ADC in and out of the low power state by controlling the CS signal. Once a data transfer is complete (DOUT has returned to threestate), another conversion can be initiated after the quiet time, tQUIET, has elapsed by bringing CS low again. –18– REV. 0 AD7904/AD7914/AD7924 PART IS IN FULL SHUTDOWN PART BEGINS TO POWER UP ON CS RISING EDGE AS PM1 = PM0 = 1 THE PART IS FULLY POWERED UP ONCE tPOWER UP HAS ELAPSED t12 CS 1 14 16 1 14 16 SCLK DOUT CHANNEL IDENTIFIER BITS + CONVERSION RESULT DATA IN TO CONTROL REGISTER DIN DATA IN TO CONTROL REGISTER CONTROL REGISTER IS LOADED ON THE FIRST 12 CLOCKS. PM1 = 1, PM0 = 1 TO KEEP THE PART IN NORMAL MODE, LOAD PM1 = PM0 = 1 IN CONTROL REGISTER Figure 12. Full Shutdown Mode Operation PART ENTERS SHUTDOWN ON CS RISING EDGE AS PM1 ⴝ 0, PM0 ⴝ 1 PART BEGINS TO POWER UP ON CS FALLING EDGE CS SCLK DOUT DIN PART IS FULLY POWERED UP PART ENTERS SHUTDOWN ON CS RISING EDGE AS PM1 ⴝ 0, PM0 ⴝ 1 DUMMY CONVERSION 1 12 16 CHANNEL IDENTIFIER BITS + CONVERSION RESULT 1 12 16 INVALID DATA 1 12 16 CHANNEL IDENTIFIER BITS + CONVERSION RESULT DATA IN TO CONTROL REGISTER DATA IN TO CONTROL REGISTER CONTROL REGISTER IS LOADED ON THE FIRST 12 CLOCKS, PM1 ⴝ 0, PM0 ⴝ 1 CONTROL REGISTER CONTENTS SHOULD NOT CHANGE, WRITE BIT ⴝ 0 TO KEEP PART IN THIS MODE, LOAD PM1 ⴝ 0, PM0 ⴝ 1 IN CONTROL REGISTER OR SET WRITE BIT = 0 Figure 13. Auto Shutdown Mode Operation Powering Up the AD7904/AD7914/AD7924 When supplies are first applied to the AD7904/AD7914/AD7924, the ADC may power up in any of the operating modes of the part. To ensure the part is placed into the required operating mode the user should perform a dummy cycle operation as outlined in Figures 14a through 14c. The dummy conversion operation must be performed to place the part into the desired mode of operation. To ensure the part is in normal mode, this dummy cycle operation can be performed with the DIN line tied HIGH, i.e., PM1, PM0 = 1,1 (depending on other required settings in the control register) but the minimum power-up time of 1 µs must be allowed from the rising edge of CS, where the control register is updated, before attempting the first valid conversion. This is to allow for the possibility that the part initially powered up in shutdown. If the desired mode of operation is Full Shutdown, then again only one dummy cycle is required after supplies are applied. In this dummy cycle the user simply sets the power management bits, PM1, PM0 = 1,0 and upon the rising edge of CS at the end of that serial transfer the part will enter full shutdown. REV. 0 If the desired mode of operation is Auto Shutdown after supplies are applied, then two dummy cycles will be required, the first with DIN tied high and the second dummy cycle to set the power management bits PM1 and PM0 = 0,1. On the second CS rising edge after the supplies are applied, the Control Register will contain the correct information and the part will enter Auto Shutdown mode as programmed. If power consumption is of critical concern, then in the first dummy cycle the user may set PM1, PM0 = 1,0, i.e., Full Shutdown, and then place the part into Auto Shutdown in the second dummy cycle. For illustration purposes, Figure 14c is shown with DIN tied high on the first dummy cycle in this case. Figures 14a, 14b, and 14c each show the required dummy cycle(s) after supplies are applied in the case of Normal mode, Full Shutdown mode, or Auto Shutdown mode, respectively, being the desired mode of operation. –19– AD7904/AD7914/AD7924 PART IS IN UNKNOWN MODE AFTER POWER-ON IF IN SHUTDOWN AT POWER-ON, PART BEGINS TO POWER UP ON CS RISING EDGE AS PM1 = PM0 = 1 ALLOW tPOWER TO ELAPSE t12 CS 1 14 16 1 14 16 SCLK DOUT INVALID DATA CHANNEL IDENTIFIER BITS + CONVERSION RESULT DIN DATA IN TO CONTROL REGISTER DIN LINE HIGH FOR FIRST DUMMY CONVERSION TO KEEP THE PART IN NORMAL MODE, LOAD PM1 = PM0 = 1 IN CONTROL REGISTER Figure 14a. To Place AD7904/AD7914/AD7924 into Normal Mode after Supplies are First Applied PART IS IN UNKNOWN MODE AFTER POWER-ON PART ENTERS SHUTDOWN ON CS RISING EDGE AS PM1 = PM0 = 0 CS 1 14 16 SCLK INVALID DATA DOUT DATA IN TO CONTROL REGISTER DIN CONTROL REGISTER IS LOADED ON THE FIRST 12 CLOCKS. PM1 = 1, PM0 = 0 Figure 14b. To Place AD7904/AD7914/AD7924 into Full Shutdown Mode after Supplies are First Applied PART IS IN UNKNOWN MODE AFTER POWER-ON PART ENTERS AUTO SHUTDOWN ON CS RISING EDGE AS PM1 = 0, PM0 = 1 CS 1 14 16 1 14 16 SCLK DOUT INVALID DATA INVALID DATA DIN DATA IN TO CONTROL REGISTER DIN LINE HIGH FOR FIRST DUMMY CONVERSION CONTROL REGISTER IS LOADED ON THE FIRST 12 CLOCKS. PM1 = 0, PM0 = 1 Figure 14c. To Place AD7904/AD7914/AD7924 into Auto Shutdown Mode after Supplies are First Applied POWER VERSUS THROUGHPUT RATE By operating in Auto Shutdown mode on the AD7904/AD7914/ AD7924, the average power consumption of the ADC decreases at lower throughput rates. Figure 15 shows how as the throughput rate is reduced, the part remains in its shutdown state longer and the average power consumption over time drops accordingly. For example, if the AD7924 is operated in a continuous sampling mode, with a throughput rate of 100 kSPS and an SCLK of 20 MHz (VDD = 5 V), and the device is placed in Auto Shutdown mode, i.e., if PM1 = 0 and PM0 = 1, then the power consumption is calculated as follows: The maximum power dissipation during normal operation is 13.5 mW (VDD = 5 V). If the power-up time from Auto Shutdown is one dummy cycle, i.e., 1 µs, and the remaining conversion time is another cycle, i.e., 1 µs, then the AD7924 can be said to dissipate 13.5 mW for 2 µs during each conversion cycle. For the remainder of the conversion cycle, 8 µs, the part remains in shutdown. The AD7924 can be said to dissipate 2.5 µW for the remaining 8 µs of the conversion cycle. If the throughput rate is 100 kSPS, the cycle time is 10 µs and the average power dissipated during each cycle is (2/10) × (13.5 mW) + (8/10) × (2.5 µW) = 2.702 mW. –20– REV. 0 AD7904/AD7914/AD7924 Figure 15 shows the maximum power versus throughput rate when using the Auto Shutdown mode with 5 V and 3 V supplies. 10 VDD = 5V POWER – mW 0.1 50 0 150 250 200 THROUGHPUT – kSPS 100 350 300 Figures 16, 17, and 18 show the detailed timing diagrams for serial interfacing to the AD7904, AD7914, and AD7924, respectively. The serial clock provides the conversion clock and also controls the transfer of information to and from the AD7904/AD7914/AD7924 during each conversion. The CS signal initiates the data transfer and conversion process. The falling edge of CS puts the track and hold into hold mode, takes the bus out of three-state and the analog input is sampled at this point. The conversion is also initiated at this point and will require 16 SCLK cycles to complete. The track and hold will go back into track on the fourteenth SCLK falling edge as shown in Figures 16, 17, and 18 at Point B. On the sixteenth SCLK falling edge, the DOUT line will go back into three-state. If the rising edge of CS occurs before 16 SCLKs have elapsed, the conversion will be terminated, the DOUT line will go back into three-state, and the Control Register will not be updated; otherwise DOUT returns to three-state on the sixteenth SCLK falling edge as shown in Figures 16, 17, and 18. VDD = 3V 1 0.01 SERIAL INTERFACE Figure 15. AD7924 Power vs. Throughput Rate CS t2 1 SCLK 2 3 t3 4 5 ZERO THREESTATE ZERO ADD1 ADD0 DB7 SEQ1 DONTC B 11 12 13 14 15 16 t5 t11 t8 DB6 2 IDENTIFICATION BITS t9 WRITE 6 t7 t4 DOUT DIN tCONVERT t6 DB0 ZERO ZERO ZERO tQUIET ZERO THREESTATE 4 TRAILING ZEROS t10 DONTC ADD1 ADD0 CODING DONTC DONTC DONTC DONTC Figure 16. AD7904 Serial Interface Timing Diagram CS t2 1 SCLK 2 3 t3 4 5 ZERO THREESTATE ZERO ADD1 ADD0 DB9 SEQ1 DONTC B 11 12 13 14 15 16 t5 t11 t8 DB8 2 IDENTIFICATION BITS t9 WRITE 6 t7 t4 DOUT DIN tCONVERT t6 DB2 DB1 DB0 ZERO tQUIET ZERO THREESTATE 2 TRAILING ZEROS t10 DONTC ADD1 ADD0 CODING DONTC DONTC DONTC DONTC Figure 17. AD7914 Serial Interface Timing Diagram CS t2 1 SCLK 2 3 t3 4 5 ZERO THREESTATE ZERO WRITE t9 SEQ1 ADD1 ADD0 DB11 2 IDENTIFICATION BITS DONTC 6 B 11 12 13 14 DONTC 15 t11 t8 DB10 DB4 DB3 DB2 DB1 tQUIET DB0 THREESTATE t10 ADD1 ADD0 CODING DONTC DONTC Figure 18. AD7924 Serial Interface Timing Diagram REV. 0 16 t5 t7 t4 DOUT DIN tCONVERT t6 –21– DONTC DONTC AD7904/AD7914/AD7924 Sixteen serial clock cycles are required to perform the conversion process and to access data from the AD7904/AD7914/AD7924. For the AD7904/AD7914/AD7924 the 8/10/12 bits of data are preceded by two leading zeros and two channel address bits ADD1 and ADD0, identifying which channel the result corresponds to. CS going low clocks out the first leading zero to be read in by the microcontroller or DSP on the first falling edge of SCLK. The first falling edge of SCLK will also clock out the second leading zero to be read in by the microcontroller or DSP on the second SCLK falling edge, and so on. The remaining two address bits and 8/10/12 data bits are then clocked out by subsequent SCLK falling edges beginning with the first address bit ADD1; thus the second falling clock edge on the serial clock has the second leading zero provided and also clocks out address bit ADD1. The final bit in the data transfer is valid on the sixteenth falling edge, having been clocked out on the previous (fifteenth) falling edge. Writing of information to the Control Register takes place on the first 12 falling edges of SCLK in a data transfer, assuming the MSB, i.e., the WRITE bit, has been set to 1. The AD7904 will output two leading zeros, two channel address bits that the conversion result corresponds to, followed by the 8-bit conversion result, and four trailing zeros. The AD7914 will output two leading zeros, two channel address bits that the conversion result corresponds to, followed by the 10-bit conversion result, and two trailing zeros. The 16-bit word read from the AD7924 will always contain two leading zeros, two channel address bits that the conversion result corresponds to, followed by the 12-bit conversion result. MICROPROCESSOR INTERFACING The serial interface on the AD7904/AD7914/AD7924 allows the part to be directly connected to a range of many different microprocessors. This section explains how to interface the AD7904/AD7914/AD7924 with some of the more common microcontroller and DSP serial interface protocols. AD7904/AD7914/AD7924 to TMS320C541 The serial interface on the TMS320C541 uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices like the AD7904/AD7914/AD7924. The CS input allows easy interfacing between the TMS320C541 and the AD7904/AD7914/ AD7924 without any glue logic required. The serial port of the TMS320C541 is set up to operate in burst mode with internal CLKX0 (TX serial clock on serial port 0) and FSX0 (TX frame sync from serial port 0). The serial port control register (SPC) must have the following setup: FO = 0, FSM = 1, MCM = 1, and TXM = 1. The connection diagram is shown in Figure 19. It should be noted that for signal processing applications, it is imperative that the frame synchronization signal from the TMS320C541 provides equidistant sampling. The VDRIVE pin of the AD7904/AD7914/AD7924 takes the same supply voltage as that of the TMS320C541. This allows the ADC to operate at a higher voltage than the serial interface, i.e., TMS320C541, if necessary. AD7904/ AD7914/ AD7924* SCLK TMS320C541* CLKX CLKR DOUT DR DIN DT CS FSX VDRIVE *ADDITIONAL PINS REMOVED FOR CLARITY FSR VDD Figure 19. Interfacing to the TMS320C541 AD7904/AD7914/AD7924 to ADSP-21xx The ADSP-21xx family of DSPs are interfaced directly to the AD7904/AD7914/AD7924 without any glue logic required. The VDRIVE pin of the AD7904/AD7914/AD7924 takes the same supply voltage as that of the ADSP-218x. This allows the ADC to operate at a higher voltage than the serial interface, i.e., ADSP-218x, if necessary. The SPORT0 control register should be set up as follows: TFSW = RFSW = 1, Alternate Framing INVRFS = INVTFS = 1, Active Low Frame Signal DTYPE = 00, Right Justify Data SLEN = 1111, 16-Bit Data-Words ISCLK = 1, Internal Serial Clock TFSR = RFSR = 1, Frame Every Word IRFS = 0 ITFS = 1 The connection diagram is shown in Figure 20. The ADSP-218x has the TFS and RFS of the SPORT tied together, with TFS set as an output and RFS set as an input. The DSP operates in Alternate Framing Mode and the SPORT control register is set up as described. The frame synchronization signal generated on the TFS is tied to CS, and as with all signal processing applications, equidistant sampling is necessary. However, in this example, the timer interrupt is used to control the sampling rate of the ADC, and under certain conditions equidistant sampling may not be achieved. The Timer register, and so on, are loaded with a value that will provide an interrupt at the required sample interval. When an interrupt is received, a value is transmitted with TFS/DT (ADC control word). The TFS is used to control the RFS and thus the reading of data. The frequency of the serial clock is set in the SCLKDIV register. When the instruction to transmit with TFS is given (i.e., AX0 = TX0), the state of the SCLK is checked. The DSP will wait until the SCLK has gone High, Low, and High before transmission will start. If the timer and SCLK values are chosen such that the instruction to transmit occurs on or near the rising edge of SCLK, then the data may be transmitted or it may wait until the next clock edge. For example, if the ADSP-2189 had a 20 MHz crystal such that it had a master clock frequency of 40 MHz, then the master cycle time would be 25 ns. If the SCLKDIV register is loaded with the value 3, then a SCLK of 5 MHz is obtained and eight master clock periods will elapse for every one SCLK period. Depending on the throughput rate selected, if the timer register was loaded with the value, say 803 (803 + 1 = 804), then 100.5 SCLKs will occur between interrupts and subsequently between transmit –22– REV. 0 AD7904/AD7914/AD7924 instructions. This situation will result in nonequidistant sampling as the transmit instruction is occurring on a SCLK edge. If the number of SCLKs between interrupts is a whole integer figure of N, then equidistant sampling will be implemented by the DSP. The printed circuit board that houses the AD7904/AD7914/ AD7924 should be designed such that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be separated easily. A minimum etch technique is generally best for ground planes as it gives the best shielding. All three AGND pins of the AD7904/AD7914/AD7924 should be sunk in the AGND plane. Digital and analog ground planes should be joined at only one place. If the AD7904/AD7914/AD7924 is in a system where multiple devices require an AGND to DGND connection, the connection should still be made at one point only, a star ground point that should be established as close as possible to the AD7904/AD7914/AD7924. ADSP-218x* AD7904/ AD7914/ AD7924* SCLK SCLK DOUT DR CS RFS TFS VDRIVE DIN DT *ADDITIONAL PINS REMOVED FOR CLARITY VDD Figure 20. Interfacing to the ADSP-218x AD7904/AD7914/AD7924 to DSP563xx The connection diagram in Figure 21 shows how the AD7904/AD7914/AD7924 can be connected to the ESSI (Synchronous Serial Interface) of the DSP563xx family of DSPs from Motorola. Each ESSI (two on board) is operated in Synchronous Mode (SYN bit in CRB = 1) with internally generated 1-bit clock period frame sync for both Tx and Rx (bits FSL1 = 0 and FSL0 = 0 in CRB). Normal operation of the ESSI is selected by making MOD = 0 in the CRB. Set the word length to 16 by setting bits WL1 = 1 and WL0 = 0 in CRA. The FSP bit in the CRB should be set to 1 so the frame sync is negative. It should be noted that for signal processing applications, it is imperative that the frame synchronization signal from the DSP563xx provides equidistant sampling. In the example shown in Figure 21 below, the serial clock is taken from the ESSI so the SCK0 pin must be set as an output, SCKD = 1. The VDRIVE pin of the AD7904/AD7914/AD7924 takes the same supply voltage as that of the DSP563xx. This allows the ADC to operate at a higher voltage than the serial interface, i.e., DSP563xx, if necessary. AD7904/ AD7914/ AD7924* VDRIVE DSP563xx* SCLK SCK DOUT SRD CS STD DIN SC2 *ADDITIONAL PINS REMOVED FOR CLARITY VDD Figure 21. Interfacing to the DSP563xx APPLICATION HINTS Grounding and Layout The AD7904/AD7914/AD7924 have very good immunity to noise on the power supplies as can be seen by the PSRR vs. Supply Ripple Frequency plot, TPC 3. However, care should still be taken with regard to grounding and layout. REV. 0 Avoid running digital lines under the device as these will couple noise onto the die. The analog ground plane should be allowed to run under the AD7904/AD7914/AD7924 to avoid noise coupling. The power supply lines to the AD7904/ AD7914/AD7924 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals, like clocks, should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never be run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This will reduce the effects of feedthrough through the board. A microstrip technique is by far the best but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes while signals are placed on the solder side. Good decoupling is also important. All analog supplies should be decoupled with 10 µF tantalum in parallel with 0.1 µF capacitors to AGND. To achieve the best from these decoupling components, they must be placed as close as possible to the device, ideally right up against the device. The 0.1 µF capacitors should have low Effective Series Resistance (ESR) and Effective Series Inductance (ESI), such as the common ceramic types or surface mount types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. Evaluating the AD7904/AD7914/AD7924 Performance The recommended layout for the AD7904/AD7914/AD7924 is outlined in the evaluation board for the AD7904/AD7914/AD7924. The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from the PC via the EVAL-BOARD CONTROLLER. The EVAL-BOARD CONTROLLER can be used in conjunction with the AD7904/AD7914/AD7924 evaluation board, as well as many other Analog Devices evaluation boards ending in the CB designator, to demonstrate/evaluate the ac and dc performance of the AD7904/AD7914/AD7924. The software allows the user to perform ac (fast Fourier transform) and dc (histogram of codes) tests on the AD7904/AD7914/ AD7924. The software and documentation are on a CD shipped with the evaluation board. –23– AD7904/AD7914/AD7924 OUTLINE DIMENSIONS 16-Lead Thin Shrink Small Outline Package (TSSOP) (RU-16) C03087–0–11/02(0) Dimensions shown in millimeters 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 COPLANARITY 0.10 SEATING PLANE 8ⴗ 0ⴗ 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153AB PRINTED IN U.S.A. 0.65 BSC 0.30 0.19 –24– REV. 0