ETC CD74HC4017NSR96

[ /Title
(CD74
HC401
7)
/Subject
(High
Speed
CMOS
Logic
Decade
Counte
CD54/74HC4017
Data sheet acquired from Harris Semiconductor
SCHS200B
November 1997 - Revised March 2002
High Speed CMOS Logic
Decade Counter/Divider with 10 Decoded Outputs
Features
Description
• Fully Static Operation
The ’HC4017 is a high speed silicon gate CMOS 5-stage
Johnson counter with 10 decoded outputs. Each of the
decoded outputs is normally low and sequentially goes high
on the low to high transition clock period of the 10 clock
period cycle. The CARRY (TC) output transitions low to high
after OUTPUT 10 goes low, and can be used in conjunction
with the CLOCK ENABLE (CE) to cascade several stages.
The CLOCK ENABLE input disables counting when in the
high state. A RESET (MR) input is also provided which when
taken high sets all the decoded outputs, except “0”, low.
• Buffered Inputs
• Common Reset
• Positive Edge Clocking
• Typical fMAX = 50MHz at VCC = 5V, CL = 15pF, TA = 25oC
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
The device can drive up to 10 low power Schottky equivalent
loads.
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
Ordering Information
• Significant Power Reduction Compared to LSTTL
Logic ICs
TEMP. RANGE
(oC)
PACKAGE
CD54HC4017F3A
-55 to 125
16 Ld CERDIP
CD74HC4017E
-55 to 125
16 Ld PDIP
CD74HC4017NSR
-55 to 125
16 Ld SOP
PART NUMBER
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer or die for this part number is available which meets all electrical specifications. Please contact your local TI sales office or
customer service for ordering information.
Pinout
CD54HC4017
(CERDIP)
CD74HC4017
(PDIP, SOP)
TOP VIEW
5 1
16 VCC
1 2
15 MR
0 3
14 CP
2 4
13 CE
6 5
12 TC
7 6
11 9
3 7
10 4
GND 8
9 8
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 2002, Texas Instruments Incorporated
1
CD54/74HC4017
Functional Diagram
2
14
CLOCK
4
CLOCK 13
ENABLE
7
10
MASTER 15
RESET
1
5
6
9
11
12
0
1
2
3
4
5
6
7
DECODED DECIMAL OUT
3
8
9
TERMINAL
COUNT
TRUTH TABLE
CP
CE
MR
OUTPUT STATE †
L
X
L
No Change
X
H
L
No Change
X
X
H
“0” = H, “1”-”9” = L
↑
L
L
Increments Counter
↓
X
L
No Change
X
↑
L
No Change
H
↓
L
Increments Counter
NOTE:
H = High Level
L = Low Level
↑ = High to Low Transition
↓ = Low to High Transition
X = Don’t Care.
† If n < 5 TC = H, Otherwise = L
2
CD54/74HC4017
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Package Thermal Impedance, θJA (see Note 3):
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67oC/W
SOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/W
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
SYMBOL
VI (V)
IO (mA)
High Level Input
Voltage
VIH
-
-
Low Level Input
Voltage
VIL
PARAMETER
High Level Output
Voltage
CMOS Loads
VOH
-
VIH or VIL
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
VOL
VIH or VIL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
VCC
(V)
25oC
-40oC TO 85oC -55oC TO 125oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
2
1.5
-
-
1.5
-
1.5
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
6
5.9
-
-
5.9
-
5.9
-
V
-
-
-
-
-
-
-
-
-
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
-5.2
6
5.48
-
-
5.34
-
5.2
-
V
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
-
-
-
-
-
-
-
-
-
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
5.2
6
-
-
0.26
-
0.33
-
0.4
V
II
VCC or
GND
-
6
-
-
±0.1
-
±1
-
±1
µA
ICC
VCC or
GND
0
6
-
-
8
-
80
-
160
µA
NOTE: For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
3
CD54/74HC4017
Prerequisite for Switching Specifications
PARAMETER
Maximum Clock
Frequency
CP Pulse Width
MR Pulse Width
Set-up Time,
CE to CP
Hold Time,
CE to CP
MR Removal Time
SYMBOL
TEST
CONDITIONS
fMAX
-
tW
-
tW
-
tSU
-
tH
-
tREM
-
VCC
(V)
25oC
MIN
-40oC TO 85oC -55oC TO 125oC
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
2
6
-
-
5
-
4
-
MHz
4.5
30
-
-
35
-
20
-
MHz
6
35
-
-
49
-
23
-
MHz
2
80
-
-
100
-
120
-
ns
4.5
16
-
-
20
-
24
-
ns
6
14
-
-
17
-
20
-
ns
2
80
-
-
100
-
120
-
ns
4.5
16
-
-
20
-
24
-
ns
6
14
-
-
17
-
20
-
ns
2
75
-
-
95
-
110
-
ns
4.5
15
-
-
19
-
22
-
ns
6
13
-
-
16
-
19
-
ns
2
0
-
-
0
-
0
-
ns
4.5
0
-
-
0
-
0
-
ns
6
0
-
-
0
-
0
-
ns
2
5
-
-
5
-
5
-
ns
4.5
5
-
-
5
-
5
-
ns
6
5
-
-
5
-
5
-
ns
Switching Specifications Input tr, tf = 6ns
PARAMETER
Propagation Delay
CP to any Dec. Out
CP to TC
CE to any Dec. Out
CE to TC
TEST
SYMBOL CONDITIONS
tPLH,
tPHL
tPLH,
tPHL
tPLH,
tPHL
tPLH,
tPHL
-40oC TO
85oC
25oC
-55oC TO 125oC
VCC
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
CL = 50pF
2
-
-
230
-
290
-
345
ns
CL = 50pF
4.5
-
-
46
-
58
-
69
ns
CL = 15pF
5
-
19
-
-
-
-
-
ns
CL = 50pF
6
-
-
39
-
49
-
59
ns
CL = 50pF
2
-
-
230
-
290
-
345
ns
CL = 50pF
4.5
-
-
46
-
58
-
69
ns
CL = 15pF
5
-
19
-
-
-
-
-
ns
CL = 50pF
6
-
-
39
-
49
-
59
ns
-
-
250
-
315
-
375
ns
CL = 50pF
2
CL = 50pF
4.5
-
-
50
-
63
-
75
ns
CL = 15pF
5
-
21
-
-
-
-
-
ns
CL = 50pF
6
-
-
43
-
54
-
64
ns
CL = 50pF
2
-
-
250
-
315
-
375
ns
CL = 50pF
4.5
-
-
50
-
63
-
75
ns
CL = 15pF
5
-
21
-
-
-
-
-
ns
CL = 50pF
6
-
-
43
-
54
-
64
ns
4
CD54/74HC4017
Switching Specifications Input tr, tf = 6ns
(Continued)
TEST
SYMBOL CONDITIONS
-40oC TO
85oC
25oC
-55oC TO 125oC
VCC
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
CL = 50pF
2
-
-
230
-
290
-
345
ns
CL = 50pF
4.5
-
-
46
-
58
-
69
ns
CL = 15pF
5
-
19
-
-
-
-
-
ns
CL = 50pF
6
-
-
39
-
49
-
59
ns
CL = 50pF
2
-
-
230
-
290
-
345
ns
CL = 50pF
4.5
-
-
46
-
58
-
69
ns
CL = 15pF
5
-
19
-
-
-
-
-
ns
CL = 50pF
6
-
-
39
-
49
-
59
ns
CL = 50pF
2
-
-
75
-
95
-
110
ns
CL = 50pF
4.5
-
-
15
-
19
-
22
ns
CL = 50pF
6
-
-
13
-
16
-
19
ns
CIN
CL = 50pF
-
-
-
10
-
10
-
10
pF
Maximum CP Frequency
fMAX
CL = 15pF
5
-
60
-
-
-
-
-
MHz
Power Dissipation Capacitance
(Notes 4, 5)
CPD
CL = 15pF
5
-
39
-
-
-
-
-
pF
PARAMETER
MR to any Dec. Out
tPLH,
tPHL
MR to TC
tPLH,
tPHL
Transition Time TC, Dec. Out
Input Capacitance
tTLH, tTHL
NOTES:
4. CPD is used to determine the dynamic power consumption, per package.
5. PD = VCC2 fi Σ
CL VCC2 fo where fi = input frequency, fo = output frequency, CL = output load capacitance, VCC = supply voltage.
Test Circuits and Waveforms
tfCL
trCL
CLOCK
90%
10%
tWL + tWH =
tr = 6ns
I
fCL
50%
VCC
90%
50%
10%
INPUT
VCC
50%
10%
tf = 6ns
50%
GND
GND
tTHL
tWL
tTLH
tWH
90%
50%
10%
INVERTING
OUTPUT
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
tPHL
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
tPLH
FIGURE 2. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
5
CD54/74HC4017
Test Circuits and Waveforms
(Continued)
tfCL
trCL
VCC
90%
CLOCK
INPUT
50%
10%
GND
tH(H)
tH(L)
VCC
DATA
INPUT
50%
GND
tSU(H)
tSU(L)
90%
tTLH
tTHL
90%
50%
10%
tPLH
tPHL
OUTPUT
tREM
VCC
SET, RESET
OR PRESET
50%
GND
IC
CL
50pF
FIGURE 3. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED
SEQUENTIAL LOGIC CIRCUITS
Timing Diagrams
D
CL
CL
CL
P
N
P
N
CL
CL
CL
C
PN
CL
CLOCK
MASTER
RESET
CLOCK
ENABLE
“0”
“1”
“2”
Q
“3”
CL
P
N
“4”
“5”
Q
“6”
CL
0
0
1
1
2
2
3
4
5
6
“7”
7
“8”
R
8
“9”
9
TERMINAL
COUNT
FF DETAIL
FIGURE 4.
FIGURE 5.
6
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