NSC MM58342V

MM58342
High Voltage Display Driver
General Description
The MM58342 is a monolithic MOS integrated circuit utilizing
CMOS metal gate low threshold P- and N-channel devices. It
is available both in 28-pin molded dual-in-line packages or
as dice. The MM58342 is particularly suited for driving high
voltage (35V max) vacuum fluorescent (VF) displays (e.g., a
20-digit alphanumeric or dot matrix display).
Applications
n
n
n
n
COPS™ or microprocessor-driven displays
Instrumentation readouts
Industrial control indicator
Digital clock, thermostat, counter, voltmeter
n Word processor text displays
n Automotive dashboards
Features
n
n
n
n
n
n
n
n
n
Direct interface to high voltage display
Serial data input
No external resistors required
Wide display power supply operation
LSTTL compatible inputs
Software compatible with NS display driver family
Compatible with alphanumeric or dot matrix displays
Display blanking control input
Simple to cascade
Block Diagram
00792501
FIGURE 1.
© 2001 National Semiconductor Corporation
DS007925
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MM58342 High Voltage Display Driver
February 1995
MM58342
Absolute Maximum Ratings
Molded DIP Package, Socket Mount
(Note 1)
1.83W (Note 3)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Junction Temperature
130˚C
Lead Temperature (Soldering, 10 sec.)
260˚C
Voltage at Any Input Pin
Operating Conditions
Voltage at Any Display Pin
VDD + 0.3V to
VSS −0.3V
VDD to VDD −36.5V
VDD + |VDIS|
Electrical Characteristics
Symbol
Units
VSS = 0V
4.5
5.5
V
Display Voltage (VDIS)
−30
−10
V
Temperature Range
−40
+85
˚C
−65˚C to +150˚C
Power Dissipation at 25˚C
Molded DIP Package, Board Mount
Max
Supply Voltage (VDD)
36.5V
Storage Temperature
Min
2.03W (Note 2)
TA = −40˚C to +85˚C, VDD = 5V ± 0.5V, VSS = 0V unless otherwise specified
Parameter
Conditions
Min
Typ
Max
Units
Power Supply Currents
IDD
VIN = VSS or VDD, VSS = 0V,
VDIS Disconnected
150
µA
IDIS
VDD = 5.5V, VSS = 0V, VDIS = −30V
All Outputs Low
10
mA
Input Logic Levels
DATA IN, CLOCK
ENABLE, BLANK
VIL
Logic “0”
VIH
Logic “1”
0.8
(Note 4)
2.4
V
V
Data Output Logic Levels
VOL
Logic “0”
IOUT = 400 µA
VOH
Logic “1”
IOUT = −10 µA
VDD −0.5
V
2.8
V
0.4
VOH
Logic “1”
IOUT = −500 µA
IIN
Input Currents DATA IN,
CLOCK ENABLE, BLANK
VIN = 0V or VDD
CIN
Input Capacitance DATA IN,
CLOCK ENABLE, BLANK
ROFF
RON
VDOL
−10
V
10
µA
15
pF
Display Output Impedances
VDD = 5.5V, VSS = 0V
Output Off (Figure 3)
VDIS = −10V
55
250
kΩ
VDIS = −20V
60
300
kΩ
VDIS = −30V
65
400
kΩ
Output On (Figure 4)
Display Output Low Voltage
VDIS = −10V
700
800
Ω
VDIS = −20V
600
750
Ω
VDIS = −30V
500
680
Ω
VDIS + 2
V
Max
Units
800
kHz
VDD = 5.5V, IOUT = Open Circuit,
−30V ≤ VDIS ≤ −10V
AC Electrical Characteristics
Symbol
TA = −40˚C to +85˚C, VDD = 5V ± 0.5V
Parameter
Clock Input
VDIS
Conditions
Min
Typ
(Notes 6, 7)
fC
Frequency
tH
High Time
300
ns
Low Time
300
ns
tL
Data Input
tDS
Set-Up Time
100
ns
tDH
Hold Time
100
ns
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2
Symbol
TA = −40˚C to +85˚C, VDD = 5V ± 0.5V (Continued)
Parameter
Enable Input
Conditions
Min
Typ
Max
Units
(Note 5)
tES
Set-Up Time
100
ns
tEH
Hold Time
100
ns
Data Output
tCDO
CL = 50 pF
500
Clock Low to Data Out
Time
ns
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2: Molded DIP Package, Board Mount, θJA = 52˚C/W, derate 19.2 mW/˚C above 25˚C.
Note 3: Molded DIP Package, Socket Mount, θJA = 58˚C/W, derate 17.2 mW/˚C above 25˚C.
Note 4: 74LSTTL VOH = 2.7V @ IOUT = −400 µA, TTL VOH = 2.4V @ IOUT = −400 µA.
Note 5: For timing purposes, the signals ENABLE and BLANK can be considered to be totally independent of each other.
Note 6: AC input waveform specification for test purposes: tr, tf ≤ 20 ns, f = 800 kHz, 50% ± 10% duty cycle.
Note 7: Clock input rise and fall times must not exceed 5 µs.
Connection Diagrams
Plastic Chip Carrier
Dual-In-Line Package
00792508
Top View
Order Number MM58342V
See NS Package Number V28B
00792502
Top View
Order Number MM58342N
See NS Package Number N28B
Functional Description
This product is specifically designed to drive multiplexed or
non-multiplexed high voltage alphanumeric or dot matrix
vacuum fluorescent (VF) displays. Character generation is
done externally in the microprocessor, with a serial data path
to the display driver. The MM58342 uses three signals,
DATA IN, CLOCK and ENABLE, where ENABLE acts as an
external load signal. Display blanking can be achieved by
means of the BLANKING CONTROL input, and a logic “1”
will turn off all sections of the display. A block diagram of the
MM58342 is shown in Figure 1.
FIGURE 2.
Figure 2 shows the pinout of the MM58342 device, where
output 1 (pin 12) is equivalent to bit 1 (i.e., the first bit of data
to be loaded into the shift register following ENABLE high). A
logic “1” at the input will turn on the corresponding display
digit/segment/dot output.
A significant reduction in discrete board components can be
achieved by use of the MM58342, because external
3
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MM58342
AC Electrical Characteristics
MM58342
Functional Description
CLOCK input signals. Data is transferred and shifted in the
internal shift register on the rising clock edge, i.e., “0”–“1”
transition. When the ENABLE signal goes low, the contents
of the shift registers are latched, and the display will show
new data. During data transfer, the display will show old
data. DATA OUT is also provided on the MM58342 being
output on the falling edge. At any time, the display may be
blanked under processor control, using the BLANKING
CONTROL input.
(Continued)
pull-down resistors are not required. Due to the nature of the
output stage, both its on and off impedance values vary as a
function of the display voltage applied. However, Figures 3, 4
show that this output impedance will remain constant for a
fixed value of display voltage.
Figure 5 demonstrates the critical timing requirements between CLOCK and DATA IN for the MM58342.
To clear (reset) the display driver at power on or any time,
the following flushing routine may be used. With the enable
signal high, clock in 20 zeroes. Drive the enable signal low
and the display will be blank. It is recommended to clear the
driver at power on.
In Figure 6, the ENABLE signal acts as an envelope, and
only while this signal is at a logic “1” does the circuit accept
Figure 7 shows a schematic diagram of a
microprocessor-based system where the MM58342 is used
to provide the grid drive for a 40-digit 2 line 5 x 7 multiplexed
vacuum fluorescent (VF) display. The anode drive in this
example is provided by another member of the high voltage
display driver family, namely the MM58348, which does not
require an extremely generated load signal.
00792503
FIGURE 3. Output Impedance Off
00792504
FIGURE 4. Output Impedance On
Timing Diagrams
00792505
FIGURE 5. Clock and Data Timings
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4
MM58342
Timing Diagrams
(Continued)
00792506
FIGURE 6. Timings (Data Format)
Typical Application
00792507
FIGURE 7. Microprocessor-Controlled Word Processor
5
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MM58342
Physical Dimensions
inches (millimeters) unless otherwise noted
Molded Dual-In-Line Package (N)
Order Number MM58342N
NS Package Number N28B
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6
MM58342 High Voltage Display Driver
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
Plastic Chip Carrier (V)
Order Number MM58342V
NS Package Number V28A
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