DDU8C data 3 delay devices, inc. 5-TAP, HCMOS-INTERFACED FIXED DELAY LINE (SERIES DDU8C) FEATURES • • • • • • PACKAGES Five equally spaced outputs Fits standard 8-pin DIP socket Low profile Auto-insertable Input & outputs fully CMOS interfaced & buffered 10 T2L fan-out capability IN 1 8 VDD T2 2 7 T1 T4 3 6 T3 GND 4 5 T5 DDU8C-xx DDU8C-xxA1 DDU8C-xxB1 DDU8C-xxM IN N/C N/C T2 N/C T4 GND DIP Gull-Wing J-Lead Military DIP 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD N/C T1 N/C T3 N/C T5 Military SMD DDU8C-xxMD1 DDU8C-xxMD4 FUNCTIONAL DESCRIPTION PIN DESCRIPTIONS The DDU8C-series device is a 5-tap digitally buffered delay line. The signal input (IN) is reproduced at the outputs (T1-T5), shifted in time by an amount determined by the device dash number (See Table). The total delay of the line is measured from IN to T5. The nominal tap-to-tap delay increment is given by one-fifth of the total delay. IN T1-T5 VDD GND Signal Input Tap Outputs +5 Volts Ground SERIES SPECIFICATIONS DASH NUMBER SPECIFICATIONS • • • • Part Number DDU8C-5050 DDU8C-5060 DDU8C-5075 DDU8C-5100 DDU8C-5125 DDU8C-5150 DDU8C-5175 DDU8C-5200 DDU8C-5250 • • Minimum input pulse width: 40% of total delay Output rise time: 8ns typical Supply voltage: 5VDC ± 5% Supply current: ICCL = 40µa typical ICCH = 10ma typical Operating temperature: 0° to 70° C Temp. coefficient of total delay: 300 PPM/°C Total Delay (ns) 50 ± 2.5 60 ± 3.0 75 ± 4.0 100 ± 5.0 125 ± 6.5 150 ± 7.5 175 ± 8.0 200 ± 10.0 250 ± 12.5 Delay Per Tap (ns) 10.0 ± 3.0 12.0 ± 3.0 15.0 ± 3.0 20.0 ± 3.0 25.0 ± 3.0 30.0 ± 3.0 35.0 ± 4.0 40.0 ± 4.0 50.0 ± 5.0 NOTE: Any dash number between 5004 and 5250 not shown is also available. 20% VDD IN 20% T1 20% T2 20% T3 20% T4 T5 GND DDU8C Functional diagram 1997 Data Delay Devices Doc #97013 1/28/97 Powered by ICminer.com Electronic-Library Service CopyRight 2003 DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 1 DDU8C APPLICATION NOTES Delay Devices if your application requires device testing at a specific input condition. HIGH FREQUENCY RESPONSE The DDU8C tolerances are guaranteed for input pulse widths and periods greater than those specified in the test conditions. Although the device will function properly for pulse widths as small as 40% of the total delay and periods as small as 80% of the total delay (for a symmetric input), the delays may deviate from their values at low frequency. However, for a given input condition, the deviation will be repeatable from pulse to pulse. Contact technical support at Data POWER SUPPLY BYPASSING The DDU8C relies on a stable power supply to produce repeatable delays within the stated tolerances. A 0.1uf capacitor from VDD to GND, located as close as possible to the VDD pin, is recommended. A wide VDD trace and a clean ground plane should be used. DEVICE SPECIFICATIONS TABLE 1: ABSOLUTE MAXIMUM RATINGS PARAMETER DC Supply Voltage Input Pin Voltage Storage Temperature Lead Temperature SYMBOL VDD VIN TSTRG TLEAD MIN -0.3 -0.3 -55 MAX 7.0 VDD+0.3 150 300 UNITS V V C C NOTES 10 sec TABLE 2: DC ELECTRICAL CHARACTERISTICS (0C to 70C, 4.75V to 5.25V) PARAMETER High Level Output Voltage SYMBOL VOH Low Level Output Voltage VOL High Level Output Current Low Level Output Current High Level Input Voltage Low Level Input Voltage Input Current IOH IOL VIH VIL IIH Doc #97013 Powered 1/28/97 by ICminer.com MIN 3.98 TYP 4.4 MAX UNITS V 0.15 0.26 V -4.0 4.0 mA mA V V µA 3.15 1.35 0.10 NOTES VDD = 5.0, IOH = MAX VIH = MIN, VIL = MAX VDD = 5.0, IOL = MAX VIH = MIN, VIL = MAX VDD = 5.0 DATA DELAY DEVICES, INC. Tel: 973-773-2299 Fax: 973-773-9672 Electronic-Library Service CopyRight 2003 http://www.datadelay.com 2 DDU8C PACKAGE DIMENSIONS 8 7 6 5 Lead Material: Nickel-Iron alloy 42 TIN PLATE 8 1 2 3 7 6 5 .440 MAX. 4 .280 MAX. .500 MAX. 1 2 3 4 .500 MAX. .290 MAX. .020 .290 TYP. MAX. .015 TYP. .010±.002 .018 TYP. .070 MAX. .180 TYP. .350 MAX. .300±.010 3 Equal spaces each .100±.010 Non-Accumulative .300 TYP. .040 TYP. 8 7 6 .010 TYP. .020 TYP. 5 2 3 7 6 .300 MAX. .050 TYP. DDU8C-xxA1 (Commercial Gull-Wing) .320 TYP. .270 TYP. 1 .110 .050 TYP. 5 .430 TYP. 4 .100 .300 .520 MAX. .040 TYP. 8 .270 TYP. 1 .300 TYP. DDU8C-xxM (Military DIP) DDU8C-xx (Commercial DIP) .020 TYP. .010 TYP. .020 TYP. 2 3 4 .100 .300 .520 MAX. .110 .350 MAX. .110 TYP. DDU8C-xxB1 (Commercial J-Lead) .650 .100 1 .100 .017 14 1 .510 MAX. .300 TYP. 7 .510 MAX. .300 .200 MAX. (Com) .225 MAX. (Mil) .065 TYP. .008 .065 TYP. DDU8C-xxD1 (Commercial SMD) DDU8C-xxMD1 (Military SMD) Doc #97013 1/28/97 Powered by ICminer.com Electronic-Library Service CopyRight 2003 8 .050 .510 MAX. .080 .025 .360 TYP. .510 MAX. .100 .050 .045 .017 .300 TYP. 7 8 .100 .300 14 .200 MAX. (Com) .225 MAX. (Mil) .005 .080 .008 .360 TYP. .065 TYP. .065 TYP. DDU8C-xxD4 (Commercial SMD) DDU8C-xxMD4 (Military SMD) DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 3 DDU8C DELAY LINE AUTOMATED TESTING TEST CONDITIONS INPUT: Ambient Temperature: 25oC ± 3oC Supply Voltage (VDD): 5.0V ± 0.1V Input Pulse: High = 5.0V ± 0.1V Low = 0.0V ± 0.1V Source Impedance: 50Ω Max. Rise/Fall Time: 5.0 ns Max. (measured between 0.5V and 4.5V ) Pulse Width: PWIN = 1.5 x Total Delay Period: PERIN = 10 x Total Delay OUTPUT: Load: Cload: Threshold: 1 FAST-TTL Gate 5pf ± 10% 2.5V (Rising & Falling) NOTE: The above conditions are for test only and do not in any way restrict the operation of the device. PRINTER COMPUTER SYSTEM REF PULSE GENERATOR OUT IN TRIG DEVICE UNDER TEST (DUT) T1 IN T2 TRIG TIME INTERVAL COUNTER T3 T4 T5 Test Setup PERIN PWIN TRISE INPUT SIGNAL TFALL VIH 4.5V 2.5V 0.5V 4.5V 2.5V 0.5V TRISE OUTPUT SIGNAL VIL TFALL VOH 2.5V 2.5V VOL Timing Diagram For Testing Doc #97013 Powered 1/28/97 by ICminer.com DATA DELAY DEVICES, INC. Tel: 973-773-2299 Fax: 973-773-9672 Electronic-Library Service CopyRight 2003 http://www.datadelay.com 4