Single Channel, 12-/16-Bit, Serial Input, Current Source and Voltage Output DACs AD5412/AD5422 FEATURES GENERAL DESCRIPTION 12-/16-bit resolution and monotonicity Current output ranges: 4 mA to 20 mA, 0 mA to 20 mA, 0 mA to 24 mA ±0.01 % FSR typical total unadjusted error (TUE) ±3 ppm/°C output drift Voltage output ranges: 0 V to 5 V, 0 V to 10 V, ±5 V, ±10 V 10% overrange ±0.01 % FSR typical total unadjusted error (TUE) ±2 ppm/°C output drift Flexible serial digital interface On-chip output fault detection On-chip reference: 10 ppm/°C maximum Asynchronous clear function Power supply range AVDD: 10.8 V to 40 V AVSS: −26.4 V to −3 V/0 V Output loop compliance: AVDD – 2.5 V Temperature range: −40°C to +85°C TSSOP and LFCSP packages The AD5412/AD5422 are low-cost, precision, fully integrated 12-/16-bit digital-to-analog converters (DAC) offering a programmable current source and programmable voltage output designed to meet the requirements of industrial process control applications. APPLICATIONS Process control Actuator control PLC The output current range is programmable at 4 mA to 20 mA, 0 mA to 20 mA, or an overrange function of 0 mA to 24 mA. Voltage output is provided from a separate pin that can be configured to provide 0 V to 5 V, 0 V to 10 V, ±5 V, or ±10 V output ranges; an overrange of 10% is available on all ranges. Analog outputs are short and open-circuit protected and can drive capacitive loads of 1 μF. The device operates with an AVDD power supply range from 10.8 V to 40 V. Output loop compliance is 0 V to AVDD – 2.5 V. The flexible serial interface is SPI- and MICROWIRE™compatible and can be operated in 3-wire mode to minimize the digital isolation required in isolated applications. The device also includes a power-on-reset function, ensuring that the device powers up in a known state. The part also includes an asynchronous clear pin (CLEAR) that sets the outputs to zero-scale/midscale voltage output or the low end of the selected current range. The total output error is typically ±0.01% in current mode and ±0.01% in voltage mode. Table 1. Pin-Compatible Devices Part Number AD5410 AD5420 Description Single channel, 12-bit, serial input current source DAC Single channel, 16-bit, serial input current source DAC Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. AD5412/AD5422 TABLE OF CONTENTS Features .............................................................................................. 1 AD5412/AD5422 Features ............................................................ 31 Applications ....................................................................................... 1 Fault Alert.................................................................................... 31 General Description ......................................................................... 1 Voltage Output Short Circuit Protection ................................ 31 Revision History ............................................................................... 2 Voltage Output Overrange ........................................................ 31 Functional Block Diagram .............................................................. 3 Voltage Output Force-Sense ..................................................... 31 Specifications..................................................................................... 4 Asynchronous Clear (CLEAR) ................................................. 31 AC Performance Characteristics ................................................ 7 Internal Reference ...................................................................... 31 Timing Characteristics ................................................................ 8 External Current Setting Resistor ............................................ 31 Absolute Maximum Ratings.......................................................... 10 Digital Power Supply.................................................................. 32 ESD Caution ................................................................................ 10 External Boost Function ........................................................... 32 Pin Configurations and Function Descriptions ......................... 11 External Compensation Capacitor........................................... 32 Typical Performance Characteristics ........................................... 13 Digital Slew Rate Control .......................................................... 32 General ......................................................................................... 13 IOUT Filtering Capacitors (LFCSP Package) ............................. 33 Voltage Output ............................................................................ 15 Applications Information .............................................................. 35 Current Output ........................................................................... 20 Driving Inductive Loads ............................................................ 35 Terminology .................................................................................... 24 Transient Voltage Protection .................................................... 35 Theory of Operation ...................................................................... 26 Galvanically Isolated Interface ................................................. 35 Architecture................................................................................. 26 Microprocessor Interfacing ....................................................... 35 Serial Interface ............................................................................ 27 Layout Guidelines....................................................................... 35 Power-On State ........................................................................... 28 Thermal and Supply Considerations ....................................... 36 Data Register ............................................................................... 29 Industrial Analog Output Module ........................................... 37 Control Register .......................................................................... 29 Outline Dimensions ....................................................................... 38 Reset Register .............................................................................. 30 Ordering Guide .......................................................................... 39 Status Register ............................................................................. 30 REVISION HISTORY 8/09—Rev. 0 to Rev. A Changes to Table 2 ............................................................................ 4 Changes to Table 3 ............................................................................ 7 Changes to Introduction to Table 4................................................ 8 Changes to Introduction to Table 5 and to Table 5 .................... 10 Changes to Pin Configurations and Function Descriptions Section, Added Figure 6, Renumbered Subsequent Figures ..... 11 Changes to Theory of Operation Section .................................... 26 Changes to Architecture Section .................................................. 26 Changes to AD5412/AD5422 Features Section ......................... 31 Added IOUT Filtering Capacitors (LFCSP Package)Section, Including Figure 69 to Figure 72 and Table 24 ........................... 33 Changes to Thermal and Supply Considerations Section......... 36 Updated Outline Dimensions ....................................................... 38 Changes to Ordering Guide .......................................................... 39 5/09—Revision 0: Initial Version Rev. A | Page 2 of 40 AD5412/AD5422 FUNCTIONAL BLOCK DIAGRAM DVCC SELECT AD5412/AD5422 AVDD R2 R3 BOOST CLEAR LATCH SCLK SDIN SDO INPUT SHIFT REGISTER AND CONTROL LOGIC 12/16 12-/16-BIT DAC IOUT FAULT RSET POWER-ON RESET RSET VREF +VSENSE RANGE SCALING VOUT –VSENSE REFOUT GND REFIN Figure 1. Rev. A | Page 3 of 40 CCOMP 06996-001 CLEAR SELECT AVSS DVCC AD5412/AD5422 SPECIFICATIONS AVDD = 10.8 V to 26.4 V, AVSS = −26.4 V to −3 V/0 V, AVDD + |AVSS| < 52.8 V, GND = 0 V, REFIN = 5 V external; DVCC = 2.7 V to 5.5 V. VOUT: RLOAD = 1 kΩ, CL = 200 pF, IOUT: RLOAD = 350 Ω; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter 1 VOLTAGE OUTPUT Output Voltage Ranges Accuracy Resolution Total Unadjusted Error (TUE) B Version A Version Relative Accuracy (INL) 2 Differential Nonlinearity (DNL) Bipolar Zero Error Bipolar Zero Error Temperature Coefficient (TC) 3 Zero-Scale Error Zero-Scale Error Temperature Coefficient (TC)3 Offset Error Offset Error Temperature Coefficient (TC)3 Gain Error Gain Error Temperature Coefficient (TC)3 Full-Scale Error Full-Scale Error Temperature Coefficient (TC)3 OUTPUT CHARACTERISTICS3 Headroom Output Voltage Drift vs. Time Short-Circuit Current Load Capacitive Load Stability RLOAD = ∞ RLOAD = 1 kΩ RLOAD = ∞ DC Output Impedance Power-On Time Min Typ 0 0 −5 −10 Max Unit 5 10 +5 +10 V V V V 16 12 −0.1 −0.05 −0.3 −0.1 −0.008 −0.032 −1 −6 −1.5 −5 −3.5 −4 −1.5 −0.07 −0.05 −0.07 −0.05 Bits Bits ±0.01 ±0.05 ±0.2 ±3 ±0.3 ±2 ±0.2 ±2 ±0.004 ±1 ±0.001 ±1 0.5 90 20 Test Conditions/Comments Output unloaded AD5422 AD5412 +0.1 +0.05 +0.3 +0.1 +0.008 +0.032 +1 +6 +1.5 % FSR % FSR % FSR % FSR % FSR % FSR LSB mV mV ppm FSR/°C +5 +3.5 mV mV ppm FSR/°C TA = 25°C +4 +1.5 mV mV ppm FSR/°C Unipolar output range TA = 25°C, unipolar output range Unipolar output range +0.07 +0.05 % FSR % FSR ppm FSR/°C TA = 25°C +0.07 +0.05 % FSR % FSR ppm FSR/°C TA = 25°C 0.8 V ppm FSR mA kΩ 20 5 1 nF nF μF 1 TA = 25°C TA = 25°C AD5422 AD5412 Guaranteed monotonic Bipolar output range TA = 25°C, bipolar output range Bipolar output range Output unloaded Drift after 1000 hours, TA = 125°C TA = 25°C 0.3 10 Ω μs Rev. A | Page 4 of 40 External compensation capacitor of 4 nF connected AD5412/AD5422 Parameter 1 DC PSRR Min CURRENT OUTPUT Output Current Ranges 0 0 4 Accuracy (Internal RSET) Resolution Max 130 12 Unit μV/V μV/V 24 20 20 mA mA mA 16 12 Total Unadjusted Error (TUE) B Version −0.3 −0.13 −0.5 −0.3 −0.024 −0.032 −1 −0.27 −0.12 A Version Relative Accuracy (INL) Typ 90 3 4 Differential Nonlinearity (DNL) Offset Error Offset Error Temperature Coefficient (TC)3 Gain Error −0.18 −0.03 −0.22 −0.06 3 Gain Temperature Coefficient (TC) Full-Scale Error Full-Scale Temperature Coefficient (TC)3 Accuracy (External RSET) Resolution Total Unadjusted Error (TUE) B Version A Version Relative Accuracy (INL)4 Differential Nonlinearity (DNL) Offset Error Offset Error Temperature Coefficient (TC)3 Gain Error Gain Temperature Coefficient (TC)3 Full-Scale Error Full-Scale Temperature Coefficient (TC)3 −0.2 −0.1 Bits Bits ±0.08 ±0.15 ±0.08 ±16 ±0.006 ±0.006 ±10 +0.3 +0.13 +0.5 +0.3 +0.024 +0.032 +1 +0.27 +0.12 % FSR % FSR % FSR % FSR % FSR % FSR LSB % FSR % FSR ppm FSR/°C +0.18 +0.03 +0.22 +0.06 % FSR % FSR % FSR % FSR ppm FSR/°C % FSR % FSR ppm FSR/°C +0.2 +0.1 ±0.08 ±6 16 12 −0.15 −0.06 −0.3 −0.1 −0.012 −0.032 −1 −0.1 −0.03 −0.08 −0.05 −0.15 −0.06 Bits Bits ±0.01 ±0.02 ±0.006 ±3 ±0.003 ±4 ±0.01 ±7 +0.15 +0.06 +0.3 +0.1 +0.012 +0.032 +1 +0.1 +0.03 % FSR % FSR % FSR % FSR % FSR % FSR LSB % FSR Test Conditions/Comments Output unloaded AD5422 AD5412 TA = 25°C TA = 25°C AD5422 AD5412 Guaranteed monotonic TA = 25°C AD5422 AD5422, TA = 25°C AD5412 AD5412, TA = 25°C TA = 25°C AD5422 AD5412 TA = 25°C TA = 25°C AD5422 AD5412 Guaranteed monotonic TA = 25°C μA/°C +0.08 +0.05 +0.15 +0.06 % FSR % FSR ppm FSR/°C % FSR % FSR ppm FSR/°C Rev. A | Page 5 of 40 TA = 25°C TA = 25°C AD5412/AD5422 Parameter 1 OUTPUT CHARACTERISTICS3 Current Loop Compliance Voltage Output Current Drift vs. Time Min Typ 0 Max Unit AVDD − 2.5 V 50 20 Resistive Load Inductive Load DC PSRR Output Impedance Output Current Leakage When Output Is Disabled REFERENCE INPUT/OUTPUT Reference Input3 Reference Input Voltage DC Input Impedance Reference Output Output Voltage Reference Temperature Coefficient (TC)3, 5 Output Noise (0.1 Hz to 10 Hz)3 Noise Spectral Density3 Output Voltage Drift vs. Time3 Capacitive Load3 Load Current3 Short-Circuit Current3 Load Regulation3 DIGITAL INPUTS3 Input High Voltage, VIH Input Low Voltage, VIL Input Current Pin Capacitance DIGITAL OUTPUTS3 SDO Output Low Voltage, VOL Output High Voltage, VOH High Impedance Leakage Current High Impedance Output Capacitance FAULT Output Low Voltage, VOL Output Low Voltage, VOL Output High Voltage, VOH POWER REQUIREMENTS AVDD AVSS |AVSS| + AVDD DVCC Input Voltage Output Voltage Output Load Current3 Short-Circuit Current3 1200 50 1 50 60 4.95 27 5 40 5.05 4.995 5 1.8 5.005 10 ppm FSR ppm FSR Ω mH μA/V MΩ pA V kΩ Test Conditions/Comments Drift after 1000 hours, TA = 125°C Internal RSET External RSET TA = 25 °C For specified performance TA = 25°C ppm/°C 10 100 50 600 5 7 95 μV p-p nV/√Hz ppm nF mA mA ppm/mA 10 V V μA pF At 10 kHz Drift after 1000 hours, TA = 125°C JEDEC compliant 2 0.8 +1 −1 0.4 DVCC − 0.5 −1 V V μA pF Sinking 200 μA Sourcing 200 μA 0.4 V V V 10 kΩ pull-up resistor to DVCC At 2.5 mA 10 kΩ pull-up resistor to DVCC 40 0 52.8 V V V 5.5 V V mA mA +1 5 0.6 3.6 10.8 −26.4 10.8 2.7 4.5 5 20 Per pin Per pin Rev. A | Page 6 of 40 Internal supply disabled DVCC, which can be overdriven up to 5.5 V AD5412/AD5422 Parameter 1 AIDD Min Typ Max Unit 2.5 3.4 3.9 3 4 4.4 mA mA mA 0.24 0.5 1.1 0.3 0.6 1.4 1 mA mA mA mA mW mW AISS DICC Power Dissipation 128 120 Test Conditions/Comments Outputs unloaded Outputs disabled Current output enabled Voltage output enabled Outputs unloaded Outputs disabled Current output enabled Voltage output enabled VIH = DVCC, VIL = GND AVDD = 40 V, AVSS = 0 V, outputs unloaded AVDD = +24 V, AVSS = −24 V, outputs unloaded 1 Temperature range: −40°C to +85°C; typical at +25°C. When the AD5412/AD5422 is powered with AVSS = 0 V, INL for the 0 V to 5 V and 0 V to 10 V ranges is measured beginning from Code 256 for the AD5422 and Code 16 for the AD5412. 3 Guaranteed by design and characterization; not production tested. 4 For 0 mA to 20 mA and 0 mA to 24 mA ranges, INL is measured beginning from Code 256 for the AD5422 and Code 16 for the AD5412. 5 The on-chip reference is production trimmed and tested at 25°C and 85°C. It is characterized from −40°C to +85°C. 2 AC PERFORMANCE CHARACTERISTICS AVDD = 10.8 V to 26.4 V, AVSS = −26.4 V to −3 V/0 V, AVDD + |AVSS| < 52.8 V, GND = 0 V, REFIN = +5 V external; DVCC = 2.7 V to 5.5 V. VOUT: RLOAD = 1 kΩ, CL = 200 pF, IOUT: RLOAD = 350 Ω; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter 1 DYNAMIC PERFORMANCE Voltage Output Output Voltage Settling Time Min Typ Max Unit Test Conditions/Comments 25 8 0.8 10 10 20 1 0.1 μs μs μs μs V/μs nV-sec nV-sec mV nV-sec LSB p-p 10 V step to ±0.03 % FSR 20 V step to ±0.03 % FSR 5 V step to ±0.03 % FSR 512 LSB step to ±0.03 % FSR (16-Bit LSB) 200 1 150 −75 μV rms kHz nV/√Hz dB 10 40 −75 μs μs dB 32 18 Slew Rate Power-On Glitch Energy Digital-to-Analog Glitch Energy Glitch Impulse Peak Amplitude Digital Feedthrough Output Noise (0.1 Hz to 10 Hz Bandwidth) Output Noise (100 kHz Bandwidth) 1/f Corner Frequency Output Noise Spectral Density AC PSRR Current Output Output Current Settling Time AC PSRR 1 Guaranteed by characterization, not production tested. Rev. A | Page 7 of 40 16-bit LSB Measured at 10 kHz, midscale output, 10 V range 200 mV 50 Hz/60 Hz sine wave superimposed on power supply voltage 16 mA step to 0.1% FSR 16 mA step to 0.1% FSR, L = 1 mH 200 mV 50 Hz/60 Hz sine wave superimposed on power supply voltage AD5412/AD5422 TIMING CHARACTERISTICS AVDD = 10.8 V to 26.4 V, AVSS = −26.4 V to −3 V/0 V, AVDD + |AVSS| < 52.8V, GND = 0 V, REFIN = +5 V external; DVCC = 2.7 V to 5.5 V. VOUT: RLOAD = 1 kΩ, CL = 200 pF, IOUT: RLOAD = 300 Ω; all specifications TMIN to TMAX, unless otherwise noted. Table 4. Parameter 1, 2, 3 WRITE MODE t1 t2 t3 t4 t5 t5 t6 t7 t8 t9 t10 READBACK MODE t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 DAISY-CHAIN MODE t21 t22 t23 t24 t25 t26 t27 t28 t29 Limit at TMIN, TMAX Unit Description 33 13 13 13 40 5 5 5 40 20 5 ns min ns min ns min ns min ns min μs min ns min ns min ns min ns min μs max SCLK cycle time SCLK low time SCLK high time LATCH delay time LATCH high time LATCH high time (after a write to the control register) Data setup time Data hold time LATCH low time CLEAR pulse width CLEAR activation time 90 40 40 13 40 5 5 40 35 35 ns min ns min ns min ns min ns min ns min ns min ns min ns max ns max SCLK cycle time SCLK low time SCLK high time LATCH delay time LATCH high time Data setup time Data hold time LATCH low time Serial output delay time (CL SDO 4 = 15 pF) LATCH rising edge to SDO tristate (CL SDO4 = 15 pF) 90 40 40 13 40 5 5 40 35 ns min ns min ns min ns min ns min ns min ns min ns min ns max SCLK cycle time SCLK low time SCLK high time LATCH delay time LATCH high time Data setup time Data hold time LATCH low time Serial output delay time (CL SDO4 = 15 pF) 1 Guaranteed by characterization; not production tested. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V. 3 See Figure 2, Figure 3, and Figure 4. 4 CL SDO = capacitive load on SDO output. 2 Rev. A | Page 8 of 40 AD5412/AD5422 t1 SCLK 1 2 24 t2 t3 t4 t5 LATCH t7 t6 SDIN t8 DB23 DB0 t9 CLEAR t10 06996-002 IOUT/VOUT Figure 2. Write Mode Timing Diagram t11 SCLK 1 1 24 2 t12 t13 t14 2 8 22 9 24 23 t15 LATCH t17 SDIN t18 DB23 DB0 DB23 DB0 NOP CONDITION INPUT WORD SPECIFIES REGISTER TO BE READ SDO X X X X DB15 DB0 FIRST 8 BITS ARE DON’T CARE BITS UNDEFINED DATA t20 t19 06996-003 t16 SELECTED REGISTER DATA CLOCKED OUT Figure 3. Readback Mode Timing Diagram t21 SCLK 1 2 25 24 26 48 t22 t23 t24 t25 LATCH SDIN DB23 DB0 INPUT WORD FOR DAC N SDO DB23 DB23 t29 DB0 t27 t28 DB0 INPUT WORD FOR DAC N – 1 DB0 DB23 UNDEFINED INPUT WORD FOR DAC N Figure 4. Daisy-Chain Mode Timing Diagram Rev. A | Page 9 of 40 t20 06996-004 t26 AD5412/AD5422 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Transient currents of up to 80 mA do not cause SCR latch-up. Table 5. Parameter AVDD to GND AVSS to GND AVDD to AVSS DVCC to GND Digital Inputs to GND Digital Outputs to GND REFIN/REFOUT to GND VOUT to GND IOUT to GND Operating Temperature Range (TA) Industrial1 Storage Temperature Range Junction Temperature (TJ max) 24-Lead TSSOP Package θJA Thermal Impedance 40-Lead LFCSP Package θJA Thermal Impedance Power Dissipation Lead Temperature Soldering ESD (Human Body Model) 1 Rating −0.3 V to +48 V +0.3 V to −48 V −0.3 V to +60 V −0.3 V to +7 V −0.3 V to DVCC + 0.3 V or 7 V (whichever is less) −0.3 V to DVCC + 0.3 V or 7 V (whichever is less) −0.3 V to +7 V AVSS to AVDD −0.3 V to AVDD Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION −40°C to +85°C −65°C to +150°C 125°C 42°C/W 28°C/W (TJ max – TA)/θJA JEDEC industry standard J-STD-020 2 kV Power dissipated on chip must be derated to keep the junction temperature below 125°C, assuming that the maximum power dissipation condition is sourcing 24 mA into GND from IOUT with a 4 mA on-chip current. Rev. A | Page 10 of 40 AD5412/AD5422 NC DVCC NC AVSS AVDD NC –VSENSE +VSENSE VOUT NC PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 24 AVDD 23 –VSENSE FAULT 3 22 +VSENSE 21 VOUT 20 BOOST 19 IOUT 18 NC SCLK 8 17 CCOMP SDIN 9 16 DVCC SELECT SDO 10 15 REFIN GND 11 14 REFOUT GND 12 13 RSET 7 AD5412/AD5422 TOP VIEW (Not to Scale) 30 29 28 27 26 25 24 23 22 21 NC CAP2 CAP1 BOOST IOUT NC CCOMP DVCC SELECT NC NC 06996-006 LATCH TOP VIEW (Not to Scale) PIN 1 INDICATOR 11 12 13 14 15 16 17 18 19 20 CLEAR 6 NC 1 FAULT 2 GND 3 CLEAR SELECT 4 CLEAR 5 LATCH 6 SCLK 7 SDIN 8 SDO 9 NC 10 NC GND GND AVSS GND RSET REFOUT REFIN NC NC CLEAR SELECT 5 AD5412/ AD5422 06996-005 GND 4 40 39 38 37 36 35 34 33 32 31 AVSS 1 DVCC 2 NOTES 1. NC = NO CONNECT 2. THE PADDLE CAN BE CONNECTED TO 0V IF THE OUTPUT VOLTAGE RANGE IS UNIPOLAR. THE PADDLE CAN BE LEFT ELECTRICALLY UNCONNECTED PROVIDED THAT A SUPPLY CONNECTION IS MADE AT THE AVSS PIN. IT IS RECOMMENDED THAT THE PADDLE BE THERMALLY CONNECTED TO A COPPER PLANE FOR ENHANCED THERMAL PERFORMANCE. NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PADDLE CAN BE CONNECTED TO 0V IF THE OUTPUT VOLTAGE RANGE IS UNIPOLAR. THE EXPOSED PADDLE CAN BE LEFT ELECTRICALLY UNCONNECTED PROVIDED THAT A SUPPLY CONNECTION IS MADE AT THE AVSS PIN. IT IS RECOMMENDED THAT THE PADDLE BE THERMALLY CONNECTED TO A COPPER PLANE FOR ENHANCED THERMAL PERFORMANCE. Figure 5. TSSOP Pin Configuration Figure 6. LFCSP Pin Configuration Table 6. Pin Function Descriptions TSSOP 1 Pin No. LFCSP 14, 37 Mnemonic AVSS 2 3 39 2 DVCC FAULT 4, 12 18 GND NC 5 3, 15 1, 10, 11, 19, 20, 21, 22, 25, 30, 31, 35, 38, 40 4 6 5 CLEAR SELECT CLEAR 7 6 LATCH 8 7 SCLK 9 10 8 9 SDIN SDO 11 13 12, 13 16 GND RSET 14 15 17 18 REFOUT REFIN Description Negative Analog Supply Pin. Voltage ranges from –3 V to –24 V. This pin can be connected to 0 V if the output voltage range is unipolar. Digital Supply Pin. Voltage ranges from 2.7 V to 5.5 V. Fault Alert. This pin is asserted low when an open circuit is detected in current mode or an overtemperature is detected. Open drain output must be connected to a pull-up resistor. These pins must be connected to 0 V. No Connection. Do not connect to these pins. Selects the voltage output clear value, either zero-scale or midscale code (see Table 21). Active High Input. Asserting this pin sets the current output to the bottom of the selected range or sets the voltage output to the user selected value (zero-scale or midscale). Positive Edge Sensitive Latch. A rising LATCH edge parallel loads the input shift register data into the DAC register, also updating the output. Serial Clock Input. Data is clocked into the shift register on the rising edge of SCLK. This operates at clock speeds of up to 30 MHz. Serial Data Input. Data must be valid on the rising edge of SCLK. Serial Data Output. Used to clock data from the serial register in daisy-chain or readback mode. Data is valid on the rising edge of SCLK (see Figure 3 and Figure 4). Ground Reference Pin. An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the IOUT temperature drift performance. See the AD5412/AD5422 Features section. Internal Reference Voltage Output. REFOUT = 5 V ± 2 mV. External Reference Voltage Input. Reference input range is 4 V to 5 V. REFIN = 5 V for a specified performance. Rev. A | Page 11 of 40 AD5412/AD5422 TSSOP 16 Pin No. LFCSP 23 Mnemonic DVCC SELECT 17 24 CCOMP 19 20 26 27 IOUT BOOST N/A 28, 29 CAP1, CAP2 21 32 VOUT 22 23 24 25 (EPAD) 33 34 36 41 (EPAD) +VSENSE −VSENSE AVDD Exposed paddle Description When connected to GND, this pin disables the internal supply, and an external supply must be connected to the DVCC pin. Leave this pin unconnected to enable the internal supply. See the AD5412/AD5422 Features section. Optional compensation capacitor connection for the voltage output buffer. Connecting a 4 nF capacitor between this pin and the VOUT pin allows the voltage output to drive up to 1 μF. It should be noted that the addition of this capacitor reduces the bandwidth of the output amplifier, increasing the settling time. Current Output Pin. Optional External Transistor Connection. Connecting an external transistor reduces the power dissipated in the AD5412/AD5422. See theAD5412/AD5422 Features section. Connection for Optional Output Filtering Capacitor. See the AD5412/AD5422 Features section. Buffered Analog Output Voltage. The output amplifier is capable of directly driving a 1 kΩ, 2000 pF load. Sense connection for the positive voltage output load connection. Sense connection for the negative voltage output load connection. Positive Analog Supply Pin. Voltage ranges from 10.8 V to 60 V. Negative Analog Supply Pin. Voltage ranges from –3 V to –24 V. This paddle can be connected to 0 V if the output voltage range is unipolar. The paddle can be left electrically unconnected provided that a supply connection is made at the AVSS pin. It is recommended that the paddle be thermally connected to a copper plane for enhanced thermal performance. Rev. A | Page 12 of 40 AD5412/AD5422 TYPICAL PERFORMANCE CHARACTERISTICS GENERAL 900 9 TA = 25°C TA = 25°C 8 DVCC OUTPUT VOLTAGE (V) 700 DICC (µA) 600 DVCC = 5V 500 400 300 200 DVCC = 3V 0 0 0.5 1.0 1.5 6 5 4 3 2 1 2.0 2.5 3.0 3.5 LOGIC VOLTAGE (V) 4.0 4.5 5.0 06996-022 100 7 0 –21 Figure 7. DICC vs. Logic Input Voltage –19 –17 –15 –13 –11 –9 –7 –5 LOAD CURRENT (mA) –3 –1 06996-024 800 1 Figure 10. DVCC Output Voltage vs. Load Current 5 AIDD 4 AVDD AIDD/AISS (mA) 3 TA = 25°C VOUT = 0V OUTPUT UNLOADED 2 3 1 REFERENCE OUTPUT 0 AISS –2 10 12 14 16 18 20 22 AVDD/|AVSS| (V) 24 26 28 CH1 2.00V CH3 5.00V Figure 8. AIDD/AISS vs. AVDD/|AVSS| M200µs CH3 2.1V 06996-025 1 06996-108 –1 Figure 11. REFOUT Turn-on Transient 5.0 TA = 25°C IOUT = 0mA 4.5 4.0 3.0 1 2.5 2.0 1.5 1.0 0 10 15 20 25 AVDD (V) 30 35 40 Figure 9. AIDD vs. AVDD CH1 2µV M2.00s LINE 1.8V 06996-026 0.5 06996-023 AIDD (mA) 3.5 Figure 12. REFOUT Output Noise (0.1 Hz to 10 Hz Bandwidth) Rev. A | Page 13 of 40 AD5412/AD5422 45 AVDD = 24V 40 POPULATION (%) 35 1 30 25 20 15 10 M2.00s LINE 0V 0 0 Figure 13. REFOUT Output Noise (100 kHz Bandwidth) 2 3 4 5 6 7 8 TEMPERATURE COEFFICIENT (ppm/°C) 9 10 Figure 15. Reference Temperature Coefficient Histogram 5.003 5.0005 50 DEVICES SHOWN AVDD = 24V TA = 25°C AVDD = 24V REFERENCE OUTPUT VOLTAGE (V) 5.0000 5.002 5.001 5.000 4.999 4.998 4.9995 4.9990 4.9985 4.9980 4.9975 4.9970 4.9965 –20 0 20 40 TEMPERATURE (°C) 60 80 Figure 14. Reference Voltage vs. Temperature 4.9955 0 1 2 3 4 5 6 LOAD CURRENT (mA) 7 Figure 16. Reference Voltage vs. Load Current Rev. A | Page 14 of 40 8 9 06996-031 4.9960 4.997 –40 06996-029 REFERENCE OUTPUT VOLTAGE (V) 1 06996-030 CH1 20µV 06996-027 5 AD5412/AD5422 VOLTAGE OUTPUT 0.0020 0.0015 0.6 0.0010 0.4 0.0005 0 –0.0005 –0.0010 ±10V RANGE ±5V RANGE +5V RANGE +10V RANGE –0.0015 –0.0020 20,000 30,000 40,000 CODE 50,000 60,000 Figure 17. Integral Nonlinearity Error vs. DAC Code, Dual Supply 0 0 –0.0005 –0.0010 –0.0015 –0.0020 10,000 20,000 30,000 40,000 50,000 60,000 CODE 60,000 –0.001 –0.003 –0.005 ±10V RANGE ±5V RANGE +5V RANGE +10V RANGE –0.007 0 10,000 20,000 30,000 40,000 CODE 50,000 60,000 Figure 21. Total Unadjusted Error vs. DAC Code, Dual Supply TOTAL UNADJUSTED ERROR (% FSR) 0.2 0 –0.2 –0.4 20,000 30,000 40,000 CODE 50,000 60,000 AVDD = 24V AVSS = 0V TA = 25°C +5V RANGE +10V RANGE 0.025 0.020 0.015 0.010 0.005 0 –0.005 –0.010 06996-119 ±10V RANGE ±5V RANGE +10V RANGE +5V RANGE 10,000 0.001 0.030 AVDD = +24V AVSS = –24V TA = 25°C 0.4 DNL ERROR (LSB) 50,000 AVDD = +24V AVSS = –24V TA = 25°C 0.003 –0.009 Figure 18. Integral Nonlinearity Error vs. DAC Code, Single Supply 0 40,000 0 10,000 20,000 30,000 40,000 50,000 60,000 CODE Figure 19. Differential Nonlinearity Error vs. DAC Code, Dual Supply Figure 22. Total Unadjusted Error vs. DAC Code, Single Supply Rev. A | Page 15 of 40 06996-122 0 06996-118 –0.0025 –1.0 30,000 06996-221 AVDD = 24V AVSS = 0V TA = 25°C 0.0005 –0.8 20,000 Figure 20. Differential Nonlinearity Error vs. DAC Code, Single Supply 0.0010 –0.6 10,000 CODE TOTAL UNADJSUTED ERROR (% FSR) INL ERROR (% FSR) 0.0015 0.6 –0.4 0.005 +5V RANGE +10V RANGE 0.0020 0.8 –0.2 –1.0 0.0025 1.0 0 –0.8 06996-117 10,000 0.2 –0.6 –0.0025 0 AVDD = 24V AVSS = 0V TA = 25°C +5V RANGE +10V RANGE 0.8 DNL ERROR (LSB) INL ERROR (% FSR) 1.0 AVDD = +24V AVSS = –24V TA = 25°C 06996-120 0.0025 AD5412/AD5422 0.012 0.0015 AVDD = +24V AVSS = –24V –0.0005 –0.0015 –40 +5V RANGE MAX INL ±5V RANGE MAX INL +5V RANGE MIN INL ±5V RANGE MIN INL –20 0 +10V RANGE MAX INL ±10V RANGE MAX INL +10V RANGE MIN INL ±10V RANGE MIN INL 20 40 TEMPERATURE (°C) 60 0.008 0.006 0.004 0.002 0 –0.002 –0.006 80 –0.008 –40 –20 0 20 40 TEMPERATURE (°C) 60 80 Figure 26. Full-Scale Error vs. Temperature Figure 23. Integral Nonlinearity Error vs. Temperature 1.5 1.0 AVDD = +24V AVSS = –24V ALL RANGES 0.8 1.0 0.6 0.4 OFFSET ERROR (mV) DNL ERROR (LSB) +5V RANGE +10V RANGE ±5V RANGE ±10V RANGE –0.004 06996-100 FULL-SCALE ERROR (% FSR) 0 06996-121 INL ERROR (% FSR) 0.0005 –0.0010 AVDD = +24V AVSS = –24V OUTPUT UNLOADED 0.010 0.0010 0.2 0 –0.2 –0.4 –0.6 0.5 0 AVDD = +24V AVSS = –24V OUTPUT UNLOADED +10V RANGE +5V RANGE –0.5 –1.0 0 20 40 60 80 TEMPERATURE (°C) –1.5 –40 0 20 40 TEMPERATURE (°C) 60 80 80 Figure 27. Offset Error vs. Temperature Figure 24. Differential Nonlinearity Error vs. Temperature 1.5 0.015 AVDD = +24V AVSS = –24V OUTPUT UNLOADED 1.0 BIPOLAR ZERO ERROR (mV) 0.010 0.005 0 –0.005 +5V RANGE +10V RANGE ±5V RANGE ±10V RANGE –0.010 –0.015 –40 –20 0 20 40 TEMPERATURE (°C) AVDD = +24V AVSS = –24V OUTPUT UNLOADED +10V RANGE 0.5 0 +5V RANGE –0.5 –1.0 60 80 06996-101 TOTAL UNADJSUTED ERROR (% FSR) –20 06996-129 –20 06996-124 –1.0 –40 06996-130 –0.8 Figure 25. Total Unadjusted Error vs. Temperature –1.5 –40 –20 0 20 40 TEMPERATURE (°C) 60 Figure 28. Bipolar Zero Error vs. Temperature Rev. A | Page 16 of 40 AD5412/AD5422 0.014 1.0 AVDD = +24V AVSS = –24V OUTPUT UNLOADED 0.012 0.6 0.008 0.4 DNL ERROR (LSB) 0.006 0.004 0.002 0 –0.002 +5V RANGE +10V RANGE ±5V RANGE ±10V RANGE –0.006 –0.008 –40 –20 0.2 0 –0.2 –0.4 –0.6 –0.8 0 20 40 TEMPERATURE (°C) 60 –1.0 80 10 14 16 18 20 AVDD/|AVSS| (V) 22 24 26 28 Figure 32. Differential Nonlinearity Error vs. AVDD/|AVSS| Figure 29. Gain Error vs. Temperature 0.0050 1.3 TOTAL UNADJUSTED ERROR (% FSR) AVDD = +24V AVSS = –24V OUTPUT UNLOADED 0.3 –0.2 –0.7 –1.2 –40 –20 0 20 40 TEMPERATURE (°C) 60 0.0040 0.0035 TA = 25°C ±10V RANGE 0.0030 0.0025 0.0020 0.0015 0.0010 0.0005 06996-102 +5V RANGE +10V RANGE ±5V RANGE ±10V RANGE 0.0045 0 10 80 12 14 16 18 20 22 AVDD/|AVSS| (V) 24 26 28 06996-033 0.8 Figure 33. Total Unadjusted Error vs. AVDD/|AVSS| Figure 30. Zero-Scale Error vs. Temperature 0.05 0.0015 TA = 25°C ±10V RANGE 0.04 CHANGE IN OUTPUT VOLTAGE (V) 0.0010 0.0005 0 –0.0005 –0.0010 0.03 0.02 AVDD = +15V AVSS = –15V TA = 25°C ±10V RANGE 0.01 0 –0.01 –0.02 –0.03 –0.0015 10 12 14 16 18 20 22 AVDD/|AVSS| (V) 24 26 28 –0.05 –20 –15 –10 –5 0 5 10 SOURCE/SINK CURRENT (mA) 15 Figure 34. Source and Sink Capability of Output Amplifier, Full-Scale Code Loaded Figure 31. Integral Nonlinearity Error vs. AVDD/|AVSS| Rev. A | Page 17 of 40 20 06996-132 –0.04 06996-231 INL ERROR (% FSR) 12 06996-232 –0.004 06996-131 GAIN ERROR (% FSR) 0.010 ZERO-SCALE ERROR (mV) TA = 25°C ±10V RANGE 0.8 AD5412/AD5422 0.05 0.03 8 OUTPUT VOLTAGE (V) CHANGE IN OUTPUT VOLTAGE (V) 0.04 12 AVDD = +15V AVSS = –15V TA = 25°C ±10V RANGE 0.02 0.01 0 –0.01 –0.02 –0.03 4 0 AVDD = +24V AVSS = –24V ±10V RANGE TA = 25°C OUTPUT UNLOADED –4 –8 –15 –10 –5 0 5 10 SOURCE/SINK CURRENT (mA) 15 20 –12 –10 06996-035 –5 12 10 15 TIME (µs) 25 30 2 OUTPUT VOLTAGE (mV) 0 4 0 –4 –2 0x8000 TO 0x7FFF 0x7FFF TO 0x8000 –4 –6 –8 –10 AVDD = +24V AVSS = –24V TA = 25°C ±10V RANGE –12 –8 –14 –12 –10 20 4 AVDD = +24V AVSS = –24V ±10V RANGE TA = 25°C OUTPUT UNLOADED –5 0 5 10 15 TIME (µs) 20 25 30 06996-136 OUTPUT VOLTAGE (V) 5 Figure 37. Full-Scale Negative Step Figure 35. Source and Sink Capability of Output Amplifier, Zero-Scale Loaded 8 0 Figure 36. Full-Scale Positive Step –16 –1 1 3 5 7 TIME (µs) 9 11 Figure 38. Digital-to-Analog Glitch Rev. A | Page 18 of 40 13 15 06996-036 –0.05 –20 06996-137 –0.04 AD5412/AD5422 35 AVDD = +15V AVSS = –15V TA = 25°C 30 VOUT (mV) 25 1 20 15 10 M 5.00ms LINE 0 1.8V M 5.00ms LINE 06996-038 1 CH1 50.0µV 2 4 6 8 10 12 TIME (µs) 14 16 Figure 41. VOUT vs. Time on Power-Up Figure 39. Peak-to-Peak Noise (0.1 Hz to 10 Hz Bandwidth) AVDD = +24V AVSS = –24V TA = 25°C 0 0V Figure 40. Peak-to-Peak Noise (100 kHz Bandwidth) Rev. A | Page 19 of 40 18 20 06996-039 CH1 5.0µV 5 06996-037 AVDD = +24V AVSS = –24V TA = 25°C AD5412/AD5422 CURRENT OUTPUT 0.002 INL ERROR (% FSR) 0 –0.002 –0.004 –0.006 AVDD = 24V AVSS = –24V/0V TA = 25°C RLOAD = 250Ω 10,000 20,000 30,000 40,000 CODE 50,000 60,000 0.6 0.003 0.002 INL ERROR (% FSR) 0.2 0 –0.2 –0.4 EXTERNAL RSET INTERNAL RSET EXTERNAL RSET , BOOST TRANSISTOR INTERNAL RSET , BOOST TRANSISTOR –0.8 –1.0 0 10,000 20,000 30,000 40,000 CODE 50,000 60,000 80 AVDD = 24V AVSS = –24V/0V 0mA TO 24mA RANGE 0 –0.001 –20 0 20 40 TEMPERATURE (°C) 60 80 Figure 46. Integral Nonlinearity vs. Temperature, External RSET 0.05 1.0 AVDD = 24V AVSS = –24V/0V 0.8 ALL RANGES INTERNAL AND EXTERNAL R SET 0.6 0.03 0.01 DNL ERROR (LSB) –0.01 –0.03 –0.05 AVDD = 24V AVSS = –24V/0V TA = 25°C RLOAD = 250Ω –0.07 –0.09 EXTERNAL RSET INTERNAL RSET EXTERNAL RSET , BOOST TRANSISTOR INTERNAL RSET, BOOST TRANSISTOR –0.11 –0.13 0 10,000 20,000 30,000 40,000 CODE 50,000 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 60,000 06996-008 TOTAL UNADJUSTED ERROR (% FSR) 60 0.001 –0.003 –40 Figure 43. Differential Nonlinearity vs. Code –0.15 0 20 40 TEMPERATURE (°C) –0.002 06996-007 DNL ERROR (LSB) 0.4 –0.6 –20 Figure 45. Integral Nonlinearity vs. Temperature, Internal RSET AVDD = 24V AVSS = –24V/0V TA = 25°C RLOAD = 250Ω 0.8 –0.006 –0.010 –40 Figure 42. Integral Nonlinearity vs. Code 1.0 –0.004 06996-009 0 –0.002 Figure 44. Total Unadjusted Error vs. Code –1.0 –40 –20 0 20 40 TEMPERATURE (°C) 60 Figure 47. Differential Nonlinearity vs. Temperature Rev. A | Page 20 of 40 80 06996-010 –0.010 0 –0.008 06996-106 –0.008 AVDD = 24V AVSS = –24V/0V 0mA TO 24mA RANGE 06996-109 0.002 INL ERROR (% FSR) 0.004 EXTERNAL RSET INTERNAL RSET EXTERNAL RSET, BOOST TRANSISTOR INTERNAL RSET , BOOST TRANSISTOR 0.004 AD5412/AD5422 0.015 AVDD = 24V AVSS = –24V/0V 0.010 INL ERROR (% FSR) 0 –0.05 –0.10 4mA TO 0mA TO 0mA TO 4mA TO 0mA TO 0mA TO –20 0 0 –0.005 –0.010 20 40 TEMPERATURE (°C) 60 80 –0.015 Figure 48. Total Unadjusted Error vs. Temperature AVDD = 24V AVSS = –24V/0V 0.015 INL ERROR (% FSR) –0.05 –0.10 –20 20mA INTERNAL R SET 20mA INTERNAL R SET 24mA INTERNAL R SET 20mA EXTERNAL RSET 20mA EXTERNAL RSET 24mA EXTERNAL RSET 35 40 0 20 0.005 0 –0.005 –0.015 40 60 80 –0.020 10 Figure 49. Offset Error vs. Temperature 15 20 25 AVDD (V) 30 35 40 Figure 52. Integral Nonlinearity Error vs. AVDD, Internal RSET 0.06 1.0 AVDD = 24V AVSS = –24V/0V 0.04 TA = 25°C 0mA TO 24mA RANG AVSS = 0V 0.8 0.6 DNL ERROR (LSB) 0.02 0 –0.02 –0.04 4mA TO 0mA TO 0mA TO 4mA TO 0mA TO 0mA TO –0.06 –0.08 –20 0 20mA INTERNAL R SET 20mA INTERNAL R SET 24mA INTERNAL R SET 20mA EXTERNAL R SET 20mA EXTERNAL R SET 24mA EXTERNAL R SET 20 40 TEMPERATURE (°C) 60 80 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 06996-018 GAIN ERROR (% FSR) 30 –0.010 06996-017 4mA TO 0mA TO 0mA TO 4mA TO 0mA TO 0mA TO TEMPERATURE (°C) –0.10 –40 25 AVDD (V) TA = 25°C 0mA TO 24mA RANGE AVSS = 0V 0.010 0 –0.25 –40 20 0.020 0.05 –0.20 15 Figure 51. Integral Nonlinearity Error vs. AVDD, External RSET 0.10 –0.15 10 06996-014 –0.20 20mA INTERNAL R SET 20mA INTERNAL R SET 24mA INTERNAL R SET 20mA EXTERNAL R SET 20mA EXTERNAL R SET 24mA EXTERNAL R SET 0.005 Figure 50. Gain Error vs. Temperature –1.0 10 15 20 25 AVDD (V) 30 35 40 Figure 53. Differential Nonlinearity Error vs. AVDD, External RSET Rev. A | Page 21 of 40 06996-012 –0.15 –0.25 –40 OFFSET ERROR (% FSR) TA = 25°C 0mA TO 24mA RANGE AVSS = 0V 06996-011 0.05 06996-013 TOTAL UNADJUSTED ERROR (% FSR) 0.10 AD5412/AD5422 2.5 1.0 AVDD = 15V AVSS = 0V IOUT = 24mA RLOAD = 500Ω 0.8 TA = 25°C 0mA TO 24mA RANGE AVSS = 0V 0.4 2.0 HEADROOM VOLTAGE (V) DNL ERROR (LSB) 0.6 0.2 0 –0.2 –0.4 1.5 1.0 0.5 –0.6 10 15 20 25 30 35 40 AVDD (V) 0 –40 06996-015 –1.0 20 40 TEMPERATURE (°C) 60 80 3.5 0.025 TA = 25°C 0mA TO 24mA RANGE AVSS = 0V 0.020 AVDD = 24V AVSS = 0V TA = 25°C RLOAD = 250Ω 3.0 0.015 OUTPUT CURRENT (µA) 2.5 0.010 0.005 0 –0.005 2.0 1.5 1.0 10 15 20 25 30 35 40 AVDD (V) 0 0 Figure 55. Total Unadjusted Error vs. AVDD, External RSET 100 200 300 TIME (µs) 400 500 600 06996-020 –0.015 5.0 06996-021 0.5 –0.010 06996-016 TOTAL UNADJUSTED ERROR (% FSR) 0 Figure 57. Compliance Voltage Headroom vs. Temperature Figure 54. Differential Nonlinearity Error vs. AVDD, Internal RSET Figure 58. Output Current vs. Time on Power-Up 20 0.05 0.03 10 OUTPUT CURRENT (µA) 0.01 –0.01 –0.03 TA = 25°C 0mA TO 24mA RANGE AVSS = 0V –0.05 –0.07 –0.09 AVDD = 24V AVSS = 0V TA = 25°C RLOAD = 250Ω 0 –10 –20 –30 –0.11 –40 –0.13 –0.15 10 15 20 25 30 35 AVDD (V) 40 06996-032 TOTAL UNADJUSTED ERROR (% FSR) –20 06996-019 –0.8 Figure 56. Total Unadjusted Error vs. AVDD, Internal RSET –50 0 0.5 1.0 1.5 2.0 2.5 3.0 TIME (µs) 3.5 4.0 4.5 Figure 59. Output Current vs. Time on Output Enable Rev. A | Page 22 of 40 AD5412/AD5422 70 25 60 OUTPUT CURRENT (mA) 50 40 30 20 TA = 25°C AVDD = 40V AVSS = 0V OUTPUT DISABLED 0 5 10 15 20 25 30 35 COMPLIANCE VOLTAGE (V) 40 45 Figure 60. Output Leakage Current vs. Compliance Voltage 10 0 –10 –20 06996-049 OUTPUT CURRENT (µA) 0x8000 TO 0x7FFF 0x7FFF TO 0x8000 AVDD = 24V AVSS = 0V TA = 25°C RLOAD = 250Ω –30 0 2 4 6 10 8 10 12 TIME (µs) 14 16 18 0 –1 0 1 2 3 4 TIME (µs) 5 6 Figure 62. 4 mA to 20 mA Output Current Step 30 20 15 5 –10 0 TA = 25°C AVDD = 24V AVSS = 0V RLOAD = 300Ω 20 Figure 61. Digital to Analog Glitch Rev. A | Page 23 of 40 7 8 06996-134 10 06996-028 LEAKAGE CURRENT (pA) 20 AD5412/AD5422 TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy, or INL, is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot can be seen in Figure 17. Differential Nonlinearity (DNL) DNL is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL vs. code plot can be seen in Figure 19. Slew Rate The slew rate of a device is a limitation in the rate of change of the output voltage. The output slewing speed of a voltageoutput DAC is usually limited by the slew rate of the amplifier used at its output. Slew rate is measured from 10% to 90% of the output signal and is expressed in V/μs. Gain Error Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal expressed in % FSR. A plot of gain error vs. temperature can be seen in Figure 29. Monotonicity A DAC is monotonic if the output either increases or remains constant for increasing digital input code. The AD5412/AD5422 are monotonic over their full operating temperature range. Gain Error Temperature Coefficient (TC) Gain error TC is a measure of the change in gain error with changes in temperature. Gain error TC is expressed in ppm FSR/°C. Bipolar Zero Error Bipolar zero error is the deviation of the analog output from the ideal half-scale output of 0 V when the DAC register is loaded with 0x8000 (straight binary coding) or 0x0000 (twos complement coding). A plot of bipolar zero error vs. temperature can be seen in Figure 28. Total Unadjusted Error (TUE) TUE is a measure of the output error taking all the various errors into account, namely INL error, offset error, gain error, and output drift over supplies, temperature, and time. TUE is expressed in % FSR. Bipolar Zero Temperature Coefficient (TC) Bipolar zero TC is a measure of the change in the bipolar zero error with a change in temperature. It is expressed in ppm FSR/°C. Full-Scale Error Full-scale error is a measure of the output error when full-scale code is loaded to the DAC register. Ideally, the output should be full-scale − 1 LSB. Full-scale error is expressed in percent of full-scale range (% FSR). Negative Full-Scale Error/Zero-Scale Error Negative full-scale error is the error in the DAC output voltage when 0x0000 (straight binary coding) or 0x8000 (twos complement coding) is loaded to the DAC register. Ideally, the output voltage should be negative full-scale − 1 LSB. A plot of zeroscale error vs. temperature can be seen in Figure 30. Zero-Scale Temperature Coefficient (TC) Zero-scale TC is a measure of the change in zero-scale error with a change in temperature. Zero-scale error TC is expressed in ppm FSR/°C. Output Voltage Settling Time Output voltage settling time is the amount of time it takes for the output to settle to a specified level for a full-scale input change. Current Loop Voltage Compliance The maximum voltage at the IOUT pin for which the output current is equal to the programmed value. Power-On Glitch Energy Power-on glitch energy is the impulse injected into the analog output when the AD5412/AD5422 is powered on. It is specified as the area of the glitch in nV-sec. See Figure 41 and Figure 58. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state, but the output voltage remains constant. It is normally specified as the area of the glitch in nV-sec and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000). See Figure 38 and Figure 61. Glitch Impulse Peak Amplitude Glitch impulse peak amplitude is the peak amplitude of the impulse injected into the analog output when the input code in the DAC register changes state. It is specified as the amplitude of the glitch in millivolt and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000). See Figure 38 and Figure 61. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC but is measured when the DAC output is not updated. It is specified in nV-sec and measured with a full-scale code change on the data bus. Rev. A | Page 24 of 40 AD5412/AD5422 Power Supply Rejection Ratio (PSRR) PSRR indicates how the output of the DAC is affected by changes in the power supply voltage. Voltage Reference TC Voltage reference TC is a measure of the change in the reference output voltage with a change in temperature. The reference TC is calculated using the box method, which defines the TC as the maximum change in the reference output over a given temperature range expressed in ppm/°C, as follows: ⎡ VREFmax − VREFmin ⎤ 6 TC = ⎢ ⎥ × 10 × V TempRange REFnom ⎣ ⎦ where: VREFmax is the maximum reference output measured over the total temperature range. VREFmin is the minimum reference output measured over the total temperature range. VREFnom is the nominal reference output voltage, 5 V. TempRange is the specified temperature range, −40°C to +85°C. Load Regulation Load regulation is the change in reference output voltage due to a specified change in load current. It is expressed in ppm/mA. Rev. A | Page 25 of 40 AD5412/AD5422 THEORY OF OPERATION ARCHITECTURE The DAC core architecture of the AD5412/AD5422 consists of two matched DAC sections. A simplified circuit diagram is shown in Figure 63. The four MSBs of the 12-/16-bit data-word are decoded to drive 15 switches, E1 to E15. Each of these switches connects one of 15 matched resistors to either ground or the reference buffer output. The remaining 8/12 bits of the dataword drive the S0 to S7/S11 switches of an 8-/12-bit voltage mode R-2R ladder network. VOUT 2R 2R 2R 2R 2R 2R S0 S1 S7/S11 E1 E2 E15 8-12 BIT R-2R LADDER 06996-057 2R FOUR MSBs DECODED INTO 15 EQUAL SEGMENTS Figure 63. DAC Ladder Structure The voltage output from the DAC core is either converted to a current (see Figure 64) which is then mirrored to the supply rail so that the application simply sees a current source output with respect to ground or it is buffered and scaled to output a software selectable unipolar or bipolar voltage range (see Figure 65). The current and voltage are output on separate pins and cannot be output simultaneously. AVDD R2 AD5412/AD5422 12-/16-BIT DAC R1 RLOAD –1V TO +3V VCM Figure 65. Voltage Output Voltage Output Amplifier The voltage output amplifier is capable of generating both unipolar and bipolar output voltages. It is capable of driving a load of 1 kΩ in parallel with 1 μF (with an external compensation capacitor) to GND. The source and sink capabilities of the output amplifier can be seen in Figure 35. The slew rate is 1 V/μs with a full-scale settling time of 25 μs maximum (10 V step). Figure 65 shows the voltage output driving a load, RLOAD, on top of a common-mode voltage (VCM) of −1 V to +3 V. In output module applications where a cable could possibly become disconnected from +VSENSE, resulting in the amplifier loop being broken and possibly resulting in large destructive voltages on VOUT, include an optional resistor (R1) between +VSENSE and VOUT, as shown in Figure 65, of a value between 2 kΩ and 5 kΩ to ensure the amplifier loop is kept closed. If remote sensing of the load is not required, connect +VSENSE directly to VOUT and connect −VSENSE directly to GND. When changing ranges on the voltage output, a glitch may occur. For this reason, it is recommended that the output be disabled by setting the OUTEN bit of the control register to logic low before changing the output voltage range; this prevents a glitch from occurring. Driving Large Capacitive Loads The voltage output amplifier is capable of driving capacitive loads of up to 1 μF with the addition of a nonpolarized 4 nF compensation capacitor between the CCOMP and VOUT pins. Without the compensation capacitor, up to 20 nF capacitive loads can be driven. R3 T1 06996-058 IOUT RSET VOUT REFIN T2 A1 RANGE SCALING –VSENSE A2 12-/16-BIT DAC +VSENSE 06996-059 The AD5412/AD5422 are precision digital-to-current loop and voltage output converters designed to meet the requirements of industrial process control applications. They provide a high precision, fully integrated, low cost single-chip solution for generating current loop and unipolar/bipolar voltage outputs. Current ranges are 0 mA to 20 mA, 0 mA to 24 mA, and 4 mA to 20 mA; the voltage ranges available are 0 V to 5 V, ±5 V, 0 V to 10 V, and ±10 V; a 10% overrange is available on all voltage output ranges. The current and voltage outputs are available on separate pins, and only one is active at any time. The desired output configuration is user selectable via the control register. Figure 64. Voltage-to-Current Conversion Circuitry Rev. A | Page 26 of 40 AD5412/AD5422 SERIAL INTERFACE CONTROLLER The AD5412/AD5422 are controlled over a versatile 3-wire serial interface that operates at clock rates of up to 30 MHz. It is compatible with SPI, QSPI™, MICROWIRE, and DSP standards. DATA OUT Input Shift Register SCLK CONTROL OUT LATCH AD5412/ AD54221 SCLK LATCH SDO SDIN AD5412/ AD54221 SCLK LSB LATCH D15 to D0 Data-word 1 ADDITIONAL PINS OMITTED FOR CLARITY. Function No operation (NOP) Data register Readback register value as per read address (see Table 9) Control register Reset register Standalone Operation The serial interface works with both a continuous and noncontinuous serial clock. A continuous SCLK source can be used only if LATCH is taken high after the correct number of data bits have been clocked in. In gated clock mode, a burst clock containing the exact number of clock cycles must be used, and LATCH must be taken high after the final clock to latch the data. The rising edge of SCLK that clocks in the MSB of the data-word marks the beginning of the write cycle. Exactly 24 rising clock edges must be applied to SCLK before LATCH is brought high. If LATCH is brought high before the 24th rising SCLK edge, the data written is invalid. If more than 24 rising SCLK edges are applied before LATCH is brought high, the input data is also invalid. 06996-060 SDO Table 8. Address Byte Functions 01010101 01010110 SDO SDIN Table 7. Input Shift Register Format Address Word 00000000 00000001 00000010 SDIN SERIAL CLOCK DATA IN The input shift register is 24 bits wide. Data is loaded into the device MSB first as a 24-bit word under the control of a serial clock input, SCLK. Data is clocked in on the rising edge of SCLK. The input register consists of eight address bits and 16 data bits, as shown in Table 7. The 24-bit word is unconditionally latched on the rising edge of the LATCH pin. Data continues to be clocked in irrespective of the state of LATCH. On the rising edge of LATCH, the data that is present in the input register is latched; in other words, the last 24 bits to be clocked in before the rising edge of LATCH is the data that is latched. The timing diagram for this operation is shown in Figure 2. MSB D23 to D16 Address byte AD5412/ AD54221 Figure 66. Daisy Chaining the AD5412/AD5422 Daisy-Chain Operation For systems that contain several devices, the SDO pin can be used to daisy-chain the devices together as shown in Figure 66. This daisy-chain mode can be useful in system diagnostics and in reducing the number of serial interface lines. Daisy-chain mode is enabled by setting the DCEN bit of the control register to 1. The first rising edge of SCLK that clocks in the MSB of the data-word marks the beginning of the write cycle. SCLK is continuously applied to the input shift register. If more than 24 clock pulses are applied, the data ripples out of the shift register and appears on the SDO line. This data is valid on the rising edge of SCLK, having been clocked out on the previous falling SCLK edge. By connecting the SDO of the first device to the SDIN input of the next device in the chain, a multidevice interface is constructed. Each device in the system requires 24 clock pulses. Therefore, the total number of clock cycles must equal 24 × n, where n is the total number of AD5412/ AD5422 devices in the chain. When the serial transfer to all devices is complete, LATCH is taken high. This latches the input data in each device in the daisy chain. The serial clock can be a continuous or a gated clock. A continuous SCLK source can be used only if LATCH is taken high after the correct number of clock cycles. In gated clock mode, a burst clock containing the exact number of clock cycles must be used, and LATCH must be taken high after the final clock to latch the data (see Figure 4 for a timing diagram). Rev. A | Page 27 of 40 AD5412/AD5422 Readback Operation Readback mode is invoked by setting the address byte and read address when writing to the input register (see Table 9 and Table 11). The next write to the AD5412/AD5422 should be a NOP command, which clocks out the data from the previously addressed register as shown in Figure 3. By default the SDO pin is disabled after having addressed the AD5412/AD5422 for a read operation; a rising edge on LATCH enables the SDO pin in anticipation of data being clocked out. After the data has been clocked out on SDO, a rising edge on LATCH disables (tristate) the SDO pin. To read back the data register, for example, implement the following sequence: 1. 2. Write 0x020001 to the input register. This configures the part for read mode with the data register selected. Follow this with a second write: a NOP condition, which is 0x000000. During this write, the data from the register is clocked out on the SDO line. Table 9. Read Address Decoding Read Address 00 01 10 Function Read status register Read data register Read control register calibration registers and ensures specified operation of the AD5412/AD5422. Voltage Output For a unipolar voltage output range, the output voltage can be expressed as D VOUT VREFIN Gain N 2 For a bipolar voltage output range, the output voltage can be expressed as D VOUT VREFIN Gain N 2 Gain VREFIN 2 where: D is the decimal equivalent of the code loaded to the DAC. N is the bit resolution of the DAC. VREFIN is the reference voltage applied at the REFIN pin. Gain is an internal gain whose value depends on the output range selected by the user as shown in Table 10. Table 10. Internal Gain Value Output Range +5 V +10 V ±5 V ±10 V POWER-ON STATE During power-on of the AD5412/AD5422, the power-on-reset circuit ensures that all registers are loaded with zero-code. As such, both outputs are disabled; that is, the VOUT and IOUT pins are in tristate. The +VSENSE pin is internally connected to ground through a 40 kΩ resistor. Therefore, if the VOUT and +VSENSE pins are connected together, VOUT is effectively clamped to ground through a 40 kΩ resistor. Also upon power-on, internal calibration registers are read, and the data is applied to internal calibration circuitry. For a reliable read operation, there must be sufficient voltage on the AVDD supply when the read event is triggered by the DVCC power supply powering up. Powering up the DVCC supply after the AVDD supply ensures this. If DVCC and AVDD are powered up simultaneously or the internal DVCC is enabled, the supplies should be powered up at a rate greater than, typically, 500 V/sec or 24 V/50 ms. If this cannot be achieved, issue a reset command to the AD5412/AD5422 after power-on; this performs a power-on-reset event, reading the Gain Value 1 2 2 4 Current Output For the 0 mA to 20 mA, 0 mA to 24 mA, and 4 mA to 20 mA current output ranges, the output current is respectively expressed as 20 mA I OUT N D 2 24 mA I OUT N D 2 16 mA I OUT N D 4 mA 2 where: D is the decimal equivalent of the code loaded to the DAC. N is the bit resolution of the DAC. Table 11. Input Shift Register Contents for a Read Operation MSB D23 0 1 D22 0 D21 0 D20 0 D19 0 D18 0 D17 1 D16 0 X = don’t care. Rev. A | Page 28 of 40 D15 to D2 X1 LSB D1 D0 Read address AD5412/AD5422 DATA REGISTER The data register is addressed by setting the address word of the input shift register to 0x01. The data to be written to the data register is entered in the D15 to D4 positions for the AD5412 and the D15 to D0 positions for the AD5422, as shown in Table 12 and Table 13. Table 12. Programming the AD5412 Data Register MSB D15 D14 D13 D12 D7 D6 D5 D4 D3 X D2 X D1 X LSB D0 X D9 D8 D7 16-bit data-word D6 D5 D4 D3 D2 D1 LSB D0 D11 D10 D9 12-bit data-word D8 Table 13. Programming the AD5422 Data Register MSB D15 D14 D13 D12 D11 D10 CONTROL REGISTER The control register is addressed by setting the address word of the input shift register to 0x55. The data to be written to the control register is entered in the D15 to D0 positions, as shown in Table 14. The control register functions are shown in Table 15. Table 14. Programming the Control Register MSB D15 CLRSEL D14 OVRRNG D13 REXT D12 OUTEN D11 D10 D9 SR clock D8 D7 D6 D5 SR step D4 SREN D3 DCEN D2 R2 D1 R1 LSB D0 R0 Table 15. Control Register Functions Option CLRSEL OVRRNG REXT OUTEN SR clock SR step SREN DCEN R2, R1, R0 Description See Table 21 for a description of the CLRSEL operation. Setting this bit increases the voltage output range by 10% (see the AD5412/AD5422 Features section). Setting this bit selects the external current setting resistor (see the AD5412/AD5422 Features section). Output enable. This bit must be set to enable the outputs. The range bits select which output is functional. Digital slew rate control (see the AD5412/AD5422 Features section). Digital slew rate control (see the AD5412/AD5422 Features section). Digital slew rate control enable. Daisy chain enable. Output range select (see Table 16). Table 16. Output Range Options R2 0 0 0 0 1 1 1 R1 0 0 1 1 0 1 1 R0 0 1 0 1 1 0 1 Output Range Selected 0 V to 5 V voltage range 0 V to 10 V voltage range ±5 V voltage range ±10 V voltage range 4 mA to 20 mA current range 0 mA to 20 mA current range 0 mA to 24 mA current range Rev. A | Page 29 of 40 AD5412/AD5422 RESET REGISTER The reset register is addressed by setting the address word of the input shift register to 0x56. The data to be written to the reset register is entered in the D0 position as shown in Table 17. The reset register options are shown in Table 17 and Table 18. Table 17. Programming the Reset Register MSB D15 D14 D13 D12 D11 D10 D9 D8 Reserved D7 D6 D5 D4 D3 D2 D1 LSB D0 Reset Table 18. Reset Register Functions Option Reset Description Setting this bit performs a reset operation, restoring the AD5412/AD5422 to its power-on state. STATUS REGISTER The status register is a read-only register. The status register functionality is shown in Table 19 and Table 20. Table 19. Decoding the Status Register MSB D15 D14 D13 D12 D11 D10 D9 Reserved D8 D7 D6 D5 D4 D3 Table 20. Status Register Functions Option IOUT Fault Slew Active Over Temp Description This bit is set if a fault is detected on the IOUT pin. This bit is set while the output value is slewing (slew rate control enabled). This bit is set if the AD5412/AD5422 core temperature exceeds ~150°C. Rev. A | Page 30 of 40 D2 IOUT fault D1 Slew active LSB D0 Over temp AD5412/AD5422 AD5412/AD5422 FEATURES FAULT ALERT ASYNCHRONOUS CLEAR (CLEAR) The AD5412/AD5422 are equipped with a FAULT pin, which is an open-drain output allowing several AD5412/AD5422 devices to be connected together to one pull-up resistor for global fault detection. The FAULT pin is forced active by one of the following fault scenarios: The CLEAR pin is an active high clear that allows the voltage output to be cleared to either zero-scale code or midscale code, user selectable via the CLEAR SELECT pin, or the CLRSEL bit of the control register, as described in Table 21. (The clear select feature is a logical OR function of the CLEAR SELECT pin and the CLRSEL bit.) The current output clears to the bottom of its programmed range. It is necessary for CLEAR to be high for a minimum amount of time to complete the operation (see Figure 2). When the CLEAR signal is returned low, the output remains at the cleared value. The preclear value can be restored by pulsing the LATCH signal low without clocking any data. A new value cannot be programmed until the CLEAR pin is returned low. • • The voltage at IOUT attempts to rise above the compliance range, due to an open-loop circuit or insufficient power supply voltage. The IOUT current is controlled by a PMOS transistor and internal amplifier, as shown in Figure 64. The internal circuitry that develops the fault output avoids using a comparator with window limits because this would require an actual output error before the FAULT output becomes active. Instead, the signal is generated when the internal amplifier in the output stage has less than ~1 V of remaining drive capability (when the gate of the output PMOS transistor nearly reaches ground). Thus, the FAULT output activates slightly before the compliance limit is reached. Because the comparison is made within the feedback loop of the output amplifier, the output accuracy is maintained by its open-loop gain, and an output error does not occur before the FAULT output becomes active. If the core temperature of the AD5412/AD5422 exceeds approximately 150°C. The IOUT fault and over temp bits of the status register are used in conjunction with the FAULT pin to inform the user which one of the fault conditions caused the FAULT pin to be asserted (see Table 19 and Table 20). VOLTAGE OUTPUT SHORT CIRCUIT PROTECTION Under normal operation, the voltage output sinks/sources 10 mA. The maximum current that the voltage output delivers is ~20 mA; this is the short-circuit current. VOLTAGE OUTPUT OVERRANGE An overrange facility is provided on the voltage output. When enabled via the control register, the selected output range is overranged by, typically, 10%. VOLTAGE OUTPUT FORCE-SENSE The +VSENSE and −VSENSE pins are provided to facilitate remote sensing of the load connected to the voltage output. If the load is connected at the end of a long or high impedance cable, sensing the voltage at the load allows the output amplifier to compensate and ensure that the correct voltage is applied across the load. This function is limited only by the available power supply headroom. Table 21. CLRSEL Options CLRSEL 0 1 Output Value Unipolar Output Range Bipolar Output Range 0V 0V Midscale Negative full scale In addition to defining the output value for a clear operation, the CLRSEL bit and CLEAR SELECT pin also define the default output value. During selection of a new voltage range, the output value is as defined in Table 21. To avoid glitches on the output, it is recommended that, before changing voltage ranges, the user disable the output by setting the OUTEN bit of the control register to logic low. When OUTEN is set to logic high, the output goes to the default value as defined by CLRSEL and CLEAR SELECT. INTERNAL REFERENCE The AD5412/AD5422 contain an integrated 5 V voltage reference with initial accuracy of ±5 mV maximum and a temperature drift coefficient of ±10 ppm/°C maximum. The reference voltage is buffered and externally available for use elsewhere within the system. See Figure 16 for a load regulation graph of the integrated reference. EXTERNAL CURRENT SETTING RESISTOR RSET is an internal sense resistor as part of the voltage-to-current conversion circuitry (see Figure 64). The stability of the output current over temperature is dependent on the stability of the value of RSET. As a method of improving the stability of the output current over temperature, an external precision 15 kΩ low drift resistor can be connected to the RSET pin of the AD5412/AD5422 to be used instead of the internal resistor (RSET). The external resistor is selected via the control register (see Table 14). Rev. A | Page 31 of 40 AD5412/AD5422 DIGITAL POWER SUPPLY By default, the DVCC pin accepts a power supply of 2.7 V to 5.5 V. Alternatively, via the DVCC SELECT pin, an internal 4.5 V power supply can be output on the DVCC pin for use as a digital power supply for other devices in the system or as a termination for pull-up resistors. This facility offers the advantage of not having to bring a digital supply across an isolation barrier. The internal power supply is enabled by leaving the DVCC SELECT pin unconnected. To disable the internal supply, tie DVCC SELECT to 0 V. DVCC is capable of supplying up to 5 mA of current (for a load regulation graph, see Figure 10). EXTERNAL BOOST FUNCTION The addition of an external boost transistor, as shown in Figure 67, reduces the power dissipated in the AD5412/AD5422 by reducing the current flowing in the on-chip output transistor (dividing it by the current gain of the external circuit). A discrete NPN transistor with a breakdown voltage, BVCEO, greater than 40 V can be used. The external boost capability has been developed for users who may wish to use the AD5412/AD5422 at the extremes of the supply voltage, load current, and temperature range. The boost transistor can also be used to reduce the amount of temperature-induced drift in the part. This minimizes the temperature-induced drift of the on-chip voltage reference, which improves on drift and linearity. BOOST MJD31C OR PBSS8110Z IOUT 0.022µF 1kΩ RLOAD 06996-061 AD5412/ AD5422 Figure 67. External Boost Configuration EXTERNAL COMPENSATION CAPACITOR The voltage output can ordinarily drive capacitive loads of up to 20 nF; if there is a requirement to drive greater capacitive loads, of up to 1 μF, an external compensation capacitor can be connected between the CCOMP and VOUT pins. The addition of the capacitor keeps the output voltage stable but also reduces the bandwidth and increases the settling time of the voltage output. DIGITAL SLEW RATE CONTROL The slew rate control feature of the AD5412/AD5422 allows the user to control the rate at which the output voltage or current changes. With the slew rate control feature disabled, the output changes at a rate limited by the output drive circuitry and the attached load. See Figure 62 for current output step and Figure 36 for voltage output step. To reduce the slew rate, enable the slew rate control feature. With the feature enabled via the SREN bit of the control register (see Table 14), the output, instead of slewing directly between two values, steps digitally at a rate defined by two parameters accessible via the control register, as shown in Table 14. The parameters are set by the SR clock and SR step bits. SR clock defines the rate at which the digital slew is updated; SR step defines by how much the output value changes at each update. Both parameters together define the rate of change of the output voltage or current. Table 22 and Table 23 outline the range of values for both the SR clock and SR step parameters. Figure 68 shows the output current changing for ramp times of 10 ms, 50 ms, and 100 ms. Table 22. Slew Rate Step Size Options SR Step 000 001 010 011 100 101 110 111 AD5412 Step Size (LSB) 1/16 1/8 1/4 1/2 1 2 4 8 AD5422 Step Size (LSB) 1 2 4 8 16 32 64 128 Table 23. Slew Rate Update Clock Options SR Clock 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Update Clock Frequency (Hz) 257,730 198,410 152,440 131,580 115,740 69,440 37,590 25,770 20,160 16,030 10,290 8280 6900 5530 4240 3300 The time it takes for the output to slew over a given output range can be expressed as follows: Slew Time = Output Change Step Size × Update Clock Frequency × LSB Size (1) where: Slew Time is expressed in seconds. Output Change is expressed in amps for IOUT or volts for VOUT. When the slew rate control feature is enabled, all output changes change at the programmed slew rate; if the CLEAR pin is asserted, the output slews to the zero-scale value at the programmed slew rate. The output can be halted at its current value with a write to the control register. To avoid halting the output slew, the slew active bit (see Table 19) can be read to check that the slew has completed before writing to any of the Rev. A | Page 32 of 40 AD5412/AD5422 AD5410/AD5420 registers. The update clock frequency for any given value is the same for all output ranges. The step size, however, varies across output ranges for a given value of step size because the LSB size is different for each output range. Table 24 shows the range of programmable slew times for a fullscale change on any of the output ranges. The values in Table 24 were obtained using Equation 1. smoothing out the steps caused by the digital code increments, as shown in Figure 72. C1 C2 CAP1 The digital slew rate control feature results in a staircase formation on the current output, as shown in Figure 72. This figure also shows how the staircase can be removed by connecting capacitors to the CAP1 and CAP2 pins, as described in the IOUT Filtering Capacitors (LFCSP Package) section. 4kΩ BOOST DAC 12.5kΩ IOUT R1 TA = 25°C AVDD = 24V RLOAD = 300Ω 20 Figure 70. IOUT Filter Circuitry 25 15 20 0 10 20 30 40 50 60 TIME (ms) 70 80 90 100 110 10 NO CAPACITOR 10nF ON CAP1 10nF ON CAP2 47nF ON CAP1 47nF ON CAP2 5 Figure 68. Output Current Slewing Under Control of the Digital Slew Rate Control Feature 0 –0.5 IOUT FILTERING CAPACITORS (LFCSP PACKAGE) Capacitors can be placed between CAP1 and AVDD, and CAP2 and AVDD, as shown in Figure 69. 0 1.5 2.0 TIME (ms) 2.5 3.0 3.5 4.0 6.8 C1 TA = 25°C AVDD = 24V RLOAD = 300Ω C2 6.7 AVDD 06996-062 Figure 69. IOUT Filtering Capacitors The CAP1 and CAP2 pins are available only on the LFCSP package. The capacitors form a filter on the current output circuitry, as shown in Figure 70, reducing the bandwidth and the slew rate of the output current. Figure 71 shows the effect the capacitors have on the slew rate of the output current. To achieve significant reductions in the rate of change, very large capacitor values are required, which may not be suitable in some applications. In this case, the digital slew rate control feature can be used. The capacitors can be used in conjunction with the digital slew rate control feature as a means of Rev. A | Page 33 of 40 OUTPUT CURRENT (mA) CAP1 AD5412/ AD5422 CAP2 IOUT 1.0 Figure 71. Slew Controlled 4 mA to 20 mA Output Current Step Using External Capacitors on the CAP1 and CAP2 Pins AVDD GND 0.5 06996-142 0 –10 10ms RAMP, SR CLOCK = 0x1, SR STEP = 0x5 50ms RAMP, SR CLOCK = 0xA, SR STEP = 0x7 100ms RAMP, SR CLOCK = 0x8, SR STEP = 0x5 TA = 25°C AVDD = 24V RLOAD = 300Ω 15 6.6 6.5 6.4 6.3 NO EXTERNAL CAPS 10nF ON CAP1 10nF ON CAP2 6.2 6.1 –1 0 1 2 3 4 TIME (ms) 5 6 7 06996-043 5 OUTPUT CURRENT (mA) 10 06996-139 OUTPUT CURRENT (mA) 40Ω 06996-063 25 AVDD CAP2 8 Figure 72. Smoothing Out the Steps Caused by the Digital Slew Rate Control Feature AD5412/AD5422 Table 24. Programmable Slew Time Values in Seconds for a Full-Scale Change on Any Output Range Update Clock Frequency (Hz) 257,730 198,410 152,440 131,580 115,740 69,440 37,590 25,770 20,160 16,030 10,290 8280 6900 5530 4240 3300 1 0.25 0.33 0.43 0.50 0.57 0.9 1.7 2.5 3.3 4.1 6.4 7.9 9.5 12 15 20 2 0.13 0.17 0.21 0.25 0.28 0.47 0.87 1.3 1.6 2.0 3.2 4.0 4.8 5.9 7.7 9.9 4 0.06 0.08 0.11 0.12 0.14 0.24 0.44 0.64 0.81 1.0 1.6 2.0 2.4 3.0 3.9 5.0 8 0.03 0.04 0.05 0.06 0.07 0.12 0.22 0.32 0.41 0.51 0.80 1.0 1.2 1.5 1.9 2.5 Step Size (LSB) 16 0.016 0.021 0.027 0.031 0.035 0.06 0.11 0.16 0.20 0.26 0.40 0.49 0.59 0.74 0.97 1.24 Rev. A | Page 34 of 40 32 0.008 0.010 0.013 0.016 0.018 0.03 0.05 0.08 0.10 0.13 0.20 0.25 0.30 0.37 0.48 0.62 64 0.004 0.005 0.007 0.008 0.009 0.015 0.03 0.04 0.05 0.06 0.10 0.12 0.15 0.19 0.24 0.31 128 0.0020 0.0026 0.0034 0.0039 0.0044 0.007 0.014 0.020 0.025 0.03 0.05 0.06 0.07 0.09 0.12 0.16 AD5412/AD5422 APPLICATIONS INFORMATION CONTROLLER SERIAL CLOCK IN When driving inductive or poorly defined loads, connect a 0.01 μF capacitor between IOUT and GND. This ensures stability with loads above 50 mH. There is no maximum capacitance limit. The capacitive component of the load may cause slower settling. The digital slew rate control feature may also prove useful in this situation. SERIAL DATA OUT SYNC OUT TRANSIENT VOLTAGE PROTECTION The AD5412/AD5422 contain ESD protection diodes that prevent damage from normal handling. The industrial control environment can, however, subject I/O circuits to much higher transients. To protect the AD5412/AD5422 from excessively high voltage transients, external power diodes and a surge current limiting resistor are required, as shown in Figure 73. The constraint on the resistor value is that, during normal operation, the output level at IOUT must remain within its voltage compliance limit of AVDD – 2.5 V, and the two protection diodes and resistor must have appropriate power ratings. Further protection can be provided with transient voltage suppressors or transorbs; these are available as both unidirectional suppressors (protect against positive high voltage transients) and bidirectional suppressors (protect against both positive and negative high voltage transients) and are available in a wide range of standoff and breakdown voltage ratings. It is recommended that all field connected nodes be protected. AVDD RP RLOAD 06996-064 GND IOUT VIB VIC VID ENCODE DECODE ENCODE DECODE ENCODE DECODE ENCODE DECODE VOA VOB VOC VOD TO SCLK TO SDIN TO LATCH TO CLEAR 1 ADDITIONAL PINS OMITTED FOR CLARITY. Figure 74. Isolated Interface MICROPROCESSOR INTERFACING Microprocessor interfacing to the AD5412/AD5422 is via a serial bus that uses a protocol compatible with microcontrollers and DSP processors. The communications channel is a 3-wire minimum interface consisting of a clock signal, a data signal, and a latch signal. The AD5412/AD5422 require a 24-bit dataword with data valid on the rising edge of SCLK. For all interfaces, the DAC output update is initiated on the rising edge of LATCH. The contents of the registers can be read using the readback function. LAYOUT GUIDELINES In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. Design the printed circuit board (PCB) on which the AD5412/AD5422 is mounted so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5412/AD5422 is in a system where multiple devices require an analog ground-to-digital ground connection, make the connection at one point only. Establish the star ground point as close as possible to the device. AVDD AD5412/ AD5422 CONTROL OUT ADuM14001 VIA 06996-065 DRIVING INDUCTIVE LOADS Figure 73. Output Transient Voltage Protection GALVANICALLY ISOLATED INTERFACE In many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that may occur. The iCoupler® products from Analog Devices, Inc., provide voltage isolation in excess of 2.5 kV. The serial loading structure of the AD5412/AD5422 makes the parts ideal for isolated interfaces because the number of interface lines is kept to a minimum. Figure 74 shows a 4-channel isolated interface to the AD5412/ AD5422 using an ADuM1400. For further information, visit http://www.analog.com/icouplers. The AD5412/AD5422 should have ample supply bypassing of 10 μF in parallel with 0.1 μF on each supply located as close to the package as possible, ideally right up against the device. The 10 μF capacitors are the tantalum bead type. The 0.1 μF capacitor should have low effective series resistance (ESR) and low effective series inductance (ESI), such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. Rev. A | Page 35 of 40 AD5412/AD5422 To ensure that the junction temperature does not exceed 125°C while driving the maximum current of 24 mA directly into ground (also adding an on-chip current of 3 mA), reduce AVDD from the maximum rating to ensure that the package is not required to dissipate more power than previously stated (see Table 25, Figure 75, and Figure 76). LFCSP 2.0 1.5 TSSOP 1.0 0 THERMAL AND SUPPLY CONSIDERATIONS At the maximum ambient temperature of 85°C, the 24-lead TSSOP package can dissipate 950 mW, and the 40-lead LFCSP package can dissipate 1.42 mW. 40 45 50 55 60 65 70 75 AMBIENT TEMPERATURE (°C) 80 85 Figure 75. Maximum Power Dissipation vs. Ambient Temperature 45 43 LFCSP 41 SUPPLY VOLTAGE (V) The AD5412/AD5422 are designed to operate at a maximum junction temperature of 125°C. It is important that the devices not be operated under conditions that cause the junction temperature to exceed this value. Excessive junction temperature can occur if the AD5412/AD5422 are operated from the maximum AVDD while driving the maximum current (24 mA) directly to ground. In this case, control the ambient temperature or reduce AVDD. The conditions depend on the device package. 06996-066 0.5 39 TSSOP 37 35 33 31 29 06996-067 Avoid crossover of digital and analog signals. Traces on opposite sides of the PCB should run at right angles to each other. This reduces the effects of feed through the board. A microstrip technique is by far the best but not always possible with a double-sided board. In this technique, the component side of the board is dedicated to the ground plane, and signal traces are placed on the solder side. 2.5 POWER DISSIPATION (W) The power supply lines of the AD5412/AD5422 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with a digital ground to avoid radiating noise to other parts of the board. Never run these near the reference inputs. A ground line routed between the SDIN and SCLK lines helps reduce crosstalk between them (this is not required on a multilayer board that has a separate ground plane, but separating the lines helps). It is essential to minimize noise on the REFIN line because it couples through to the DAC output. 27 25 25 35 45 55 65 AMBIENT TEMPERATURE (°C) 75 85 Figure 76. Maximum Supply Voltage vs. Ambient Temperature Table 25. Thermal and Supply Considerations for Each Package Considerations Maximum Allowed Power Dissipation When Operating at an Ambient Temperature of 85°C TSSOP TJ max − TA Maximum Allowed Ambient Temperature When Operating from a Supply of 40 V and Driving 24 mA Directly to Ground Maximum Allowed Supply Voltage When Operating at an Ambient Temperature of 85°C and Driving 24 mA Directly to Ground TJ max − PD × θ JA = 125 − (40 × 0.028) × 42 = 78°C TJ max − PD × θ JA = 125 − (40 × 0.028) × 28 = 94°C T J max − T A 125 − 85 = = 34 V 0.028 × 42 AI DD × θ JA 125 − 85 TJ max − TA = = 51 V 0.028 × 28 AI DD × θ JA θ JA 125 − 85 = = 950 mW 42 Rev. A | Page 36 of 40 LFCSP T J max − T A 125 − 85 = = 1 .42 mW 28 θ JA AD5412/AD5422 Isolation between the AD5412/AD5422 and the backplane circuitry is provided with ADuM1400 and ADuM1200 iCoupler digital isolators; further information on iCoupler products is available at www.analog.com/icouplers. The internally generated digital power supply of the AD5412/ AD5422 powers the field side of the digital isolaters, removing the need to generate a digital power supply on the field side of the isolation barrier. The AD5412/AD5422 digital supply output supplies up to 5 mA, which is more than enough to supply the 2.8 mA requirements of the ADuM1400 and ADuM1200 operating at a logic signal frequency of up to 1 MHz. To reduce the number of isolators required, nonessential signals such as CLEAR can be connected to GND. FAULT and SDO can be left unconnected, reducing the isolation requirements to just three signals. INDUSTRIAL ANALOG OUTPUT MODULE Many industrial control applications have requirements for accurately controlled current and voltage output signals. The AD5412/AD5422 are ideal for such applications. Figure 77 shows the AD5412/AD5422 in a circuit design for an output module, specifically for use in an industrial control application. The design provides for a current or voltage output. The module is powered from a field supply of 24 V. This supplies AVDD directly. An inverting buck regulator generates the negative supply for AVSS. For transient overvoltage protection, transient voltage suppressors (TVS) are placed on all field accessible connections. A 24 V volt TVS is placed on each IOUT, VOUT, +VSENSE, and −VSENSE connection, and a 36 V TVS is placed on the field supply input. For added protection, clamping diodes are connected from the IOUT, VOUT, +VSENSE, and −VSENSE pins to the AVDD and AVSS power supply pins. If remote voltage load sensing is not required, the +VSENSE pin can be directly connected to the VOUT pin and the –VSENSE pin can be connected to GND. –15V 0.1µF ADuM1400 DIGITAL OUTPUTS VDD1 VDD2 VE2 NC VIA VOA VIB VOB VIC VOC VID VOD GND1 GND2 GND1 GND2 DIGITAL INPUTS MICROCONTROLLER BACKPLANE INTERFACE BACKPLANE SUPPLY VDD2 VDD1 VOA VIA VOB VIB GND2 GND1 0.1µF + INVERTING BUCK REGULATOR 24V FIELD SUPPLY 10µF SMAJ36CA 0.1µF 36V FIELD GROUND 4nF 10kΩ AVDD DVCC DVCC S ELECT CLEAR SELECT CLEAR LATCH SCLK SDIN FAULT SDO CCOMP +VSENSE 4.7kΩ VOUT AD5412/ AD54221 –VSENSE IOUT GND AVSS 100Ω REFOUT ADuM1200 REFIN +VSENSE +VOUT –VSENSE 18Ω IOUT 24V SMAJ24CA 0.1µF + –15V 1 ADDITIONAL PINS OMITTED FOR CLARITY. Figure 77. AD5412/AD5422 in an Industrial Analog Output Module Application Rev. A | Page 37 of 40 06996-068 10µF 0.1µF AD5412/AD5422 OUTLINE DIMENSIONS 5.02 5.00 4.95 7.90 7.80 7.70 24 13 4.50 4.40 4.30 1 3.25 3.20 3.15 EXPOSED PAD (Pins Up) 6.40 BSC 12 BOTTOM VIEW TOP VIEW 1.05 1.00 0.80 0.15 0.05 SEATING PLANE 0.10 COPLANARITY 0.65 BSC FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 8° 0° 0.20 0.09 0.30 0.19 0.75 0.60 0.45 061708-A 1.20 MAX COMPLIANT TO JEDEC STANDARDS MO-153-ADT Figure 78. 24-Lead Thin Shrink Small Outline Package, Exposed Pad [TSSOP_EP] (RE-24) Dimensions shown in millimeters 6.00 BSC SQ 0.60 MAX 0.60 MAX TOP VIEW 0.50 BSC 5.75 BSC SQ 0.50 0.40 0.30 12° MAX 0.80 MAX 0.65 TYP 0.30 0.23 0.18 1 4.25 4.10 SQ 3.95 EXPOSED PAD (BOT TOM VIEW) 21 20 11 10 0.25 MIN 4.50 REF 0.05 MAX 0.02 NOM SEATING PLANE 40 0.20 REF COPLANARITY 0.08 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2 Figure 79. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 6 mm × 6 mm Body, Very Thin Quad (CP-40-1) Dimensions shown in millimeters Rev. A | Page 38 of 40 072108-A PIN 1 INDICATOR 1.00 0.85 0.80 PIN 1 INDICATOR 31 30 AD5412/AD5422 ORDERING GUIDE Model AD5412AREZ 1 AD5412AREZ-REEL71 AD5412ACPZ-REEL1 AD5412ACPZ-REEL71 AD5422AREZ1 AD5422AREZ-REEL1 AD5422BREZ1 AD5422BREZ-REEL1 AD5422ACPZ-REEL1 AD5422ACPZ-REEL71 AD5422BCPZ-REEL1 AD5422BCPZ-REEL71 EVAL-AD5422EBZ 1 Resolution 12 Bits 12 Bits 12 Bits 12 Bits 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits IOUT TUE 0.5% FSR max 0.5% FSR max 0.5% FSR max 0.5% FSR max 0.5% FSR max 0.5% FSR max 0.3% FSR max 0.3% FSR max 0.5% FSR max 0.5% FSR max 0.3% FSR max 0.3% FSR max VOUT TUE 0.3% FSR max 0.3% FSR max 0.3% FSR max 0.3% FSR max 0.3% FSR max 0.3% FSR max 0.1% FSR max 0.1% FSR max 0.3% FSR max 0.3% FSR max 0.1% FSR max 0.1% FSR max Temperature Range −40°C to +85°C −40°C to +85°C −40°C to+85°C −40°C to+85°C −40°C to+85°C −40°C to+85°C −40°C to+85°C −40°C to+85°C −40°C to+85°C −40°C to+85°C −40°C to+85°C −40°C to+85°C Z = RoHS Compliant Part. Rev. A | Page 39 of 40 Package Description 24 Lead TSSOP_EP 24 Lead TSSOP_EP 40 Lead LFCSP_VQ 40 Lead LFCSP_VQ 24 Lead TSSOP_EP 24 Lead TSSOP_EP 24 Lead TSSOP_EP 24 Lead TSSOP_EP 40 Lead LFCSP_VQ 40 Lead LFCSP_VQ 40 Lead LFCSP_VQ 40 Lead LFCSP_VQ Evaluation Board Package Option RE-24 RE-24 CP-40-1 CP-40-1 RE-24 RE-24 RE-24 RE-24 CP-40-1 CP-40-1 CP-40-1 CP-40-1 AD5412/AD5422 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06996-0-8/09(A) Rev. A | Page 40 of 40