ETC NS32CG821A

October 1990
NS32CG821A microCMOS Programmable
1M Dynamic RAM Controller/Driver
General Description
Features
The NS32CG821A dynamic RAM controller provides a low
cost, single chip interface between dynamic RAM and the
NS32CG16. The NS32CG821A generates all the required
access control signal timing for DRAMs. An on-chip refresh
request clock is used to automatically refresh the DRAM
array. Refreshes and accesses are arbitrated on chip. If
necessary, a WAIT output inserts wait states into memory
access cycles, including burst mode accesses. RAS low
time during refreshes and RAS precharge time after refreshes and back to back accesses are guaranteed through the
insertion of wait states. Separate on-chip precharge counters for each RAS output can be used for memory interleaving to avoid delayed back to back accesses because of
precharge.
Y
Control
NS32CG821A
Y
Y
Y
Y
Y
Y
Y
Y
Y
Allows zero wait state operation
On chip high precision delay line to guarantee critical
DRAM access timing parameters
microCMOS process for low power
High capacitance drivers for RAS, CAS, WE and DRAM
address on chip
On chip support for page and static column DRAMs
Byte enable signals on chip allow byte writing with no
external logic
Selection of controller speeds: 20 MHz and 25 MHz
On board access refresh arbitration logic
Direct interface to the NS32CG16 microprocessor
4 RAS and 4 CAS drivers (the RAS and CAS configuration is programmable)
Ý of Pins
Ý of Address
(PLCC)
Outputs
68
10
Largest
DRAM
Possible
Direct Drive
Memory
Capacity
1 Mbit
8 Mbytes
Block Diagram
NS32CG821A DRAM Controller
TL/F/10126 – 1
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C1995 National Semiconductor Corporation
TL/F/10126
RRD-B30M105/Printed in U. S. A.
NS32CG821A microCMOS Programmable 1M Dynamic RAM Controller/Driver
PRELIMINARY
Table of Contents
6.0 ADDITIONAL ACCESS SUPPORT FEATURES
1.0 INTRODUCTION
6.1 Address Latches and Column Increment
2.0 SIGNAL DESCRIPTIONS
6.2 Delay CAS During Write Accesses
2.1 Address, R/W and Programming Signals
2.2 DRAM Control Signals
7.0 RAS AND CAS CONFIGURATION MODES
2.3 Refresh Signals
7.1 Byte Writing
2.4 Memory Access Signals
7.2 Memory Interleaving
2.5 Power Signals and Capacitor Input
7.3 Page/Burst Mode
2.6 Clock Inputs
8.0 PROGRAMMING AND RESETTING
3.0 MEMORY ACCESS
8.1 Mode Load Only Programming
4.0 REFRESH OPTIONS
8.2 Chip Selected Access Programming
4.1 Automatic Internal Refresh
8.3 External Reset
4.2 Refresh Cycle Types
8.4 Definition of Programming Bits
4.2.1 Conventional Refresh
4.2.2 Staggered Refresh
9.0 DRAM CRITICAL TIMING OPTIONS
9.1 Programming Values of tRAH and tASC
4.3 Clearing the Refresh Address Counter
9.2 Calculation of tRAH and tASC
5.0 WAIT STATE SUPPORT
10.0 ABSOLUTE MAXIMUM RATINGS
5.1 WAIT Output
11.0 DC ELECTRICAL CHARACTERISTICS
5.1.1 WAIT During Single Accesses
5.1.2 WAIT During Page/Burst Accesses
12.0 AC TIMING PARAMETERS
5.2 Dynamically Increasing the Number of Wait States
13.0 FUNCTIONAL DIFFERENCES
NSCG821A AND THE NSCG821
5.3 Guaranteeing RAS Low Time and RAS Precharge
Time
14.0 NSCG821A USER HINTS
2
BETWEEN
THE
1.0 Introduction
The controller has two types of refreshing available: conventional and staggered. Any refresh control mode can be
used with internal refreshing. In a conventional refresh, all of
the RAS outputs will be asserted and negated at once. In a
staggered refresh, the RAS outputs will be asserted one
positive clock edge apart.
The NS32CG821A has wait support available as programmable WAIT, which connects directly to the NS32CG16
CWAIT pin. This signal is used by the on-chip arbiter to
insert wait states to guarantee the arbitration between accesses and refreshes or precharge.
WAIT is asserted during the start of the access (ALE and
CS) and will negate a number of clock edges from the event
that starts the access RAS. After WAIT is negated, it will
stay negated until the next access. WAIT can also be programmed to toggle with ECAS inputs during a burst/page
mode access.
WAIT can be dynamically delayed further through the
WAITIN signal to the NS32CG821A.
The NS32CG821A has address latches, used to latch the
bank, row and column address inputs. Once the address is
latched, a column increment feature can be used to increment the column address. The address latches can also be
programmed to be fall through.
The RAS and CAS drivers can be configured to drive a one,
two, four or eight bank memory array. The ECAS signals can
then be used to select one of four CAS drivers for byte
writing with no external logic.
When configuring the NS32CG821A for more than one
bank, memory interleaving can be used. By tying the low
order address bits to the bank select lines, B0 and B1, sequential back to back accesses will not be delayed since
the NS32CG821A has separate precharge counters per
bank.
The following explains the terminology used in this data
sheet. The terms negated and asserted are used. Asserted
refers to a ‘‘true’’ signal. Thus, ‘‘ECAS0 asserted’’ means
the ECAS0 input is at a logic 0. The term ‘‘COLINC asserted’’ means the COLINC input is at a logic 1. The term negated refers to a ‘‘false’’ signal. Thus, ‘‘ECAS0 negated’’
means the ECAS0 input is at a logic 1. The term ‘‘COLINC
negated’’ means the input COLINC is at a logic 0. The table
shown below clarifies this terminology.
The NS32CG821A is a CMOS Dynamic RAM controller that
incorporates many advanced features including the capabilities of address latches, refresh counter, refresh clock, row,
column and refresh address multiplexer, delay line, refresh/
access arbitration logic and high capacitive drivers. The programmable system interface allows the NS32CG16 microprocessor to directly interface via the NS32CG821A to
DRAM arrays up to 8 Mbytes in size. (See Figure 3 for an
example.)
After power up, the NS32CG821A must first be reset and
programmed before accessing the DRAM. The chip is programmed through the address bus.
Resetting
Due to the differences in power supply characteristics, the
internal reset circuit may not always reset correctly. Therefore, an external (hardware) reset must be performed before
programming the chip.
There are two methods of programming the chip. The first
method, mode load only, is accomplished by asserting the
signal mode load, ML. A valid programming selection is presented on the row, column, bank and ECAS0 inputs, then
ML is negated. When ML is negated, the chip is programmed with the valid programming bits on the address
bus.
The second method, chip selected access, is accomplished
by asserting ML and performing a chip selected access.
When CS and TSO are asserted for the access, the chip is
programmed. During this programming access, the programming bits affecting the wait logic become effective immediately, allowing the access to terminate. After the access, ML is negated and the rest of the programming bits
take effect.
Once the NS32CG821A has been programmed, a 60 ms
initialization period is entered. During this time, the
NS32CG821A controller performs refreshes to the DRAM
array so further DRAM warm up cycles are unnecessary.
To access the DRAM, the signal ALE is asserted along with
CS to ensure a valid DRAM access. ALE asserting sets an
internal latch and only needs to be pulsed and not held
throughout the entire access. Once CS and ALE are both
asserted, WAIT is asserted, unless WAIT is programmed as
OT and a non-delayed access occurs, and follows CS until
the rising clock edge. This is not a problem since the
32CG16 will not process the WAIT signal until the end of
state T2. WAIT only has to guarantee that it meets the setup
time to this edge of CLK on which it is sampled. On the next
rising clock edge, RAS will be asserted for that access. The
NS32CG821A will place the row address on the DRAM address bus, guarantee the programmed value of row address
hold time of the DRAM, place the column address on the
DRAM address bus, guarantee the programmed value of
column address setup time and assert CAS. TSO can be
asserted anytime after the clock edge which starts the access RAS. RAS and CAS will extend until TSO is negated.
The NS32CG821A has greatly expanded refresh capabilities compared to other DRAM controllers.
When
using
internal
automatic
refreshing,
the
NS32CG821A will generate an internal refresh request from
the refresh request clock. The NS32CG821A will arbitrate
between the refresh requests and accesses. Assuming an
access is not currently in progress, a refresh will occur and
on the next positive clock edge, refreshing will begin. If an
access had been in progress, the refresh will begin after the
access has terminated.
Signal
Action
Logic Level
Active High
Asserted
High
Active High
Negated
Low
Active Low
Asserted
Low
Active Low
Negated
High
External Reset
The power up state can again be entered by asserting ML
and DISRFSH for a minimum of 16 positive edges of CLK.
After resetting if the user negates DISRFSH at least one
CLK period before negating ML as shown in Figure 1A, ML
negated will program the chip. If ML is negated before
DISRFSH as shown in Figure 1B , the chip will not be programmed. After the chip is programmed, the 60 ms initialization period will be entered into if this is the first programming
after power up or reset.
3
1.0 Introduction (Continued)
TL/F/10126 – 39
FIGURE 1A. Chip Reset and Programmed
TL/F/10126 – 40
FIGURE 1B. Chip Reset but Not Programmed
Note 1: The positive going edge of DISRFSH needs to be delayed a few nanoseconds after the positive going edge of ML. Any gate delay is sufficient.
4
Connection Diagram
TL/F/10126 – 2
Top View
FIGURE 2
Order Number NS32CG821AV-20 or NS32CG821AV-25
See NS Package Number V68A
TL/F/10126 – 48
*Standard components in any NS32CG16 design
FIGURE 3. NS32CG16 – NS32CG821A Connection Diagram (Note 1)
Note 1: This is only one possible way to connect the NS32CG821A. See Sections 7 and 8 for additional options and configurations for hookup.
5
2.0 Signal Descriptions
Pin
Name
Input/
Output
Description
2.1 ADDRESS, R/W AND PROGRAMMING SIGNALS
R0 – 9
I
ROW ADDRESS: These inputs are used to specify the row address during an access to the DRAM. They are
also used to program the chip when ML is asserted (except R10).
C0 – 9
I
COLUMN ADDRESS: These inputs are used to specify the column address during an access to the DRAM.
They are also used to program the chip when ML is asserted (except C10).
B0, B1
I
BANK SELECT: Depending on programming, these inputs are used to select a group of RAS and CAS
outputs to assert during an access. They are also used to program the chip when ML is asserted.
ECAS0 – 3
I
ENABLE CAS: These inputs are used to enable a single or group of CAS outputs when asserted. In
combination with the B0, B1 and the programming bits, these inputs select which CAS output or CAS outputs
will assert during an access. The ECAS signals can also be used to toggle a group of CAS outputs for page
mode accesses. They also can be used for byte write operations.
WIN
I
WRITE ENABLE IN: This input is used to signify a write operation to the DRAM. The WE output follows this
input. This input asserted will also cause CAS to delay to the next positive clock edge if address bit C9 is
asserted during programming.
COLINC
I
COLUMN INCREMENT: When the address latches are used, this input functions as COLINC. Asserting this
signal causes the column address to be incremented by one.
ML
I
MODE LOAD: This input signal, when low, enables the internal programming register that stores the
programming information.
2.2 DRAM CONTROL SIGNALS
Q0 – 9
O
DRAM ADDRESS: These outputs are the multiplexed output of the R0 – 9 and C0 – 9 and form the DRAM
address bus. These outputs contain the refresh address whenever refreshing is taking place. They contain
high capacitive drivers with 20X series damping resistors.
RAS0 – 3
O
ROW ADDRESS STROBES: For an access, these outputs are asserted to latch the row address contained
on the outputs Q0–9 into the DRAM. For refreshing, the RAS outputs are used to latch the refresh row
address contained on the Q0–9 outputs in the DRAM. These outputs contain high capacitive drivers with
20X series damping resistors.
CAS0 – 3
O
COLUMN ADDRESS STROBES: These outputs are asserted to latch the column address contained on the
outputs Q0–9 into the DRAM. These outputs have high capacitive drivers with 20X series damping resistors.
WE
O
WRITE ENABLE: This output asserted specifies a write operation to the DRAM. When negated, this output
specifies a read operation to the DRAM. This output has a high capacitive driver and a 20X series damping
resistor.
2.3 REFRESH SIGNALS
CLRF
I
CLEAR REFRESH: This pin, in conjunction with DISRFSH is used to clear the internal refresh counter.
DISRFSH
I
DISABLE REFRESH: When asserted with ML asserted for 16 positive edges of clock, the entire chip is reset
and when negated with CLRF asserted clears the internal refresh address counter.
2.4 MEMORY ACCESS
ALE
I
ADDRESS LATCH ENABLE: When ALE asserted along with CS causes an internal latch to be set. Once
this latch is set and precharge time has been met an access will start from the positive clock edge of CLK as
soon as possible. If Address Latch (B0 e 0) is programmed, the low going edge of this signal latches the
bank, row, and column address.
CS
I
CHIP SELECT: This input signal must be asserted to enable an access.
TSO
I
TIMING STATE OUTPUT: This input signal must be asserted some time after the first positive clock edge
after ALE has been asserted. When this signal is negated, RAS is negated for the access.
6
2.0 Signal Descriptions (Continued)
Pin
Name
Input/
Output
Description
2.4 MEMORY ACCESS (Continued)
WAIT
O
WAIT: This output can be programmed to insert wait states into a CPU access cycle. This signal can be
delayed by a number of positive clock edges or negative clock levels of CLK, depending on how it is
programmed, to increase the microprocessor’s access cycle through the insertion of wait states.
WAITIN
I
I
WAIT
INCREASE: This input can be used to dynamically increase the number of positive clock edges of
CLK until WAIT will be negated during a DRAM access.
2.5 POWER SIGNALS AND CAPACITOR INPUT
VCC
I
POWER: Supply Voltage.
GND
I
GROUND: Supply Voltage Reference.
CAP
I
CAPACITOR: This input is used by the internal PLL for stabilization. The value of the ceramic capacitor
should be 0.1 mF and should be connected between this input and ground.
2.6 CLOCK INPUTS
There are two clock inputs to the NS32CG821A, CLK and DELCLK. These two clocks may both be tied to the same clock input, or
they may be two separate clocks, running at different frequencies, asynchronous to each other.
CLK
I
SYSTEM CLOCK: This input may be in the range of 0 Hz up to 25 MHz. This input is generally a constant
frequency but it may be controlled externally to change frequencies or perhaps be stopped for some arbitrary
period of time.
This input provides the clock to the internal state machine that arbitrates between accesses and refreshes.
This clock’s positive edges and negative levels are used to extend the WAIT signal. This clock is also used
as the reference for the RAS precharge time and RAS low time during refresh.
All memory accesses are assumed to be synchronous to the system clock CLK.
DELCLK
I
DELAY LINE CLOCK: The clock input DELCLK, may be in the range of 6 MHz to 20 MHz and should be a
multiple of 2 (i.e., 6, 8, 10, 12, 14, 16, 18, 20 MHz) to have the NS32CG821A switching characteristics hold. If
DELCLK is not one of the above frequencies the accuracy of the internal delay line will suffer. This is
because the phase locked loop that generates the delay line assumes an input clock frequency of a multiple
of 2 MHz.
For example, if the DELCLK input is at 7 MHz and we choose a divide by 3 (program bits C0 – 2) this will
produce 2.333 MHz which is 16.667% off of 2 MHz. Therefore, the NS32CG821A delay line would produce
delays that are shorter (faster delays) than what is intended. If divide by 4 was chosen the delay line would
be longer (slower delays) than intended (1.75 MHz instead of 2 MHz). (See Section 10 for more information.)
This clock is also divided to create the internal refresh clock.
3.0 Memory Access
The NS32CG821A will guarantee the minimum row address
hold time, before switching the internal multiplexer to place
the column address on the DRAM address bus, Q0 – 9;
The NS32CG821A will guarantee the minimum column address setup time before asserting the appropriate CAS or
CASs;
An access to DRAM is initiated by two input signals: ALE
and CS. The access is always terminated by one signal:
TSO. These input signals should be synchronous to the input clock, CLK. Once an access has been requested by CS
and ALE, the NS32CG821A will guarantee the following:
The NS32CG821A will have the row address valid to the
DRAMs’ address bus, Q0–9 given that the row address setup time to the NS32CG821A was met;
The NS32CG821A will bring the appropriate RAS or RASs
low;
The NS32CG821A will hold the column address valid the
minimum specified column address hold time.
The memory access shown in Figure 4 is selected by negating the input B1 during programming. This access mode al-
7
3.0 Memory Access (Continued)
TL/F/10126 – 3
FIGURE 4. Memory Access
Sometime after the first positive edge of CLK after ALE and
CS have been asserted, the input TSO must be asserted.
Once TSO has been asserted, CS can be negated. Once
TSO is negated, RAS and CAS will be negated. ALE can
stay asserted several periods of CLK. However, ALE must
be negated before or during the period of CLK in which TSO
is negated.
There are 2 methods by which this chip can be used to do
read-modify-write access cycles. The first method involves
doing a late write access where the WIN input is asserted
some delay after CAS is asserted. The second method involves doing a page mode read access followed by a page
mode write access with RAS held low (see Figure 5 ).
lows accesses to DRAM to always be initiated from the positive edge of the system input clock, CLK. To initiate an
access, ALE is pulsed high and CS is asserted. Pulsing ALE
high and asserting CS, sets an internal latch which requests
an access. If the precharge time from the last access or
DRAM refresh had been met and a refresh of DRAM was
not in progress, the RAS or group of RASs would be initiated from the first positive edge of CLK. If a DRAM refresh is
in progress or precharge time is required, the controller will
wait until these events have taken place and assert RAS on
the next positive edge of CLK.
Once ALE and CS are both asserted, WAIT is asserted,
unless WAIT is programmed as OT and a non-delayed access occurs, and follows CS until the rising clock edge. This
is not a problem since the 32CG16 will not process the
WAIT signal until the end of state T2. WAIT only has to
guarantee that it meets the setup time to this edge of CLK
on which it is sampled.
*There may be idle states inserted here by the CPU.
TL/F/10126 – 5
FIGURE 5. Read-Modify-Write Access Cycle
8
3.0 Memory Access (Continued)
CASn must be toggled using the ECASn inputs and WIN has
to be changed from negated to asserted (read to write)
while CAS is negated. This method is better than changing
WIN from negated to asserted in a late write access because here a problem may arise with DATA IN and DATA
OUT being valid at the same time. This may result in a data
line trying to drive two different levels simultaneously. The
page mode method of a read-modify-write access allows
the user to have transceivers in the system because the
data in (read data) is guaranteed to be high impedance during the time the data out (write data) is valid.
TL/F/10126 – 6
Explanation of Terms
IRFRQ e Internal ReFresh ReQuest of the NS32CG821A. IRFRQ has the
ability to hold off a pending access.
IRFIP e Internal ReFresh In Progress
ACIP e ACcess In Progress. This means that either RAS is low for an
access or is in the process of transitioning low for an access.
4.0 Refresh Options
FIGURE 6. NS32CG821A Access/Refresh
Arbitration State Program
The NS32CG821A supports automatic internally controlled
refresh. Different types of refreshes can be performed.
These different types include all RAS refresh and staggered
refresh.
There are two inputs, DISRFSH and CLRF, associated with
refresh. There are also ten programming bits; R0 – 1, R9,
C0 – 6 and ECAS0 used to program the various types of refreshing.
The NS32CG821A will increment the refresh address counter automatically. The refresh address counter will be incremented once all the refresh RASs have been negated.
In every combination of internal refresh and refresh type,
the NS32CG821A is programmed to keep RAS asserted a
number of CLK periods. The values of RAS low time during
refresh are programmed with the programming bits R0 and
R1.
4.2 REFRESH CYCLE TYPES
Two different types of refresh cycles are available for use.
The two different types are mutually exclusive and can be
used with the internal refresh control. The two different refresh cycle types are: all RAS refresh and staggered RAS
refresh. In all refresh cycle types, the RAS precharge time is
guaranteed: between the previous access RAS ending and
the refresh RAS0 starting; between refresh RAS3 ending
and access RAS beginning; between burst refresh RASs.
4.2.1 Conventional RAS Refresh
A conventional refresh cycle causes RAS0 – 3 to all assert
from the first positive edge of CLK after refresh begins as
shown in Figure 8 . RAS0 – 3 will stay asserted until the number of positive edges of CLK programmed have passed. On
the last positive edge, RAS0 – 3 will be negated and the refresh cycle will end. This type of refresh cycle is programmed by negating address bit R9 during programming.
4.1 AUTOMATIC INTERNAL REFRESH
The NS32CG821A has an internal refresh clock. The period
of the refresh clock is generated from the programming bits
C0 – 3. Every period of the refresh clock, an internal refresh
request is generated. As long as a DRAM access is not
currently in progress and precharge time has been met, the
internal refresh request will generate an automatic internal
refresh. If a DRAM access is in progress, the NS32CG821A
on-chip arbitration logic will wait until the access is finished
before performing the refresh. The refresh/access arbitration logic can insert a refresh cycle between two accesses.
If the two accesses are back to back, the arbitration logic
can insert a refresh cycle into the beginning of the next
access. The CPU will wait to complete that access until the
refresh cycle is completed. However, the refresh arbitration
logic can not interrupt an access cycle in progress to perform a refresh. To enable automatic internally controlled refreshes, the input DISRFSH must be negated.
4.2.2 Staggered RAS Refresh
A staggered refresh staggers each RAS or group of RASs
by a positive edge of CLK as shown in Figure 9 . The number
of RASs, which will be asserted on each positive edge of
CLK, is determined by the RAS, CAS configuration mode
programming bits C4 – C6. If single RAS outputs are selected during programming, then each RAS will assert on successive positive edges of CLK. If two RAS outputs are selected during programming then RAS0 and RAS1 will assert
on the first positive edge of CLK after refresh cycle begins.
RAS2 and RAS3 will assert on the second positive edge of
CLK after refresh cycle begins. If all RAS outputs were selected during programming, all RAS outputs would assert on
the first positive edge of CLK after refresh cycle begins.
Each RAS or group of RASs will meet the programmed RAS
low time and then negate.
9
10
*IRFRQ and IRFIP are internal variables, they are only shown in the timing diagrams to make the diagrams easier to understand.
FIGURE 9. Staggered RAS Refresh
FIGURE 8. Conventional RAS Refresh
FIGURE 7. Automatic Internal Refresh with Internal Refresh Request (3T of RAS low during refresh programmed)
TL/F/10126 – 9
TL/F/10126 – 8
TL/F/10126 – 7
4.0 Refresh Options (Continued)
signer must ensure that the data from the DRAMs will be
present for the CPU to sample or that the data has been
written to the DRAM before allowing the CPU access cycle
to terminate.
4.0 Refresh Options (Continued)
4.3 CLEARING THE REFRESH ADDRESS COUNTER
The refresh address counter can be cleared by asserting
CLRF while DISRFSH is negated as shown in Figure 10 .
This can be used prior to a burst refresh of the entire memory array. An end-of-count signal can be generated from the
Q DRAM address outputs of the NS32CG821A and used to
negate CLRF.
The insertion of wait states also allows a CPU’s access cycle to be extended until the DRAM access has taken place.
The NS32CG821A inserts wait states into CPU access cycles due to; guaranteeing precharge time, refresh currently
in progress, user programmed wait states, and the WAITIN
signal being asserted. If one of these events is taking place
and the CPU starts an access, the NS32CG821A will insert
wait states into the access cycle, thereby increasing the
length of the CPU’s access. Once the event has been completed, the NS32CG821A will allow the access to take place
and stop inserting wait states.
There are six programming bits, R2 – R7; an input, WAITIN;
and an output that functions as WAIT.
TL/F/10126 – 10
FIGURE 10. Clearing the Refresh Address Counter
5.1 WAIT OUTPUT
If WAIT is sampled asserted by the CPU, wait states (extra
clock periods) are inserted into the current access cycle as
shown in Figure 11 . Once WAIT is sampled negated, the
access cycle is completed by the CPU. WAIT is asserted at
the beginning of a chip selected access and is programmed
to negate a number of positive edges and/or negative levels of CLK from the event that starts the access. WAIT can
also be programmed to function in page/burst mode applications. Once WAIT is negated during an access, and the
ECAS inputs are negated with TSO asserted, WAIT can be
programmed to toggle, following the ECAS inputs. Once
TSO is negated, ending the access, WAIT will stay negated
until the next chip selected access.
5.0 Wait State Support
Wait states allow a CPU’s access cycle to be increased by
one or multiple CPU clock periods. By increasing the CPU’s
access cycle, all signals associated with that access cycle
are extended. The CPU samples a wait line to determine if
another clock period should be inserted into the access cycle. If another clock period is inserted, the CPU will continue
to sample the input every CPU clock period until the input
signal changes polarity, allowing the CPU access cycle to
terminate. The user determines which value to select for
WAIT depending upon the CPU speed used and where the
user wants the CPU to sample its wait input during an access cycle.
The decision to terminate the CPU access cycle is directly
affected by the speed of the DRAMs used. The system de-
TL/F/10126 – 11
FIGURE 11. WAIT Type Output
11
5.0 Wait State Support (Continued)
0T during non delayed and delayed acceses: WAIT will stay
negated during a non-delayed access as shown in Figure
12 . During an access that is delayed, WAIT will assert at the
start of the access (CS and ALE) and negate from the positive edge of CLK that starts RAS for that access as shown
in Figure 13 .
5.1.1 Wait during Single Accesses
WAIT can be programmed to delay a number of positive
edges and/or negative levels of CLK. These options are
programmed through address bits R2 and R3 at programming time. The user is given four options described below.
TL/F/10126 – 12
FIGURE 12. Non-Delayed Access with WAIT 0T (WAIT is Sampled at the End of the ‘‘T2’’ Clock State)
TL/F/10126 – 13
FIGURE 13. Delayed Access with WAIT 0T
(‘‘2T’’ RAS Precharge, WAIT is Sampled at the End of the ‘‘T2’’ Clock State)
12
5.0 Wait State Support (Continued)
0T during non-delayed accesses and (/2T during delayed
accesses: WAIT will stay negated during a non-delayed access as shown in Figure 14 . During an access that is delayed, WAIT will assert at the start of the access (CS and
ALE) and negate on the negative level of CLK after the
positive edge of CLK that asserted RAS for that access as
shown in Figure 15 .
TL/F/10126 – 14
FIGURE 14. Non-Delayed Access with WAIT 0T (WAIT is Sampled at the ‘‘T3’’ Falling Clock Edge)
TL/F/10126 – 15
FIGURE 15. Delayed Access with WAIT (/2T (WAIT is Sampled at the ‘‘T3’’ Falling Clock Edge)
13
5.0 Wait State Support (Continued)
(/2T during non-delayed and delayed accesses: WAIT will
assert when ALE is asserted and CS is asserted. WAIT will
then negate on the negative level of CLK after the positive
edge of CLK that asserts RAS for the access as shown in
Figure 16 . During delayed accesses in both modes, WAIT
will assert at the start of the access and negate on the
negative level of CLK after the positive edge of CLK that
started RAS for that access as shown in Figure 17 .
TL/F/10126 – 16
FIGURE 16. Non-Delayed Access with WAIT (/2T
(WAIT is Sampled at the ‘‘T2’’ Falling Clock Edge)
TL/F/10126 – 17
FIGURE 17. Delayed Access with WAIT (/2T
(WAIT is Sampled at the ‘‘T2’’ Falling Clock Edge)
14
5.0 Wait State Support (Continued)
WAIT will assert at the beginning of the access and will
negate on the first positive edge of CLK after the positive
edge of CLK that starts RAS for the access as shown in
Figure 19 .
1T during non-delayed and delayed accesses. WAIT will assert from ALE asserted and CS asserted. WAIT will negate
from the next positive edge of CLK that asserts RAS for the
access as shown in Figure 18 . During delayed accesses,
TL/F/10126 – 18
FIGURE 18. Non-Delayed Access with WAIT 1T (WAIT is Sampled at the End of the ‘‘T2’’ Clock State)
TL/F/10126 – 19
FIGURE 19. Delayed Access with WAIT 1T (WAIT is Sampled at the End of the ‘‘T2’’ Clock State)
15
5.0 Wait State Support (Continued)
When ending WAIT from a negative level of CLK; if RAS is
asserted while CLK is high then WAIT will negate from the
negative edge of CLK; if RAS is asserted while CLK is low
then WAIT will negate from RAS asserting. When ending
WAIT from a positive edge of CLK, the user can think of the
positive edge of CLK that starts RAS as 0T and the next
positive edge of CLK as 1T. In a delayed access, the positive edge of CLK that starts RAS can be thought of as 0T
and the next positive edge as 1T.
0T: WAIT will be asserted when the ECAS inputs are negated with TSO remaining asserted. When a single or group of
ECAS inputs are asserted, WAIT will be negated as shown
in Figure 21 .
(/2T: WAIT will be asserted when the ECAS inputs are negated with TSO remaining asserted. When a single or group of
ECAS inputs are asserted again, WAIT will be negated from
the first negative level of CLK after a single ECAS or group
of ECASs are asserted as shown in Figure 22 .
1T: WAIT will be asserted when the ECAS inputs are negated with TSO remaining asserted. When a single or group of
ECAS inputs are asserted again, WAIT will be negated from
the first positive edge of CLK after a single ECAS or group
of ECASs are asserted as shown in Figure 23 .
When ending WAIT from a negative level of CLK; if the
ECASs are asserted while CLK is high then WAIT will negate from the negative edge of CLK, if the ECASs are asserted while CLK is low then WAIT will negate from the
ECASs asserting. When ending WAIT from a positive edge
of CLK, the positive edge of CLK that ECAS is setup to can
be thought of as 1T.
5.1.2 Wait during Page Burst Accesses
WAIT can be programmed to function differently during
page/burst types of accesses. During a page/burst access,
the ECAS inputs will be asserted then negated while TSO is
asserted. Through address bits R4 and R5, WAIT can be
programmed to assert and negate during this type of access. The user is given four programming options described
below.
No Wait States: In this case, WAIT will remain negated even
if the ECAS inputs are toggled as shown in Figure 20 .
TL/F/10126 – 20
FIGURE 20. No Wait States during Burst (WAIT is Sampled at the End of the ‘‘T3’’ Clock State)
TL/F/10126 – 21
FIGURE 21. 0T during Burst (WAIT is Sampled at the End of the ‘‘T3’’ Clock State)
16
5.0 Wait State Support (Continued)
TL/F/10126 – 22
FIGURE 22. (/2T during Burst Access (WAIT is Sampled at the ‘‘T3’’ Falling Clock Edge)
TL/F/10126 – 23
FIGURE 23. 1T during Burst Access (WAIT is Sampled at the End of the ‘‘T3’’ Clock State)
WAITIN can increase the number of positive edges in a
page/burst access. WAITIN can be permanently asserted in
systems requiring an increased number of wait states.
WAITIN can also be asserted and negated, depending on
the type of access. As an example, a user could connect
the DDIN output from the NS32CG16 to the WAITIN input.
This could be used to perform write accesses with 1 wait
state and read accesses with 2 wait states as shown in
Figure 24 .
5.2 DYNAMICALLY INCREASING
THE NUMBER OF WAIT STATES
The user can increase the number of positive edges of CLK
before WAIT is negated. With the input WAITIN asserted,
the user can delay WAIT negating either one or two more
positive edges of CLK. The number of edges is programmed
through address bit R6. If the user is increasing the number
of positive edges in a delay that contains a negative level,
the positive edges will be met before the negative level.
TL/F/10126 – 24
FIGURE 24. WAITIN Example (WAIT is Sampled at the End of ‘‘T2’’)
17
5.0 Wait State Support (Continued)
6.0 Additional Access
Support Features
5.3 GUARANTEEING RAS LOW TIME
AND RAS PRECHARGE TIME
To support the different modes of accessing, the
NS32CG821A have multiple access features. These features allow the user to take advantage of CPU or DRAM
functions. These additional features include: address latches and column increment for page/burst mode support; and
delay CAS, to allow the user with a multiplexed bus to ensure valid data is present before CAS is asserted.
The NS32CG821A will guarantee RAS precharge time between accesses; between refreshes; and between access
and refreshes. The programming bits R0 and R1 are used to
program combinations of RAS precharge time and RAS low
time referenced by positive edges of CLK. RAS low time is
programmed for refreshes only. During an access, the system designer guarantees the time RAS is asserted through
the NS32CG821A wait logic. Since inserting wait states into
an access increases the length of the CPU signals which
are used to create ALE and TSO, the time that RAS is asserted can be guaranteed.
Precharge time is also guaranteed by the NS32CG821A.
Each RAS output has a separate positive edge of CLK
counter. TSO is negated setup to a positive edge of CLK to
terminate the access. That positive edge is 1T. The next
positive edge is 2T. RAS will not be asserted until the programmed number of positive edges of CLK have passed.
Once the programmed precharge time has been met, RAS
will be asserted from the positive edge of CLK. However,
since there is a precharge counter per RAS, an access using another RAS will not be delayed. Precharge time before
a refresh is always referenced from the access RAS negating before RAS0 for the refresh asserting. After a refresh,
precharge time is referenced from RAS3 negating, for the
refresh, to the access RAS asserting.
6.1 ADDRESS LATCHES AND COLUMN INCREMENT
The address latches can be programmed, through programming bit B0, to either latch the address or remain permanently in fall-through mode. If the address latches are used
to latch the address, the rising edge of ALE places the
latches in fall-through. Once ALE is negated, the address
present on the row, column and bank inputs is latched.
Once the address is latched, the column address can be
incremented with the input COLINC. With COLINC asserted,
the column address is incremented.
If COLINC is asserted with all of the bits of the column address asserted, the column address will return to zero. COLINC can be used for sequential accesses of static column
DRAMs. COLINC can also be used with the ECAS inputs to
support sequential accesses to page mode DRAMs as
shown in Figure 25 . COLINC should only be asserted during
an access.
TL/F/10126 – 25
FIGURE 25. Column Increment
TL/F/10126 – 26
FIGURE 26. Delay CAS
18
of DRAM with 16-bit words and 2 parity bits. The
NS32CG821A can drive more than 72 DRAMs, but the AC
timing must be increased. Since the RAS and CAS outputs
are configurable, all RAS and CAS outputs should be used
for the maximum amount of drive.
6.0 Additional Access
Support Features (Continued)
6.2 DELAY CAS DURING WRITE ACCESSES
Address bit C9 asserted during programming will cause CAS
to be delayed until the first positive edge of CLK after RAS
is asserted when the input WIN is asserted. Delaying CAS
during write accesses ensures that the data to be written to
DRAM will be setup to CAS asserting as shown in Figure 26 .
If the possibility exists that data still may not be present
after the first positive edge of CLK, CAS can be delayed
further with the ECAS inputs. If address bit C9 is negated
during programming, read and write accesses will be treated
the same (with regard to CAS).
7.1 BYTE WRITING
By selecting a configuration in which all CAS outputs are
selected during an access, the ECAS inputs enable a single
or group of CAS outputs to select a byte (or bytes) in a
word. In this case, the RAS outputs are used to select which
of up to 4 banks is to be used as shown in Figure 29 . In
systems with a word size of 16 bits, the byte enables can be
gated with a high order address bit to produce four byte
enables which gives an equivalent to 8 banks of 16-bit
words as shown in Figure 30 . If less memory is required,
each CAS should be used to drive each nibble in the 16-bit
word as shown in Figures 27 and 28 .
7.0 RAS and CAS
Configuration Modes
7.2 MEMORY INTERLEAVING
Memory interleaving allows the cycle time of DRAMs to be
reduced by having sequential accesses to different memory
banks. Since the NS32CG821A have separate precharge
counters per bank, sequential accesses will not be delayed
if the accessed banks use different RAS outputs. To ensure
different RAS outputs will be used, a mode is selected
where either one or two RAS outputs will be asserted during
an access. The bank select or selects, B0 and B1, are then
tied to the least significant address bits, causing a different
The NS32CG821A allow the user to configure the DRAM
array to contain one, two, four or eight banks of DRAM.
Depending on the functions used, certain considerations
must be used when determining how to set up the DRAM
array. Programming address bits C4, C5 and C6 along with
bank selects, B0–1, and CAS enables, ECAS0–3, determine which RAS or group of RASs and which CAS or group
of CASs will be asserted during an access. Different memory schemes are described. The NS32CG821A is specified
driving a heavy load of 72 DRAMs, representing four banks
TL/F/10126 – 27
FIGURE 27. 1 Bank DRAM Array Setup for 16-Bit System (C6, C5, C4 e 011 during Programming)
TL/F/10126 – 28
FIGURE 28. 2 Banks DRAM Array Setup for 16-Bit System (C6, C5, C4 e 101 during Programming)
19
7.0 RAS and CAS Configuration Modes (Continued)
TL/F/10126 – 29
FIGURE 29. 4 Banks Array Setup for 16-Bit System (C6, C5, C4 e 110 during Programming)
TL/F/10126 – 30
FIGURE 30. 8 Bank DRAM Array for 16-Bit System (C6, C5, C4 e 1, 1, 0 during Programming)
20
7.0 RAS and CAS Configuration Modes (Continued)
to ensure that the page/burst accesses are to sequential
memory addresses, as shown in Figure 32 . The ECAS inputs may then be toggled with the NS32CG821A’s address
latches in fall-through mode, while TSO is asserted. The
ECAS inputs can also be used to select individual bytes. In
page or static column modes, the two address bits after the
page size can be tied to the bank select inputs to select a
new bank if the page size is exceeded.
group of RASs to assert during each sequential access as
shown in Figure 31 . In this figure there should be at least
one clock period of all RAS’s negated between different
RAS’s being asserted to avoid the condition of a CAS before RAS refresh cycle.
7.3 PAGE/BURST MODE
In a static column, page or burst mode system, the least
significant bits must be tied to the column address in order
TL/F/10126 – 31
FIGURE 31. Memory Interleaving (C6, C5, C4 e 1, 1, 0 during Programming)
TL/F/10126 – 32
*See table below for row, column & bank address bit map. A0 is used for byte addressing in this example.
Page Mode/Static Column Mode Page Size
Addresses
256 Bits/Page
512 Bits/Page
1024 Bits/Page
Column
Address
C0 – 7 e A1– 8
C8 – 9 e X
C0– 8 e A1– 9
C9 e X
C0– 9 e A1– 10
Row
Address
X
X
X
B0
B1
A9
A10
A10
A11
A11
A12
X e DON’T CARE, the user can do as he pleases.
FIGURE 32. Page, Static Column, Mode System
21
8.0 Programming and Resetting
ML, enabling the internal programming register. After ML is
asserted, a valid programming selection is placed on the
address bus (and ECAS0), then ML is negated. When ML is
negated, the value on the address bus (and ECAS0) is
latched into the internal programming register and the
NS32CG821A is programmed, as shown in Figure 33 . After
ML is negated, the NS32CG821A will enter the 60 ms initialization period only if this is the first programming after power
up or reset.
Using this method, a set of transceivers on the address bus
can be put at TRI-STATEÉ by the system reset signal. A
combination of pull-up and pull-down resistors can be used
on the address inputs of the NS32CG821A to select the
programming values, as shown in FIgure 34 .
The NS32CG821A must be programmed by one of two possible programming sequences before it can be used. Once
the chip is programmed, the bits effecting the wait logic become effective immediately, thus allowing the programming
bus cycle to end. At power up, the NS32CG821A must be
externally reset before programming. Initially, the programming bits are in an undefined state. After programming, the
NS32CG821A enters a 60 ms initialization period. During
this initialization period, the NS32CG821A performs refreshes about every 15 ms; this makes further DRAM warmup
cycles unnecessary. The chip can be programmed as many
times as the user wishes. After the first programming, the 60
ms initialization period will not be entered into unless the
chip is reset. During the 60 ms initialization period, internal
refreshes are taking place and the CPU is not allowed to
enter into a memory access cycle. If a memory access is
attempted, the NS32CG821A will send out wait states into
the processor until initialization is complete. The actual initialization time period is given by the following formula:
T e 4096*(Clock Divisor Select)
*(Refresh Clock Fine Tune)
/(DELCK Frequency)
8.2 CHIP SELECTED ACCESS PROGRAMMING
The chip can also be programmed by asserting ML and performing a chip selected access. ALE is disabled internally
until after programming. To program the chip using this
method, ML is asserted. After ML is asserted, CS is asserted and a valid programming selection is placed on the address bus. When TSO is asserted, the chip is programmed
with the programming selection on the address bus. After
TSO is negated, ML can be negated as shown in Figure 35 .
8.1 MODE LOAD ONLY PROGRAMMING
MODE LOAD, ML, asserted enables an internal 23-bit programmable register. To use this method, the user asserts
TL/F/10126 – 33
FIGURE 33. Mode Load Only Programming
TL/F/10126 – 34
*Pull-Up or Pull-Down Resistors on Each Address Input
FIGURE 34. Programming during System Reset
TL/F/10126 – 35
FIGURE 35. CS Access Programming
22
8.0 Programming and Resetting (Continued)
Using this method, various programming schemes can be
used. For example if extra upper address bits are available,
an unused high order address bit can be tied to the signal
ML. Using this method, one need only write to a page of
memory, thus asserting the high order bit and in turn programming the chip as shown in Figure 36 .
TL/F/10126 – 37
FIGURE 37. Programming the NS32CG821A
through the Address Bus and an I/O Port
Another simple way the chip can be programmed is the first
write after system reset. This method requires only a flipflop and an OR gate as shown in Figure 38. At reset, the flipflop is preset, which pulls the Q output low. Since WR is
negated, ML is not enabled. The first write access is used to
program the chip. When WR is asserted, ML is asserted.
WR negated clocks the flip-flop, negates ML, and programs
the NS32CG821A with the address and ECAS0 available at
that time. CS does not need to be asserted using this
method.
TL/F/10126 – 36
FIGURE 36. Programming the NS32CG821A
through the Address Bus Only
An I/O port can also be used to assert ML. After ML is
asserted, a chip selected access can be performed to program the chip. After the chip selected access, ML can be
negated through the I/O port as shown in Figure 37 .
TL/F/10126 – 38
FIGURE 38. Programming the NS32CG821A on the First CPU Write after Power Up
23
8.0 Programming and Resetting (Continued)
8.4 PROGRAMMING BIT DEFINITIONS (Notes 1 and 2)
Symbol
Description
B0
Address Latch Mode
0
1
ALE asserted latches the input row, column and bank address.
The row, column and bank latches are fall through.
C9
Delay CAS during WRITE Accesses
0
1
CAS is treated the same for both READ and WRITE accesses.
During WRITE accesses, CAS will be asserted by the event that occurs last: CAS asserted by the internal
delay line or CAS asserted on the positive edge of CLK after RAS is asserted.
C8
Row Address Hold Time
0
1
Row Address Hold Time e 25 ns minimum
Row Address Hold Time e 15 ns minimum
C7
Column Address Setup Time
0
1
Column Address Setup Time e 10 ns minimum
Column Address Setup Time e 0 ns minimum
C6, C5, C4
RAS and CAS Configuration Modes
0, 1, 1
RAS0–3 and CAS0–3 are all selected during an access. ECASn must be asserted for CASn to be asserted.
B1, B0 are not used during an access.
1, 0, 1
RAS and CAS pairs are selected by B1. ECASn must be asserted for CASn to be asserted.
B1 e 0 during an access selects RAS0–1 and CAS0 –1.
B1 e 1 during an access selects RAS2–3 and CAS2 –3.
B0 is not used during an access.
1, 1, 0
RAS singles are selected by B0–1. CAS0– 3 are all selected. ECASn must be asserted for CASn to be
asserted.
B1 e 0, B0 e 0 during an access selects RAS0 and CAS0 –3.
B1 e 0, B0 e 1 during an access selects RAS1 and CAS0 –3.
B1 e 1, B0 e 0 during an access selects RAS2 and CAS0 –3.
B1 e 1, B0 e 1 during an access selects RAS3 and CAS0 –3.
C3
Refresh Clock Fine Tune Divisor
0
Divide delay line/refresh clock further by 30 (If DELCLK/Refresh Clock Clock Divisor e 2 MHz e 15 ms
refresh period).
Divide delay line/refresh clock further by 26 (If DELCLK/Refresh Clock Clock Divisor e 2 MHz e 13 ms
refresh period).
1
C2, C1, C0
Delay Line/Refresh Clock Divisor Select
0, 0, 0
0, 0, 1
0, 1, 0
0, 1, 1
1, 0, 0
1, 0, 1
1, 1, 0
1, 1, 1
Divide DELCLK by 10 to get as close to 2 MHz as possible.
Divide DELCLK by 9 to get as close to 2 MHz as possible.
Divide DELCLK by 8 to get as close to 2 MHz as possible.
Divide DELCLK by 7 to get as close to 2 MHz as possible.
Divide DELCLK by 6 to get as close to 2 MHz as possible.
Divide DELCLK by 5 to get as close to 2 MHz as possible.
Divide DELCLK by 4 to get as close to 2 MHz as possible.
Divide DELCLK by 3 to get as close to 2 MHz as possible.
R9
Refresh Mode Select
0
1
RAS0–3 will all assert and negate at the same time during a refresh.
Staggered Refresh. RAS outputs during refresh are separated by one positive clock edge. Depending on the
configuration mode.
R6
Add Wait States to the Current Access if WAITIN is Low.
0
1
WAIT will be delayed by one additional positive edge of CLK.
WAIT will be delayed by two additional positive edges of CLK.
24
8.0 Programming and Resetting (Continued)
8.4 PROGRAMMING BIT DEFINITIONS (Continued)
Symbol
Description
R5, R4
WAIT during Burst (See Section 5.1.2)
0, 0
NO WAIT STATES; WAIT will remain negated during burst portion of access.
0, 1
1T; WAIT will assert when the ECAS inputs are negated with TSO asserted. WAIT will negate from the
positive edge of CLK after the ECASs have been asserted.
1, 0
(/2T; WAIT will assert when the ECAS inputs are negated with TSO asserted. WAIT will negate on the
negative level of CLK after the ECASs have been asserted.
1, 1
0T; WAIT will assert when the ECAS inputs are negated. WAIT will negate when the ECAS inputs are
asserted.
R3, R2
WAIT Delay Times (See Section 5.1.1)
0, 0
NO WAIT STATES; WAIT will remain high during non-delayed accesses. WAIT will negate when RAS is
negated during delayed accesses.
0, 1
(/2T; WAIT will negate on the negative level of CLK, after the access RAS.
1, 0
NO WAIT STATES, (/2 T; WAIT will remain high during non-delayed accesses. WAIT will negate on the
negative level of CLK, after the access RAS, during delayed accesses.
1, 1
1T; WAIT will negate on the positive edge of CLK after the access RAS.
R1, R0
RAS Low and RAS Precharge Time
0, 0
RAS asserted during refresh e 2 positive edges of CLK.
RAS precharge time e 1 positive edge of CLK.
0, 1
RAS asserted during refresh e 3 positive edges of CLK.
RAS precharge time e 2 positive edges of CLK.
1, 0
RAS asserted during refresh e 2 positive edges of CLK.
RAS precharge time e 2 positive edges of CLK.
1, 1
RAS asserted during refresh e 4 positive edges of CLK.
RAS precharge time e 3 positive edges of CLK.
Note 1: During programming ECAS0, B1, R7 have to be set to low, and R8 has to be set high.
Note 2: RAS and CAS configuration modes C6, C5, C4 e 000, 001, 010, 100 and 111 are reserved.
25
9.0 DRAM Critical Timing Parameters
The two critical timing parameters, shown in Figure 39 , that
must be met when controlling the access timing to a DRAM
are the row address hold time, tRAH, and the column address setup time, tASC. Since the NS32CG821A contains a
precise internal delay line, the values of these parameters
can be selected at programming time. These values will
also increase and decrease if DELCLK varies from 2 MHz.
The clock input, DELCLK, controls the internal delay line
and refresh request clock. DELCLK should be a multiple of
2 MHz. If DELCLK is not a multiple of 2 MHz, tRAH and
tASC will change. The new values of tRAH and tASC can be
calculated by the following formulas:
If tRAH was programmed to equal 15 ns then tRAH e
30*(((DELCLK Divisor)* 2 MHz/(DELCLK Frequency))b1)
a 15 ns.
If tRAH was programmed to equal 25 ns then tRAH e
30*(((DELCLK Divisor)* 2 MHz/(DELCLK Frequency))b1)
a 25 ns.
If tASC was programmed to equal 0 ns then tASC e 15*
((DELCLK Divisor)* 2 MHz/(DELCLK Frequency)) b 15 ns.
If tASC was programmed to equal 10 ns then tASC e 25*
((DELCLK Divisor)* 2 MHz/(DELCLK Frequency)) b 15 ns.
Since the values of tRAH and tASC are increased or decreased, the time to CAS asserted will also increase or decrease. These parameters can be adjusted by the following
formula:
Delay to CAS e Actual Spec. a Actual tRAH b
Programmed tRAH a Actual tASC b Programmed tASC.
9.1 PROGRAMMABLE VALUES OF tRAH AND tASC
The NS32CG821A allow the values of tRAH and tASC to be
selected at programming time. For each parameter, two
choices can be selected. tRAH, the row address hold time,
is measured from RAS asserted to the row address starting
to change to the column address. The two choices for tRAH
are 15 ns and 25 ns, programmable through address bit C8.
tASC, the column address setup time, is measured from the
column address valid to CAS asserted. The two choices for
tASC are 0 ns and 10 ns, programmable through address bit
C7.
9.2 CALCULATION OF tRAH AND tASC
There are two clock inputs to the NS32CG821A. These two
clocks, DELCLK and CLK can either be tied together to the
same clock or be tied to different clocks running asynchronously at different frequencies.
TL/F/10126 – 41
FIGURE 39. tRAH and tASC
26
10.0 Absolute Maximum Ratings (Note 1)
All Input or Output Voltage
with Respect to GNDÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀb0.5V to a 7V
Power Dissipation @ 20 MHzÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0.5W
ESD Rating to be determined.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Temperature under Bias ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0§ C to a 70§ C
Storage Temperature ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀb65§ C to a 150§ C
11.0 DC Electrical Characteristics TA e 0§ C to a 70§ C, VCC e 5V g 10%, GND e 0V
Symbol
Parameter
Conditions
Min
VIH
Logical 1 Input Voltage
Tested with a Limited
Functional Pattern
VIL
Logical 0 Input Voltage
Tested with a Limited
Functional Pattern
VOH1
Q and WE Outputs
IOH e b10 mA
VOL1
Q and WE Outputs
IOL e 10 mA
VOH2
All Outputs except Qs, WE
IOH e b3 mA
VOL2
All Outputs except Qs, WE
IOL e 3 mA
IIN
Input Leakage Current
VIN e VCC or GND
IIL ML
ML Input Current (Low)
VIN e GND
ICC1
Standby Current
CLK at 8 MHz (VIN e VCC or GND)
ICC1
Standby Current
ICC1
ICC2
Typ
Max
Units
2.0
VCC a 0.5
V
b 0.5
0.8
V
0.5
V
V
VCC b 1.0
VCC b 1.0
V
b 10
0.5
V
10
mA
200
mA
6
15
mA
CLK at 20 MHz (VIN e VCC or GND)
8
17
mA
Standby Current
CLK at 25 MHz (VIN e VCC or GND)
10
20
mA
Supply Current
CLK at 8 MHz (Inputs Active)
(ILOAD e 0) (VIN e VCC or GND)
20
40
mA
ICC2
Supply Current
CLK at 20 MHz (Inputs Active)
(ILOAD e 0) (VIN e VCC or GND)
40
75
mA
ICC2
Supply Current
CLK at 25 MHz (Inputs Active)
(ILOAD e 0) (VIN e VCC or GND)
50
95
mA
CIN*
Input Capacitance
fIN at 1 MHz
10
pF
*Note: CIN is not 100% tested.
12.0 AC Timing Parameters: NS32CG821A
300 – 315 Memory access parameters used in both single
and dual access applications
500 – 506 Programming parameters
Unless otherwise stated VCC e 5.0V g 10%, 0 k TA k
70§ C, the output load capacitance is typical for 4 banks of
18 DRAMs per bank, including trace capacitance (see Note
2).
Two different loads are specified:
CL e 50 pF loads on all outputs except
CL e 150 pF loads on Q0 – 9 and WE; or
Two speed selections are given, the NS32CG821A-20 and
the NS32CG821A-25. The differences between the two
parts are the maximum operating frequencies of the input
CLKs and the maximum delay specifications. Low frequency
applications may use the ‘‘b25’’ part to gain improved timing.
The AC timing parameters are grouped into sectional numbers as shown below. These numbers also refer to the timing diagrams.
1 – 36
Common parameters to all modes of operation
50 – 56
Difference parameters used to calculate;
RAS low time,
RAS precharge time,
CAS high time and
CAS low time
200 – 212 Refresh parameters
CH e 50 pF loads on all outputs except
CH e 125 pF loads on RAS0 – 3 and CAS0 –3 and
CH e 380 pF loads on Q0 – 9 and WE.
27
12.0 AC Timing Parameters: NS32CG821A (Continued)
Unless otherwise stated VCC e 5.0V g 10%, 0§ C k TA k 70§ C, the output load capacitance is typical for 4 banks of 18 DRAMs
per bank, including trace capacitance (see Note 2).
CH e 50 pF loads on all outputs except
Two different loads are specified:
CH e 125 pF loads on RAS0 – 3 and CAS0 –3 and
CL e 50 pF loads on all outputs except
CL e 150 pF loads on Q0–9 and WE; or
CH e 380 pF loads on Q0 – 9 and WE.
Number
Symbol
Common Parameter
Description
NS32CG821A-20
NS32CG821A-25
CL
CL
CH
CH
Min
Max
Min
Max
Min
Max
Min
Max
1
fCLK
CLK Frequency
0
20
0
20
0
25
0
25
2
tCLKP
CLK Period
50
50
40
40
3, 4
tCLKPW
CLK Pulse Width
15
15
12
12
5
fDCLK
DELCLK Frequency
5
20
5
20
5
20
5
20
6
tDCLKP
DELCLK Period
50
200
50
200
50
200
50
200
7, 8
tDCLKPW
DELCLK Pulse Width
15
15
12
12
9a
tPRASCAS0
RAS Asserted to CAS Asserted
(tRAH e 15 ns, tASC e 0 ns)
30
30
30
30
9b
tPRASCAS1
RAS Asserted to CAS Asserted
(tRAH e 15 ns, tASC e 10 ns)
40
40
40
40
9c
tPRASCAS2
(RAS Asserted to CAS Asserted
(tRAH e 25 ns, tASC e 0 ns)
40
40
40
40
9d
tPRASCAS3
(RAS Asserted to CAS Asserted
(tRAH e 25 ns, tASC e 10 ns)
50
50
50
50
10a
tRAH
Row Address Hold Time (tRAH e 15)
15
15
15
15
10b
tRAH
Row Address Hold Time (tRAH e 25)
25
25
25
25
11a
tASC
Column Address Setup Time (tASC e 0)
0
0
0
0
11b
tASC
Column Address Setup Time (tASC e 10)
10
10
10
10
12
tPCKRAS
CLK High to RAS Asserted
following Precharge
27
32
22
26
13
tPARQRAS
TSO Negated to RAS Negated
38
43
31
35
14
tPENCL
ECAS0–3 Asserted to CAS Asserted
23
31
20
27
15
tPENCH
ECAS0–3 Negated to CAS Negated
25
33
20
27
16
tPARQCAS
TSO Negated to CAS Negated
60
68
47
54
17
tPCLKWH
CLK to WAIT Negated
39
39
24
31
19
tPEWL
ECAS Negated to WAIT Asserted
during a Burst Access
44
44
36
36
20
tSECK
ECAS Asserted Setup to CLK High to
Recognize the Rising Edge of CLK
during a Burst Access
24
5
24
19
23
tSWCK
WAITIN Asserted Setup to CLK
24
tPWINWEH
WIN Asserted to WE Asserted
34
44
27
37
25
tPWINWEL
WIN Negated to WE Negated
34
44
27
37
26
tPAQ
Row, Column Address Valid to
Q0–9 Valid
29
38
26
35
27
tPCINCQ
COLINC Asserted to Q0–9
Incremented
34
43
30
39
28
tSCINEN
COLINC Asserted Setup to ECAS
Asserted to Ensure tASC e 0 ns
18
28
5
19
19
5
17
5
19
12.0 AC Timing Parameters: NS32CG821A (Continued)
Unless otherwise stated VCC e 5.0V g 10%, 0§ C k TA k 70§ C, the output load capacitance is typical for 4 banks of 18 DRAMs
per bank, including trace capacitance (see Note 2).
CH e 50 pF loads on all outputs except
Two different loads are specified:
CL e 50 pF loads on all outputs except
CH e 125 pF loads on RAS0 – 3 and CAS0 –3 and
CL e 150 pF loads on Q0–9 and WE; or
CH e 380 pF loads on Q0 – 9 and WE.
Number
Symbol
Common Parameter
Description
Min
NS32CG821A-20
NS32CG821A-25
CL
CL
CH
Max
Min
Max
Min
CH
Max
Min
Max
29a
tSARQCK1
TSO Negated Setup to CLK
High with 1 Period of Precharge
46
46
37
37
29b
tSARQCK2
TSO Negated Setup to CLK High with
l 1 Period of Precharge Programmed
19
19
15
15
31
tPCKCAS
CLK High to CAS Asserted
when Delayed by WIN
32
tSCADEN
Column Address Setup to ECAS
Asserted to Guarantee tASC e 0
14
15
14
16
33
tWCINC
COLINC Pulse Width
20
20
20
20
34a
tPCKCL0
CLK High to CAS Asserted following
Precharge (tRAH e 15 ns, tASC e 0 ns)
81
89
72
79
34b
tPCKCL1
CLK High to CAS Asserted following
Precharge (tRAH e 15 ns, tASC e 10 ns)
91
99
82
89
34c
tPCKCL2
CLK High to CAS Asserted following
Precharge (tRAH e 25 ns, tASC e 0 ns)
91
99
82
89
34d
tPCKCL3
CLK High to CAS Asserted following
Precharge (tRAH e 25 ns, tASC e 10 ns)
101
109
92
99
35
tCAH
Column Address Hold Time
(Interleave Mode Only)
36
tPCQR
CAS Asserted to Row Address
Valid (Interleave Mode Only)
31
32
32
90
29
39
25
32
90
32
32
90
90
12.0 AC Timing Parameters: NS32CG821A (Continued)
Unless otherwise stated VCC e 5.0V g 10%, 0§ C k TA k 70§ C, the output load capacitance is typical for 4 banks of 18 DRAMs
per bank, including trace capacitance (see Note 2).
CH e 50 pF loads on all outputs except
Two different loads are specified:
CL e 50 pF loads on all outputs except
CH e 125 pF loads on RAS0 – 3 and CAS0 –3 and
CL e 150 pF loads on Q0–9 and WE; or
CH e 380 pF loads on Q0 – 9 and WE.
NS32CG821A-20
Number
Difference Parameter
Description
Symbol
CL
Min
50
tD1
NS32CG821A-25
CH
Max
Min
CL
Max
Min
CH
Max
Min
Max
(TSO Negated to RAS
Negated) Minus (CLK High to RAS
Asserted)
16
16
14
14
51
tD2
(CLK High to Refresh RAS Negated)
Minus (CLK High to RAS Asserted)
13
13
11
11
53
tD3b
(CLK High to RAS Asserted
Minus (TSO Negated to RAS Negated)
4
4
4
4
54
tD4
(ECAS Asserted to CAS Asserted)
Minus (ECAS Negated to CAS Negated)
55
tD5
(CLK to Refresh RAS Asserted) Minus
(CLK to Refresh RAS Negated)
b7
7
b7
7
6
b7
7
6
b7
7
6
6
Unless otherwise stated VCC e 5.0V g 10%, 0§ C k TA k 70§ C, the output load capacitance is typical for 4 banks of 18 DRAMs
per bank, including trace capacitance (see Note 2).
CH e 50 pF loads on all outputs except
Two different loads are specified:
CL e 50 pF loads on all outputs except
CH e 125 pF loads on RAS0 – 3 and CAS0 –3 and
CL e 150 pF loads on Q0–9 and WE; or
CH e 380 pF loads on Q0 – 9 and WE.
NS32CG821A-20
Number
Symbol
Refresh Parameter
Description
CL
Min
NS32CG821A-25
CH
Max
Min
CL
Max
Min
CH
Max
Min
Max
207
tPCKRFRASH
CLK High to Refresh RAS Negated
35
40
29
33
208
tPCKRFRASL
CLK High to Refresh RAS Asserted
28
33
23
27
30
12.0 AC Timing Parameters: NS32CG821A (Continued)
Unless otherwise stated VCC e 5.0V g 10%, 0§ C k TA k 70§ C, the output load capacitance is typical for 4 banks of 18 DRAMs
per bank, including trace capacitance (see Note 2).
CH e 50 pF loads on all outputs except
Two different loads are specified:
CL e 50 pF loads on all outputs except
CH e 125 pF loads on RAS0 – 3 and CAS0 –3 and
CL e 150 pF loads on Q0–9 and WE; or
CH e 380 pF loads on Q0 – 9 and WE.
Number
Symbol
Memory Access
Parameter Description
Min
NS32CG821A-20
NS32CG821A-25
CL
CL
CH
Max
Min
Max
Min
CH
Max
Min
300
tSCSCK
CS Asserted to CLK High
14
14
13
13
301a
tSALECKNL
ALE Asserted Setup to CLK High
Not Using On-Chip Latches or
if Using On-Chip Latches and
B0, B1, Are Constant, Only 1 Bank
16
16
15
15
ALE Asserted Setup to CLK High,
if Using On-Chip Latches if B0, B1
Can Change, More Than One Bank
29
29
29
29
301b
tSALECKL
302
tWALE
ALE Pulse Width
18
18
13
13
303
tSBADDCK
Bank Address Valid Setup to CLK High
20
20
18
18
304
tSADDCK
Row, Column Valid Setup to
CLK High to Guarantee
tASR e 0 ns
11
15
11
16
Row, Column, Bank Address
Held from ALE Negated
(Using On-Chip Latches)
10
10
8
8
Row, Column, Bank Address
Setup to ALE Negated
(Using On-Chip Latches)
3
3
2
2
305
306
tHASRCB
tSRCBAS
Max
307
tPCKRL
CLK High to RAS Asserted
27
32
22
26
308a
tPCKCL0
CLK High to CAS Asserted
(tRAH e 15 ns, tASC e 0 ns)
81
89
72
79
308b
tPCKCL1
CLK High to CAS Asserted
(tRAH e 15 ns, tASC e 10 ns)
91
99
82
89
308c
tPCKCL2
CLK High to CAS Asserted
(tRAH e 25 ns, tASC e 0 ns)
91
99
82
89
308d
tPCKCL3
CLK High to CAS Asserted
(tRAH e 25 ns, tASC e 10 ns)
101
109
92
99
309
tHCKALE
ALE Negated Hold from CLK High
310
tSWINCK
WIN Asserted Setup to CLK High that
starts access RAS
to Guarantee CAS is Delayed
0
0
0
0
b 21
b 21
b 16
b 16
311
tPCSWL
CS Asserted to WAIT Asserted
26
26
22
22
312
tPCSWH
CS Negated to WAIT Negated
30
30
25
25
314
tPALEWL
ALE Asserted to WAIT Asserted
(CS is Already Asserted)
35
35
29
29
315
316
TSO Negated to CLK High That Starts
Access RAS to Guarantee tASR e 0 ns
ttPCKCV0
CLK to Column Addr. Valid
(tRAH e 15 ns, tASC e 0 ns)
41
45
78
31
34
87
39
60
75
12.0 AC Timing Parameters: NS32CG821A (Continued)
Unless otherwise stated VCC e 5.0V g 10%, 0§ C k TA k 70§ C, the output load capacitance is typical for 4 banks of 18 DRAMs
per bank, including trace capacitance (see Note 2).
CH e 50 pF loads on all outputs except
Two different loads are specified:
CL e 50 pF loads on all outputs except
CH e 125 pF loads on RAS0 – 3 and CAS0 –3 and
CL e 150 pF loads on Q0–9 and WE; or
CH e 380 pF loads on Q0 – 9 and WE.
Number
Symbol
Programming
Parameter Description
Min
NS32CG821A-20
NS32CG821A-25
CL
CL
CH
Max
8
Min
8
Max
Min
CH
Max
7
Min
500
tHMLADD
Mode Address Held from ML Negated
501
tSADDML
Mode Address Setup to ML Negated
6
6
6
6
502
tWML
ML Pulse Width
15
15
15
15
503
tSADAQML
Mode Address Setup to TSO Asserted
0
0
0
0
504
tHADAQML
Mode Address Held from TSO Asserted
51
51
38
38
505
tSCSARQ
CS Asserted Setup to
TSO Asserted
6
6
6
6
506
tSMLARQ
ML Asserted Setup to TSO Asserted
10
10
10
10
Max
7
Note 1: ‘‘Absolute Maximum Ratings’’ are the values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation.
Note 2: Input pulse 0V to 3V; tR e tF e 2.5 ns. Input reference point on AC measurements is 1.5V. Output reference points are 2.4V for High and 0.8V for Low.
Note 3: AC Production testing is done at 50 pF.
TL/F/10126 – 42
FIGURE 40. Clock, DELCLK Timing
TL/F/10126 – 43
FIGURE 41. 200: Refresh Timing
32
12.0 AC Timing Parameters: NS32CG821A (Continued)
TL/F/10126 – 44
FIGURE 42. 300: Memory Access Timing
33
12.0 AC Timing Parameters: NS32CG821A (Continued)
TL/F/10126 – 45
(Programmed as C4 e 1, C5 e 1, C6 e 1)
FIGURE 43. 300: Access Interleaving
34
12.0 AC Timing Parameters: NS32CG821A (Continued)
TL/F/10126 – 46
FIGURE 44. 400: COLINC Page/Static Column Access Timing
TL/F/10126 – 47
FIGURE 45. 500: Programming
35
13.0 Timing Differences Between the NS32CG821A and the NS32CG821
The only differences between the NS32CG821A and the NS32CG821 are AC timing. The 4 tables below list the differences.
TABLE I
NS32CG821-25
Number
Symbol
Common Parameter
Description
CL
Min
NS32CG821A-25
CH
Max
Min
CL
Max
Min
CH
Max
Min
Max
10a
tRAH
Row Address Hold
Time (tRAH e 15)
17
15
15
15
10b
tRAH
Row Address Hold
Time (tRAH e 25)
27
25
25
25
11a
tASC
Column Address Setup
Time (tASC e 0)
2
0
0
0
11b
tASC
Column Address Setup
Time (tASC e 10)
12
10
10
10
17
tPCLKWH
CLK to WAIT Negated
39
39
24
31
19
tPEWL
ECAS Negated to WAIT
Asserted During a Burst Access
34
34
36
36
24
tPWINWEH
WIN Asserted to WE Asserted
34
44
27
37
25
tWINWEL
WIN Negated to WE Negated
31
41
27
37
28
tSCINEN
COLINC Asserted to Q0–9
Incremented
15
17
17
19
29a
tSARQCK1
TSO Negated Setup to CLK
High with 1 Period of Precharge
34
34
37
37
TABLE II
Number
Symbol
NS32CG821-25
Difference Parameter
Description
CL
Min
55
tD5
NS32CG821A-25
CH
Max
(CLK to Refresh RAS Asserted)
Minus (CLK to Refresh RAS Negated)
Min
CL
Max
5
Min
CH
Max
5
Min
Max
6
6
TABLE III
Number
Symbol
NS32CG821-25
Memory Access
Parameter Description
CL
Min
NS32CG821A-25
CH
Max
Min
CL
Max
Min
CH
Max
Min
Max
312
tPCSWL
CS Negated to WAIT Negated
22
22
25
25
314
tPALEWL
ALE Asserted to WAIT Asserted
(CS is Already Asserted)
39
39
29
29
316
tPCKCVO
CLK to Column Address Valid
(tRAH e 15 ns, tASC e 0 ns)
66
75
60
75
TABLE IV
Number
Symbol
NS32CG821-25
Programming Parameter
Description
CL
Min
NS32CG821A-25
CH
Max
Min
CL
Max
Min
CH
Max
Min
500
tHMLADD
Mode Address Held
from ML Negated
5
5
7
7
504
tHADAQML
Mode Address Held
from TSO Asserted
29
29
38
38
36
Max
14.0 NS32CG821A User Hints
7. ECAS0 should be held low during programming if the user
wishes that the NS32CG821A be compatible with
NSCG821 design.
1. All inputs to the NS32CG821A should be tied high, low or
the output of some other device.
Note: One signal is active high. COLINC should be tied low to disable.
8. PARAMETER CHANGES DUE TO LOADING
All A.C. parameters are specified with the equivalent load
capacitances, including traces, of 64 DRAMs organized
as 4 banks of 18 DRAMs each. Maximums are based on
worst-case conditions. If an output load changes then the
A.C. timing parameters associated with that particular
output must be changed. For example, if we changed our
output load to
C e 250 pF loads on RAS0 – 3 and CAS0 –3
2. Each ground on the NS32CG821A must be decoupled to
the closest on-chip supply (VCC) with 0.1 mF ceramic capacitor. This is necessary because these grounds are
kept separate inside the NS32CG821A. The decoupling
capacitors should be placed as close as possible with short leads to the ground and supply pins of the
NS32CG821A.
3. The output called ‘‘CAP’’ should have a 0.1 mF capacitor
to ground.
4. The NS32CG821A has 20X series damping resistors built
into the output drivers of RAS, CAS, address and WE.
Space should be provided for external damping resistors
on the printed circuit board (or wire-wrap board) because
they may be needed. The value of these damping resistors (if needed) will vary depending upon the output, the
capacitance of the load, and the characteristics of the
trace as well as the routing of the trace. The value of the
damping resistor also may vary between the wire-wrap
board and the printed circuit board. To determine the value of the series damping resistor it is recommended to
use an oscilloscope and look at the furthest DRAM from
the NS32CG821A. The undershoot of RAS, CAS, WE and
the addresses should be kept to less than 0.5V below
ground by varying the value of the damping resistor. The
damping resistors should be placed as close as possible
with short leads to the driver outputs of the
NS32CG821A.
5. The circuit board must have a good VCC and ground
plane connection. If the board is wire-wrapped, the VCC
and ground pins of the NS32CG821A, the DRAM associated logic and buffer circuitry must be soldered to the
VCC and ground planes.
6. The traces from the NS32CG821A to the DRAM should
be as short as possible.
C e 760 pF loads on Q0 – 9 and WE
we would have to modify some parameters (not all calculated here)
$308a Clock to CAS asserted
(tRAH e 15 ns, tASC e 0 ns)
A ratio can be used to figure out the timing change per
change in capacitance for a particular parameter by using
the specifications and capacitances from heavy and light
load timing.
$308a w/heavy load b $308a w/light load
CH(CAS) b CL(CAS)
79 ns b 72 ns
7 ns
e
e
125 pF b 50 pF
75 pF
$308a (actual) e (capacitance difference c
ratio) a $308a (specified)
7 ns
e 250 pF b 125 pF
a 79 ns
75 pF
e 11.7 ns a 79 ns
e 90.7 ns @ 250 pF load
9. It is recommended that the user perform an external
hardware reset of the NSCG821A before programming
and using the chip. A hardware reset consists of asserting both ML and DISRFSH for a minimum of 16 positive
edges of CLK.
Ratio e
#
37
J
NS32CG821A microCMOS Programmable 1M Dynamic RAM Controller/Driver
Physical Dimensions inches (millimeters)
Plastic Chip Carrier (V)
Order Number NS32CG821AV-20 or NS32CG821AV-25
NS Package Number V68A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
National Semiconductor
Corporation
1111 West Bardin Road
Arlington, TX 76017
Tel: 1(800) 272-9959
Fax: 1(800) 737-7018
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
National Semiconductor
Europe
Fax: (a49) 0-180-530 85 86
Email: cnjwge @ tevm2.nsc.com
Deutsch Tel: (a49) 0-180-530 85 85
English Tel: (a49) 0-180-532 78 32
Fran3ais Tel: (a49) 0-180-532 93 58
Italiano Tel: (a49) 0-180-534 16 80
National Semiconductor
Hong Kong Ltd.
13th Floor, Straight Block,
Ocean Centre, 5 Canton Rd.
Tsimshatsui, Kowloon
Hong Kong
Tel: (852) 2737-1600
Fax: (852) 2736-9960
National Semiconductor
Japan Ltd.
Tel: 81-043-299-2309
Fax: 81-043-299-2408
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.