Data Sheet
JulY 2010
AR8032 Integrated 10/100 Fast Ethernet Transceiver
General Description
The Atheros AR8032 Fast Ethernet transceiver
is a highly integrated physical layer device that
transmits and receives high-speed data over
standard category 5 (CAT 5) unshielded
twisted pair cable.
The AR8032 is compliant with 100 BASE-TX
and 10 BASE-T IEEE 802.3 standards. The
AR8032 device uses advanced mixed-signal
processing technology and integrates functions
such as adaptive equalization, and timing
recovery to deliver substantial power savings
and operation in noisy environments.
The AR8032 device supports the Media
Independent Interface (MII) and Reduced
Media Independent Interface (RMII) for direct
connection to a Fast Ethernet-capable MAC.
The AR8032 supports the Atheros Cable
Diagnostic Test (CDT) feature, which uses Time
Domain Reflectometry (TDR) technology to
quickly and remotely identify potential cable
malfunctions without deploying field support
personnel or bringing down the network. The
AR8032 solution detects and reports issues
such as PHY malfunctions, bad/marginal cable
or patch cord segments or connectors, thus
significantly reducing installation time, cable
debug efforts, and overall network support
cost.
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Manufactured in a standard CMOS process, the
AR8032 is packaged in a 32-pin QFN, featuring
a small body size of 5 x 5mm.
Features
■ 10/100 BASE-T IEEE 802.3 compliant
■ Supports MII/RMII interface
■ Low power modes with internal automatic
DSP power saving scheme
■ Fully integrated digital adaptive equalizers
All digital baseline wander correction
■ Supports external 25 MHz clock source in
MII mode
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■ Supports external 50 MHz clock source in
■
■
■
■
■
■
■
■
■
RMII mode
Automatic speed downshift mode
Automatic MDI/MDIX crossover
Automatic polarity correction
Loopback modes for diagnostics
IEEE 802.3u compliant Auto-Negotiation
Software programmable LED modes
Cable Diagnostic Test (CDT)
Requires only one 3.3V power supply
32-pin QFN 5mm x 5 mm package
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AR8032 Functional Block Diagram
DAC
MDIP/
N[0:1]
Symbol
Encoder
MII
Tx
Symbol
Decoder/
Alignment
MII
Rx
AGC
PGA
PMA
AutoNegotiation
ADC
Feed
Forward
Equalizer
Decision
Feedback
Equalizer
Timing & Phase
Recovery
MII Management
Registers
DLL
© 2009 by Atheros Communications, Inc. All rights reserved. Atheros®, Atheros Driven®, Atheros XR®, Driving the Wireless Future®, ROCm®, Super A/G®, Super G®,
Super N®, Total 802.11®, XSPAN®, Wireless Future. Unleashed Now.®, and Wake on Wireless® are registered by Atheros Communications, Inc. Atheros SST™, SignalSustain Technology™, the Air is Cleaner at 5-GHz™, and 5-UP™ are trademarks of Atheros Communications, Inc. The Atheros logo is a registered trademark of Atheros
Communications, Inc. All other trademarks are the property of their respective holders. Subject to change without notice.
COMPANY CONFIDENTIAL
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AR8032 Integrated 10/100 Mbps Ethernet Transceiver
JulY 2010
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COMPANY CONFIDENTIAL
Table of Contents
General Description......................................... 1
Features ............................................................. 1
AR8032 Functional Block Diagram ............... 1
1 Pin Descriptions ......................................... 5
2 Functional Description .............................. 9
2.1 Transmit Functions ............................. 9
2.2 Receive Functions................................ 9
2.2.1 Decoder Modes ......................... 9
2.2.2 Analog to Digital Converter . 10
2.2.3 Baseline Wander Canceller ... 10
2.2.4 Digital Adaptive Equalizer ... 10
2.2.5 Auto-Negotiation.................... 10
2.2.6 Smartspeed Function ............. 10
2.2.7 Polarity Correction ................. 10
2.3 Loopback Modes ............................... 11
2.3.1 Digital Loopback .................... 11
2.3.2 External Cable Loopback....... 11
2.3.3 Cable Diagnostic Test............. 11
2.3.4 LED Interface........................... 11
2.3.5 Power Supplies ....................... 11
2.3.6 Low Power Modes.................. 11
2.3.7 Hibernation Mode .................. 11
3 Electrical Characteristics ......................... 13
3.1 Absolute Maximum Ratings............ 13
3.2 Recommended Operating Conditions
13
3.3 XTAL/OSC Timing........................... 14
3.4 MII DC Characteristics ..................... 15
3.5 MDIO Characteristics ....................... 16
3.5.8 MDIO Timing.......................... 16
3.6 Power-On Strapping ......................... 18
3.7 Typical Power Consumption Parameters ....................................................... 18
4 Register Descriptions ............................... 21
4.1 PHY Register Summary ................... 21
4.1.1 Control Register ...................... 22
4.1.2 Status Register......................... 24
4.1.3 PHY Identifier ......................... 26
4.1.4 PHY Identifier 2 ...................... 26
4.1.5 Auto-Negotiation Advertisement Register .......................... 27
4.1.6 Auto-Negotiation Expansion
Register..................................... 29
4.1.7 Link partner ability register(base
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page)......................................... 30
4.1.8 Function Control Register ..... 31
4.1.9 PHY Specific Status Register 33
4.1.10 Interrupt Enable Register ...... 34
4.1.11 Interrupt Status Register ....... 36
4.1.12 Smart Speed Register ............. 38
4.1.13 Receive Error Count Register 40
4.1.14 Virtual Cable Tester Control
Register .................................... 40
4.1.15 LED Control Register............. 41
4.1.16 Manual LED Override Register
42
4.1.17 Virtual Cable Tester Status Register ........................................... 43
4.1.18 Debug Port (Address Offset Set)
Register .................................... 43
4.1.19 Debug Port 2 (R/W Port) Register .............................................. 44
4.2 Power Saving and Debug Register
Summary ............................................ 45
4.2.20 10Base-T Test Configuration
Register .................................... 45
4.2.21 100Base-TX Test Configuration
Register .................................... 46
4.2.22 Hibernate Control Register ... 48
4.2.23 Power Saving Control............ 49
5 Package Dimensions................................ 51
6 Ordering Information.............................. 53
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July 2010 • 3
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AR8032 Integrated 10/100 Mbps Ethernet Transceiver
July 2010
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COMPANY CONFIDENTIAL
1. Pin Descriptions
This section contains a package pinout for the
AR8032 QFN 32pin and a listing of the signal
descriptions (see Figure 1-1).
The following nomenclature is used for signal
names:
NC
No connection to the internal die
is made from this pin
_L
At the end of the signal name,
indicates active low signals
P
Power
The following nomenclature is used for signal
types described in Table 1-1:
D
Open drain
IA
Analog input
I
Digital input
IH
Digital input with histeresis
I/O
Digital input/output
OA
Analog output
O
Digital output
PD
Internal pull-down for digital
input
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PU
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P
Internal pull-up for digital input
AR8032 Integrated 10/100 Mbps Ethernet Transceiver •
July 2010 •
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5
TXD1
TXD2
TXD3
COL
CRS
LED0
LED1
REXT
Figure 1-1 shows the pinout diagram for the
AR8032.
32 31 30 29 28 27 26 25
VDD12_REG
1
24 TXD0
VDD3
2
23 TXEN
VDD25_REG
3
22
TXC
RX‐
4
21
INTP
RX+
5
20
RXER
TX‐
6
19
RXC
TX+
7
18 RX_DV
XO
8
17 VDD25
Figure 1-1. Pinout Diagram
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RXD 0
RXD 1
AR8032 Integrated 10/100 Mbps Ethernet Transceiver
July 2010
RXD 2
RXD 3
15 16
MDC
RST#
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12 13 14
O
N
NOTE: There is an exposed ground pad on the
back side of the package.
O
D
MDIO
9
10 11
XI
AR8022
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Atheros Communications, Inc.
COMPANY CONFIDENTIAL
Table 1-1. Signal to Pin Relationships and Descriptions
Symbol
Pin
Type
VDD12_REG
1
AO
VDD3
2
P
VDD25_REG
3
AO
RX-
4
AI, AO
Media Dependent Interface 0, terminate with a 49.9Ω resister and
connect to XFMR
RX+
5
AI, AO
Media Dependent Interface 0, terminate with a 49.9Ω resister and
connect to XFMR
TX-
6
AI, AO
Media Dependent Interface 1, terminate with a 49.9Ω resister and
connect to XFMR
TX+
7
AI, AO
Media Dependent Interface 1, terminate with a 49.9Ω resister and
connect to XFMR
XO
8
AO
Crystal oscillator output. 27 pF to GND.
XI
9
AI
Crystal oscillator input. 27 pF to GND. An external 25/50 MHx
clock source with swing from 0 to 1.2V can inject from this pin
when a crystal is not used and the two 27pF caps removed. The 25
Mhz clock input is for MII mode, while the 50 Mhz clock input is
for RMII mode.
RST#
10
IH, PU
MDIO
11
MDC
12
I, PU
Management clock reference.
RXD3
13
I/O, PU,
POS
MII Receive data output [3].
14
I/O, PD,
POS
MII Receive data output [2].
15
I/O, PD,
POS
MII/RMII Receive data output [1].
16
I/O, PU,
POS
MII/RMII Receive data output [0].
VDD25
17
P
RX_DV
18
I/O, PD,
POS
Receive data valid output
RXC
19
I/O, PD,
POS
Receive clock output
RXER
20
I/O, PD,
POS
Receive error output
INTP
21
I/O, PU,
POS
Interrupt Output
TXC
22
I/O, PU,
POS
Transmit clock output
TXEN
23
I, PU
Transmit data enable
RXD2
RXD1
RXD0
1.2V regulator output. A 1 uF plus a 0.1 uF cap needed to stabilize
the output
3.3V power supply.
2.5V regulator output. A 1 uF ceramic cap needed to stabalize the
output. It is for analog, digital I/O and the transformer center taps.
O
C
T
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P
System reset input.
O
N
I/O, D, PU Management data.
O
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Atheros Communications, Inc.
COMPANY CONFIDENTIAL
Description
2.5V I/O power, connect with pin 3, 0.1uF to GND.
AR8032 Integrated 10/100 Mbps Ethernet Transceiver •
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Table 1-1. Signal to Pin Relationships and Descriptions (continued)
Symbol
Pin
Type
Description
TXD0
24
I, PD
MII/RMII Transmit data input [0]
TXD1
25
I, PD
MII/RMII Transmit data input [1]
TXD2
26
I, PD
MII Transmit data input [2]
TXD3
27
I, PD
MII Transmit data input [3]
COL
28
I/O, PD,
POS
Collision Detect output
CRS
29
I/O, PD
POS
Carrier Sense output
LED0
30
I/O, PU
POS
Programable LED0, the default indicates Link and Activity
LED1
31
I/O, PU
POS
Programmable LED1, The default indicates Speed
REXT
32
AO
Connect 2.37 K to GND
GND
Gnd
Ground
PADDLE
NOTE: All of the digital input only pads are 3.3V
input tolerant. The O and I/O pads are powered
with 2.5V power. The input level of any I/O pads
(except open-drain type) is limited to 3 V.
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2. Functional Description
transmit and receive high-speed data over
standard category 5 (CAT5) unshielded twisted
pair cable.
The Atheros AR8032 is a highly integrated
analog front end (AFE) and digital signal
transceiver (see Figure 2-1), providing high
performance with substantial cost reduction.
AFE consists of automatic gain control (AGC),
ADC, DAC, drivers, and clock generation. The
AR8032 provides physical layer functions to
See also the “AR8032 Functional Block
Diagram” on page 1.
Coarse
Baseline Wander
Watchdog
ADC
Fine
Programmable Gain
Amplifier
Line Side
Hybrid Circuits
PLL
Line Driver
TXDAC
Transceiver
Side
25 MHz Crystal
AFE
Figure 2-1. Analog Front End
The AR8032 10/100 PHY is fully 802.3, 802.3u
compliant, and supports the mediaindependent interface (MII) and Reduced
Media Independent Interface (RMII) to connect
to a Fast Ethernet-capable MAC.
The AR8032 transceiver combines feedforward equalizer, feedback equalizer, and
timing recovery, to enhance signal performance
in noisy environments.
2.1 Transmit Functions
The AR8032 transmit channel includes 4B/5B
mapper and scrambler. Table 2-1 describes the
transmit function encoder modes.
2.2 Receive Functions
The AR8032 receive channel includes digital
gain control, feed forward adaptive equalizer,
decision feedback equalizer, slicer, 5B/4B demapper and de-scrambler, PCS receive
functional block, and timing recovery logic.
2.2.1 Decoder Modes
Table 2-2 describes the receive function
decoder modes.
Table 2-2. Receive Function Decoder Modes
Decoder Mode Description
100BASE-TX
Table 2-1. Transmit Function Encoder Modes
Encoder Mode Description
100BASE-TX
10BASE-T
In 100BASE-TX mode, 4-bit data
from the MII is 4B/5B serialized,
scrambled, and encoded to a
three-level MLT3 sequence
transmitted by the PMA.
In 10BASE-T mode, the AR8032
transmits and receives
Manchester-encoded data.
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10BASE-T
In 100BASE-TX mode, the receive
data stream is recovered and
descrambled to align to the
symbol boundaries. The aligned
data is then parallelized and 5B/
4B decoded to 4-bit data. This
output runs to the MII/RMII
receive data pins after data stream
delimiters have been translated.
In 10BASE-T mode, the recovered
10BASE-T signal is decoded from
Manchester then aligned.
AR8032 Integrated 10/100 Mbps Ethernet Transceiver •
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2.2.2 Analog to Digital Converter
2.2.6 Smartspeed Function
The AR8032 device employs an advanced high
speed ADC on each receive channel with high
resolution, which results in better SNR and
lower error rates.
The Atheros Smartspeed function is an
enhanced feature of auto-negotiation that
allows the AR8032 device to fall back in speed
based on cabling conditions as well as operate
over CAT3 cabling (in 10BASE-T mode) or twopair CAT5 cabling (in 100BASE-TX mode).
2.2.3 Baseline Wander Canceller
Baseline wander results from Ethernet links
that AC-couple to the transceivers and from
AC coupling that cannot maintain voltage
levels for longer than a short time. As a result,
transmitted pulses are distorted, resulting in
erroneous sampled values for affected pulses.
The AR8032 device uses an advanced baseline
wander cancellation circuit that continuously
monitors and compensates for this effect,
minimizing the impact of DC baseline shift on
the overall error rate.
By default, the Smartspeed feature is enabled.
Refer to the register “Smart Speed Register” on
page 38, which describes how to set the
parameters. Set these register bits to control the
Smartspeed feature:
■ Bit [5]: 1 = Enables Smartspeed (default)
■ Bits [4:2]: Sets the number of link attempts
before adjusting
■ Bit [1]: Timer to determine the stable link
condition
2.2.4 Digital Adaptive Equalizer
The digital adaptive equalizer removes intersymbol interference at the receiver. The digital
adaptive equalizer takes unequalized signals
from ADC output and uses a combination of
feedforward equalizer (FFE) and decision
feedback equalizer (DFE) for the bestoptimized signal-to-noise (SNR) ratio.
2.2.7 Polarity Correction
If cabling has been incorrectly wired, the
AR8032 automatically corrects polarity errors
on the receive pairs.
2.2.5 Auto-Negotiation
The AR8032 device supports 10/100 BASE-T
Copper auto-negotiation in accordance with
IEEE 802.3 clauses 28 and 40. Auto-negotiation
provides a mechanism for transferring
information between a pair of link partners to
choose the best possible mode of operation in
terms of speed, duplex modes, and master/
slave preference. Auto-negotiation is initiated
upon any of the following scenarios:
■ Power-up reset
■ Hardware reset
■ Software reset
■ Auto-negotiation restart
■ Transition from power-down to power-up
■ The link goes down
If auto-negotiation is disabled, a 10BASE-T or
100BASE-TX can be manually selected using
the IEEE MII registers.
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AR8032 Integrated 10/100 Mbps Ethernet Transceiver
July 2010
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
2.3 Loopback Modes
2.3.3 Cable Diagnostic Test
2.3.1 Digital Loopback
Digital loopback provides the ability to loop
transmitted data back to the receiver using
digital circuitry in the AR8032 device. The
registers“100Base-TX Test Configuration
Register” on page 46 and “10Base-T Test
Configuration Register” on page 45 are used to
determine at which point the signal loops back
(for different modes, respectively).
Figure 2-2 shows a block diagram of digital
loopback.
MAC/
Switch
MII
PHY
Digital
The Cable Diagnostic Test (CDT) feature in the
AR8032 device uses Time Domain
Reflectometry (TDR) to identify remote and
local PHY malfunctions, bad/marginal cable or
patch cord segments, or connectors. Some of
the possible problems that can be diagnosed
include opens, shorts, cable impedance
mismatch, bad connectors, termination
mismatch, and bad magnetics. The CDT can be
performed when there is no link partner or
when the link partner is auto-negotiating.
2.3.4 LED Interface
The LED interface can either be controlled by
the PHY or controlled manually, independent
of the state of the PHY. Two status LEDs are
available. These can be used to indicate
operation speed, and link status. The LEDs can
be programmed to different status functions
from their default value. They can also be
controlled directly from the MII register
interface.
PH
Y
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E
Figure 2-2. Digital Loopback
2.3.5 Power Supplies
2.3.2 External Cable Loopback
MAC/
Switc
h
MII
PHY
Digital
PH
Y
AF
E
Figure 2-3. External Cable Loopback
RJ-45
External cable loopback loops MII Tx to MII Rx
through a complete digital and analog path
and an external cable, thus testing all the
digital data paths and all the analog circuits.
Figure 2-3 shows a block diagram of external
cable loopback.
The AR8032 device requires only one power
supply: 3.3V.
2.3.6 Low Power Modes
The AR8032 device supports the software
power-down low power mode. The standard
IEEE power-down mode is entered by setting
the POWER_DOWN bit (bit [11]) of the register
“Control Register” on page 22 equal to one.
In this mode, the AR8032 device ignores all
MAC interface signals except the MDC/MDIO.
It does not respond to any activity on the CAT
5 cable. The device cannot wake up on its own.
It can only wake up by setting the
POWER_DOWN bit (bit [11]) of the register
“Control Register” on page 22” to 0.
2.3.7 Hibernation Mode
The AR8032 device supports hibernation
mode. When the cable is unplugged, the
AR8032 will enter hibernation mode after
about 10 seconds. The power consumption in
this mode is very low compared to the normal
mode of operation. When the cable is reconnected, the AR8032 wakes up and normal
functioning is restored.
Atheros Communications, Inc.
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AR8032 Integrated 10/100 Mbps Ethernet Transceiver
July 2010
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AR8032 Integrated 10/100 Mbps Ethernet Transceiver
July 2010
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COMPANY CONFIDENTIAL
3. Electrical Characteristics
3.1 Absolute Maximum Ratings
Table 3-1 summarizes the absolute maximum
ratings and Table 3-2 lists the recommended
operating conditions for the AR8032. Absolute
maximum ratings are those values beyond
which damage to the device can occur.
Functional operation under these conditions,
or at any other condition beyond those
indicated in the operational sections of this
document, is not recommended.
Table 3-1. Absolute Maximum Ratings
Symbol
Parameter
Max Rating
Unit
VDD33
3.3V supply voltage
3.8
V
Tstore
Storage temperature
–65 to 150
°C
HBM
Human Body Model
±3500
V
CDM
Charged-Device Model
±1000
V
MM
Machine Model
±200
V
3.2 Recommended Operating Conditions
Table 3-2. Recommended Operating Conditions
Symbol
Parameter
Min
Typ
Max
Unit
VDD33
3.3V supply voltage
3.0
3.3
3.6
V
Ambient Temperature for normal opteration —
Commercial chip version, AR8032-BL1A (see
“Ordering Information — page 53”)
0
—
70
°C
Ambient Temperature for normal opteration —
Industrial chip version, AR8032-BL1B (see
“Ordering Information — page 53”)
-40
—
85
°C
Junction Temperature
0
—
125
°C
Thermal Dissipation Coefficient
—
4
—
°C/W
TA
ΤJ
ΨJT
NOTE: The following condition must be satisfied:
ΤJmax > TCmax + ΨJT x PTypical
Where:
ΤJmax = Maximum allowable temperature of the Junction
TCmax = Maximum allowable Case temperature
ΨJT = Thermal Dissipation Coefficient
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AR8032 Integrated 10/100 Mbps Ethernet Transceiver
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PTypical = Typical power dissipation
3.3 XTAL/OSC Timing
Figure 3-1 shows the XTAL timing diagram.
tXI_PER
tXI_HI
tXI_LO
VIH-XI
VIL-XI
tXI_RISE
tXI_FALL
Figure 3-1. XTAL/OSC Timing Diagram
Table 3-3. XTAL/OSC Timing — MII mode
Symbol
Parameter
Min
Typ
Max
Unit
T_XI_PER
XI/OSCI Clock Period
40.0 50ppm
40.0
40.0 +
50ppm
ns
T_XI_HI
XI/OSCI Clock High
14
20.0
ns
T_XI_LO
XI/OSCI Clock Low
14
20.0
ns
T_XI_RISE
XI/OSCI Clock Rise Time, VIL (max)
to VIH (min)
4
ns
T_XI_FALL
XI/OSCI Clock Fall time, VIL (max)
to VIH (min)
4
ns
V_IH_XI
The XTLI input high level
0.8
1.2
1.5
V
V_IL_XI
The xtli input low lever voltage
-0.3
0
0.15
V
Table 3-4. XTAL/OSC Timing — RMII mode
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Symbol
Parameter
Min
Typ
Max
Unit
T_XI_PER
XI/OSCI Clock Period
20.0 50ppm
20.0
20.0 +
50ppm
ns
T_XI_HI
XI/OSCI Clock High
8
10.0
ns
T_XI_LO
XI/OSCI Clock Low
8
10.0
ns
AR8032 Integrated 10/100 Mbps Ethernet Transceiver
July 2010
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
T_XI_RISE
XI/OSCI Clock Rise Time, VIL (max)
to VIH (min)
2
ns
T_XI_FALL
XI/OSCI Clock Fall time, VIL (max)
to VIH (min)
2
ns
V_IH_XI
The XTLI input high level
0.8
1.4
V
V_IL_XI
The xtli input low lever voltage
-0.3
0.15
V
3.4 MII DC Characteristics
Table 3-5 shows the MII DC characteristics.
Table 3-5. MII DC Characteristics
Symbol
Parameter
Min
Max
Unit
VOH
Output high voltage
2.0
3.0
V
VOL
Output low voltage
GND
0.4
V
VIH
Input high voltage
1.7
—
V
VIL
Input low voltage
—
0.7
V
IIH
Input high current
—
15
μA
IIL
Input low current
–15
—
μA
Figure 3-2 shows the MII input AC timing
diagram.
VIH
VIL
TXC
VIH
VIL
TXD[3:0]/TXEN
Min setup 5 ns
0 ns Min
Figure 3-2. MII Input AC Timing Diagram
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AR8032 Integrated 10/100 Mbps Ethernet Transceiver
July 2010
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Figure 3-3 shows the MII output AC timing
diagram.
VIH
RXC
VIL
VIH
VIL
RXD[3:0]/RX_DV/RXER
100Base-TX: 15 to 25ns
10Base-T: 15 to 205ns
Figure 3-3. MII Output AC Timing Diagram
3.5 MDIO Characteristics
Table 3-6 shows the MDIO DC characteristics.RMII Timing
Table 3-6. MDIO DC Characteristics
Symbol
Parameter
Min
Max
Unit
VOH
Output high voltage
2.4
—
V
VOL
Output low voltage
—
0.4
V
IIH
Input high current
—
0.4
mA
IIL
Input low current
-0.4
—
mA
3.5.8 MDIO Timing
Figure 3-4 shows the MDIO timing diagram.
tmdc
t mdch
MDC
tmdcl
t mdsu
t mdhold
MDIO
Figure 3-4. MDIO Timing Diagram
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AR8032 Integrated 10/100 Mbps Ethernet Transceiver
July 2010
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
Table 3-7. MDIO Timing
Symbol
Parameter
Min
Typ
Max
Unit
tmdc
MDC Period
100
nS
tmdcl
MDC Low Period
40
nS
tmdch
MDC High Period
40
nS
tmdsu
MDIO to MDC rising setup time
10
nS
tmdhold
MDIO to MDC rising hold time
10
nS
Table 3-8 shows the RMII AC timing
characteristics.
Table 3-8. RMII AC Timing
Symbol
Parameter
Tck
XI Period
Min
Max
Unit
20 -50ppm
20 +50ppm
nS
Tsu
TXEN, TXD to XI rising setup time
4
—
nS
Thold
TXEN, TXD to XI rising hold time
2
—
nS
Tdly
XI to RX_DV, RXD output delay
3
14
nS
Figure 3-5 shows the AC RMII timing diagram.
tck
XI
tsu
thold
TXEN
TXD[1:0]
tdly
RX_DV
RXD[1:0]
Figure 3-5. RMII AC Timing Diagram
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
AR8032 Integrated 10/100 Mbps Ethernet Transceiver
July 2010
•
•
17
17
3.6 Power-On Strapping
Table 3-9 shows the pin-to-PHY core configuration signal power-on strapping.
Table 3-9. Power-On Strapping[1]
PHY Pin Name
Pin
PHY Core
Configuration Signal Description
RXD3
13
PHYADDRESS[0]
PHY address
RXD2
14
PHYADDRESS[1]
RXD1
15
PHYADDRESS[2]
RXD0
16
DUPLEX
1 = Full Duplex
RXDV
18
CONFIG2
CONFIG[2:0]
000 = MII
001 = RMII
All other binary combinations are Reserved.
CRS
29
CONFIG1
COL
28
CONFIG0
TXC
22
EN_AB
Enable class AB mode
RXC
19
POWER_DOWN
Enable Power Down mode
RXER
20
ISOLATE
INTP
21
TESTMODE
LED0
30
AUTONEGOTIATION
LED1
31
SPEED
1 = enable
0 = disable
1 = normal operation
0 = test mode
1 = enable
0 = disable
1 = 100Mbps
0 = 10 Mbps
[1]Default values: 0 = Pull-down, 1 = Pull-up with 10 K resistor.
3.7 Typical Power Consumption Parameters
The following conditions apply to the typical
characteristics unless otherwise specified:
VDD33 = 3.3V, Tamb = 25 °C
Table 3-10 shows the typical power drain as a function of the AR8032’s operating mode.
Table 3-10. Total System Power
18
18
Symbol
AR8032 Power
Consumption (mW)
Total System (includes
XFMR and LED0 Power
Consumption (mW)
PLDPS
10.9
10.9
Link down, power-saving mode
PPWD
6.6
6.6
Power Down Mode
PIsolate
39.6
52.8
Isolate mode
P100F
123
280
100Base-T Full Duplex
•
•
AR8032 Integrated 10/100 Mbps Ethernet Transceiver
July 2010
Description
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
Table 3-10. Total System Power
Symbol
AR8032 Power
Consumption (mW)
Total System (includes
XFMR and LED0 Power
Consumption (mW)
P10F
52.5
272
P10TX
49.5
257.4
10Base-T Transmit
P10RX
49.5
59.4
10Base-T Receive
P10IDLE
47.8
69.3
10Base-T Idle
Description
10Base-T Full Duplex
NOTE: Total power includes power consumed by the center-tap of the transformer and the LEDs
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
AR8032 Integrated 10/100 Mbps Ethernet Transceiver
July 2010
•
•
19
19
20
20
•
•
AR8032 Integrated 10/100 Mbps Ethernet Transceiver
July 2010
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
4. Register Descriptions
Table 4-1 shows the reset types used in this
document.
Table 4-1. Reset Types (continued)
Table 4-1. Reset Types
Type
LH
Description
Register field with latching high function.
If status is high, then the register is set to
one and remains set until a read operation
is performed through the management
interface or a reset occurs.
LL
Register field with latching low function.
If status is low, then the register is cleared
to a zero and remains cleared until a read
operation is performed through the
management interface or a reset occurs.
Type
Description
R/W
Read/Write
RWC
Read/Write Clear. After read, register
field is cleared to zero.
RWR
Read/Write Reset. All bits are readable
and writable. After reset or read, the
register field is cleard to zero.
RWS
Read/Write Set. All bits are readable and
writable. After reset or read, the register
field is set to a non-zero value specified in
the text.
SC
Self-Clear. Writing a one to this register
causes the desired function to be
immediately executed, then the register
field is cleared to zero when the function
is complete.
WO
Write Only. Reads to this type of register
return undefined data.
Retain Value written to a register field takes
effect without a software reset.
SC
Self-Clear. Writing a one to this register
causes the desired function to execute
immediately, and the register field clears
to zero when the function is complete.
Update The value written to the register field does
not take effect until a software reset is
executed. The value can still be read after
it is written.
RES
Reserved for future use. All reserved bits
are read as a zero unless otherworse
noted.
RO
Read Only
ROC
4.1 PHY Register Summary
Table 4-2 summarizes the registers for the
AR8032.
Read Only Clear. After read, register field
is cleard to zero.
Table 4-2. Register Summary
Offset
Register
Page
0x00
Control Register
page 22
0x01
Status
page 24
0x02
PHY Identifier
page 26
0x03
PHY Identifier 2
page 26
0x04
Auto-Negotiation Advertisement
page 29
0x05
Link Partner Ability
page 30
0x06
Auto-Negotiation Expansion
page 29
0x07
Reserved
0x08
Reserved
0x09
Reserved
0x0A
Reserved
0x0B
Reserved
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
AR8032 Integrated 10/100 Mbps Ethernet Transceiver
July 2010
•
•
21
21
Table 4-2. Register Summary (continued)
Offset
Register
Page
0x0C
Reserved
0x0D
Reserved
0x0E
Reserved
0x0F
Reserved
0x10
Function Control Register
page 22
0x11
PHY Specific Status Register
page 33
0x12
Interrupt Enable Register
page 34
0x13
Interrupt Status Register
page 36
0x14
Smart Speed Register
page 38
0x15
Recieve Error Counter Register
page 40
0x16
Virtual Cable Tester Control Register
page 40
0x18
LED Control Register
0x19
Manual LED Override Register
page 41
0x1A
Reserved
page 42
0x1B
Reserved
0x1C
Virtual Cable Tester Status Register
page 40
0x1D
Debug Port 1 (Address offset)
page 43
0x1E
Debug Port 2 (R/W Port) Register
0x1F
Reserved
4.1.1 Control Register
Offset: 0x00
Bit
Name
15
Reset
Type
Mode
HW
Rst
SW
Rst
14
Loopback
Mode
HW
Rst
SW
Rst
13
Speed Selection
(LSB)
Mode
HW
Rst
SW
Rst
22
22
•
•
Description
R/W PHY Software Reset. Writing a "1" to this bit causes the PHY the
reset operation is done , this bit is cleared to "0" automatically. The
0
reset occurs immediately.
1= PHY reset
SC 0 =Normal operation
R/W When loopback is activated, the transmitter data presented on
TXD is looped back to RXD internally. Link is broken when
0
loopback is enabled.
1 = Enable Loopback
0
0 = Disable Loopback
R/W Upon hardware reset , this bit and 0.6 bit depend upon
See anen(bit0.12) and SPEED:
Desc. anen {0.6 , 0.13}
0 {0, SPEED}
Retain
1 2'b01
(00:10Mbps, 01:100Mbps, 10:Reserved, 11:Reserved)
AR8032 Integrated 10/100 Mbps Ethernet Transceiver
July 2010
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
Bit
Name
12
Auto-negotiation
Type
Mode
HW
Rst
SW
Rst
11
Power Down
Mode
HW
Rst
SW
Rst
10
Isolate
Mode
HW
Rst
SW
Rst
9
Restart Autonegotiation
Mode
HW
Rst
SW
Rst
8
Duplex mode
Mode
HW
Rst
Description
R/W Upon hardware reset, this bit depends on ANEN_PAD.
See 1 = Enable Auto-Negotiation Process
Desc. 0 = Disable Auto-Negotiation Process
Retain
R/W When the port is switched from power down to normal operation,
software reset and restart Auto-Negotiation are performed even
0
when bits Reset (0.15) and Restart Auto-Negotiation (0.9) are not
set by the user.
0
1 = Power down
0 = Normal operation
R/W The MII output pins are tristated when this bit is set to 1.
The MII inputs are ignored.
0
1 = Isolate
0 = Normal operation
0
R/W, Auto-Negotiation automatically restarts after hardware or
SC software reset regardless of whether or not the restart bit (0.9) is
set.
0
1 = Restart Auto-Negotiation Process
0 = Normal operation
SC
R/W, Upon hardware reset, this bit bit depends on
SC DUPLEX_MODE_PAD and anen bit(0.12):
See
Desc.
0.12
0
1
SW
Rst
0.8
0
DUPLEX_MODE_PAD
1:Full Duplex
0:Half Duplex
7
Collision Test
Mode
HW
Rst
SW
Rst
6
Speed Selection
(MSB)
Mode
HW
Rst
R/W Setting this bit to 1 will cause the COL pin to assert whenever the
TX_EN pin is asserted.
0
1 = Enable COL signal test
0 = Disable COL signal test
0
R/W See bit 0.13.
See
Desc.
SW
Rst
5:0
RES
Mode
RO
HW
Rst
00000
SW
Rst
00000
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
Reserved for future use.
AR8032 Integrated 10/100 Mbps Ethernet Transceiver
July 2010
•
•
23
23
4.1.2
Status Register
Offset: 0x01
Bit
Name
15
100Base-T4
14
100Base-Tx FullDuplex
13
100Base-Tx HalfDuplex
12
10 Mbps FullDuplex
11
10 Mbps HalfDuplex
10
100Base-T2 FullDuplex
9
100Base-T2 HalfDuplex
8
24
24
Extended Status
•
•
Type
Description
Mode
RO
HW
Rst
0
SW
Rst
0
Mode
RO
HW
Rst
1
SW
Rst
1
Mode
RO
HW
Rst
1
SW
Rst
1
Mode
RO
HW
Rst
1
SW
Rst
1
Mode
Capable of 100Base-Tx Full-Duplex operation
Capable of 100Base-Tx Half-Duplex operation
Capable of 10Base-T Full-Duplex operation
R/W Capable of 10 Mbps Half-Duplex operation
HW
Rst
1
SW
Rst
1
Mode
RO
HW
Rst
0
SW
Rst
0
Mode
100BASE-T4.
This protocol is not available.
0 = PHY not able to perform 100BASE-T4
Not able to perform 100Base-T2 Full-Duplex operation
R/W Not able to perform 100Base-T2 Half-Duplex operation
HW
Rst
0
SW
Rst
0
Mode
RO
HW
Rst
1
SW
Rst
1
Extended status information in register 15
AR8032 Integrated 10/100 Mbps Ethernet Transceiver
July 2010
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
Bit
Name
7
RES
6
5
4
3
2
1
0
MF Preamble
Suppression
Auto-negotiation
Complete
Remote Fault
Auto-Negotiation
Ability
Link Status
Jabber Detect
Extended
Capability
Type
Description
Mode
RO
HW
Rst
0
SW
Rst
0
Mode
RO
HW
Rst
1
SW
Rst
1
Mode
RO
HW
Rst
0
SW
Rst
0
Mode
RO,
LH
HW
Rst
0
SW
Rst
0
Mode
PHY accepts management frames with preamble suppressed
1: Auto negotiation process complete
0:Auto negotiation process not complete
1: Remote fault condition detected
0:Remote fault condition not detected
R/W 1: PHY able to perform auto-negotiation
HW
Rst
1
SW
Rst
1
Mode
RO,
LL
HW
Rst
0
SW
Rst
0
Mode
RO,
LH
HW
Rst
0
SW
Rst
0
Mode
RO
HW
Rst
1
SW
Rst
1
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
Reserved
This register bit indicates whether the link was lost since the last
read. For the current link status, read
register bit 17.10 Link Real Time.
1 = Link is up
0 = Link is down
1: Jabber condition detected
0: Jabber condition not detected
1: Extended register capabilitites
AR8032 Integrated 10/100 Mbps Ethernet Transceiver
July 2010
•
•
25
25
4.1.3
PHY Identifier
Offset: 0x02
Bit
Name
15:0
Organizationally
Unique Identifer
Bits 3:18
4.1.4
Type
Mode
RO
HW
Rst
Always
SW
Rst
Always
Description
Organizationally Unique Identifer Bits 3:18
16’h
004d
16’h
004d
PHY Identifier 2
Offset: 0x03
Bit
Name
15:0
OUI bit 19:24
Model Number
Revision Number
26
26
•
•
Type
Mode
RO
HW
Rst
Always
SW
Rst
Always
Description
16’h
d023
16’h
d023
AR8032 Integrated 10/100 Mbps Ethernet Transceiver
July 2010
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
4.1.5
Auto-Negotiation Advertisement Register
Offset: 0x04
Bit
Name
15
Next Page
Type
Mode
HW
Rst
SW
Rst
14
13
12
11
Ack
Remote Fault
Reserved
Asymmetric Pause
R/W
The value of this bit will be updated immediately after writing
this register. But the value written to this bit does not takes effect
0
until any one of the following occurs:
o Software reset is asserted (register 0.15)
Update o Restart Auto-Negotiation is asserted (register 0.9)
o Power down (register 0.11) transitions from power down to
normal operation
o Link goes down
If 1000BASE-T is advertised then the required next pages are
automatically transmitted. Register 4.15 should be set to 0 if no
additional next pages are needed.
1 = Advertise
0 = Not advertised
Mode
RO
HW
Rst
Always
0
SW
Rst
Always
0
Mode
R/W
HW
Rst
See
Desc.
SW
Rst
Update
Mode
RO
HW
Rst
Always
0
SW
Rst
Always
0
Mode
R/W
HW
Rst
SW
Rst
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
Description
Must be 0
1 = Set Remote Fault bit
0 = Do not set Remote Fault bit
Always 0.
Upon hardware reset , this bit depends on ASYM_PAUSE_PAD.
The
value of this bit will be updated immediately after writing
See
Desc. this register. But the value written to this bit does not takes effect
until any one of the following occurs:
Update o Software reset is asserted (register 0.15)
o Restart Auto-Negotiation is asserted (register 0.9)
o Power down (register 0.11) transitions from power down to
normal operation
o Link goes down
1 = Asymmetric Pause
0 = No asymmetric Pause
AR8032 Integrated 10/100 Mbps Ethernet Transceiver
July 2010
•
•
27
27
Bit
Name
10
PAUSE
Type
Mode
HW
Rst
SW
Rst
9
100BASE-T4
8
100BASE-TX
Full Duplex
100BASE-TX
Half Duplex
HW
Rst
Always
0
SW
Rst
Always
0
Mode
R/W
Mode
HW
Rst
SW
Rst
6
10BASE-TX
Full Duplex
Mode
HW
Rst
SW
Rst
28
28
•
•
Upon hardware reset , this bit depends on PAUSE_PAD.
The value of this bit will be updated immediately after writing
See
Desc. this register. But the value written to this bit does not takes effect
until any one of the following occurs:
Update o Software reset is asserted (register 0.15)
o Restart Auto-Negotiation is asserted (register 0.9)
o Power down (register 0.11) transitions from power down to
normal operation
o Link goes down
1 = MAC PAUSE implemented
0 = MAC PAUSE not implemented
RO
SW
Rst
7
R/W
Mode
HW
Rst
Description
Not able to perform 100BASE-T4
The value of this bit will be updated immediately after writing
this register. But the value written to this bit does not takes effect
1
until any one of the following occurs:
o Software reset is asserted (register 0.15)
Update o Restart Auto-Negotiation is asserted (register 0.9)
o Power down (register 0.11) transitions from power down to
normal operation
o Link goes down
1 = Advertise
0 = Not advertised
R/W
The value of this bit will be updated immediately after writing
this register. But the value written to this bit does not takes effect
1
until any one of the following occurs:
o Software reset is asserted (register 0.15)
Update o Restart Auto-Negotiation is asserted (register 0.9)
o Power down (register 0.11) transitions from power down to
normal operation
o Link goes down
1 = Advertise
0 = Not advertised
R/W
The value of this bit will be updated immediately after writing
this register. But the value written to this bit does not takes effect
1
until any one of the following occurs:
o Software reset is asserted (register 0.15)
Update o Restart Auto-Negotiation is asserted (register 0.9)
o Power down (register 0.11) transitions from power down to
normal operation
o Link goes down
1 = Advertise
0 = Not advertised
AR8032 Integrated 10/100 Mbps Ethernet Transceiver
July 2010
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
Bit
Name
Type
Mode
5
10BASE-TX
Half Duplex
HW
Rst
SW
Rst
4:0
4.1.6
Selector field
Mode
Description
R/W
The value of this bit will be updated immediately after writing
this register. But the value written to this bit does not takes effect
1
until any one of the following occurs:
o Software reset is asserted (register 0.15)
Update o Restart Auto-Negotiation is asserted (register 0.9)
o Power down (register 0.11) transitions from power down to
normal operation
o Link goes down
1 = Advertise
0 = Not advertised
RO
HW
Rst
Selector Field mode
Always 00001 = 802.3
00001
SW
Rst
Always
00001
Auto-Negotiation Expansion Register
Offset: 0x06
Bit
Name
15:5
RES
4
Parallel Detection
Fault
Type
Description
Mode
RO
HW
Rst
Always
0
SW
Rst
Always
0
Reserved. Must be 0.
Mode RO, LH 1: a fault has been detect
0: no fault has been detected
HW
0
Rst
3
2
Link Partner Next
Page Able
Local Next Page
Able
SW
Rst
0
Mode
RO
HW
Rst
0
SW
Rst
0
Mode
RO
HW
Rst
0
SW
Rst
0
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
1: Link partner is Next page able
0: Link partner is not next page able
1: Local Device is Next Page able
0: Local Device is not Next Page able
AR8032 Integrated 10/100 Mbps Ethernet Transceiver
July 2010
•
•
29
29
Bit
Name
1
Page Received
Type
Description
Mode RO, LH 1: A new page has been received
0: No new page has been received
HW
0
Rst
0
Link Partner AutoNegotiation Able
4.1.7
SW
Rst
0
Mode
RO
HW
Rst
0
SW
Rst
0
1: Link partner is auto negotiation able
0: Link partner is not auto negotiation able
Link partner ability register(base page)
Offset: 0x05
Bit
Name
15
Next page
14
Ack
13
Remote Fault
12
Reserved
11
30
30
Asymmetric Pause
•
•
Type
Description
Mode
RO
HW
Rst
0
SW
Rst
0
Mode
RO
HW
Rst
0
SW
Rst
0
Mode
RO
HW
Rst
0
SW
Rst
0
Mode
RO
HW
Rst
0
SW
Rst
0
Mode
RO
HW
Rst
0
SW
Rst
0
Received Code Word Bit 15
1 = Link partner capable of next page
0 = Link partner not capable of next page
Acknowledge
Received Code Word Bit 14
1 = Link partner received link code word
0 = Link partner does not have Next Page ability
Remote Fault
Received Code Word Bit 13
1 = Link partner detected remote fault
0 = Link partner has not detected remote fault
Technology Ability Field
Received Code Word Bit 12
Technology Ability Field
Received Code Word Bit 11
1 = Link partner requests asymmetric pause
0 = Link partner does not request asymmetric pause
AR8032 Integrated 10/100 Mbps Ethernet Transceiver
July 2010
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
Bit
Name
10
PAUSE
9
8
7
6
5
4:0
100BASE-T4
100BASE-TX
Full Duplex
100BASE-TX
Half Duplex
10BASE-TX
Full Duplex
10BASE-TX
Half Duplex
Selector field
Type
Description
Mode
RO
HW
Rst
0
SW
Rst
0
Mode
RO
HW
Rst
0
SW
Rst
0
Mode
RO
HW
Rst
0
SW
Rst
0
Mode
RO
HW
Rst
0
SW
Rst
0
Mode
RO
HW
Rst
0
SW
Rst
0
Mode
RO
HW
Rst
0
SW
Rst
0
Technology Ability Field
Received Code Word Bit 10
1 = Link partner is capable of pause operation
0 = Link partner is not capable of pause operation
Technology Ability Field
Received Code Word Bit 9
1 = Link partner is 100BASE-T4 capable
0 = Link partner is not 100BASE-T4 capable
Technology Ability Field
Received Code Word Bit 8
1 = Link partner is 100BASE-TX full-duplex capable
0 = Link partner is not 100BASE-TX full-duplex capable
Technology Ability Field
Received Code Word Bit 7
1 = Link partner is 100BASE-TX half-duplex capable
0 = Link partner is not 100BASE-TX half-duplex capable
Technology Ability Field
Received Code Word Bit 6
1 = Link partner is 10BASE-T full-duplex capable
0 = Link partner is not 10BASE-T full-duplex capable
Technology Ability Field
Received Code Word Bit 5
1 = Link partner is 10BASE-T half-duplex capable
0 = Link partner is not 10BASE-T half-duplex capable
Mode RO, LH Selector Field
Received Code Word Bit 4:0
HW
0
Rst
SW
Rst
4.1.8
0
Function Control Register
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
AR8032 Integrated 10/100 Mbps Ethernet Transceiver
July 2010
•
•
31
31
Offset: 0x10
Bit
Name
15:12
RES
11
Assert CRS on
Transmit
10
RES
9:7
6:5
RES
MDI Crossover
Mode
Type
Mode
R/W
HW
Rst
0
SW
Rst
Retain
Mode
R/W
HW
Rst
1
SW
Rst
Retain
Mode
R/W
HW
Rst
0
SW
Rst
Retain
Mode
R/W
HW
Rst
0
SW
Rst
Retain
Mode
R/W
HW
Rst
SW
Rst
4:3
2
SQE Test
1
32
32
RES
RES
•
•
Description
Reserved
1 = when transmitting, crs_o is asserted to 1;
0 = crs_o is asserted to 1 only when receiving.
When in RMII mode, this bit is fixed to 0.
Reserved
Reserved
Changes to these bits are disruptive to the normal operation;
therefore any changes to these registers must be followed by a
11
software reset to take effect.
00 = Manual MDI configuration
Update 01 = Manual MDIX configuration
10 = Reserved
11 = Enable automatic crossover for all modes
Mode
R/W
HW
Rst
0
SW
Rst
Retain
Mode
R/W
HW
Rst
0
SW
Rst
Retain
Mode
R/W
HW
Rst
1
SW
Rst
Retain
Reserved
SQE Test is automatically disabled in full-duplex mode
1 = SQE test enabled
0 = SQE test disabled
Reserved
AR8032 Integrated 10/100 Mbps Ethernet Transceiver
July 2010
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
Bit
Name
0
Disable Jabber
4.1.9
Type
Description
Mode
R/W
HW
Rst
0
SW
Rst
Retain
Jabber has effect only in 10BASE-T half-duplex mode.
1 = Disable jabber function
0 = Enable jabber function
PHY Specific Status Register
Offset: 0x11
Bit
Name
15:14
Speed
13
Duplex
Type
Description
Mode
RO
HW
Rst
00
SW
Rst
Retain
Mode
RO
This status bit is valid only after resolved bit 17.11 = 1. The
resolved bit is set when Auto-Negotiation is completed or AutoNegotiation is disabled.
1 = Full-duplex
0 = Half-duplex
Mode
RO
HW
Rst
0
1 = Page received
0 = Page not received
SW
Rst
Retain
Mode
RO
HW
Rst
0
SW
Rst
0
Mode
RO
HW
Rst
0
SW
Rst
0
Mode
RO
HW
Rst
Always
0
SW
Rst
Always
0
HW
Rst
SW
Rst
12
11
10
9:7
Page Received
(real-time)
Speed and Duplex
Resolved
Link (real-time)
RES
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
These status bits are valid only after resolved bit 17.11 = 1. The
resolved bit is set when Auto-Negotiation is completed or AutoNegotiation is disabled.
11 = Reserved
10 = Reserved
01 = 100 Mbps
00 = 10 Mbps
When Auto-Negotiation is not enabled, 17.11 = 1 for force speed
mode.
1 = Resolved
0 = Not resolved
1 = Link up
0 = Link down
Reserved
AR8032 Integrated 10/100 Mbps Ethernet Transceiver
July 2010
•
•
33
33
Bit
Name
6
MDI Crossover
Status
5
Wirespeed
Downgrade
4
RES
3
Transmit Pause
Enabled
Type
Description
Mode
RO
HW
Rst
0
SW
Rst
Retain
Mode
RO
HW
Rst
0
SW
Rst
0
Mode
RO
HW
Rst
1
SW
Rst
1
Mode
RO
This is a reflection of the MAC pause resolution. This bit is for
information purposes and is not used by the device.
This status bit is valid only after resolved bit 17.11 = 1. The
resolved bit is set when Auto-Negotiation is completed; While in
force mode, this bit is set to be 0.
1 = Transmit pause enabled
0 = Transmit pause disabled
RO
This is a reflection of the MAC pause resolution. This bit is for
information purposes and is not used by the device.
This status bit is valid only after resolved bit 17.11 = 1. The
resolved bit is set when Auto-Negotiation is completed; While in
force mode, this bit is set to be 0.
1 = Receive pause enabled
0 = Receive pause disabled
Mode
RO
HW
Rst
0
1 = Reversed
0 = Normal
SW
Rst
Retain
Mode
RO
HW
Rst
0
SW
Rst
Retain
HW
Rst
SW
Rst
2
Receive Pause
Enabled
Mode
HW
Rst
SW
Rst
1
Polarity (real-time)
0
Jabber (real-time)
This status bit is valid only after resolved bit 17.11 = 1. The
resolved bit is set when Auto-Negotiation is completed or AutoNegotiation is disabled. This bit is 0 or 1 depending on what is
written to 16.6:5 in manual configuration mode. Register 16.6:5
are updated with software reset.
1 = MDIX
0 = MDI
1 = Downgrade
0 = No Downgrade
Reserved
1 = Jabber
0 = No jabber
4.1.10 Interrupt Enable Register
34
34
•
•
AR8032 Integrated 10/100 Mbps Ethernet Transceiver
July 2010
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
Offset: 0x12
Bit
Name
15
Auto-Negotiation
Error Interrupt
Enable
14
13
12
11
10
9
8
Speed Changed
Interrupt Enable
Duplex Changed
Interrupt Enable
Page Received
Interrrupt Enable
Link Fail Interrupt
Enable
Link Success
Interrupt Enable
RES
RES
Type
Description
Mode
R/W
HW
Rst
0
SW
Rst
Retain
Mode
R/W
HW
Rst
0
SW
Rst
Retain
Mode
R/W
HW
Rst
0
SW
Rst
Retain
Mode
R/W
HW
Rst
0
SW
Rst
Retain
Mode
R/W
HW
Rst
0
SW
Rst
Retain
Mode
R/W
HW
Rst
0
SW
Rst
Retain
Mode
R/W
HW
Rst
0
SW
Rst
Retain
Mode
R/W
HW
Rst
0
SW
Rst
0
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
1 = Interrupt enable
0 = Interrupt disable
1 = Interrupt enable
0 = Interrupt disable
1 = Interrupt enable
0 = Interrupt disable
1 = Interrupt enable
0 = Interrupt disable
1 = Interrupt enable
0 = Interrupt disable
1 = Interrupt enable
0 = Interrupt disable
Reserved
Reserved
AR8032 Integrated 10/100 Mbps Ethernet Transceiver
July 2010
•
•
35
35
Bit
Name
7
RES
6
MDI Crossover
Changed Interrupt
Enable
5
Wirespeeddowngrade
Interrupt Enable
4:2
1
RES
Polarity Changed
Interrupt Enable
0
Jabber Interrupt
Enable
Type
Description
Mode
R/W
HW
Rst
0
SW
Rst
Retain
Mode
R/W
HW
Rst
0
SW
Rst
Retain
Mode
R/W
HW
Rst
0
SW
Rst
Retain
Mode
R/W
HW
Rst
000
SW
Rst
Retain
Mode
R/W
HW
Rst
0
SW
Rst
Retain
Mode
R/W
HW
Rst
Reserved
1 = Interrupt enable
0 = Interrupt disable
1 = Interrupt enable
0 = Interrupt disable
Reserved
1 = Interrupt enable
0 = Interrupt disable
1 = Interrupt enable
0 = Interrupt disable
SW
Rst
4.1.11 Interrupt Status Register
Offset: 0x13
Bit
Name
15
Auto-Negotiation
Error
36
36
•
•
Type
Description
Mode RO, LH An error is said to occur if MASTER/SLAVE does not resolve,
parallel detect fault, no common HCD, or link does not come up
HW
0
after negotiation is completed.
Rst
1 = Auto-Negotiation Error
SW
Retain 0 = No Auto-Negotiation Error
Rst
AR8032 Integrated 10/100 Mbps Ethernet Transceiver
July 2010
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
Bit
Name
14
Speed Changed
Type
Description
Mode RO, LH 1 = Speed changed
0 = Speed not changed
HW
0
Rst
SW
Rst
13
Duplex Changed
Retain
Mode RO, LH 1 = Duplex changed
0 = Duplex not changed
HW
0
Rst
SW
Rst
12
Page Received
Retain
Mode RO, LH 1 = Page received
0 = Page not received
HW
0
Rst
SW
Rst
11
Link Fail Interrupt
Retain
Mode RO, LH 1 = Link down happened.
0 = Link down not happened.
HW
0
Rst
SW
Rst
10
Link Success
Interrupt
Retain
Mode RO, LH 1 = Link down happened.
0 = Link down not happened.
HW
0
Rst
SW
Rst
9
8
7
6
RES
RES
RES
MDI Crossover
Changed
Retain
Mode RO, LH Reserved
HW
Rst
0
SW
Rst
Retain
Mode
RO
HW
Rst
0
SW
Rst
0
Mode
RO
HW
Rst
0
SW
Rst
0
Reserved
Reserved
Mode RO, LH 1 = Crossover changed
0 = Crossover not changed
HW
0
Rst
SW
Rst
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
Retain
AR8032 Integrated 10/100 Mbps Ethernet Transceiver
July 2010
•
•
37
37
Bit
Name
5
Wirespeeddowngrade
Interrupt
4:2
RES
1
Polarity Changed
Type
Description
Mode RO, LH 1 = Wirespeed-downgrade detected.
0 = No Wirespeed-downgrade.
HW
0
Rst
SW
Rst
Retain
Mode
RO
HW
Rst
000
SW
Rst
000
Reserved
Mode RO, LH 1 = Polarity Changed
0 = Polarity not changed
HW
0
Rst
SW
Rst
0
Jabber
Retain
Mode RO, LH 1 = Jabber
0 = No jabber
HW
0
Rst
SW
Rst
Retain
4.1.12 Smart Speed Register
Offset: 0x14
Bit
Name
15:11
RES
10:9
8
38
38
Reserved
RES
•
•
Type
Description
Mode
RO
HW
Rst
0
SW
Rst
0
Mode
R/W
HW
Rst
2’b00
SW
Rst
Retain
Mode
RO
HW
Rst
1’b0
SW
Rst
Update
Reserved. Must be 00000000.
Reserved
Reserved
AR8032 Integrated 10/100 Mbps Ethernet Transceiver
July 2010
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
Bit
Name
7:6
RES
5
Smartspeed_en
Type
Mode
R/W
HW
Rst
0
SW
Rst
Update
Mode
R/W
HW
Rst
SW
Rst
4:2
1
0
Smartspeed_retry_
limit
R/W
HW
Rst
3’b011
SW
Rst
Update
R/W
0
SW
Rst
Update
Mode
R/W
HW
Rst
0
SW
Rst
0
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
Reserved
The default value is one; if this bit is set to one and cable inhibits
completion of the training phase, then
1
After a few failed attempts, the Atheros card automatically
downgrades the highest ability to the next lower speed: from 100
Update to 10.
Mode
Bypass_smartspeed Mode
_timer
HW
Rst
RES
Description
The default value is three; if these bits are set to three, then the
Atheros card will attempt five times before downgrading; The
number of attempts can be changed through setting these bits.
The default value is zero; if this bit is set to one, the Smartspeed
FSM will bypass the timer used for stability.
Reserved.
AR8032 Integrated 10/100 Mbps Ethernet Transceiver
July 2010
•
•
39
39
4.1.13 Receive Error Count Register
Offset: 0x15
Bit
Name
15:0
Receive Error
Count
Type
Description
Mode
RO
HW
Rst
0
SW
Rst
0
Counter will peg at 0xFFFF and will not roll over.
(when rx_dv is valid, count rx_er numbers)
(in this version, only for 100Base-T)
4.1.14 Virtual Cable Tester Control Register
Offset: 0x16
Bit
Name
15:11
Vct_dbg_psw
10
vct_wp_
Max_vcode[3]
9:8
MDI Pair Select
7:5
vct_wp_
Max_vcode[2:0]
4:1
40
40
•
•
vct_np_
Max_vcode[3:0]
Type
Description
Mode
RO
HW
Rst
0
SW
Rst
0
Mode
RO
HW
Rst
1’b1
SW
Rst
Retain
Mode
R/W
HW
Rst
00
SW
Rst
00
Mode
RO
HW
Rst
3’b111
SW
Rst
Retain
Mode
R/W
HW
Rst
3’b100
SW
Rst
Retain
For VCT debug
For VCT debug
Virtual Cable Tester™ Control registers. Use the Virtual Cable
Tester Control Registers to select which MDI pair is shown in the
Virtual Cable Tester Status register.
00 = MDI[0] pair
01 = MDI[1] pair
10 = Reserved
11 = Reserved
For VCT debug
For VCT debug
AR8032 Integrated 10/100 Mbps Ethernet Transceiver
July 2010
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
Bit
Name
0
Enable Test
Type
Description
Mode
R/W
HW
Rst
0
SW
Rst
Retain
When set, hardware automatically disable this bit when VCT is
done.
1 = Enable VCT Test
0 = Disable VCT Test
4.1.15 LED Control Register
Offset: 0x18
Bit
Name
15
Disable LED
14:12
11
10:8
7:5
4:3
LED On Time
Force Interrupt
LED Off Time
RES
Type
Description
Mode
R/W
HW
Rst
0
SW
Rst
Retain
Mode
R/W
HW
Rst
3’b011
SW
Rst
Retain
Mode
RO
HW
Rst
0
SW
Rst
0
Mode
R/W
HW
Rst
3’b010
SW
Rst
0
Mode
RO
HW
Rst
000
SW
Rst
000
LED_LINK Control Mode
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
R/W
HW
Rst
0
SW
Rst
Retain
Control the output LED pins.
0 = Enable
1 = Disable
000 = 5 ms
001 = 10ms
010 = 21 ms
011 = 42ms
100 = 84 ms
101 = 168ms
110 to 111 = 42ms
Always 0
000 = 21 ms
001 = 42 ms
010 = 84 ms
011 =168 ms
100 =330 ms
101 = 670 ms
110 to 111 = 168ms
Reserved
00 = Direct LED mode
11 = Master/Slave LED mode
01, 10 = Combined LED modes
AR8032 Integrated 10/100 Mbps Ethernet Transceiver
July 2010
•
•
41
41
Bit
Name
2
RES
1
RES
0
RES
Type
Description
Mode
R/W
HW
Rst
0
SW
Rst
Retain
Mode
R/W
HW
Rst
0
SW
Rst
Retain
Mode
R/W
HW
Rst
0
SW
Rst
Retain
Reserved
Reserved
Reserved
4.1.16 Virtual Cable Tester Status Register
Offset: 0x1C
Bit
Name
15:10
RES
9:8
7:0
42
42
•
•
Status
Delta_Time
Type
Description
Mode
RO
HW
Rst
0
SW
Rst
0
Mode
RO
HW
Rst
00
SW
Rst
00
Mode
R/W
HW
Rst
0
SW
Rst
0
Reserved
The content of the Virtual Cable Tester Status Registers applies to
the cable
pair selected in the Virtual Cable Tester™ Control Registers.
11 = Link-up state, no short or open in cable
00 = Valid test, normal cable (no short or open in cable)
10 = Valid test, open in cable (Impedance > 333 ohms)
01 = Valid test, short in cable (Impedance < 33 ohms)
Delta time indicates distance along the cable
AR8032 Integrated 10/100 Mbps Ethernet Transceiver
July 2010
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
4.1.17 Debug Port (Address Offset Set) Register
Offset: 0x1D
Bit
Name
15:6
RES
5:0
Addres Offset
Type
Description
Mode
RO
HW
Rst
0
SW
Rst
0
Mode
R/W
HW
Rst
0
SW
Rst
0
Reserved
The address index of the register will be written or read.
4.1.18 Debug Port 2 (R/W Port) Register
Offset: 0x1E
Bit
Name
15:0
Debug Data Port
Type
Mode
HW
Rst
SW
Rst
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
Description
R/W
The data port for the debug register.
Before
accessing this register, you must set the address offset
0x02EE
first.
0x02EE
AR8032 Integrated 10/100 Mbps Ethernet Transceiver
July 2010
•
•
43
43
4.2
Power Saving and Debug Register Summary
Table 4-3. Register Summary
Offset
Register
Page
0x12
Test Configuration for 10Base-T
page 45
0x10
Test Configuration for 100Base-Tx
page 46
0x0B
Hibernate Control
page 48
0x29
Power Saving Control
page 49
4.2.19 10Base-T Test Configuration Register
Offset: 0x12
Bit
Name
15:14
Interval_sel_timer
13:12
11
En_mask_bt
10
En_10bt_idle
9:6
5
44
44
Triger_sel_timer
RES
Test_mode[2]
•
•
Type
Description
Mode
R/W
HW
Rst
01
SW
Rst
Retain
Mode
R/W
HW
Rst
00
SW
Rst
Retain
Mode
R/W
HW
Rst
1
SW
Rst
0
Mode
R/W
HW
Rst
1
SW
Rst
0
Mode
RO
HW
Rst
1000
SW
Rst
1000
Mode
R/W
HW
Rst
0
SW
Rst
0
Controls the interval that PHY detects whether the data frames
on the cable are MLT-3 coded. This logic is used to divide
Manchester code from MLT-3 code.
Controls the threshold that PHY detects at the end of the interval
whether the data frames on the cable are MLT-3 coded. This logic
is used to divide Manchester code from MLT-3 code.
1: enable the function of dividing Manchester code from MLT-3
code.
0: disable the function.
1: In 10BT mode , if there's no data or NLP to transmit, shut off
dac; otherwise turn on the dac;
0: In 10BT, dac will not be turn off.
Reserved
bit 2 of test_mode
AR8032 Integrated 10/100 Mbps Ethernet Transceiver
July 2010
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
Bit
Name
4
En_longcable
3
2
1:0
RES
Loopback mode
select
Test_mode[1:0]
Type
Description
Mode
R/W
HW
Rst
0
SW
Rst
Retain
Mode
R/W
HW
Rst
0
SW
Rst
Retain
Mode
RO
HW
Rst
1
SW
Rst
1
Mode
R/W
HW
Rst
0
SW
Rst
0
Enable long cable test
Reserved
1: lpbk2-deep in Loopback mode
0: lpbk1-shallow in Loopback mode
(connect to dig10.test_mode_i[0])
[001]: packet with all ones, 10MHz sine wave, For harmonic test.
[010]: pseudo random, for TP_IDLE/Jitter/Differential Voltage
test.
[011]: normal link pulse only,
[100]: 5MHz sin wave.
Others: normal mode.
4.2.20 100Base-TX Test Configuration Register
Offset: 0x10
Bit
Name
15
RES
14:8
7
RES
Jitter_test
Type
Description
Mode
R/W
HW
Rst
0
SW
Rst
Retain
Mode
R/W
HW
Rst
0111001
SW
Rst
Retain
Mode
R/W
HW
Rst
0
SW
Rst
Retain
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
Reserved
Reserved
100Base-Tx Jitter test
AR8032 Integrated 10/100 Mbps Ethernet Transceiver
July 2010
•
•
45
45
Bit
Name
6
Os_test
5
Dcd_test
4
RES
3
RES
2
RES
1
RES
0
46
46
RES
•
•
Type
Description
Mode
R/W
HW
Rst
0
SW
Rst
Retain
Mode
R/W
HW
Rst
0
SW
Rst
Retain
Mode
R/W
HW
Rst
0
SW
Rst
0
Mode
R/W
HW
Rst
0
SW
Rst
0
Mode
R/W
HW
Rst
0
SW
Rst
0
Mode
R/W
HW
Rst
0
SW
Rst
0
Mode
R/W
HW
Rst
0
SW
Rst
0
100Base-Tx Overshoot test
100Base-Tx DCD test
Reserved
Reserved
Reserved
Reserved
Reserved
AR8032 Integrated 10/100 Mbps Ethernet Transceiver
July 2010
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
4.2.21 Hibernate Control Register
Offset: 0x0B
Bit
Name
15
Ps_hib_en
14
13
12
11
10
9:0
RES
RES
RES
RES
RES
RES
Type
Description
Mode
RO
HW
Rst
1
SW
Rst
0
Mode
RO
HW
Rst
0
SW
Rst
0
Mode
RO
HW
Rst
1
SW
Rst
1
Mode
RO
HW
Rst
1
SW
Rst
1
Mode
RO
HW
Rst
1
SW
Rst
1
Mode
RO
HW
Rst
1
SW
Rst
1
Mode
RO
HW
Rst
0
SW
Rst
0
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
Power hibernate conrol bit;
‘1’ : hibernate enable
‘0’ : hibernate disable
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
AR8032 Integrated 10/100 Mbps Ethernet Transceiver
July 2010
•
•
47
47
4.2.22 Power Saving Control
Offset: 0x29
Bit
Name
15
TOP_PS_EN
14:12
11:9
RES
Dac_amp_100
Type
Description
Mode
RO
HW
Rst
1
SW
Rst
Retain
Mode
R/W
HW
Rst
3’h3
SW
Rst
Retain
Mode
R/W
HW
Rst
3’h3
SW
Rst
Retain
‘1’ : Top level Power Saving Enable
‘0’ : Top level Power Saving Disable
Reserved
Control amplitude of transmit signal in 100BT mode.
000: -2%
……
111: +12%
8:6
Dac_amp_10
Mode
R/W
HW
Rst
3’h3
SW
Rst
Retain
Control amplitude of transmit signal in 10BT mode.
000: -2%
……
111: +12%
5:1
0
48
48
RES
RES
•
•
Mode
R/W
HW
Rst
10010
SW
Rst
10010
Mode
R/W
HW
Rst
1
SW
Rst
Retain
Reserved
Reserved
AR8032 Integrated 10/100 Mbps Ethernet Transceiver
July 2010
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
5. Package Dimensions
The AR8032 is packaged in a QFN 32. The body
size is 5 mm by 5 mm. The package drawings
and dimensions are provided in Figure 5-1 and
Table 5-1.
Figure 5-1. Package Views
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
AR8032 Integrated 10/100 Mbps Ethernet Transceiver
July 2010
•
•
51
51
;
Table 5-1. Package Dimensions
Dimension Label
Min
Nom
Max
Unit
A
0.70
0.75
0.80
mm
A1
—
0.01
0.05
mm
b
0.18
0.25
0.30
mm
c
0.18
0.20
0.25
mm
D
4.90
5.00
5.10
mm
D2
3.50REF
mm
e
0.50 Basic
mm
Ne
3.50 Basic
mm
E
4.90
E2
5.00
5.10
3.50REF
mm
mm
L
0.35
0.40
0.45
mm
h
0.30
0.35
0.40
mm
Notes:
1. Dimensioning and tolerences conform to JEDEC MO-220
52
52
•
•
AR8032 Integrated 10/100 Mbps Ethernet Transceiver
July 2010
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
6. Ordering Information
The order number AR8032-BL1A specifies a Commercial version of the AR8032.
The order number AR8032-BL1B specifies an Industrial version of the AR8032.
Atheros Communications, Inc.
Transceiver • 53
AR8032 Integrated 10/100 Mbps Ethernet
The information in this document has been carefully reviewed and is believed to be accurate. Nonetheless, this document is subject to
change without notice. Atheros assumes no responsibility for any inaccuracies that may be contained in this document, and makes no
commitment to update or to keep current the contained information, or to notify a person or organization of any updates. Atheros reserves
the right to make changes, at any time, to improve reliability, function or design and to attempt to supply the best product possible.
Document Number: 981-00072-001
MKG-1359 Rev. 2
Atheros Communications, Incorporated
5480 Great America Parkway
Santa Clara, CA 95054
t: 408/773-5200
f: 408/773-9940
www.atheros.com