ETC C627

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Chipnuts Technology Inc.
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C627
Hardware Design Guide
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Document No.：CNUT-QT-SH-SoC-C627-Solution-3-06-V01.02.01
Title: C627 Hardware Design Guide
CNUT-QT-SH-SoC-C627-Solution-3-06-V01.02.01
Chipnuts Technology Inc.
Document number: CNUT-QT-SH-SoC-C627-Solution-3-06-V01.02.01
Date: 2008.1.4
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Application Information
To obtain the most updated Application Notes and other useful information for your design,
contact your local Chipnuts sales office. Please also visit the Chipnuts web site at
www.chipnuts.com
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Copyright Notice
This manual is copyrighted by Chipnuts Technology Inc. Do not reproduce or transform
the manual to any other format, or send/transmit any part of this documentation without
the expressed written permission of Chipnuts Technology Inc.
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Trademark Acknowledgment
Chipnuts Technology® Digital logo is registered trademark of Chipnuts Technology Inc.
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Disclaimer
This document provides technical information for the user. Chipnuts Technology Inc.
reserves the right to modify the information in this document as necessary. The customer
should make sure that they have the most recent data sheet version. Chipnuts Technology
Inc. holds no responsibility for any errors that may appear in this document. Customers
should take appropriate action to ensure their use of the products does not infringe upon
any patents. Chipnuts Technology Inc. respects valid patent rights of third parties and
does not infringe upon or assist others to infringe upon such rights.
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Copyright © Chipnuts Technology Inc., 2006-2010. All rights reserved.
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Page 1 of 35
Title: C627 Hardware Design Guide
CNUT-QT-SH-SoC-C627-Solution-3-06-V01.02.01
Revision History
Version
Editing Note
V01.01.01
New issue
V01.02.01
Approved/Date
Tiger Li
Fred Zheng
Fred Zheng
/2007.10.25
/2007.10.26
/2007.10.26
Tiger Li
Fred Zheng
Fred Zheng
/2008.01.04
/2008.01.04
Implement
Date
2007.10.26
Ball φ b change into
0.3mm
2.
Confirm/Date
Add a attention about
/2008.01.04
2008.01.04
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ball paste opening size
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1.
Owner/Date
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Title: C627 Hardware Design Guide
CNUT-QT-SH-SoC-C627-Solution-3-06-V01.02.01
Contents
Foreword..................................................................................................5
C627 Applications ...................................................................................5
2.1
2.2
2.3
3.
C627 Application Diagram............................................................................... 5
C627 System Diagram .................................................................................... 6
C627 Work Mechanism ................................................................................... 6
C627 Reference Design Description .....................................................7
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1.
2.
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3.1
C627 Power Supply module............................................................................ 7
3.1.1 C627 Power Supplies Introduction .............................................................. 8
3.1.2 C627 Power Supply Arrangement ............................................................... 9
3.1.3 C627 Power Supply LDO Select guide .......................................................11
3.1.4 C627 Power Supply Layout Guide............................................................. 12
3.2
C626 Host ..................................................................................................... 12
3.2.1 C626 CLKI clock Input
14
3.2.2 C627 Host Interface Layout Guide ............................................................ 14
3.3
C627 LCD Interface Circuit ........................................................................... 15
3.3.1 C627 LCD Interface Layout Guide............................................................. 16
3.4
C627 Sensor Interface Circuit ....................................................................... 16
3.4.1 Camera module power supply LDO selection............................................ 17
3.4.2 C627 Camera Interface Layout Guide ....................................................... 18
3.5
C627 SD Interface Circuit.............................................................................. 18
3.5.1 SD Plug-in/out Hardware Detection ........................................................... 19
3.5.2 SD Plug-in/out Software Detection ............................................................ 20
3.5.3 C627 SD Card Interface Layout Guide ...................................................... 20
3.6
C627 USB Interface Circuit ........................................................................... 20
3.6.1 C627 USB Module active Mechanism ....................................................... 22
3.6.2 USB/Charge Cable Distinguish Method..................................................... 23
3.6.3 C627 USB Interface Layout Guide ............................................................ 23
3.7
C627 Audio Interface Circuit.......................................................................... 24
3.7.1 System Audio Solution with C627 .............................................................. 25
3.7.2 C627 Audio Input
25
3.7.3 C627 Earphone Output Circuit................................................................... 25
3.7.4 C627 Speaker output circuit 26
3.7.5 Audio PA circuit Parameter Selection ........................................................ 27
3.7.6 C627 Audio Interface Layout Guide ........................................................... 28
3.8
C627 Touch Panel Controller Circuit ............................................................. 29
3.8.1 C627 Touch Panel controller Interface Layout guide ................................. 30
3.9
C627 Nand Flash Interface Circuit ................................................................ 30
3.9.1 C627 Nand Flash Interface Layout guide .................................................. 31
3.10 C627 Other Module Interface Circuit ............................................................. 31
3.10.1 PWM Output PWM[0:2]
31
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Title: C627 Hardware Design Guide
CNUT-QT-SH-SoC-C627-Solution-3-06-V01.02.01
3.10.2
3.10.3
3.10.4
3.10.5
4.
Game Key GKA/GKB
31
C627 Vibrator control signal, VIB............................................................... 32
Flash control Signal SLEN 32
Test Interface Test [1:6]
32
C627 Package and Chip Layout...........................................................33
C627 Package Size....................................................................................... 33
C627 Footprint Noted .................................................................................... 34
C627 Chip Layout ......................................................................................... 34
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4.1
4.2
4.3
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Title: C627 Hardware Design Guide
CNUT-QT-SH-SoC-C627-Solution-3-06-V01.02.01
1. Foreword
This document is for hardware engineers who adopt C627 to design multimedia systems。
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To design hardware systems with C627, 4 documents are needed as following:
z C627 Hardware Design Notes (This one)
z C627 Data Sheet
z C627 Reference design schematic
z C627 Reference design BOM
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2. C627 Applications
C627 Application Diagram
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2.1
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C627 is low-power consumption Multimedia Co-processor which can be applied in
portable multimedia devices such as PMP, Mobile Phone and so on.
Figure 2-1 blow shows main function of C627
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Figure 2-1 C627 Multimedia Functions
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Title: C627 Hardware Design Guide
CNUT-QT-SH-SoC-C627-Solution-3-06-V01.02.01
2.2
C627 System Diagram
C627 Work Mechanism
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2.3
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Figure 2-2 below is chip select and address/data bus distribution diagram of system
including C627
Figure 2-2 System diagram(Including C627)
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C627 adopt self-start method. It need not to be downloaded any program by external host,
only some parameters should be configured to make it work properly so C627 can start up
to work very quickly, in millisecond level time(Detail timing parameter please refer C627
Datasheet)
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Communication between C627 and host(such as Base band in Mobile phone) is based on
command-response method through Data bus and address bus high bits. Several address
locations determined by host chip select and address bit can be seen as the
command-response communication window.
图 2-2 Communication Mechanism between Host and C627
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Title: C627 Hardware Design Guide
CNUT-QT-SH-SoC-C627-Solution-3-06-V01.02.01
3. C627 Reference Design Description
3.1
C627 Power Supply module
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Figure 3-1 C627 Power Supply Module
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Figure 3-1 below described all the Power supplies need by C627
Table 3-1 C627 Power supply List
Voltage
(V)
Name
1
1.8
VDDC[1~4]
Core Power Supply
2
2.8/1.8
VDD_HOST
Host Interface IO Power
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Index
3
2.8/1.8
Min
Cur(uA)(1)
Typical
Cur(mA) (1)
Max
Cur (mA) (1)
1.5
45
TBD
0
TBD
TBD
0
1.15
TBD
18.5
1.5
TBD
IO
0
3.07
TBD
SD Interface IO Power
0
0.25
TBD
Description
Supply
VDD_SYS
System Control IO Power
Supply
4
2.8/1.8
VDD_LCD
LCD Interface IO Power
Supply
5
2.8/1.8
VDD_SNR
Camera
Interface
Power Supply
6
2.8/1.8
DC Level 3
VDD_SD
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Title: C627 Hardware Design Guide
CNUT-QT-SH-SoC-C627-Solution-3-06-V01.02.01
Supply
7
2.8V
AVDD_PLL
PLL Power Supply
0
2.38
TBD
8
3.3V
USB_VDD
USB Power Supply
0
2.8
TBD
9
2.8/1.8
VDD_NAND
13.3
0.07
TBD
0
TBD
TBD
0
11.8
TBD
76.6
TBD
TBD
Nand Flash Interface IO
Power Supply
10
3.3~4.2
PBAT[1~2]
Internal audio PA Power
Supply
11
3.0
AVDD_CDC
Codec
Analog
Power
12
3.0
AVDD_TP
Touch Panel Controller
analog Power Supply
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Supply
C627 Power Supplies Introduction
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3.1.1
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Attention:
(1) All the current values listed in the above table is just the current consumed by C627
chip, all the peripherals current is not included. When you select LDO/DCDC power
source, Power consumption of both the C627 and its peripherals should be considered.
1. Core power Supply: VDDC[1:4]:
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VDD_Core s power supply for all the C627 internal Digital logic and IP core, so there will
be very high current peak value when C627 changes from Power down mode into Power
up mode. This requires that power source should be able to endure a high peak output
current which means that it should not power off because of C627 power up peak current.
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In addition, in some C627 work mode(such as MP4 playing), VDD_Core current could be
quite high. So we strongly suggest that VDD_Core should not to share PMU 1.8V output
with other system device (such as Baseband chip and Flash/ram MCP), otherwise a
obvious dropout on 1.8V output even whole PMU protect-power off may occur.
2. IO Power Supply: VDD_HOST/SYS/LCD/SNR/SD/NAND:
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Nearly all the chips including C627 may have the Current/voltage-leak problem caused by
different IO domain power supply level. To avoid this problem, we suggest to use one LDO
output as source of all these IO power supplies. In addition, power supply network can not
appear such a circumstance that a net work is both a C627 IO power supply and enable
signal of a LDO whose output is another C627 IO Power supply(As desribed in Figure 3-2
below), otherwise a current/voltage leak loop will occur and LDO output stay at a mid-level
voltage not Zero when enable signal go inactive consequently there will be a continuous
leak current in system power-off mode.
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Title: C627 Hardware Design Guide
CNUT-QT-SH-SoC-C627-Solution-3-06-V01.02.01
Figure 3-2 current/Voltage leak loop
VIO_1
Internal
Leak Path
Current voltage
Leak Loop
Enable
LDO
IC
Output
VIO_2
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Exteranl
Power
VBAT
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3. Analog Power Supply: AVDD_PLL/CDC/TP:
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These Analog 3 Power Supplies are for PLL(Phase Lock Loop), Audio Codec, Touch
Panel Controllers irrespectively. Because All these analog module are quite sensitive to
Power noise and ripples, High PSRR LDOs should be chosen as C627 analog power
source. These 3 power supply can share a common High PSRR 3.0V LDO output to
simply system design
4. USB Module Power Supply: VDD_USB:
A 3.3 LDO output should used as VDD_USB power source. Lower level USB module
Power source may lead to USB access may fail
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5. Audio PA Power Supply: PBAT[1:2]
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PBAT[1:2] is Power Supply of internal audio PA which is designed to drive external 8OHM
speaker, So Current derived from these 2 pins may be quite high. PBAT[1:2] input voltage
ranges from 3.3V to 4.2V. Mobile phone Li-ion Battery voltage may be connected to
PBAT[1:2] through a LC network to filter ripples and noises.
3.1.2
C627 Power Supply Arrangement
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Base on the Introduction in 3.1.1, System designer can adopt a dual-output 1.8/2.8
LDO(Called LDOA) for Core and all IO Power supply; a high PSRR dual-output 3.0/3.3
LDO(Called LDOB) as all Analog and USB module Power supplies; “AVBAT” separated
from Li-ion battery voltage through a LC network as PBAT[1:2],Described as following
Table 3-2 and Table 3-3/3-4/3-5
Table 3-2 Power Supply Arrangement
DC Level 3
Name
Power Source
VDDC[1~4]
1.8V(LDOA VOUT1)
VDD_HOST
2.8V(LDOA VOUT2)/ 1.8V_IO(LDOA VOUT1)
VDD_SYS
2.8V(LDOA VOUT2)/ 1.8V_IO (LDOA VOUT1)
VDD_LCD
2.8V(LDOA VOUT2)/ 1.8V_IO (LDOA VOUT1)
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Title: C627 Hardware Design Guide
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VDD_SNR
2.8V(LDOA VOUT2)/ 1.8V_IO (LDOA VOUT1)
VDD_SD
2.8V(LDOA VOUT2)/ 1.8V_IO (LDOA VOUT1)
AVDD_PLL
3.0V(LDOB VOUT1)
USB_VDD
3.3V(LDOB VOUT2)
VDD_NAND
2.8V(LDOA VOUT2)/ 1.8V_IO (LDOA VOUT1)
PBAT[1~2]
AVBAT
AVDD_CDC
3.0V(LDOB VOUT1)
AVDD_TP
3.0V(LDOB VOUT1)
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Figure 3-3 LDOA Reference design
Figure 3-5 AVBAT Reference design
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Figure 3-4 LDOB Reference design
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Title: C627 Hardware Design Guide
CNUT-QT-SH-SoC-C627-Solution-3-06-V01.02.01
3.1.3
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Attentions
1.
To guarantee the proper system start-up and initialization, C627 VDDC,
VDD_HOST, VDD_SYS should be powered at the same time with system bus.
So LDOA enable signal “VDD_IO_HIGH” must be a system bus power supply
2.
Base band GPIO signal can never be used as LDOA Enable signal, other
wise C627 may pull system bus this will make system startup fail.
3.
Any C627 Power supply can never be used as LDOA enable signal described
as 3.1.1.
C627 Power Supply LDO Select guide
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Several electrical characteristic should be consider when select LDO for C627
power supply
1. Output Current
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The LDO max output should be larger than corresponding C627 Power supply
max current with at least 50% margin. VDDC powers all the digital logic and IPs,
its current is quite high. LDO Output current for it should be atleast 150mA, and
should not be protect-power off when C627 VDDC leak current occurs.
2. Power dissipation and Package
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LDO Power dissipation can be calculated by the formula P = (VIN - VOUT) * IOUT,
Because of low voltage level and high current, dissipation of VDDC LDO may be
quite high.
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Then Package can be determined according to package power dissipation table
provided by LDO Vendor. Following table 3-3 is a example from Torex XC6219
LDO Product.
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Table 3-3 Torex LDO package rating power dissipation
Parameter
Power
Dissipation
Symbol
SOT-25
SOT-89
Rating
Units
250
Pd
USP-6B
500
mW
100
3. PSRR (Power Supply Reject Rate)
C627 Analog modules are quite sensitive for power supply noise and ripple, PSRR
of LDO for AVDD_PLL/CDC/TP should be at least 70dB.
4. Output Fast Discharge Path
If enable signal of 3.3 LDO is driven by BB GPIO, this LDO should have no fast
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discharge path on output pin, otherwise there may be a current leakage from nearby IO
power domain though this fast discharge path to ground when LDO disabled.
3.1.4
C627 Power Supply Layout Guide
1. PCB space is quite limited in most circumstance, digital ground VSS and analog
ground AVSS can share the same main ground. It is much better that AVSS is
connected directly to main ground through a single point (via or resistor)
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2. Wire width of CAP should be at least 8mil, Its 4.7u and 0.1u decouple
capacitors should be placed as closed to Pin CAP as possible
3. Wire width of VDDC should be at least 15mil
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4. Wire width of VDD_HOST/SYS/LCD/SNR/SD/NAND/USB should be at least
10mil
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5. AVDD_PLL/CDC/TP is analog power supply, their traces should be
well-shielded by ground in all directions and wire width should be at least 15mil
3.2
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6. PBAT is audio PA power supply, their traces should be well-shielded by ground
in all directions and wire width should be at least 20mil
C626 Host
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For the debug and test convenience, it is suggested to design some test point of host
interface signal especially when C627 is work with a new Host/Base Band chip.
Figure 3-6 C627 Host Interface Module
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Table 3-4 C627 Host Interface Signal Description
Signal
Name
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Signal Description
LS_SEL
C627 Bypass Control Signal
1:Host access LCD directly through address/data bus
0:Host access C627 IOU through address/data bus
ADDR22
Normal Mode: C627 IOU command/data control
Power Down/Bypass Mode: LCD command/data control
ADDR1
You can use a high address bit or Ground as its source
WR_N
Normal Mode: C627 IOU Write enable input(active low)
Power Down/Bypass Mode: LCD Write enable input
RD_N3
Normal Mode: C627 IOU Write enable input(active low)
Power Down/Bypass Mode: LCD Write enable input
CS_N
Normal Mode:C627 chip select(Active low)
Power Down/Bypass Mode: Main LCD Chip Select
LCS2_N
Power Down/Bypass Mode: Sub LCD Chip Select
RESET_N
C627 reset input, active low
AD[0:15]
Normal Mode: C627 host data bus
Power Down/Bypass Mode: LCD data bus
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1
INT
C627 interrupt output to Host, Polarity Adjustable
CLKI
C627 Clock Input(ranges from 3MHz to 32MHz, Typically 13MHz)
CLKO
C627 Clock output
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PWDN
C627 power down control input
1: C627 enter normal mode
0: c627 enter power down mode
Attentions:
1. System Designer can assign a host GPIO or address bit as LS_SEL source, according
to the compare table below
Table 3-5 LS _SEL Signal Source Compare
GPIO
Have no effect on RF
Performance
1. have to occupy GPIO
resource
2. LCD refresh is slow
Address bit
May affect RF
Performance
1.Easy to control
2.LCD refresh is fast
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2. In order to minimize the effected on RF performance from ADDR2, a high address bit
should be chosen to drive ADDR2
3.2.1
C626 CLKI clock Input
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Figure 3-7 C627 Clock Input
3.2.2
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The frequency of C627 clock input ranges from 3MHz to 32MHz, typical value is 13MHz.
BB clock or output from a dedicate can both be used as this clock source, as described in
Figure3-7 above. Other method has it own merit and shortcoming listed in Table 3-6.
C627 Host Interface Layout Guide
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1. C627 Host Interface signal AD [0:15], CS_N, LCS2_N, WR_N, RD_N, ADDR2 should
be viewed as high-speed signal interface when layout.
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a. Wire width and security distance should be at least 4mil. And all the traces be far-away
from RF part.
b. Distance with other signals should be 6 mil at least.
c. There should be a complete reference ground for these signals so that the current
return path length is minimum.
d. The traces for these signals should be parallel and equal in length so that all the
signals’ time delay is the same
2. The frequency of signal “ClKI” is typically 13MHz, it should also be treated as
high-speed signal interface when layout.
a. Wire width is 6 mil at least.
b. Shield this signal with ground in all directions. If these all over shield methods are
difficult, the distance to other traces should be as far as possible.
3. RESET_N, PWDN, INT are not high speed signals, it can be deled with in a relative low
priority.
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3.3
C627 LCD Interface Circuit
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Figure 3-8 C627 LCD Interface Circuit
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Table 3-6 C627 LCD interface Circuit design notes
Index
Signal
Note 1
LCD_RST#
Active Low, support Active Low reset LCD
Note 2
LO_D[0:15]
1. for 16-bit LCD, use LO_D0~D15
2. for 8-bit LCD, use LO_D0~D7; LO_D8~D15 can be left not connect
3. for 9-bit LCD, use LO_D0~D8; LO_D9~D15 can be left not connect
3.3.1
Design Notes
C627 LCD Interface Layout Guide
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1. C627 LCD Interface signal LO_D[0:15], LO_MCSN, LO_SCSN、LO_WRN、LO_RDN、
LO_ADS should be viewed as high-speed signal interface when layout. And all the traces
be far away from RF part
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a. Wire width and security distance should be at least 4mil.
b. Distance with other signals should be 6 mil at least.
c. There should be a complete reference ground for these signals so that the current
return path length is minimum.
d. The traces for these signals should be parallel and equal in length so that all the
signals’ time delay is the same
3.4
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2. LO_RSTN is not a high speed signal; it can be deled with in a relative low priority.
C627 Sensor Interface Circuit
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Figure 3-9 C627 Camera Interface Circuit
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Title: C627 Hardware Design Guide
CNUT-QT-SH-SoC-C627-Solution-3-06-V01.02.01
表 3-7 C626 Sensor Interface Design Notes
Index
1
Signal
Design Notes
AVDD
The Camera Analog Power supply should be filtered sufficiently though RC
network, otherwise there swill be
2
C_SCK/ C_SDA
The 4.7kOHM pull-up resistor on signal ”SCK/SDA” is just a suggested value,
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system designer can modify it according to the camera module used, but
general speaking, 4.7kOHM is proper to most camera driver ICs
C_MCLK/C_PCLK
Because the frequency of these 2 clocks is quite high, a staring-end matching
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network is required. But the capacitor can be just reserved, only adopt this
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when necessary.
C_PWDN
C_PWDN is high-impedance when C627 is in power-down mode, so designed
can use pull-up/or pull-down resistor as following:
Camera enter standby when C_PWDN is high: a pull-up resistor should be used
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Camera enter standby when C_PWDN is low: a pull-down resistor should be
3.4.1
used
Camera module power supply LDO selection
System designers can use C_PWDN to control camera power consumption, but if the
power down leak current is too high, a dedicate LDO should be used so that camera
power supply can be shut down independently.
Just as host interface, a LDO without output fast discharge path should be used,
otherwise there will be a leak current from Camera interface signal (for example
C_RESET) to Camera power and LDO output to ground.
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3.4.2
C627 Camera Interface Layout Guide
1. C627 Camera Interface signal C_D[0:7] should be viewed as high-speed signal
interface when layout.
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a. Wire width and security distance should be at least 4mil. And all the traces be far-away
from RF part.
b. Distance with other signals should be 6 mil at least.
c. There should be a complete reference ground for these signals so that the current
return path is minimum.
d. The traces for these signals should be parallel and equal in length so that all the
signals’ time delay is the same
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2. The frequency of signal MCLK/PCLK is typically 13MHz, it should also be treated as
high-speed signal interface when layout.
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a. Wire width is at-least 6 mil.
b. Shield this signal with ground in all directions. If these all over shield methods are
difficult, the distance to other traces should be as far as possible.
c. The starting-end RC network of MCLK/PCLK should be placed closed to C627/Cemera
module respectively
3. VSYNC and HREF are low frequency synchronous signals, be careful they are not
disturbed by other high-speed signals
C627 SD Interface Circuit
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3.5
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4. C_SCL/C_SDA should be routed in parallel and equal in length so that signal time delay
is the same.
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图 3-10 C627 SD Interface Circuit
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Table 3-8 C627 SD Interface Design Notes
Signal
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Index
SD_CLK_IN
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1
2
3
Design Notes
A high-capacitance ESD device should not be use on
this signal, otherwise the rise time may be too long,
some SD card may not be compatible. System
designer can consider to use a tip-end discharge pad
instead of ESD device.
SD_CMD_IN
Suggest to adopt a 10kOHM pull-up resistor on this
signal to prevent unstable SD card access
SD card DAT3
Should be pulled up to 2.8V power supply VDD_SD to
guarantee card compatibility
4
3.5.1
SD_INDEC
May be used for card plug-in hardware detection
SD Plug-in/out Hardware Detection
Signal SD_INDEC is a card status indicator described as following Table 3-9, it can be
connected to host GPIO or interrupt input. For GPIO input, High means no card in socket,
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low means card in socket; for Interrupt input, rising edge means card plug-in, falling edge
means card plug-out.
Table 3-9 SD_INDEC Level/ SD CardStatus
Card Socket Pin10 is not connected to
ground signal SD_INDEC is pulled to 2.8V
Card Plug-in
Card Socket Pin10 is connected to ground
signal SD_INDEC is low
SD Plug-in/out Software Detection
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3.5.2
Without Card
3.5.3
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When SD Card socket does not provide the signal SD_INDEC, software can also send out
inquire command for time to time, if proper reply does not come back in a prior-defined
time out period, SD Card is supposed to be unavailable.
C627 SD Card Interface Layout Guide
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1. SD_CLK should also be treated as high-speed clock signal interface when layout.
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a. Wire width is at-least 6 mil.
b. Shield this signal with ground in all directions. If these all over shield methods are
difficult, the distance to other traces should be as far as possible
2. SD_CMD and SD_DAT0 should be viewed as high-speed signal interface when layout
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a. Wire width and security distance should be at least 4mil. And all the traces be far-away
from RF part.
b. Distance with other signals should be 6 mil at least.
c. There should be a complete reference ground for these signals so that the current
return path is minimum.
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3. EMI/ESD devices should be placed close to SD socket in order to guarantee ESD
protect effect
C627 USB Interface Circuit
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3.6
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Figure 3-11 C627 USB Interface Circuit
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C627 USB Interface Circuit Design Notes
1. According to USB1.1 Spec, a 1.5KOHM pull-up resistor should be added to C627
USB_D+ signal.
2. In order to make USB_D- signal stable, a 150kOHM resistor is added.
3. PAI style filter network and ESD device should be adopted to increase ESD/EMI
performance. All the ESD/EMI separate parts and 1.5k pull-up resistor can be
replaced by a integrate device PACUSB-U1/U2/U3 from CMD.
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3.6.1
C627 USB Module active Mechanism
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C627 provide a controllable GPIO output to enable USB_D+ Pull up. When a Cable plug
in Baseband will let C627 exit Power down mode at first, then prepare C627 USB module
in the second step, USB_PULL go high in the third step, USB_D+ will be high
consequently. At this time BB can judge the cable plug-in is USB cable or charger cable
through the method described in 3.6.2. If it is a USB cable, USB Host can simultaneously
sense that a USB device has been attached, then USB connection start. This mechanism
can guarantee USB hot plug-in success without enable USB manually first. Described as
following figure 3-12
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Figure 3-12 USB Module Active Mechanism
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3.6.2
USB/Charge Cable Distinguish Method
According to new national charger interface specification (YD/T 1591-2600), charge cable
will use USB A Series connector. System designers can use only one Cable for both
charge and USB access. In the charger specified by YD/T 1591-2600, USB_D+ and
USB_D- are short together. So a 2-input “and” gate can be used to distinguish USB Host
and charger, as described in Table 3-10.
Table 3-2 USBD+/- & AND Output Level
Mode
D+ Level
1
1
Charger attached(D+ and D- are short together)
high
2
USB Differential 1
high
USB Differential 0
low
Single-END0(SE0)
low
D- Level
high
high
low
low
high
low
low
low
low
low
low
high
low
low
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USB Reset
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No USB/charger attached
AND ouput
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Index
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Attentions
1. D+ is strongly pulled up by a 1.5kOHM resistor and D- is weakly pulled low by a 150k
OHM resistor, so they will be both high when shorted.
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It can be found that only in Charger attached mode AND gate output high From Table 3-10.
So the AND gate output ca be connected to a GPIO. Every time Baseband senses a
charge voltage plug-in it should judge it is a real charger or USB cable Figure 3-13 gives
out the details.
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Figure 3-13 USB/charger Distinguish
3.6.3
C627 USB Interface Layout Guide
C627 USB_D+/D- should be routed according to differential signal:
a. USB_D+/D- PCB traces should always be parallel.
b. wire width is and internal distance(between USB_D+/D- traces) is 4mil
c. It is better to shield these trace with ground in all directions, If this is difficult distance
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with other traces should be as far as possible.
3.7
C627 Audio Interface Circuit
Table 3-11 627 Audio Interface Signal
HR
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3
HL
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4
MIC1
I
5
MIC2
I
6
MINP
I
7
MINN
I
8
SKPP
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9
SPKN
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10
SPIN
Earphone R-channel
output
Earphone L-channel
output
To Drive earphone
To Drive earphone
Audio Analog Input1
From
for Mixer and ADC
Micro-phone
Audio Analog Input2
From
for Mixer and ADC
Micro-phone
LINE-IN
Positive
Audio Analog input
LINE-IN
system
On
Board
system
On
Board
or
Ear
or
Ear
Differential audio input for record or mix
Negative
Audio Analog input
Differential audio input for record or mix
Internal Speaker PA
Differential
output
Positive output
speaker directly
Internal Speaker PA
Differential
Negative output
speaker directly
Internal Speaker PA
From MIXOUT or other audio source to be
Input
amplified
output
to
drive
external
to
drive
external
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Function
To Drive External/Internal Audio PA
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2
Describe
Mono output
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Direction
MIXOUT
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Signal
1
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Index
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3.7.1
System Audio Solution with C627
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Figure 3-14 System Audio solution with C627
C627 Audio Input
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3.7.2
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Some external audio circuit in C627 design have been canceled because of C627 analog
part enhancement such as earphone output analog switch and OB-MIc pre-amplifier
circuit. The Internal Audio PA added can directly drive a 8OHM Speaker and differential
audio input and output can provide a high CMRR. Detail Analog part description and audio
Path can be found in C627 Datasheet
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C627 have a single-end audio input and a pair of differential audio inputs, system designer
can assign these inputs to upstream/Downstream voice signals according to system
situations. Our suggestion is to assign single-end Audio input MIC1/MIC2 to On Board
MIC/Earphone MIC upstream voice, differential audio inputs to downstream receiver voice
output. So that both upstream and downstream voice can be mixed or record by c627.
3.7.3
C627 Earphone Output Circuit
Figure 3-15 C627 Ear phone ouput Circuit
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Attention: A_EARPHONE_OUTR/L is output from C627 HR/HL output
C627 Ear phone output can be connected to earphone jack directly without external
analog switch, because Multimedia audio signal and BB voice signal have been switched
internal. The value of serial resistor and Capacitor should be determined according to
Frequency cross point. In order to get high audio performance, this frequency cross point
should be as lower as possible and capacitor value should be no less than 22uF.
3.7.4
C627 Speaker output circuit
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C627 has an internal audio PA, so if the system has only one speaker, you can use the
internal PA and connect SPKN/SPKP to speaker directly
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Figure 3-16 C627 Internal PA Drives Speaker
Attentions: 1. A_SPIN is input to C627 SPIN
2. PA_COM is from internal PA power decouple pin PACOM
3. A_MIXOUT is output from C627 MIXOUT
4. A_SPEAKER_N/ A_SPEAKER_N is output from C627 SPKP/SPKN
C627 has only integrated a audio PA, RC net work has to be configured outside, as shown
in the figure above. C9&R12 composes the input RC network and determines low limit of
PA work frequency range. Normally，R12 should be 20k for the internal audio PA ;
C10&R13 composes the feedback RC network and determines high limit of PA work
frequency range, which should be no less than 20KHz.
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If the system has 2 speakers you can connect MIXOUT signal to an external audio PA as
its input , to drive the other or both speaker.
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Figure 3-17 External PA Drives Speakers
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Attentions: 1. A_MIXOUT is output from C627 MIXOUT
2. BB_AMP_ON is controlled by a BB GPIO
In the above figure, C4/R75 and C5/R7 compose input RC network for audio PA IN-/IN+
respectively and determines low limit of PA work frequency range.
Audio PA circuit Parameter Selection
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3.7.5
and
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Suggested external audio PA is Class-D ones such as TPA2010(TI)
NCP2820(Onsemi) for higher efficiency and less heat produced than Class-AB.
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The low limit of work frequency range determined by input RC value and amplify multiple
determined by input and feed back impedance are important for both internal and external
audio PA. This is related closely to the some factors such as audio resonance cavum size,
amplify multiple and speaker frequency response, etc.
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General speaking, the audio PA output power can not exceed speaker rated input power,
or there will audio distortion. Exceed more, distort more. Especially for low frequency part,
as shown in following figure, most speakers have a low response in low frequency part, if
audio PA outputs too much low frequency power, there will be an obvious audio distortion.
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Figure 3-18 Common Speaker Frequency
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On the other hand, too less low frequency power will make audio hear screechy. So the
final audio PA parameter must be a compromise between loudness, distortion and
screechy, according to following 3 basic rules
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1. Under the same loudness requirement, bigger audio resonance cavum size can amplify
audio more multiple; this allows a relatively lower audio PA circuit amplify multiple which
can decrease audio distortion.
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2. Under the same audio distortion requirement, a larger rated input power and better
frequency response curve speaker give out more low frequency power, you need not set a
higher low frequency limit, this consequently avoid audio hear screechy.
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3. Relatively higher low frequency limit and lower PA amplify multiple can decrease audio
distortion, but will lead to less loudness and more serious screechy.
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Based on the analysis above, the best speaker audio performance should based on larger
resonance cavum, better speaker frequency response curve and larger speaker rate
power
3.7.6
C627 Audio Interface Layout Guide
1. All the C627 input/output audio signal is sensitive analog signal
a. wire width should be no less than 6 mil,
b. All the C627 audio traces should be shielded by Ground in all directions.
2. MINN/MINP and SPKP/SPKP are 2 pair of differential signals, their traces should be
routed always in parallel and distance should be no more than 4mil.
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3.8
C627 Touch Panel Controller Circuit
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Figure 3-19 C627 Touch Panel Controller Circuit
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C627 has integrated a internal resistor-type touch panel controller to simplify system
design. Like separate touch panel controller, it always serves as BB I2C slave and I2C is
0xBC (Write) and 0xBD (Read). Several notes should be paid attention to in design
Table 3-12 C627 Touch Panel Controller Interface Design Notes
Index
TP_SCL/ TP_SDA
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1
Signal
Design Notes
C627 touch panel controller is controller by BB through I2C bus; system
designer must guarantee that no device on I2 bus has the same slave
address as C627.
The pull-up resistors pad is just reserved, general speaking, only 1 resistor
for SCL and SDA respectively is enough.
2
TP_INT
This signal should be connected to a BB interrupt input
3
A_TP_XP/XN/YP/YN
These 4 signals are analog signal for position detection, designer should
assign a 1nF capacitor for each signal in order to filter system noise and
ripples. ESD-protect device should be placed close to LCD connect.
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3.8.1
C627 Touch Panel controller Interface Layout guide
3.9
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1. TP_SCL/TP_SDA should be routed in parallel and equal in length so that signal
time delay is the same.
2. A_TP_XP/XN/YP/YN are analog signals
a. Wire width is no less than 6 mil
b. These signal traces should be shielded by ground in directions
c. The connection order should be C627---Capacitor(1nF)---ESD device---LCD
touch panel pad
C627 Nand Flash Interface Circuit
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Figure 3-20 C627 Nand Flash Interface Circuit
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All the Nand Flash Interface signal is multiplexed with other signals, so must be
configured before use.
3.9.1
C627 Nand Flash Interface Layout guide
C627 Nand Flash Interface signal NF_DAT [0:7], NF_CEN, NF_WEN, NF_REN, NF_ALE,
NF_CLE, NF_RBN should be viewed as high-speed signal interface when layout.
b. Distance with other signals should be no less than 6 mil.
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a. Wire width and security distance should be at least 4mil. And all the traces be far-away
from RF part.
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c. There should be a complete reference ground for these signals so that the current
return path is minimum.
3.10 C627 Other Module Interface Circuit
PWM Output PWM[0:2]
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3.10.1
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d. The traces for these signals should be parallel and equal in length so that all the
signals’ time delay is the same
PWM signal is used to control flash, it must be paid attention that these signal can not
drive led directly. MOSFET should be use to switch on/off led as following
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Figure 3-21 C627 PWM Signal Usage
3.10.2
Game Key GKA/GKB
C627 has 2 dedicated Game controller keys, GKA and GKB. These 2 signals are low
when
C627 is in power down and reset mode, so the common mode without key-pressing
should be pulled-down in order to avoid power down leak current.
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C627 Vibrator control signal, VIB
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Figure 3-22 C627 Game Key Interface Circuit
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C627 vibrator control signal VIB(Multiplexed with GKB) is used to switch on/off through a
MOSFET, this signal can not be connected to Vibrator.
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Figure 3-23 C627 Vibrator Interface Circuit
Flash control Signal SLEN
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3.10.4
SLEN is for Camera flash lamp driver IC, the switch on duration is controllable through
register configuration
3.10.5
Test Interface Test [1:6]
Test Interface is for hardware debug convenience. Designer should reserve test points for
these test points in the first design version.
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4. C627 Package and Chip Layout
4.1
C627 Package Size
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Figure 4-1 C627 Package Outline
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Table 4-1 C617 Package Size
D
E
MAX(mm)
10.1
10.1
NOR(mm)
10.0
10.0
MIN(mm)
9.9
9.9
4.2
D1
φb
E1
e
0.35
8.45
8.45
0.30
0.65
0.25
C627 Footprint Noted
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Figure 4-2 C627 Footprint Ball opening
The pad opening size on PCB recommended is 0.3mm~0.32mm, smaller or bigger
opening size will lead to bad soldering risk in mass production of PCB assembly!!!
C627 Chip Layout
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4.3
C627 PBGA ballφb is 0.3mm and ball centre-to-centre distance is 0.65mm, so there is
about 13 mil space between balls. The second ring signals (Yellow-marked) can easily
routed out between outer ring balls (Green-marked) as shown in following Figure.
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Figure 4-3 The Second Circle Signal Route Out
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The Third ring can route out from space between the external and internal balls as shown
in following Figure
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Figure 4-4 The Third Circle signal Route Out
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