ETC WT61P4

Weltrend Semiconductor, Inc.
WT61P4
Embedded Micro-Controller for Monitor
(Flash Memory Type)
Data Sheet
REV. 1.03
Aug 20, 2004
The information in this document is subject to change without notice.
Weltrend Semiconductor, Inc. All Rights Reserved.
2F, No. 24, Industry E. 9th RD., Science-Based Industrial Park, Hsin-Chu, Taiwan
TEL:886-3-5780241 FAX:886-3-5794278.5770419
Email:[email protected]
WT61P4 v1.03
Monitor Controller
GENERAL DESCRIPTION
The WT61P4 is a microcontroller for digital controlled monitor with 1) 8051 compatible cpu, 2) 64K
bytes Flash memory, 3) 1024 bytes SRAM, 4) 16 PWMs, 5) SYNC signal processor, 6) 2 timers, 7)
DDC1/2B interface, 8) master/slave I2C interface, 9) 8-bit A/D converter, 10) watch-dog timer, 11) ISP,
12) power down mode 13)IR detect.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
8-bit 8051 compatible CPU with 12/24MHz operating frequency
64K bytes flash memory, 1024 bytes SRAM (256 bytes internal + 768 bytes external)
12/24MHz crystal oscillator
16 channels PWM outputs (15 8-bit + 1 16-bit)
Sync signal processor with H+V separation, H/V frequency counter, H/V polarity detection/control
and clamp pulse output
Programmable free-running SYNC signal output & White video pattern (Horizontal frequency up to
250KHz with programmable H pulse width and V pulse width)
Programmable H and V overflow interrupt for fast blanking
Two timers compatible to 8051
DMA DDC1/2B module for EDID1.3, EDID2.0 (A2/A3, A6/A7) and Enhance EDID (60/61)
Fast mode master/slave I2C interface (up to 400KHz)
8-bit A/D converter with 4 selectable inputs
Watchdog timer
Maximum 35 programmable I/O pins (PLCC package)
Two external interrupt request input
5/3.3 volt operate voltage supported
Low VDD reset supported
ISP function supported
Power down mode supported
IR detect
C compiler supported
ORDERING INFORMATION
Package Type
Part Number
40-pin PDIP
61P4-N400WT(3.3v/5v)
40-pin PDIP
61P4-N401WT(3.3v)
42-pin Shrink PDIP
61P4-K420WT(3.3v/5v)
42-pin Shrink PDIP
61P4-K421WT(3.3v)
44-pin PLCC
61P4-L440WT(3.3v/5v)
44-pin PLCC
61P4-L441WT(3.3v/5v)
Weltrend Semiconductor, Inc.
Page 2
WT61P4 v1.03
Monitor Controller
PIN ASSIGNMENT AND PACKAGE TYPE
VDD=3.3v/5v
PD7/PWM2/VIN2
PE0/PWM0
NRES
VDD3V
VDD5V
GND
OSCO
OSCI
PB6/SDA2
PB5/SCL2
PB4/PAT
PB3/FDO/T0
PB2/FDI/T1
PB1/NIRQ2/IRIN
PB0/NIRQ1
PC7/SOGIN/P17
PC6/P16
PC5/P15
PC4/P14
PC3/AD3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
61P4_N400
VDD=3.3v
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VIN1
HIN1
PD6/PWM3/HIN2
PD5/PWM4/P10
PD4/PWM5/P11
PD3/PWM6/P12
PD2/PWM7/P13
PD1/HOUT
PD0/VOUT
PA7/PWM13/CLAMP
PA6/PWM12/1/2VO
PA5/PWM11/1/2HO
PA4/PWM10
PA3/PWM9
PA2/PWM8
PA1/SCL1/RXD
PA0/SDA1/TXD
PC0/AD0
PC1/AD1
PC2/AD2
PD7/PWM2/VIN2
PE1/PWM1
PE0/PWM0
NRES
VDD3V
GND
OSCO
OSCI
PB6/SDA2
PB5/SCL2
PB4/PAT
PB3/FDO/T0
PB2/FDI/T1
PB1/NIRQ2/IRIN
PB0/NIRQ1
PC7/SOGIN/P17
PC6/P16
PC5/P15
PC4/P14
PC3/AD3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
VDD=3.3v/5v
61P4_K420
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
PD7/PWM2/VIN2
VIN1
HIN1
PD6/PWM3/HIN2
PD5/PWM4/P10
PD4/PWM5/P11
PD3/PWM6/P12
PD2/PWM7/P13
PD1/HOUT
PD0/VOUT
PA7/PWM13/CLAMP
PA6/PWM12/1/2VO
PA5/PWM11/1/2HO
PA4/PWM10
PA3/PWM9
PA2/PWM8
PA1/SCL1/RXD
PA0/SDA1/TXD
PC0/AD0
PC1/AD1
PC2/AD2
PE3/PWM15
PE2/PWM14
PE1/PWM1
PE0/PWM0
NRES
VDD3V
GND
OSCO
OSCI
PB6/SDA2
PB5/SCL2
PB4/PAT
PB3/FDO/T0
PB2/FDI/T1
PB1/NIRQ2/IRIN
PB0/NIRQ1
PC7/SOGIN/P17
PC6/P16
PC5/P15
PC4/P14
PC3/AD3
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
PD7/PWM2/VIN2
VIN1
HIN1
PD6/PWM3/HIN2
PD5/PWM4/P10
PD4/PWM5/P11
PD3/PWM6/P12
PD2/PWM7/P13
PD1/HOUT
PD0/VOUT
PA7/PWM13/CLAMP
PA6/PWM12/1/2VO
PA5/PWM11/1/2HO
PA4/PWM10
PA3/PWM9
PA2/PWM8
PA1/SCL1/RXD
PA0/SDA1/TXD
PC0/AD0
PC1/AD1
PC2/AD2
39
38
37
36
35
34
33
32
31
30
29
PD5/PWM4/P10
PD4/PWM5/P11
PD3/PWM6/P12
PD2/PWM7/P13
PD1/HOUT
PD0/VOUT
PA7/PWM13/CLAMP
PA6/PWM12/1/2VO
PA5/PWM11/1/2HO
PA4/PWM10
PA3/PWM9
NRES
VDD5V
NC1
GND
OSCO
OSCI
PB6/SDA2
PB5/SCL2
PB4/PAT
PB3/FDO/T0
PB2/FDI/T1
7
8
9
10
11
12
13
14
15
16
17
VDD=3.3v/5v
61P4_L441
(PLCC)
PB1/NIRQ2/IRIN
PB0/NIRQ1
PC7/SOGIN/P17
PC6/P16
PC5/P15
PC4/P14
PC3/AD3
PC2/AD2
PC1/AD1
PC0/AD0
PA0/SDA1/TXD
PC7/SOGIN/P17
PC6/P16
PC5/P15
PC4/P14
PC3/AD3
PC2/AD2
PC1/AD1
PC0/AD0
PA0/SDA1/TXD
PA1/SCL1/RXD
PA2/PWM8
18
19
20
21
22
23
24
25
26
27
28
VDD=3.3v/5v
61P4_L440
(PLCC)
61P4_K421
6
5
4
3
2
1
44
43
42
41
40
6
5
4
3
2
1
44
43
42
41
40
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VDD5V
GND
OSCO
OSCI
PB6/SDA2
PB5/SCL2
PB4/PAT
PB3/FDO/T0
PB2/FDI/T1
PB1/NIRQ2/IRIN
PB0/NIRQ1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
PE0/PWM0
PE1/PWM1
VDD3V
PE3/PWM15
PD7/PWM2/VIN2
NC2
VIN1
HIN1
PD6/PWM3/HIN2
PD5/PWM4/P10
PD4/PWM5/P11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
VIN1
HIN1
PD6/PWM3/HIN2
PD5/PWM4/P10
PD4/PWM5/P11
PD3/PWM6/P12
PD2/PWM7/P13
PD1/HOUT
PD0/VOUT
PA7/PWM13/CLAMP
PA6/PWM12/1/2VO
PA5/PWM11/1/2HO
PA4/PWM10
PA3/PWM9
PA2/PWM8
PA1/SCL1/RXD
PA0/SDA1/TXD
PC0/AD0
PC1/AD1
PC2/AD2
VDD=3.3v
VDD3V
NRES
PE0/PWM0
PE1/PWM1
PE2/PWM14
PE3/PWM15
NC
PD7/PWM2/VIN2
VIN1
HIN1
PD6/PWM3/HIN2
PE2/PWM14
PE1/PWM1
PE0/PWM0
NRES
VDD3V
VDD5V
GND
OSCO
OSCI
PB6/SDA2
PB5/SCL2
PB4/PAT
PB3/FDO/T0
PB2/FDI/T1
PB1/NIRQ2/IRIN
PB0/NIRQ1
PC7/SOGIN/P17
PC6/P16
PC5/P15
PC4/P14
PC3/AD3
61P4_N401
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Weltrend Semiconductor, Inc.
Page 3
39
38
37
36
35
34
33
32
31
30
29
PD3/PWM6/P12
PD2/PWM7/P13
PD1/HOUT
PD0/VOUT
PA7/PWM13/CLAMP
PA6/PWM12/1/2VO
PA5/PWM11/1/2HO
PA4/PWM10
PA3/PWM9
PA2/PWM8
PA1/SCL1/RXD
WT61P4 v1.03
Monitor Controller
PIN DESCRIPTION (5V-package)
Pin No.
441 440 420 400
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
1
2
-
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
-
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
1
-
Pin Name
I/O
Description
PE3/PWM15
PE2/PWM14
VDD3V
PE1/PWM1
PE0/PWM0
NRES
VDD3V
VDD5V
NC
GND
OSCO
OSCI
PB6/SDA2
PB5/SCL2
PB4/PAT
PB3/FDO/T0
PB2/FDI/T1
PB1/NIRQ2/IRIN
PB0/NIRQ1
PC7/SOGIN/P17
PC6/P16
PC5/P15
PC4/P14
PC3/AD3
PC2/AD2
PC1/AD1
PC0/AD0
PA0/SDA1/TXD
PA1/SCL1/RXD
PA2/PWM8
PA3/PWM9
PA4/PWM10
PA5/PWM11/(1/2HO)
PA6/PWM12/(1/2VO)
PA7/PWM13/CLAMP
PD0/VOUT
PD1/HOUT
PD2/PWM7/P13
PD3/PWM6/P12
PD4/PWM5/P11
PD5/PWM4/P10
PD6/PWM3/HIN2
HIN1
VIN1
NC
PD7/PWM2/VIN2
NC
I/O
I/O
P
I/O
I/O
I/O
P
P
Port E3 or PWM15
Port E2 or PWM14
+3.3V power supply
Port E1 or PWM1
Port E0 or PWM0 (12 bits)
Reset input
+3.3V power supply
+5V power supply
No Connection
Ground
12Mhz or 24MHz oscillator output
12Mhz or 24MHz oscillator input
Port B6 or IIC SDA
Port B5 or IIC SCL
Port B4 or test pattern output
Port B3 or frequency divider output
Port B2 or frequency divider input
Port B1 or External interrupt II request input or IR input
Port B0 or External interrupt I request input
Port C7 or Sync on Green input or 8031 P1.7
Port C6 or 8031 P1.6
Port C5 or 8031 P1.5
Port C4 or 8031 P1.4
Port C3 or ADC input 3
Port C2 or ADC input 2
Port C1 or ADC input 1
Port C0 or ADC input 0
Port A0 or DDC SDA pin or RS232C TXD
Port A1 or DDC SCL pin or RS232C RXD
Port A2 or PWM8
Port A3 or PWM9
Port A4 or PWM10
Port A5 or PWM11 or 1/2 HOUT
Port A6 or PWM12 or 1/2 VOUT
Port A7 or PWM13 or CLAMP output
Port D0 or VSYNC output
Port D1 or HSYNC output
Port D2 or PWM7 or 8031 P1.3
Port D3 or PWM6 or 8031 P1.2
Port D4 or PWM5 or 8031 P1.1
Port D5 or PWM4 or 8031 P1.0
Port D6 or PWM3 or HSYNC II Input
HSYNC I Input.
VSYNC I input.
No Connection
Port D7 or PWM2 or VSYNC II Input
No Connection
P
O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I/O
Weltrend Semiconductor, Inc.
Page 4
WT61P4 v1.03
Monitor Controller
FUNCTIONAL DESCRIPTION
CPU
8-bit 8051 compatible CPU with 16-bit address bus and 8-bit data bus operates at 12/24MHz.
RAM
The 1024 bytes SRAM include:
128 bytes internal SRAM are from $0000H to $007FH (direct & indirect addressing)
128 bytes internal SRAM are from $0080H to $00FFH (indirect addressing)
384 bytes external SRAM are from $0080H to $01FFH
256 bytes external SRAM are from $0200H to $02FFH or from $0280H to $037FH share with DDC
(A2/A3 or A6/A7) EDID
128 bytes external SRAM are from $0300H to $037FH or from $0200H to $027FH or from $0280H to
$02FFH share with DDC (A0/A1) EDID
Flash Memory
64K bytes flash memory for program. Address is located from $0000h to $FFFFh.
Weltrend Semiconductor, Inc.
Page 5
WT61P4 v1.03
Monitor Controller
Memory Mapping
Program Memory
Internal Memory
Data memory
$FFFFH
$FFFFH
Reserved
$0380H
ROM
$037FH
DDC
$0300H
128 bytes
RAM 3
$02FFH
$0280H
$027FH
$0200H
DDC
128 bytes
RAM 2
DDC
128 bytes
RAM 1
$01FFH
$00FFH
$0080H
$007FH
$0000H
$0000H
Upper
128 bytes
RAM
Lower
128 bytes
RAM
Weltrend Semiconductor, Inc.
Page 6
384 bytes
RAM
SFR
Registers
$0080H
$007FH
Registers
$0000H
WT61P4 v1.03
Monitor Controller
System Reset
There are three reset sources of this controller. All reset signals will last 1.024ms. Fig.1 shows the
block diagram of reset logic.
NRES
LATCH
Watchdog Timer Reset
CPU
R
VDD
Low VDD Reset
1.024ms
Timer
Peripheral
Circuits
Fig. 1 Reset Signals
NRES
The NRES-Reset happens when there is a low level on the NRES pin.
Low VDD Reset
The Low-VDD-Reset is generated when VDD3V is below 2.7V either VDD=5v or VDD=3.3v. The reset
signal will last 1.024ms after the voltage is higher than 2.7V.
Watchdog Timer Reset
The Watchdog-Timer-Reset happens when the watchdog timer is time out. Please refer to the
watchdog timer section for more detail.
Weltrend Semiconductor, Inc.
Page 7
WT61P4 v1.03
Monitor Controller
I/O Port
I/O Port A
The PA0 and PA1 are general purpose IO shared with DDC interface and 8031 UART interface. They
are the IO port only when both ENDDC and REN are “0”. If the PA0OE is “1”, Pin PA0 is an open-drain
output port. If the PA0OE is “0”, Pin PA0 is an input port without internal pull-up resistor. The PA1 is
the same as the PA0. Fig. 2 shows the structure of PA0.
INTERNAL_DATA_BUS
DATA[0]
D
Q
PA0OE
PA0
C
WRITE_PA_CTRL
QN
R
RESET
DATA[0]
D
WRITE_PA_DATA
Q
C
PA0O
QN
R
RESET
READ_PA_DATA
DATA[0]
Fig.2 Structure of PA0 and PA1
The PA2 to PA7 are general purpose IO shared with PWM output and some special functions. When
the EPWMn is “0” and the special function is disabled, PAn is a general purpose I/O port. If the PAnOE
is “1”, the PAn is configured as an output port in a push-pull type which can source or sink 6mA. If the
PAnOE is “0”, the PAn is configured as an input port with internal pull-up resistor.
INTERNAL_DATA_BUS
DATA[2]
D
WRITE_PA_CTRL
Q
C
PA2OE
QN
PA2
R
RESET
DATA[2]
D
WRITE_PA_DATA
Q
C
PA2O
QN
R
RESET
READ_PA_DATA
DATA[2]
Fig.3 Structure of PA2
Weltrend Semiconductor, Inc.
Page 8
WT61P4 v1.03
Monitor Controller
Port A control and data register
Name Addr R/W Initial Bit 7
PA_CTRL 0000h
PA_DATA 0001h
Bit Name
PAnOE
PAn (W)
PAn (R)
W
R
W
00h
ffh
ffh
PA7OE
PA7
PA7
Bit 6
Bit 5
Bit4
Bit 3
Bit 2
Bit 1
Bit 0
PA6OE
PA6
PA6
PA5OE
PA5
PA5
PA4OE
PA4
PA4
PA3OE
PA3
PA3
PA2OE
PA2
PA2
PA1OE
PA1
PA1
PA0OE
PA0
PA0
Description
Port An Output Enable.
When it is set, PAn is configured as an output pin.
When it is cleared, PA2~PA7 are configured as the input pin with internal pull-up resistor.
PA0 and PA1 are configured as the input pin without internal pull-up resistor.
This bit controls the output level when the corresponding PAnOE bit is set.
When PAn=1, PAn pin outputs high level. (PA0 and PA1 are open-drain output)
When PAn=0, PAn pin outputs low level.
When PAnOE=1 (i.e. output port), the data of this bit is the same to PAn (W).
When PAnOE=0, this bit indicates the input level. “1” is high and “0” is low.
I/O Port B
The PB0~PB6 are general purpose IO shared with some special functions. When the special function is
disabled, the PBn is a general purpose I/O port and is same as PA2. If it is configured as an output, it
could source/sink 6mA. If it is configured as an input, there is an internal pull-up resistor enabled.
Port B control and data register
Name
Addr R/W Initial
PB_CTRL 0002h W
00h
R
xfh
PB_DATA 0003h
W
Xfh
Bit Name
PBnOE
PBn (W)
PBn (R)
Bit 7
----
Bit 6
PB6OE
PB6
PB6
Bit 5
PB5OE
PB5
PB5
Bit4
PB4OE
PB4
PB4
Bit 3
PB3OE
PB3
PB3
Bit 2
PB2OE
PB2
PB2
Bit 1
PB1OE
PB1
PB1
Description
Port Bn Output Enable.
When it is “1”, PBn is configured as an output pin.
When it is “0”, PBn is configured as an input pin with internal pull high
This bit controls the output level when the corresponding PBnOE bit is set.
When PBn=1, the PBn pin outputs high level.
When PBn=0, the PBn pin outputs low level.
When PBnOE=1 (i.e. output port), the data of this bit is the same to PBn (W).
When PBnOE=0, this bit indicates the input level. “1” is high and “0” is low.
Weltrend Semiconductor, Inc.
Page 9
Bit 0
PB0OE
PB0
PB0
WT61P4 v1.03
Monitor Controller
I/O Port C
The PC0~PC7 are general purpose IO shared with some special functions. When the function is
disabled, the PCn is a general purpose I/O port and is the same as PA2. If it is configured as output, it
could source 6mA and sink 10mA. If it is configured as an input, it has an internal pull-up resistor.
Port C control and data register
Name
Addr R/W Initial Bit 7
PC_CTRL 0004h W
00h PC7OE
R
ffh
PC7
PC_DATA 0005h
W
ffh
PC7
Bit 6
PC6OE
PC6
PC6
Bit Name
PCnOE
PCn (W)
PCn (R)
Bit 5
PC5OE
PC5
PC5
Bit4
PC4OE
PC4
PC4
Bit 3
PC3OE
PC3
PC3
Bit 2
PC2OE
PC2
PC2
Bit 1
PC1OE
PC1
PC1
Bit 0
PC0OE
PC0
PC0
Description
Port Cn Output Enable.
When it is “1”, PCn is configured as an output pin.
When it is “0”, PCn is configured as an input pin with internal pull-up resistor.
This bit controls the output level when the corresponding PCnOE bit is set.
When PCn=1, PCn pin outputs high level.
When PCn=0, PCn pin outputs low level.
When PCnOE=1 (i.e. output port), the data of this bit is the same as PCn (W).
When PCnOE=0, this bit indicates the input level. “1” is high and “0” is low.
I/O Port E
The PE0~PE3 are the general purpose IO shared with PWM output. When the corresponding EPWMn
bit is “0”, it is a general I/O port and is the same as PA2. If it is configured as an output, it could
source/sink 6mA. If it is configured as an input, it has an internal pull-up resistor.
Port E control and data register
Name
Addr R/W Initial
PE_CTRL 0008h W
00h
R
xfh
PE_DATA 0009h
W
xfh
Bit 7
----
Bit Name
PEnOE
PEn (W)
PEn (R)
Bit 6
----
Bit 5
----
Bit4
----
Bit 3
PE3OE
PE3
PE3
Bit 2
PE2OE
PE2
PE2
Bit 1
PE1OE
PE1
PE1
Description
Port En Output Enable.
When it is “1”, the PEn is configured as an output pin.
When it is “0”, the PEn is configured as an input pin with internal pull-up resistor.
This bit controls the output level when the corresponding PEnOE bit is set.
When PEn=1, PEn pin outputs high level.
When PEn=0, PEn pin outputs low level.
When PEnOE=1 (i.e. output port), the data of this bit is the same as PEn (W).
When PEnOE=0, this bit indicates the input level. “1” is high and “0” is low.
Weltrend Semiconductor, Inc.
Page 10
Bit 0
PE0OE
PE0
PE0
WT61P4 v1.03
Monitor Controller
I/O Port D
The PD0~PD7 are the general purpose IO shared with some special functions. When the special
function is disabled, it is a general purpose I/O port. If it is configured as output, it could source/sink
6mA. If it is configured as input and PdnHE is “0”, it has an internal pull-up resistor. If the PDn is
configured as input and the PDnHE is “1”, it doesn’t have an internal pull-up resistor.
INTERNAL_DATA_BUS
DATA[0]
D
WRITE_PD_CTRL2
Q
C
PD0HE
QN
R
RESET
DATA[0]
D
WRITE_PD_CTRL
Q
C
PD0OE
QN
PD0
R
RESET
DATA[0]
D
WRITE_PD_DATA
Q
C
PD0O
QN
R
RESET
READ_PD_DATA
DATA[0]
Fig.4 Structure of PD0
Port D control and data register
Name
Addr R/W Initial Bit 7
PD_CTRL 0006h W
00h PD7OE
R
ffh
PD7
PD_DATA 0007h
W
ffh
PD7
PD_CTRL2 000Ah W
00h PD7HE
Bit Name
PDnOE
PDn (W)
PDn (R)
PDnHE
Bit 6
PD6OE
PD6
PD6
PD6HE
Bit 5
PD5OE
PD5
PD5
PD5HE
Bit4
PD4OE
PD4
PD4
PD4HE
Bit 3
PD3OE
PD3
PD3
PD3HE
Bit 2
PD2OE
PD2
PD2
PD2HE
Bit 1
PD1OE
PD1
PD1
PD1HE
Description
Port Dn Output Enable.
When it is “1”, PDn is configured as an output pin.
When it is “0”, PDn is configured as an input pin with internal pull-up resistor.
This bit controls the output level when the corresponding PDnOE bit is set.
When PDn=1, PDn pin outputs high level.
When PDn=0, PDn pin outputs low level.
When PDnOE=1 (i.e. output port), the data of this bit is same as PDn (W).
When PDnOE=0, this bit indicates the input level. “1” is high and “0” is low.
Configured the Port Dn pull-up resistor.
When PDnHE =1, PDn pin without pull-up resistor.
When PDnHE =0, PDn pin with pull-up resistor.
Weltrend Semiconductor, Inc.
Page 11
Bit 0
PD0OE
PD0
PD0
PD0HE
WT61P4 v1.03
Monitor Controller
SYNC Processor
The functional block diagram of Sync Processor is shown in Fig.5. It contains H and V polarity detection
circuit, H and V frequency counter, composite sync signal separation circuit, free-running H and V sync
signal generator, video signal generation circuit for burn-in test and clamp pulse generator.
H Period Counter
SOG HVIN2
HCHG
SEPART
HIN
SOGIN
EXTRHS
MUX
H Polarity
Detect
Composite Signal
Separator
MUX
H Freq Counter
ENFREE
EXTRVS
HVPASS
HIN2
FREEHS
MUX
H Polarity Control
MUX
HOUT
HINPOL
Polarity
Change
HVIN2
SEPART
POLINT
Clamp Pulse
Generator
ENFREE
CLAMP
HVPASS
VIN
MUX
MUX
MUX
VIN2
V Polarity Control
VINPOL
V Polarity
Detect
Free run SYNC
& Test Pattern
Generator
MUX
VOUT
V Freq Counter
FREEVS
PAT
Fig.5 Block diagram of sync signal processor
Horizontal Frequency Counter
A 13-bit counter is used to measure horizontal frequency.
Name
Addr R/W Initial
HFREQ_L 0010h R
xxh
HFREQ_H 0011h R
xxh
Bit 7
HLVL
HFH7
Bit 6
HINPOL
HFH6
Bit 5
HCHG
HFH5
Bit4
HFL4
HFH4
Bit 3
HFL3
HFH3
Bit 2
HFL2
HFH2
Bit 1
HFL1
HFH1
Bit Name
Description
HLVL
“1”: Indicates Hsync pin is high level.
“0”: Indicates Hsync pin is low level.
HINPOL “1”: Indicates Hsync input is positive polarity.
“0”: Indicates Hsync input is negative polarity.
HCHG
“1”: If the H period has been changed.
HFH7~ Indicates the Hsync frequency in kHz.
HFH0
HFL4~ When QUICK=”0”, HFL4 ~ HFL0 indicates the Hsync frequency in 31.25Hz unit.
HFL0
When QUICK=”1”, HFL4 ~ HFL1 indicates the Hsync frequency in 62.5Hz.
Weltrend Semiconductor, Inc.
Page 12
Bit 0
HFL0
HFH0
WT61P4 v1.03
Monitor Controller
Horizontal polarity detect
The horizontal polarity is detected by sampling HIN signal with a delay time after rising and falling edge
of HIN. When the 126kHz<HIN, sample level at 3.5us – 4.5us after HIN transition edge. When the
23kHz<HIN<126kHz, sample level at 5.5us – 6.5us after HIN transition edge. When the HIN<23khz,
sample level at 8.5us – 9.5us after HIN transition edge.
Horizontal frequency detect
User can choose 16ms or 32ms time interval to count pulse number of Hsync every 16.384ms or
32.768ms. For example, if QUICK bit is set, when a 16.384ms time frame begins, it resets the counter
and starts counting Hsync pulses till 16ms reached, then loads the counter value to HFREQ_H and
HFREQ_L registers. If the H frequency is over 192kHz, the H counter will stop counting.
The sync processor interrupt is generated every 16.384ms or 32.768ms for checking H frequency. This
interrupt will be cleared after reading the HFREQ_H register.
Hsync
Interrupt
Hfreq Counter
Enable
16/32 ms
16.384/32.768 ms
Hfreq Counter
clock
Fig.6 Horizontal Frequency Counter timing
Example of Hsync Frequency Calculation
QUICK=”0”
HFH6..0 HFL4..0
Max. Freq
Min. Freq
$40h
$00010b 64.0938KHz 64.0312KHz
$40h
$00011b 64.1250KHz 64.0625KHz
$51h
$10000b 81.5313KHz 81.4687KHz
$51h
$10001b 81.5625KHz 81.5000KHz
$51h
$10010b 81.5938KHz 81.5312KHz
$51h
$10011b 81.6250KHz 81.5625KHz
HFH6..0
$40h
QUICK=”1”
HFL4..0
Max. Freq Min. Freq
$0001xb 64.1250KHz 64.0000KHz
$51h
$1000xb
81.5625KHz 81.4375KHz
$51h
$1001xb
81.6250KHz 81.5000KHz
Weltrend Semiconductor, Inc.
Page 13
WT61P4 v1.03
Monitor Controller
Vertical Frequency Counter
A 13-bit counter is used to measure the time interval between two vertical sync pulses.
Name
Addr R/W Initial
VFREQ_L 0012h R
xxh
VFREQ_H 0013h R
xxh
Bit 7
VF7
VLVL
Bit 6
VF6
VINPOL
Bit 5
VF5
VOVF
Bit4
VF4
VF12
Bit 3
VF3
VF11
Bit 2
VF2
VF10
Bit 1
VF1
VF9
Bit 0
VF0
VF8
Bit Name
Description
VLVL
“1”: Indicates Vsync pin is high level.
“0”: Indicates Vsync pin is low level.
VNPOL “1”: Indicates Vsync input is positive polarity. (SEPART in HV_CR1 also make it “1”)
“0”: Indicates Vsync input is negative polarity.
VOVF
“1”: Indicates V counter is overflowed. Vsync frequency is lower than 15.25Hz.
“0”: Vsync frequency is over 15.25Hz.
VF12 ~ VF0 Indicates the Vertical Total Time. Vertical frequency is [125000 / (counter value +1) ] Hz
Vertical polarity detect
Vertical polarity is detected by sampling VIN level at 2.048ms after rising edge of VIN. If the level is low,
the polarity is positive (VINPOL=1). If the level is high, the polarity is negative (VINPOL=0). But if
SEPART bit is set, the VINPOL bit is “1” because the Vsync from composite signal separator is always
positive polarity.
Vertical frequency detect
It will be updated every vertical frame. The clock of this counter is 125kHz. So the frequency of Vsync is
[125000 / (counter value + 1)] Hz. When V frequency is lower than 15.25Hz, this counter stops counting
and set VOVF bit to “1”.
Vertical polarity is detected by sampling VIN level at 2.048ms after rising edge of VIN.
Example of Vsync frequency calculation
VF12..0 Max. Freq
Min. Freq
$05BDh
85.15Hz
85.034Hz
$05BEh 85.092Hz
84.976Hz
$05BFh 85.034Hz
84.918Hz
$0681h
75.12Hz
75.03Hz
$0682h
75.075Hz
74.985Hz
$0683h
75.03Hz
74.94Hz
$06C7h 72.088Hz
72.005Hz
$06C8h 72.046Hz
71.963Hz
$06C9h 72.005Hz
71.921Hz
VF12..0
$0783h
$0784h
$0785h
$0823h
$0824h
$0825h
$1FFDh
$1FFEh
$1FFFh
Weltrend Semiconductor, Inc.
Page 14
Max. Freq
65.036Hz
65.003Hz
64.969Hz
60.038Hz
60.01Hz
59.981Hz
15.266Hz
15.264Hz
15.262Hz
Min. Freq
64.969Hz
64.935Hz
64.901Hz
59.981Hz
59.952Hz
59.923Hz
15.262Hz
15.260Hz
15.258Hz
WT61P4 v1.03
Monitor Controller
Hsync Period Counter
The H_PERD is an 8-bit counter to detect the cycle time of the Hsync input.
Name
Addr R/W Initial
Bit 7
H_PERD 0014h R
xxh
HPRD7
Bit 6
HPRD6
Bit 5
HPRD5
Bit4
HPRD4
Bit 3
HPRD3
Bit 2
HPRD2
Bit 1
HPRD1
Bit 0
HPRD0
This is an 8-bit counter that uses 6MHz clock to measure time interval between two H pulses. If the H
frequency is lower than 23437.5Hz, this counter will overflow and register H_PERD value is zero.
Hsync Counter In One Vsync Period
Enumerate the H pulses between two V pulses.
Name
HF_VL
HF_VH
Addr R/W Initial
0015h R
00h
0016h R
x0h
Bit 7
HFV7
Bit 6
HFV6
Bit 5
HFV5
Bit4
HFV4
Bit 3
HFV3
HFV11
Bit 2
HFV2
HFV10
Bit 1
HFV1
HFV9
Bit 0
HFV0
HFV8
Bit 3
OVVF3
Bit 2
OVVF2
Bit 1
OVVF1
Bit 0
OVVF0
The register can be used as H total.
Vsync overflow control register
The VFQ_OVF is used in blanking for Vertical frequency changed.
Name
Addr R/W Initial
VFQ_OVF 0010h W
FFh
Bit 7
OVVF7
Bit 6
OVVF6
Bit 5
OVVF5
Bit4
OVVF4
If the VIN frequency is lower than (7812.5Hz/OVVFn), the vertical frequency overflow flag of the
interrupt will be set.
VFQ_OVF reference table
VFQ_OVF Frequency VFQ_OVF Frequency VFQ_OVF Frequency VFQ_OVF Frequency
78.125 Hz
65.104 Hz
55.803 Hz
48.828 Hz
100
120
140
160
76.593 Hz
64.037 Hz
55.017 Hz
48.225 Hz
102
122
142
162
75.120 Hz
63.004 Hz
54.253 Hz
47.637 Hz
104
124
144
164
73.703 Hz
62.004 Hz
53.510 Hz
47.063 Hz
106
126
146
166
72.338 Hz
61.035 Hz
52.787 Hz
46.503 Hz
108
128
148
168
71.022 Hz
60.096 Hz
52.083 Hz
45.955 Hz
110
130
150
170
69.754 Hz
59.185 Hz
51.398 Hz
45.421 Hz
112
132
152
172
68.530 Hz
58.302 Hz
50.730 Hz
44.899 Hz
114
134
154
174
67.934 Hz
57.445 Hz
50.080 Hz
44.389 Hz
116
136
156
176
66.207 Hz
56.612 Hz
49.446 Hz
43.890 Hz
118
138
158
178
Weltrend Semiconductor, Inc.
Page 15
WT61P4 v1.03
Monitor Controller
Sync Processor Control Register
The HV_CR1 and HV_CR2 control the HOUT, VOUT and Clamp model.
Name
Addr R/W Initial
Bit 7
Bit 6
Bit 5
Bit4
Bit 3
Bit 2
Bit 1
Bit 0
HV_CR1 0011h W
00h ENHOUT ENVOUT HOPOL VOPOL QUICK SEPART ENFREE ENPAT
HV_CR2 0012h W
00h ENCLP CLPEG CLPPO CLPPW1 CLPPW0 SOG HVPASS BYPASS
Bit Name
ENHOUT
ENVOUT
HOPOL
VOPOL
QUICK
SEPART
ENFREE
ENPAT
ENCLP
CLPEG
CLPPO
CLPPW1 ~
CLPPW2
SOG
HVPASS
BYPASS
Description
“1”: Enable HOUT.
“0”: Disable HOUT. Pin is configured as I/O port PD1.
“1”: Enable VOUT.
“0”: Disable VOUT. Pin is configured as I/O port PD0.
“1”: HOUT is positive polarity.
“0”: HOUT is negative polarity.
“1”: VOUT is positive polarity.
“0”: VOUT is negative polarity.
“1”: Select 16ms time interval to count H pulses every 16.384ms.
“0”: Select 32ms time interval to count H pulses every 32.768ms.
When H+V mode, the falling edge of extracted Vsync is synchronized with Hsync leading
edge.
“1”: Enable sync separator circuit and use the extracted Vsync signal as VOUT.
“0”: VOUT pin outputs Vsync from VIN pin
Enable free-running sync signal output on HOUT and VOUT pins when this bit is set.
“1”: Enable self-test pattern output on PAT pin when this bit is set.
“0”: Disable test pattern output. Pin is configured as I/O port PB3.
“1”: Enable clamp pulse output on CLAMP pin.
“0”: Disable clamp pulse output. Pin is configured as I/O port PA7.
“1”: Clamp pulse follows HOUT signal’s rising edge.
“0”: Clamp pulse follows HOUT signal’s falling edge.
“1”: Clamp pulse is positive polarity.
“0”: Clamp pulse is negative polarity.
(CLPPW1,CLPPW0)=(0,0) : clamp pulse width=125ns – 208ns
(CLPPW1,CLPPW0)=(0,1) : clamp pulse width=208ns – 292ns
(CLPPW1,CLPPW0)=(1,0) : clamp pulse width=458ns – 542ns
(CLPPW1,CLPPW0)=(1,1) : clamp pulse width=958ns – 1042ns
Select composite sync signal input source.
“1” : Composite sync signal comes from SOGIN pin.
“0” : Composite sync signal comes from HIN pin.
Select bypass HSYNC & VSYNC.
“1” : HOUT = HIN & VOUT=VIN without polarity changed.
“0” : HOUT = HIN & VOUT=VIN with polarity changed.
Select bypass the composite signal separator or not.
“1” : HOUT pin outputs sync signal bypass the composite signal separator.
“0” : HOUT pin outputs sync signal from the composite signal separator.
Weltrend Semiconductor, Inc.
Page 16
WT61P4 v1.03
Monitor Controller
Output Polarity Control
HOPOL and VOPOL bits control the polarities of HOUT and VOUT. When the bit is “1”, the output
polarity is positive. When the bit is “0”, the output polarity is negative.
HVPASS
HVPASS will deliver the Hsync and Vsync from HIN and VIN to HOUT and VOUT without polarity
changed.
Composite Sync Signal Separator
The composite sync signal separator can handle H+V and H exclusive-OR V signals. It will extract
Vsync signal from HIN or SOGIN input pin by filtering abnormal pulses. The output Vsync signal will be
widened about 4.5~5.5us. The output Hsync will be replaced by 2us pulse during Vsync pulse. Fig.7
shows the relationship of the extracted H and V sync signals.
If inserting the pseudo H pulses (Extracted HS signal) during Vsync pulse is not necessary, set
BYPASS bit can make HOUT pin output waveform the same as Hsync input (Note: polarity can be
controlled by HOPOL bit), set HVPASS can make HOUT pin output waveform fully the same to Hsync
input.
Hsync
Vsync
H+V
H V SERR
Bypass H pulse
Insert H pulse
2us
Bypass H pulse
2us
Extracted HS
Extracted VS
Hsync
Vsync
H V EOR
Bypass H pulse
Insert H pulse
2us
Bypass H pulse
2us
Extracted HS
Extracted VS
Fig.7 Timing relationship of composite SYNC signal separator
Weltrend Semiconductor, Inc.
Page 17
WT61P4 v1.03
Monitor Controller
Free-Run Frequency Control Registers
Name
FRH_CR
FRHD_CR
FRHB_CR
FRV_CR
FRVD_CR
FRVB_CR
Addr R/W Initial
Bit 7
0013h W
00h
0014h W
00h FRHB4
0015h W
00h FRHB3
0016h W
00h
FRV7
0017h W
00h FRVD7
0018h W
00h FRVB4
Bit 6
FRHD6
FRHB2
FRV6
FRVD6
FRVB3
Bit 5
FRH5
FRHD5
FRHB1
FRV5
FRVD5
FRVB2
Bit4
FRH4
FRHD4
FRHB0
FRV4
FRVD4
FRVB1
Bit 3
Bit 2
Bit 1
Bit 0
FRH3
FRH2
FRH1
FRH0
FRHD3 FRHD2 FRHD1 FRHD0
FRHW3 FRHW2 FRHW1 FRHW0
FRV3
FRV2
FRV1
FRV0
FRVD3 FRVD2 FRVD1 FRVD0
FRVB0 FRVW2 FRVW1 FRVW0
HOUT(VOUT)
PATTERN
FRHW(FRVW)
FRHB(FRVB)
FRHD(FRVD)
FRH(FRV)
Fig. 8 Free-running SYNC signal and test pattern timing
Bit Name
FRH
FRHD
FRHB
FRHW
FRV
FRVD
FRVB
FRVW
Description
The FRH defines the horizontal free run frequency as HFFREE=750K/FRH_CR.
The FRHD defines the time from the horizontal blanking to the pattern end.
TFRHD=FRHD*0.667µs=H display+ H back porch+ H blanking
The FRHB defines the time from the horizontal blanking to the pattern start.
TFRHB=FRHB*0.333µs=H back porch+ H blanking
The FRHW defines the time for the horizontal blanking.
TFRHW=FRHW*0.333µs=H blanking width
The FRV defines the vertical free run frequency as VFFREE=HFFREE/(FRV_CR*8)
The FRVD defines the time from the vertical blanking to the vertical pattern end.
TFRVD=HFFREE/(FRVD*8)=V display+ V back porch+ V blanking
The FRVB defines the time from the vertical blanking to the pattern start.
TFRVD=HFFREE/(FRVB*2)=V back porch+ V blanking
The FRVW defines the time for the vertical blanking.
TFRVW=HFFREE/(FRVW*2)=V blanking width
H pulse & period = X + 83.3ns
V pulse & period = 2xn H + 1H
Weltrend Semiconductor, Inc.
Page 18
WT61P4 v1.03
Monitor Controller
FRH reference table
FRH
Frequency
0
-1
750 kHz
2
375 kHz
3
250 kHz
4
187.5 kHz
5
150 kHz
125 kHz
6
107.14 kHz
7
93.75 kHz
8
83.33 kHz
9
75 kHz
10
68.18 kHz
11
62.5 kHz
12
57.69 kHz
13
53.57 kHz
14
50 kHz
15
FRH
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Frequency
46.88 kHz
44.12 kHz
41.67 kHz
39.47 kHz
37.5 kHz
35.71 kHz
34.09 kHz
32.6 kHz
31.25 kHz
30 kHz
28.85 kHz
27.78 kHz
26.79 kHz
25.86 kHz
25 kHz
24.19 kHz
FRH
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
Frequency
23.44 kHz
22.73 kHz
22.06 kHz
21.43 kHz
20.83 kHz
20.27 kHz
19.74 kHz
19.23 kHz
18.75 kHz
18.29 kHz
17.86 kHz
17.44 kHz
17.05 kHz
16.67 kHz
16.30 kHz
15.96 kHz
FRH
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
Frequency
15.63 kHz
15.31 kHz
15 kHz
14.76 kHz
14.42 kHz
14.15 kHz
13.89 kHz
13.64 kHz
13.39 kHz
13.16 kHz
12.93 kHz
12.71 kHz
12.5 kHz
12.30 kHz
12.10 kHz
11.90 kHz
Clamp pulse
Clamp pulse is generated on either rising or falling edge of HOUT pin by setting the CLPEG bit. The
pulse width of clamp is defined by CLPPW bit. Output polarity is specified by CLPPO bit.
(CLPPW1, CLPPW0)=(0,0): clamp pulse width=125ns – 208ns
(CLPPW1, CLPPW0)=(0,1): clamp pulse width=208ns – 292ns
(CLPPW1, CLPPW0)=(1,0): clamp pulse width=458ns – 542ns
(CLPPW1, CLPPW0)=(1,1): clamp pulse width=958ns – 1042ns
HOUT
CLAMP
CLPPO=1
CLPEG=1
CLAMP
CLPPO=0
CLPEG=1
CLAMP
CLPPO=1
CLPEG=0
CLAMP
CLPPO=0
CLPEG=0
CLPPW
CLPPW
CLPPW
CLPPW
Fig. 9 Clamp pulse waveform
Weltrend Semiconductor, Inc.
Page 19
WT61P4 v1.03
Monitor Controller
H Period Interrupt Control
Name
Addr R/W Initial
HPD_CHG 0019h W
00h
Bit Name
EN_LMT
HCNT
Bit 7
Bit 6
Bit 5
Bit4
Bit 3
Bit 2
EN_LMT HCNT2
Bit 1
HCNT1
Bit 0
HCNT0
Bit 1
Bit 0
HVIN2
Description
Enable H period change interrupt.
The range of the H_PERD changed.
1/2HIN, 1/2VIN control
Name
Addr R/W Initial
Bit 7
1/2HV_CR 001Ah W
00h ENH2D
Bit Name
ENH2D
ENV2D
HVDEG
HVIN2
Bit 6
ENV2D
Bit 5
HVEDG
Bit4
Bit 3
Description
Enable the 1/2 HIN output at the PA5 pin.
Enable the 1/2 VIN output at the PA6 pin.
HIN & VIN trigger edge control.
HVEDG=0: leading edge trigger
HVEDG=1: tailing edge trigger
The duty cycle of both the 1/2HIN and 1/2VIN output are 50%.
Select the 2nd HIN & VIN as sync processor frequency source.
Weltrend Semiconductor, Inc.
Page 20
Bit 2
WT61P4 v1.03
Monitor Controller
Frequency Divide Function
Name
Addr R/W Initial
Bit 7
Bit 6
Bit 5
FDM_CON 0040h W
00h ENFDM FDMEG FDMPOL
Bit Name
ENFDM
FDMEG
FDMPOL
FO1M
FO2D
FO3D
Bit4
Bit 3
Bit 2
FO1M
Bit 1
FO2D
Bit 0
FO3D
Description
Enable the FDM input and output..
“1”: the output is synchronized with rising edge of input.
“0”: the output is synchronized with falling edge of input.
“1”: polarity inverted to input.
“0”: polarity same as input.
Output Frequency = 1x input frequency.
Output Frequency = (1/2) x input frequency.
Output Frequency = (1/3) x input frequency.
The frequency range of FDI is between 20khz and 180khz and the pulse width of (1/3) input frequency
& (1/2) input frequency is a input period (1T).
FDI
FDO
FO1M=1
FDMPOL=1
FDO
FO1M=1
FDMPOL=0
FDO
FO2D=1
FDMEG=1
FDO
FO2D=1
FDMEG=0
FO3D=1
FDO
FDMEG=1
FDMPOL=0
FO3D=1
FDO
FDMEG=0
FDMPOL=1
Fig. 10 FDI and FDO waveform
Weltrend Semiconductor, Inc.
Page 21
WT61P4 v1.03
Monitor Controller
DDC & Alignment I2C Interface
DDC Status Register
Name
Addr R/W Initial
Bit 7
R
01h ALGRDY
R
00h
DDC_STA1 0024h
DDC_STA2 0025h
Bit Name
ALGRDY
BB
DDC2
FIRST
STOP
ALGRW
MATCH
RXNAK1
IN_CMD
WR_D3
Bit 6
BB
Bit 5
DDC2
Bit4
FIRST
Bit 3
STOP
Bit 2
Bit 1
Bit 0
ALGRW MATCH RXNAK1
IN_CMD WR_D3
Description
DDC_AR1 or DDC_AR2 ready. Write the DDC_AR1 will clear this flag.
Bus busy.
“1”: DDC2 selected
“0”: DDC1 selected
Indicates the first byte (address) is received when this bit is set.
Indicates STOP condition is received when this bit is set.
Indicates the received R/W bit after 7-bit address.
“1”: Read
“0”: Write
0: DDC_ADR1
1: DDC_ADR2
Received the NAK by DDC_AR1 or DDC_AR2.
DDC_ADR0, DDC_ADR1 or DDC_ADR2 have been received.
Written 0 to DDC2 will clear this flag.
H/W DDC data has been updated.
Written 1 to CLR_WD3 then 0 to CLR_WD3 will clear this flag.
DDC Control Register
Name
Addr R/W Initial
Bit 7
Bit 6
Bit 5
Bit4
Bit 3
Bit 2
Bit 1
Bit 0
DDC_CON1 0024h W
00h ENDDC
DDC2
TX
TXNAK1
DDC_CON2 0025h W
80h RAMAS1 RAMAS0 ENRAMA RAMBS ENRAMB CLR_ADR CLR_WD WR_EN
3
Bit Name
ENDDC
Description
Enable the H/W DDC function of DDC_AR0.
DDC2=0: DDC1 selected
DDC2
DDC2=1: DDC2 selected
“1”: Set transmit direction.
TX
“0”: Set received direction.
TXNAK1 Transmit NAK and IRQ may happen with DDC_AR1 and DDC_AR2.
RAMAS1=0, RAMAS0=0: 128bytes format H/W DDC from 0200h to 027Fh
ENRAMA RAMAS1=0, RAMAS0=1: 128bytes format H/W DDC from 0280h to 02FFh
RAMAS1=1, RAMAS0=0: 128bytes format H/W DDC from 0300H to 037FH (default)
RAMBS1=0: 256bytes format H/W DDC from 0200h to 02FFh (default)
ENRAMB
RAMBS1=1: 256bytes format H/W DDC from 0280h to 037Fh
CLR_ADR Reset all DDC address pointer to 0.
CLR_WD3 Clear the flag indicated that the H/W DDC data has been changed.
WR_EN Enable the H/W DDC_WRITE.
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WT61P4 v1.03
Monitor Controller
DDC receive & transmit buffer register
Name
Addr R/W Initial
DDC_RTX 0026h R/W FFh
Bit 7
DRX7
Bit 6
DRX6
Bit 5
DRX5
Bit4
DRX4
Bit 3
DRX3
Bit 2
DRX2
Bit 1
DRX1
Bit 0
DRX0
Bit4
ENADRA4
ENADRB4
DAR04
DAR14
DAR24
Bit 3
ENADRA3
ENADRB3
-DAR13
DAR23
Bit 2
ENADRA2
ENADRB2
-DAR12
DAR22
Bit 1
ENADRA1
ENADRB1
-DAR11
DAR21
Bit 0
ENADRA0
ENADRB0
ENAR0
ENAR1
ENAR2
DDC port control register
Name
DDC_AAE
DDC_ABE
DDC_AR0
DDC_AR1
DDC_AR2
Addr R/W Initial
Bit 7
Bit 6
Bit 5
0027h W
FFh ENADRA7 ENADRA6 ENADRA5
0028h W
00h ENADRB7 ENADRB6 ENADRB5
0029h W
X0h DAR07 DAR06 DAR05
002Ah W
X0h DAR17 DAR16 DAR15
002Bh W
X0h DAR27 DAR26 DAR25
Bit Name
DDC_AAE
DDC_ABE
DDC_AR0
DDC_AR1
DDC_AR2
Description
Optional address as DDC_AR0 bit0~bit3. Also used as 128 bytes H/W DDC address
option.
Optional address as DDC_AR0 bit0~bit3. Also used as 256 bytes H/W DDC address
option.
The I2C slave address0 defines by user as DDC port. The bits from bit0 to bit3 are
defined by DDC_AAE and DDC_ABE. Refer to 24h and 25h for hardware DDC setting.
The I2C slave address1 defines by user and shares with DDC port.
The I2C slave address2 defines by user and shares with DDC port.
(1) DDC2 slave I, II write mode :
START
Pull low SCL
STOP
SCL
Slave Address
SDA
SDA ouput
0 A
RX DATA 1
A
ALGRDY
A
RX DATA 2
A
A
A
write 2AH
ALGRDY=1
BB=1
DDC2=1
FIRST=1
STOP=0
ALGRW=0
MATCH=0,1
NXNAK1=0
ALGRDY=1
BB=1
DDC2=1
FIRST=0
STOP=0
ALGRW=0
MATCH=0,1
NXNAK1=0
ALGRDY=1
BB=1
DDC2=1
FIRST=0
STOP=0
ALGRW=0
MATCH=0,1
NXNAK1=0
ALGRDY=1
BB=0
DDC2=1
FIRST=0
STOP=1
ALGRW=0
MATCH=0,1
NXNAK1=0
(2) DDC2 slave I, II read mode :
START
Pull low SCL
STOP
SCL
SDA
SDA ouput
Slave Address
1 A
TX DATA 1
A
TX DATA 1
ALGRDY
A
TX DATA 2
N
TX DATA 2
write 2AH
ALGRDY=1
BB=1
DDC2=1
FIRST=1
STOP=0
ALGRW=1
MATCH=0,1
NXNAK1=0
set
TX
Weltrend Semiconductor, Inc.
Page 23
ALGRDY=1
BB=1
DDC2=1
FIRST=0
STOP=0
ALGRW=1
MATCH=0,1
NXNAK1=0
ALGRDY=1
BB=1
DDC2=1
FIRST=0
STOP=0
ALGRW=1
MATCH=0,1
NXNAK1=0
ALGRDY=1
BB=0
DDC2=1
FIRST=0
STOP=1
ALGRW=0
MATCH=0,1
NXNAK1=0
WT61P4 v1.03
Monitor Controller
START
DDC data =>
DDC SRAM
set ENDDC
slave 0 address =>
DDC_AR0
slave I address =>
DDC_AR1
slave II address =>
DDC_AR2
No
ALGRDY=1 ?
Yes
MATCH=0 ?
No
Yes
FIRST=1 ?
slave II address
subprogram
No
Yes
STOP=1 ?
No
ALGRW=1 ?
Yes
set TX
sended data =>
DDC_RTX
No
Yes
ALGRW=1 ?
slave I address
=>DDC_AR1
END
Yes
No
RXNACK1=0 ?
Yes
slave I address
=>DDC_AR1
sended data =>
DDC_RTX
slave I address
=>DDC_AR1
Weltrend Semiconductor, Inc.
Page 24
No
read DDC_RTX
slave I address
=>DDC_AR1
WT61P4 v1.03
Monitor Controller
Master/Slave I2C Interface
I2C interface Status Register
Name
I2C_STA
Addr R/W Initial
0020h R
22h
Bit Name
BB
SFIRST
SSTOP
SRW
RXNAK2
I2CRDY
Bit 7
Bit 6
Bit 5
BB
Bit4
SFIRST
Bit 3
SSTOP
Bit 2
SRW
Bit 1
Bit 0
RXNAK2 I2CRDY
Description
“1”: Bus busy.
“0”: Bus idle. Both SDA2 and SCL2 pins keep in high level for 5us after STOP condition.
This bit is set when received START and first byte in slave mode.
This bit is set when received STOP condition in slave mode.
Received R/W bit in slave mode.
“1”: Read command is received.
“0”: Write command is received.
“1”: NACK is received.
“0”: ACK is received.
This bit is set when a byte is received, transmitted or STOP condition is detected.
I2C interface Control Register
Name
Addr R/W Initial
I2C_CON 0020h W
02h
Bit 7
ENI2C
Bit 6
MCLK1
Bit 5
MCLK0
Bit Name
Bit4
MSTR
Bit 3
MSTOP
Bit 2
Bit 1
Bit 0
I2CRW TXNAK2 SLAVE
Description
“1”: Enable I2C interface.
ENI2C
“0”: Pin PB5 and pin PB4 are I/O port.
Select SCL clock in master mode
“00”: 400KHz
MCLK1, 0 “01”: 200KHz
“10”: 100KHz
“11”: 50KHz
MSTR
Output START condition in master mode when this bit is set.
MSTOP Output STOP condition in master mode when this bit is set.
“0”: Transmitter, “1”: Receiver in master mode.
I2CRW
“1”: Transmitter, “0”: Receiver in slave mode
(“0”: I2C write mode, “1”: I2C read mode.)
“1”: Output NACK.
TXNAK2
“0”: Output ACK. It will pull low the SDA2 pin on acknowledge bit.
“1”: Slave mode.
SLAVE
“0”: Master mode.
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WT61P4 v1.03
Monitor Controller
I2C interface Transmit/Receive Buffer Register
Name
I2C_TX
I2C_RX
Addr R/W Initial
0021h W
xxh
0021h R
xxh
Bit 7
MTX7
MRX7
Bit 6
MTX6
MRX6
Bit 5
MTX5
MRX5
Bit4
MTX4
MRX4
Bit 3
MTX3
MRX3
Bit 2
MTX2
MRX2
Bit 1
MTX1
MRX1
Bit 0
MTX0
MRX0
Bit 6
SAR6
Bit 5
SAR5
Bit4
SAR4
Bit 3
SAR3
Bit 2
SAR2
Bit 1
SAR1
Bit 0
DLYHLD
I2C interface Address Register
Name
Addr R/W Initial
I2C_ADR 0022h W
X0h
Bit 7
SAR7
Bit Name
Description
SAR7 ~ SAR1 7-bit address to be compared in slave mode.
DLYHLD
Delay 1/2 SCL clock hold time.
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WT61P4 v1.03
Monitor Controller
I2C Data Sequence
(1) Master write mode :
START
MSCL Pull low
STOP
SCL
SDA
internal MSDA
Slave Address
0 A
TX DATA 1
Slave Address
0
TX DATA 1
I2CRDY
A
TX DATA 2
A
TX DATA 2
write 22H
set
set
MSTOP
MSTR
BB=1
RXNAK2=0
I2CRDY=1
BB=1
RXNAK2=0
I2CRDY=1
BB=1
RXNAK2=0
I2CRDY=1
BB=1
(2) Master read mode :
START
MSCL Pull low
STOP
SCL
SDA
internal MSDA
Slave Address
1 A
Slave Address
1
RX DATA 1
A
RX DATA 2
A
I2CRDY
N
N
write 22H
set
MSTR
set
I2CRW
BB=1
RXNAK2=1
I2CRDY=1
set
set
MSTOP
TXNAK2
BB=1
RXNAK2=0
I2CRDY=1
BB=1
RXNAK2=1
I2CRDY=1
BB=1
(3) Slave write mode :
START
MSCL Pull low
STOP
SCL
Slave Address
SDA
0 A
internal MSDA
RX DATA 1
A
I2CRDY
A
RX DATA 2
A
A
A
write 22H
BB=1
SFIRST=1
SSTOP=0
SRW=0
RXNAK2=0
I2CRDY=1
BB=1
SFIRST=0
SSTOP=0
SRW=0
RXNAK2=0
I2CRDY=1
BB=1
BB=1
SFIRST=0
SFIRST=0
SSTOP=0
SSTOP=1
SRW=0
SRW=0
RXNAK2=0 RXNAK2=0
I2CRDY=1 I2CRDY=1
(4) Slave read mode :
START
MSCL Pull low
STOP
SCL
SDA
internal MSDA
Slave Address
1 A
TX DATA 1
A
TX DATA 1
A
TX DATA 2
N
TX DATA 2
I2CRDY
write 22H
BB=1
SFIRST=1
SSTOP=0
SRW=1
RXNAK2=0
I2CRDY=1
set
I2CRW
Weltrend Semiconductor, Inc.
Page 27
BB=1
SFIRST=0
SSTOP=0
SRW=1
RXNAK2=0
I2CRDY=1
BB=1
BB=1
SFIRST=0
SFIRST=0
SSTOP=0
SSTOP=1
SRW=1
SRW=1
RXNAK2=1 RXNAK2=1
I2CRDY=1 I2CRDY=1
WT61P4 v1.03
Monitor Controller
Master I2C Flow Chart
START
set ENMI2C
select I2C clock
(MCLK1,MCLK0)
No
BB=0?
Yes
No
No
time out ?
clear I2CRW &
TXNAK2
sended slave address
=>MI2C_RTX
set MSTR
Yes
hardware fail
I2CRDY=1?
Yes
RXNAK2=0?
No
Yes
set MSTOP
"XX"=>MI2C_ADR
sended data
=>MI2C_RTX
"XX"=>MI2C_ADR
WRITE mode
read last byte ?
I2CRDY=1?
No
No
sended data
=>MI2C_RTX
"XX"=>MI2C_ADR
set TXNAK2
"XX"=>MI2C_ADR
"XX"=>MI2C_ADR
No
I2CRDY=1?
Yes
send all bytes ?
Yes
No
Yes
RXNAK2=0?
READ mode
set I2CRW
Yes
Yes
read MI2C_RTX
set MSTOP
"XX"=>MI2C_ADR
No
No
I2CRDY=1?
Yes
read MI2C_RTX
set MSTOP
"XX"=>MI2C_ADR
END
END
Weltrend Semiconductor, Inc.
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WT61P4 v1.03
Monitor Controller
Master I2C (reSTART mode) Flow Chart
START
set ENMI2C
select I2C clock
(MCLK1,MCLK0)
BB=0?
No
Yes
No
No
time out ?
clear I2CRW &
TXNAK2
sended slave address
=>MI2C_TX
set MSTR
Yes
hardware fail
I2CRDY=1?
Yes
No
RXNAK2=0?
Yes
sended data
=>MI2C_TX
"XX"=>MI2C_ADR
No
I2CRDY=1?
Yes
No
RXNAK2=0?
Yes
set I2CRW
sended slave address
=>MI2C_TX
set MSTR
"XX"=>MI2C_ADR
read last byte ?
Yes
No
No
"XX"=>MI2C_ADR
I2CRDY=1?
Yes
I2CRDY=1?
RXNAK2=0?
set TXNAK2
"XX"=>MI2C_ADR
Yes
Yes
No
read MI2C_RX
set MSTOP
"XX"=>MI2C_ADR
END
Weltrend Semiconductor, Inc.
Page 29
No
No
I2CRDY=1?
Yes
read MI2C_RX
set MSTOP
"XX"=>MI2C_ADR
WT61P4 v1.03
Monitor Controller
Salve I2C Flow Chart
START
set ENMI2C
slave address
=>MI2C_ADR
set SLAVE
No
I2CRDY=1?
Yes
SFIRST=1?
No
Yes
SSTOP=1?
No
SRW=1?
Yes
set I2CRW
sended data =>
MI2C_RTX
No
Yes
SRW=1?
slave address
=>MI2C_ADR
END
Yes
No
RXNAK2=0?
Yes
sended data =>
MI2C_RTX
slave address
=>MI2C_ADR
Weltrend Semiconductor, Inc.
Page 30
No
read MI2C_RTX
WT61P4 v1.03
Monitor Controller
Interrupt Control
Interrupt flag register
Name
Addr R/W Initial
Bit 7
Bit 6
Bit 5
Bit4
Bit 3
Bit 2
Bit 1
INT_FLG 002Ch R
00h IF_DDC IF_MI2C
IF_SYNC IF_IRQ2 IF_IRQ1 IF_VSO
INT_FLG2 002Dh R
00h IF_POL IF_OVV IF_HCHG IF_IR
Bit 0
IF_VIN
These interrupt sources are connected to CPU8051 /INT1
Bit Name
Description
IF_DDC “1” indicate DDC interrupt has been triggered.
IF_MI2C “1” indicate I2C interrupt has been triggered.
IF_SYNC “1” indicate Hsync counter ready interrupt has been triggered.
IF_IRQ2 “1” indicate IRQ2 interrupt has been triggered.
IF_IRQ1 “1” indicate IRQ1 interrupt has been triggered.
IF_VSO “1” indicate Vsync output leading edge interrupt has been triggered.
IF_VIN
“1” indicate Vsync input leading edge interrupt has been triggered.
IF_POL “1” indicate Hsync or Vsync input polarity changed interrupt has been triggered.
IF_OVV “1” indicate Vsync input overflow interrupt has been triggered.
(Refer to Addr 10h VFQ_OVF Vsync overflow control register)
IF_HCHG “1” indicate Hsync input period changed interrupt has been triggered.
(Refer to Addr 19h H period interrupt control)
IF_IR
“1” indicate IR event interrupt has been triggered.
Interrupt enable register
Name
Addr R/W Initial
Bit 7
Bit 6
Bit 5
Bit4
Bit 3
Bit 2
Bit 1
IE_SYNC IE_IRQ2 IE_IRQ1 IE_VSO
INT_EN 002Ch W
00h IE_DDC IE_MI2C
INT_EN2 002Dh W
00h IE_POL IE_OVV IE_HCHG IE_IR
Bit Name
IE_DDC
IE_MI2C
IE_SYNC
IE_IRQ2
IE_IRQ1
IE_VSO
IE_VIN
IE_POL
IE_OVV
IE_HCHG
IE_IR
Description
Enable DDC interrupt when this bit is set.
Enable I2C interrupt when this bit is set.
Enable Hsync ready interrupt when this bit is set.
Enable IRQ2 interrupt when this bit is set.
Enable IRQ1 interrupt when this bit is set.
Enable VOUT interrupt when this bit is set.
Enable VIN interrupt when this bit is set.
Enable POLINT interrupt when this bit is set.
Enable V overflow interrupt when this bit is set.
Enable HCHG interrupt when this bit is set.
Enable IR interrupt when this bit is set.
Weltrend Semiconductor, Inc.
Page 31
Bit 0
IE_VIN
WT61P4 v1.03
Monitor Controller
Interrupt Source Register
Name
Addr R/W Initial
Bit 7
Bit 6
INT_SRC 002Eh R
00h POLINT OVVINT
Bit Name
POLINT
OVVINT
SYNC
IRQ2
IRQ1
VSO
VIN
Bit 5
Bit4
SYNC
Bit 3
IRQ2
Bit 2
IRQ1
Bit 1
VSO
Bit 0
VIN
Bit 3
Bit 2
Bit 1
Bit 0
Description
“1”: Polarity Change
“1”: Vsync input is lower than OVVFn
“1”: Hsync detect counter is ready
“1”: IRQ2 has been triggered.
“1”: IRQ1 has been triggered.
“1”: Vsync output leading edge has been triggered.
“1”: Vsync input leading edge has been triggered.
Interrupt Control Register
Name
Addr R/W Initial
Bit 7
Bit 6
IRQ_CON1 002Eh W
00h CLR_POL CLR_OV
IRQ_CON2 002FH W
00h
Bit 5
Bit Name
CLR_POL
CLR_OV
CLR_IRQ2
CLR_IRQ1
CLR_VSO
CLR_VIN
Bit4
CLR_IRQ2 CLR_IRQ1 CLR_VSO CLR_VIN
IRQ2_RF IRQ2_EG IRQ1_RF IRQ1_EG
Description
Set CLR_POL to clear polarity changed interrupt event.
Set CLR_OV to clear Vsync input overflow interrupt event.
Set CLR_IRQ2 to clear the IRQ2 interrupt event.
Set CLR_IRQ1 to clear the IRQ1 interrupt event.
Clear VOUT interrupt when this bit is set.
Clear Vsync input interrupt when this bit is set.
IRQ2_EG=0, IRQ2_RF=x, IRQ2 will be triggered by a low level over 1us.
IRQ2_EG&
IRQ2_EG=1, IRQ2_RF=0, IRQ2 will be triggered by a falling edge.
IRQ2_RF
IRQ2_EG=1, IRQ2_RF=1, IRQ2 will be triggered by a rising edge.
IRQ1_EG=0, IRQ1_RF=x, IRQ1 will be triggered by a low level over 1us.
IRQ1_EG&
IRQ1_EG=1, IRQ1_RF=0, IRQ1 will be triggered by a falling edge.
IRQ1_RF
IRQ1_EG=1, IRQ1_RF=1, IRQ1 will be triggered by a rising edge.
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WT61P4 v1.03
Monitor Controller
Interrupt Control and Clear
DDC interface interrupt
Interrupt Condition
Receive one byte in DDC2 mode.
Transmit data buffer is empty in DDC2 mode.
Received a STOP condition in DDC2 mode.
Clear Interrupt
Write address to DDC_AR1 (Addr 2Ah) register.
Write address to DDC_AR1 (Addr 2Ah) register.
Write address to DDC_AR1 (Addr 2Ah) register.
I2C interface interrupt
Interrupt Condition
After transmit a byte.
After receive a byte.
Received a STOP condition when slave mode.
Clear Interrupt
Write address to MI2C_AR register.
Write address to MI2C_AR register.
Write address to MI2C_AR register.
Sync Processor interrupt
Interrupt Condition
Clear Interrupt
Latch a new H frequency to HFREQ_H and Read HFREQ_H Register.
HFREQ_L register every 32.768ms or 16.384ms.
IRQ1 pin interrupt
Interrupt Condition
NIRQ1 has been triggered.
Clear Interrupt
Write “1” to CLR_IRQ1 bit in IRQ_CON1 register
then write “0” to CLR_IRQ1.
IRQ2 pin interrupt
Interrupt Condition
NIRQ2 has been triggered.
Clear Interrupt
Write “1” to CLR_IRQ2 bit in IRQ_CON1 register
then write “0” to CLR_IRQ2.
Vsync output leading edge interrupt
Interrupt Condition
Leading edge of VOUT pin signal.
Clear Interrupt
Write “1” to CLR_VSO bit in IRQ_CON1 register
then write “0” to CLR_VSO.
Vsync input leading edge interrupt
Interrupt Condition
Leading edge of VIN pin signal.
Clear Interrupt
Write “1” to CLR_VIN bit in IRQ_CON1 register then
write “0” to CLR_VSI.
Polarity change interrupt
Interrupt Condition
HIN or VIN polarity has been changed.
Clear Interrupt
Write “1” to CLR_POL bit in IRQ_CON1 register
then write “0” to CLR_POL.
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WT61P4 v1.03
Monitor Controller
Vsync input overflow interrupt
Interrupt Condition
VIN is lower than VFQ_OVF.
Clear Interrupt
Write “1” to CLR_OV bit in IRQ_CON1 register then
write “0” to CLR_OV.
Hsync input change interrupt
Interrupt Condition
Clear Interrupt
The new H_PERD is not in the old H_PERD ± Read H_PERD (Addr 14h) to clear this interrupt and
H_CNT (addr 19h).
HCHG.
IR interrupt
Interrupt Condition
Receive DATA.
Receive the REPEAT code.
Transmit timing error.
Clear Interrupt
Read IR_DATA (Addr 43h) will clear this bit.
Write “1” to CLR_KP bit in IR_CTL (Addr 42h)
register then write “0” to CLR_KP.
Write “1” to CLR_ERR bit in IR_CTL (Addr 42h)
register then write “0” to CLR_ERR.
Weltrend Semiconductor, Inc.
Page 34
WT61P4 v1.03
Monitor Controller
A/D Converter
The Analog-to-Digital Converter (ADC) is 8-bit resolution with four selectable input channels. When
EN_CHn is set, PCn is configured as ADC input and PCn pull-high resistor is disabled. When CHn is
set, it will reset the ADC_DA register and start converting. After the conversion is done, the ADRDY bit
is set and valid data is stored in ADC_DA. The total conversion time is 12us. If program wants to make
a new conversion, it writes CHn register again and it will start another conversion.
ADC Data Register
Name
Addr R/W Initial
Bit 7
ADC_DA 001Ch R
xxh
AD7
ADC_RD 001Dh R
xxh ADRDY
Bit 6
AD6
Bit 5
AD5
Bit4
AD4
Bit 3
AD3
Bit 2
AD2
Bit 1
AD1
Bit 0
AD0
Bit 3
CH3
Bit 2
CH2
Bit 1
CH1
Bit 0
CH0
Bit Name
Description
ADRDY ADC data is ready to read when this bit is set.
AD7 ~ AD0 ADC data.
ADC Channel Select Register
Name
Addr R/W Initial
Bit 7
Bit 6
Bit 5
Bit4
ADC_CH 001Ch W
00h EN_CH3 EN_CH2 EN_CH1 EN_CH0
Bit Name
EN_CH3
EN_CH2
EN_CH1
EN_CH0
CH3
CH2
CH1
CH0
Description
“1”: PC3 is configured as ADC interface. (tri-state with no I/O function).
“0”: PC3 is configured as I/O port.
“1”: PC2 is configured as ADC interface. (tri-state with no I/O function).
“0”: PC2 is configured as I/O port.
“1”: PC1 is configured as ADC interface. (tri-state with no I/O function).
“0”: PC1 is configured as I/O port.
“1”: PC0 is configured as ADC interface. (tri-state with no I/O function).
“0”: PC0 is configured as I/O port.
Select AD3 pin to ADC convert when this bit is set.
Select AD2 pin to ADC convert when this bit is set.
Select AD1 pin to ADC convert when this bit is set.
Select AD0 pin to ADC convert when this bit is set.
Note: The EN_CHn must be set before CHn.
Weltrend Semiconductor, Inc.
Page 35
WT61P4 v1.03
Monitor Controller
CH3
AD3
CH2
AD2
Comparator
CH1
AD1
CH0
AD0
Resistor Array
ADRDY
ADC 8-bits Control
Fig. 11 Block diagram of ADC
START
set EN_CH3(W1C.7) or
EN_CH2(W1C.6) or
EN_CH1(W1C.5) or
EN_CH0(W1C.4)
set CH3(W1C.3) or
CH2(W1C.2) or
CH1(W1C.1) or
CH0(W1C.0)
No
ADRDY(R1D.7)=1 ?
Yes
read ADC_DA(R1C)
Weltrend Semiconductor, Inc.
Page 36
WT61P4 v1.03
Monitor Controller
Remote Control IR Detector
IR Control Register
Name
IR_CTL
Addr R/W Initial
0042h W
00h
Bit Name
ENIR
IN_HL
CLR_KP
CLR_ERR
Bit 7
ENIR
Bit 6
IN_HL
Bit 5
Bit4
Bit 3
Bit 2
Bit 1
Bit 0
CLR_KP CLR_ERR
Description
Enable remote control IR function.
IR input H or L trigger, IN_HL=1: H trigger, IN_HL=0: L trigger.
Clear IR_KEEP interrupt.
Clear IR_ERR interrupt.
IR Status & Data
Name
Addr R/W Initial
IR_STA 0042h R
00h
IR_DATA 0043h R
00h
Bit Name
IRRDY
IR_RD
IR_KEEP
IR_ERR
IRDCNTx
IRD7~IRD0
Bit 7
IRRDY
IRD7
Bit 6
Bit 5
Bit4
IR_RD IR_KEEP IR_ERR
IRD6
IRD5
IRD4
Bit 2
Bit 1
Bit 0
IRDCNT1 IRDCNT0
IRD3
IRD2
IRD1
IRD0
Description
IR event ready when (a) receive DATA (b) IR_KEEP=1 (c) IR_ERR=1, data time out.
“1” receive DATA. Read IR_DATA (Addr 43h) will clear this bit.
“1” receive the REPEAT code.
“1” transmit timing error. Data time out <0.56ms or >1.69ms.
Byte count of the received IR data.
Receive DATA.
CODE
01
01
01
CODE
01
01
01
01
DATA
01
01
01
01
DATA
01
01
01
01
01
IRRDY=1
IR_RD=1
IRDCNT1=0
IRDCNT0=0
IRRDY=1
IR_RD=1
IRDCNT1=0
IRDCNT0=1
2.25ms
1.125ms
2.25ms
4.5ms
0.56ms
9ms
Bit 3
IRRDY=1
IR_RD=1
IRDCNT1=1
IRDCNT0=0
01
9ms
IRRDY=1
IR_KEEP=1
IRRDY=1
IR_ERR=1
Weltrend Semiconductor, Inc.
Page 37
IRRDY=1
IR_RD=1
IRDCNT1=1
IRDCNT0=1
WT61P4 v1.03
Monitor Controller
Watchdog Timer
Watchdog Timer Register
Name
WDT
Addr R/W Initial
Bit 7
001Eh W
00h DISWDT
Bit Name
DISWDT
WDT
Bit 6
Bit 5
Bit4
Bit 3
Bit 2
Bit 1
WDT1
Bit 0
WDT0
Bit 3
Vin1
Bit 2
Hin2
Bit 1
Vin2
Bit 0
Description
“1” : Disable Watchdog Timer.
“0” : Enable Watchdog Timer.
(WDT1, WDT0)=(0,0): reset time = 1.536s
(WDT1, WDT0)=(0,1): reset time = 3.072s
(WDT1, WDT0)=(1,0): reset time = 48ms
(WDT1, WDT0)=(1,1): reset time = 96ms
Power Saving Control
Power Saving Control Register
Name
Addr R/W Initial
Bit 7
Bit 6
Bit 5
Bit4
PSC_CTL 0041h W
00h IRQ1_WK IRQ2_WK DDC_WK Hin1&SOG
Bit Name
IRQ1_WK
IRQ2_WK
DDC_WK
Hin1_WK&
SOG_WK
Vin1_WK
Hin2_WK
Vin2_WK
Bit0
Description
NIRQ1 falling edge trigger to wake up OSC.
NIRQ2 falling edge trigger to wake up OSC.
SCL, SDA falling edge trigger to wake up OSC.
Hin1, SOG falling edge trigger to wake up OSC.
Vin1 falling edge trigger to wake up OSC.
Hin2 falling edge trigger to wake up OSC.
Vin2 falling edge trigger to wake up OSC.
Must be 0.
It will clear all PSC_CTL trigger latch buffer when write data to the register 41H. The trigger latch buffer
must be cleared before entering the power down mode. After the external trigger signal received, CPU
delays 64ms and wakes up..
Function Configuration Register
Name
Addr R/W Initial
OTH_CTL1 004Eh W
00h
Bit 7
Bit 6
Bit 5
Bit4
PWMCLK
ENT0T1
Bit Name
ENT0T1
Bit 3
ICLK
Bit 2
Bit 1
Description
“1”: Enable the 8031 T0 and T1 source by external.
“0”: Disable.
“1”: PWM clock is 1.5MHz.
PWMCLK
“0”: PWM clock is 12MHz.
“1”: The clock of CPU is the same to OSCI but the clock of system is OSCI/2.
ICLK
“0”: The clock of CPU and system is the same as OSCI.
Weltrend Semiconductor, Inc.
Page 38
Bit 0
WT61P4 v1.03
Monitor Controller
PWM
PWM0: 12-bit PWM and +5/3.3V push-pull output, shared with I/O.
PWM1 ~ PWM15: 8-bit PWM and +5/3.3V push-pull output, shared with I/O.
The corresponding PWM register controls the PWM duty cycle. Duty cycle range is from 0/256 to
255/256. PWM0 duty cycle range is from 0/4096 to 4095/4096.
LSB 3-bit of the PWM1~PWM15 will extend Tpwm to the frame0~7, Fig.
000: no Tpwm extended.
001: extended Tpwm to the frame 4.
010: extended Tpwm to the frame 2 and 6.
011: extended Tpwm to the frame 2, 4 and 6.
100: extended Tpwm to the frame 1, 3, 5 and 7.
101: extended Tpwm to the frame 1, 3, 4, 5 and 7.
110: extended Tpwm to the frame 1, 2, 3, 5, 6 and 7.
111: extended Tpwm to the frame 1, 2, 3, 4, 5, 6 and 7.
PWMCLK=0, Tpwm=1/12MHz. PWMCLK=1, Tpwm=1/1.5MHz. Tframe=32Tpwm.
MSB 5-bit of the PWM1~PWM15: 0/32 to 31/32 duty of the Tframe.
LSB 6-bit of the PWM0 will extend Tpwm to the frame0~63, Fig.
000000 : no Tpwm extended.
000001 : extended Tpwm to the frame 32.
000010 : extended Tpwm to the frame 16 and 48.
000100 : extended Tpwm to the frame 8, 24, 40 and 56.
001000 : extended Tpwm to the frame 4, 12, 20, 28, 36, 44, 52 and 60.
010000 : extended Tpwm to the frame 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58 and 62.
100000 : extended Tpwm to the frame 1, 3, 5, 7, 9, ………57, 59, 61 and 63.
PWMCLK=0, Tpwm=1/12MHz. PWMCLK=1, Tpwm=1/1.5MHz. Tframe=64Tpwm.
MSB 6-bit of the PWM0: 0/64 to 63/64 duty of the Tframe.
Frame 0 Frame 1 Frame 2 Frame 3 Frame 4 Frame 5 Frame 6 Frame 7
Tpwm
PWM=00001000B
32 Tpwm
256 Tpwm
Tpwm
PWM=00000001B
PWM=00000010B
PWM=00000100B
Tpwm
Tpwm
Tpwm
Tpwm
2Tpwm
Tpwm
Tpwm
Tpwm
Tpwm
2Tpwm
2Tpwm
3Tpwm
2Tpwm
2Tpwm
2Tpwm
3Tpwm
2Tpwm
2Tpwm
PWM=00001001B
PWM=00010010B
Fig. 14 PWM output waveform
Weltrend Semiconductor, Inc.
Page 39
WT61P4 v1.03
Monitor Controller
PWM Registers
Name
PWM0L
PWM0H
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
PWM8
PWM9
PWM10
PWM11
PWM12
PWM13
PWM14
PWM15
PWM_EN1
PWM_EN2
Addr
000Ch
000Dh
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
000Eh
000Fh
R/W Initial
Bit 7
R/W 00h
R/W 80h PWM011
R/W 80h PWM17
R/W 80h PWM27
R/W 80h PWM37
R/W 80h PWM47
R/W 80h PWM57
R/W 80h PWM67
R/W 80h PWM77
R/W 80h PWM87
R/W 80h PWM97
R/W 80h PWM107
R/W 80h PWM117
R/W 80h PWM127
R/W 80h PWM137
R/W 80h PWM147
R/W 80h PWM157
W
00h EPWM7
W
00h EPWM15
Bit 6
Bit 5
PWM010
PWM16
PWM26
PWM36
PWM46
PWM56
PWM66
PWM76
PWM86
PWM96
PWM106
PWM116
PWM126
PWM136
PWM146
PWM156
EPWM6
EPWM14
Bit4
Bit 3
PWM03
PWM07
PWM13
PWM23
PWM33
PWM43
PWM53
PWM63
PWM73
PWM83
PWM93
PWM103
PWM113
PWM123
PWM133
PWM143
PWM153
EPWM3
Bit 2
PWM02
PWM06
PWM12
PWM22
PWM32
PWM42
PWM52
PWM62
PWM72
PWM82
PWM92
PWM102
PWM112
PWM122
PWM132
PWM142
PWM152
EPWM2
Bit 1
PWM01
PWM09 PWM08
PWM05
PWM15 PWM14
PWM11
PWM25 PWM24
PWM21
PWM35 PWM34
PWM31
PWM45 PWM44
PWM41
PWM55 PWM54
PWM51
PWM65 PWM64
PWM61
PWM75 PWM74
PWM71
PWM85 PWM84
PWM81
PWM95 PWM94
PWM91
PWM105 PWM104
PWM101
PWM115 PWM114
PWM111
PWM125 PWM124
PWM121
PWM135 PWM134
PWM131
PWM145 PWM144
PWM141
PWM155 PWM154
PWM151
EPWM5 EPWM4
EPWM1
EPWM13 EPWM12 EPWM11 EPWM10 EPWM9
Bit 0
PWM00
PWM04
PWM10
PWM20
PWM30
PWM40
PWM50
PWM60
PWM70
PWM80
PWM90
PWM100
PWM110
PWM120
PWM130
PWM140
PWM150
EPWM0
EPWM8
Bit Name
Description
PWMX7 ~ PWMX0 Select duty cycle of PWM1~15 output.
00000000: duty cycle = 0
00000001: duty cycle = 1/256
00000010: duty cycle = 2/256
:
11111110: duty cycle = 254/256
11111111: duty cycle = 255/256
PWM011 ~ PWM00 Select duty cycle of PWM0 output.
duty cycle = 0/4096 ~ 4095/4096
EPWMx
Set the corresponding EPPWMx will enable the PWM output. (x from 0 to 15)
Weltrend Semiconductor, Inc.
Page 40
WT61P4 v1.03
Monitor Controller
WT61P4 Register Map:
Name
PA_CTRL
PA_DATA
PB_CTRL
PB_DATA
PC_CTRL
PC_DATA
PD_CTRL
PD_DATA
PE_CTRL
PE_DATA
PD_CTRL2
HFREQ_L
HFREQ_H
VFREQ_L
VFREQ_H
H_PERD
HF_VL
HF_VH
VFQ_OVF
HV_CR1
Addr
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0010h
0011h
HV_CR2
FRH_CR
FRHD_CR
FRHB_CR
FRV_CR
FRVD_CR
FRVB_CR
HPD_CHG
1/2HV_CR
ADC_DA
ADC_CH
ADC_RD
WDT
I2C_STA
I2C_CON
I2C_RX
I2C_TX
I2C_ADR
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Ch
001Ch
001Dh
001Eh
0020h
0020h
0021h
0021h
0022h
0024h
0025h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
DDC_STA1
DDC_STA2
DDC_CON1
DDC_CON2
DDC_RTX
DDC_AAE
DDC_ABE
DDC_AR0
DDC_AR1
DDC_AR2
R/W Initial
Bit 7
Bit 6
Bit 5
R/W 00h PA7OE PA6OE PA5OE
R/W ffh
PA7
PA6
PA5
R/W 00h
PB6OE PB5OE
R/W xfh
PB6
PB5
R/W 00h PC7OE PC6OE PC5OE
R/W ffh
PC7
PC6
PC5
R/W 00h PD7OE PD7OE PD5OE
R/W ffh
PD7
PD6
PD5
R/W 00h
R/W xfh
W
00h PD7HE PD6HE PD5HE
R
xxh
HLVL HINPOL HCHG
R
xxh
HOVF
HFH6
HFH5
R
xxh
VF7
VF6
VF5
R
xxh
VLVL VINPOL VOVF
R
xxh HPRD7 HPRD6 HPRD5
R
00h
HFV7
HFV6
HFV5
R
00h
W
FFh OVVF11 OVVF10 OVVF9
W
00h ENHOU ENVOUT HOPOL
T
W
00h ENCLP CLPEG CLPPO
W
00h
FRH5
W
00h FRHB4 FRHD6 FRHD5
W
00h FRHB3 FRHB2 FRHB1
W
00h
FRV7
FRV6
FRV5
W
00h FRVD7 FRVD6 FRVD5
W
00h FRVB4 FRVB3 FRVB2
W
00h
HVIN2
W
00h ENH2D ENV2D HEDG
R
xxh
AD7
AD6
AD5
W
00h EN_CH3 EN_CH2 EN_CH1
R
xxh ADRDY
W
00h DISWDT
R
22h
BB
W
02h
ENI2C MCLK1 MCLK0
R
xxh
MRX7
MRX6
MRX5
W
xxh
MTX7
MTX6
MTX5
W
X0h
SAR7
SAR6
SAR5
R
01h ALGRDY
BB
DDC2
R
00h
W
00h ENDDC
DDC2
W
80h RAMAS1 RAMAS0 ENRAMA
R/W FFh
DRX7
DRX6
DRX5
W
FFh ENADRA7 ENADRA6 ENADRA5
W
00h ENADRB7 ENADRB6 ENADRB5
W
X0h DAR07 DAR06 DAR05
W
X0h DAR17 DAR16 DAR15
W
X0h DAR27 DAR26 DAR25
Weltrend Semiconductor, Inc.
Page 41
Bit4
PA4OE
PA4
PB4OE
PB4
PC4OE
PC4
PD4OE
PD4
PD4HE
HFL4
HFH4
VF4
VF12
HPRD4
HFV4
OVVF8
VOPOL
Bit 3
Bit 2
PA3OE PA2OE
PA3
PA2
PB3OE PB2OE
PB3
PB2
PC3OE PC2OE
PC3
PC2
PD3OE PD2OE
PD3
PD2
PE3OE PE2OE
PE3
PE2
PD3HE PD2HE
HFL3
HFL2
HFH3
HFH2
VF3
VF2
VF11
VF10
HPRD3 HPRD2
HFV3
HFV2
HFV11 HFV10
OVVF7 OVVF6
QUICK SEPART
CLPPW1
FRH4
FRHD4
FRHB0
FRV4
FRVD4
FRVB1
CLPPW0
FRH3
FRHD3
FRHW3
FRV3
FRVD3
FRVB0
EN_LMT
AD4
EN_CH0
AD3
CH3
Bit 1
PA1OE
PA1
PB1OE
PB1
PC1OE
PC1
PD1OE
PD1
PE1OE
PE1
PD1HE
HFL1
HFH1
VF1
VF9
HPRD1
HFV1
HFV9
OVVF5
ENFREE
Bit 0
PA0OE
PA0
PB0OE
PB0
PC0OE
PC0
PD0OE
PD0
PE0OE
PE0
PD0HE
HFL0
HFH0
VF0
VF8
HPRD0
HFV0
HFV8
OVVF4
ENPAT
SOG HVPASS BYPASS
FRH2
FRH1
FRH0
FRHD2 FRHD1 FRHD0
FRHW2 FRHW1 FRHW0
FRV2
FRV1
FRV0
FRVD2 FRVD1 FRVD0
FRVW2 FRVW1 FRVW0
HCNT2 HCNT1 HCNT0
AD2
CH2
SFIRST SSTOP
SRW
MSTR MSTOP I2CRW
MRX4
MRX3
MRX2
MTX4
MTX3
MTX2
SAR4
SAR3
SAR2
FIRST
STOP ALGRW
IN_CMD
TX
RAMBS ENRAMB CLR_ADR
DRX4
DRX3
DRX2
AD1
CH1
AD0
CH0
WDT1
RXNAK2
TXNAK2
MRX1
MTX1
SAR1
MATCH
WR_D3
WDT0
I2CRDY
SLAVE
MRX0
MTX0
DLYHLD
RXNAK1
TXNAK1
CLR_WD3 WR_EN
DRX1
DRX0
ENADRA4 ENADRA3 ENADRA2 ENADRA1 ENADRA0
ENADRB4 ENADRB3 ENADRB2 ENADRB1 ENADRB0
DAR04
DAR14
DAR24
DAR13
DAR23
DAR12
DAR22
DAR11
DAR21
ENAR0
ENAR1
ENAR2
WT61P4 v1.03
Monitor Controller
Name
INT_FLG
INT_EN
INT_FLG2
INT_EN2
INT_SRC
IRQ_CON1
IRQ_CON2
PWM0L
PWM0H
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
PWM8
PWM9
PWM10
PWM11
PWM12
PWM13
PWM14
PWM15
PWM_EN1
PWM_EN2
PSC_CTL
IR_STA
IR_DATA
IR_CTL
OTH_CTL1
Addr
002Ch
002Ch
002Dh
002Dh
002Eh
002Eh
002FH
000Ch
000Dh
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
000Eh
000Fh
0041h
0042h
0043h
0042h
004Eh
R/W Initial
Bit 7
Bit 6
Bit 5
Bit4
R
00h IF_DDC IF_MI2C IF_RGB IF_SYNC
W
00h IE_DDC IE_MI2C IE_RGB IE_SYNC
R
00h IF_POL IF_OVV IF_HCHG IF_IR
W
00h IE_POL IE_OVV IE_HCHG IE_IR
R
00h POLINT OVVINT RGBRDY SYNC
W
00h CLR_POL CLR_OV
W
00h
R/W 00h
R/W 80h PWM011 PWM010 PWM09 PWM08
R/W 80h PWM17 PWM16 PWM15 PWM14
R/W 80h PWM27 PWM26 PWM25 PWM24
R/W 80h PWM37 PWM36 PWM35 PWM34
R/W 80h PWM47 PWM46 PWM45 PWM44
R/W 80h PWM57 PWM56 PWM55 PWM54
R/W 80h PWM67 PWM66 PWM65 PWM64
R/W 80h PWM77 PWM76 PWM75 PWM74
R/W 80h PWM87 PWM86 PWM85 PWM84
R/W 80h PWM97 PWM96 PWM95 PWM94
R/W 80h PWM107 PWM106 PWM105 PWM104
R/W 80h PWM117 PWM116 PWM115 PWM114
R/W 80h PWM127 PWM126 PWM125 PWM124
R/W 80h PWM137 PWM136 PWM135 PWM134
R/W 80h PWM147 PWM146 PWM145 PWM144
R/W 80h PWM157 PWM156 PWM155 PWM154
W
00h EPWM7 EPWM6 EPWM5 EPWM4
W
00h EPWM15 EPWM14 EPWM13 EPWM12
W
00h IRQ1_WK IRQ2_WK DDC_WK Hin1&SOG
R
00h
IRRDY IR_RD IR_KEEP IR_ERR
R
00h
IRD7
IRD6
IRD5
IRD4
W
00h
ENIR
IN_HL
W
00h
ENT0T1 PWMCLK
Weltrend Semiconductor, Inc.
Page 42
Bit 3
Bit 2
Bit 1
IF_IRQ2 IF_IRQ1 IF_VSO
IE_IRQ2 IE_IRQ1 IE_VSO
IRQ2
IRQ1
VSO
Bit 0
IF_VIN
IE_VIN
VIN
CLR_IRQ2 CLR_IRQ1 CLR_VSO CLR_VIN
IRQ2_RF IRQ2_EG IRQ1_RF IRQ1_EG
PWM03
PWM07
PWM13
PWM23
PWM33
PWM43
PWM53
PWM63
PWM73
PWM83
PWM93
PWM103
PWM113
PWM123
PWM133
PWM143
PWM153
EPWM3
PWM02
PWM06
PWM12
PWM22
PWM32
PWM42
PWM52
PWM62
PWM72
PWM82
PWM92
PWM102
PWM112
PWM122
PWM132
PWM142
PWM152
EPWM2
PWM01
PWM05
PWM11
PWM21
PWM31
PWM41
PWM51
PWM61
PWM71
PWM81
PWM91
PWM101
PWM111
PWM121
PWM131
PWM141
PWM151
EPWM1
EPWM11 EPWM10 EPWM9
Vin1
Hin2
Vin2
IRD3
IRD2
PWM00
PWM04
PWM10
PWM20
PWM30
PWM40
PWM50
PWM60
PWM70
PWM80
PWM90
PWM100
PWM110
PWM120
PWM130
PWM140
PWM150
EPWM0
EPWM8
IRDCNT1 IRDCNT0
ICLK
IRD1
IRD0
CLR_KP CLR_ERR
WT61P4 v1.03
Monitor Controller
TARGET AC AND DC SPECIFICATION
Absolute Maximum Ratings
Parameter
DC Supply Voltage (VDD)
Input and output voltage with respect to Ground
Storage temperature
Ambient temperature with power applied
Min.
-0.3
-0.3
-25
-10
Max.
5.5
VDD+0.3
125
85
Units
V
V
o
C
o
C
D.C Characteristics (VDD=5.0V±10%, Ta=0-70°C)
Symbol
VDD5v
IVDD
ISuspend
VIH,IO
VIL,IO
VOH,IO
VOL,IO
VOL,IO
RPH
VIH,SYNC
VIL,SYNC
IIL,SYNC
VIH,SCL
VIH,SDA
VIH,SCL
VIH,SDA
VIH,RES
VIL,RES
VLVD
Parameter
+5v Supply Voltage
Operating Current
Power Down Mode Current
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Output Low Voltage (PC0-PC7)
Pull High Resistance
HIN, VIN, SOG Input High
Voltage (Schmitt trigger)
HIN, VIN, SOG Input Low
Voltage (Schmitt trigger)
Input Leakage Current
HSYNC and VSYNC pins
SCL, SDA Input High Voltage
(Schmitt trigger)
SCL, SDA Input Low Voltage
(Schmitt trigger)
Reset Input High Voltage
Reset Input Low Voltage
Low VDD Reset Voltage
Condition
FOSC= 12MHz, No load
No load
IOH = -6mA
IOL = 6mA
IOL = 10mA
0V <VIN < VDD
Weltrend Semiconductor, Inc.
Page 43
Min.
4.5
--0.7VDD
-0.3
4
0
0
---
Typ.
5
12
150
--4.5
0.18
0.15
25
1.6
Max.
5.5
30
-VDD+0.3
0.2VDD
VDD
0.4
0.4
50
--
Units
V
mA
µA
V
V
V
V
V
Kohm
V
--
1.2
--
V
-1
--
1
µA
2.8
--
VDD+0.3
V
-0.3
--
1.6
V
2.8
-0.3
2.5
--2.7
VDD+0.3
1.6
2.9
V
V
V
WT61P4 v1.03
Monitor Controller
D.C Characteristics (VDD=3.3V±10%, Ta=0-70°C)
Symbol
VDD5v
IVDD
ISuspend
VIH,IO
VIL,IO
VOH,IO
VOL,IO
VOL,IO
RPH
VIH,SYNC
VIL,SYNC
IIL,SYNC
VIH,SCL
VIH,SDA
VIH,SCL
VIH,SDA
VIH,RES
VIL,RES
VLVD
Parameter
+5v Supply Voltage
Operating Current
Power Down Mode Current
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Output Low Voltage (PC0-PC7)
Pull High Resistance
HIN,VIN,SOGIN Input High
Voltage (Schmitt trigger)
HIN,VIN,SOG Input High
Voltage(Schmitt trigger)
Input Leakage Current
HSYNC and VSYNC pins
SCL,SDA Input High Voltage
(Schmitt trigger)
SCL,SDA Input Low Voltage
(Schmitt trigger)
Reset Input High Voltage
Reset Input Low Voltage
Low VDD Reset Voltage
Condition
FOSC= 12MHz, No load
No load
IOH = -6mA
IOL = 6mA
IOL = 10mA
0V <VIN < VDD
Weltrend Semiconductor, Inc.
Page 44
Min.
3.0
--0.7VDD
-0.3
2.8
0
0
---
Typ.
3.3
12
50
---
25
1.2
Max.
3.6
30
-VDD+0.3
0.2VDD
VDD
0.4
0.4
50
--
Units
V
mA
µA
V
V
V
V
V
Kohm
V
--
0.9
--
V
-1
--
1
µA
2.0
--
VDD+0.3
V
-0.3
--
1.0
V
2.0
-0.3
2.5
--2.7
VDD+0.3
1.0
2.9
V
V
V
WT61P4 v1.03
Monitor Controller
A.C Characteristics (VDD=5.0V±5%, fosc=24MHz, Ta=0-70°C)
NRES and NIRQ Timing
Symbol
Parameter
tLOW,RES
tLOW,IRQ
NRES pin low pulse
NIRQ low pulse (level trigger)
Min.
Typ.
Max.
Units
83
83
---
---
ns
ns
RESET
IRQ
t LOW ,RE S
t HIGH,IRQ
SYNC Processor Timing
Symbol
Parameter
Min.
Typ.
Max.
Units
tHIGH,SYNC
tLOW,SYNC
HSYNC and VSYNC high time
HSYNC and VSYNC low time
167
167
---
---
ns
ns
HSYNC
VSYNC
tHIGH,SYNC
tLOW,SYNC
DDC1 Timing
Symbol
Parameter
Min.
Typ.
Max.
Units
tVAA,DDC1
SDA1 output valid from VSYNC rising edge
125
--
500
ns
t V A A ,D D C 1
SDA1
B it 0 (LS B )
N ull B it
V S YN C
t H IG H ,SY N C
t LO W ,SY N C
Weltrend Semiconductor, Inc.
Page 45
B it 7 (M S B )
WT61P4 v1.03
Monitor Controller
DDC2B Timing
Symbol
fSCL
tBF
tHD,START
tSU,START
tHIGH,SCL
tLOW,SCL
tHD,DATA
tSU,DATA
tRISE,DDC
tFALL.DDC
tSU,STOP
Parameter
SCL1 input clock frequency
Bus free time
Hold time for START condition
Set-up time for START condition
SCL1 clock high time
SCL1 clock low time
Hold time for DATA input
Hold time for DATA output
Set-up time for DATA input
Set-up time for DATA output
SCL1 and SDA1 rise time
SCL1 and SDA1 fall time
Set-up time for STOP condition
Min.
-1.3
0.6
0.6
0.6
1.3
0
-100
---0.6
Typ.
--------------
Max.
400
---------300
300
--
Units
kHz
us
us
us
us
us
ns
ns
ns
ns
Ns
ns
us
Min.
0
2
1
1
1
1
0
167
167
334
2
Typ.
-
Max.
100
1
300
-
Units
kHz
us
us
us
us
us
ns
ns
ns
ns
us
ns
us
SLAVE I or II I2C Timing
Symbol
fSCL
tBF
tHD,START
tSU,START
tHIGH,SCL
tLOW,SCL
tHD,DATA
tSU,DATA
tRISE,DDC
tFALL.DDC
tSU,STOP
Parameter
SCL1 input clock frequency
Bus free time
Hold time for START condition
Set-up time for START condition
SCL1 clock high time
SCL1 clock low time
Hold time for DATA input
Hold time for DATA output
Set-up time for DATA input
Set-up time for DATA output
SCL1 and SDA1 rise time
SCL1 and SDA1 fall time
Set-up time for STOP condition
tBF
SDA1
tHD,START
tRISE
tFALL
SCL1
tSU,STOP
tLOW,SCL
tHD,DATA
Weltrend Semiconductor, Inc.
Page 46
tHIGH,SCL
tSU,DATA
tSU,START
WT61P4 v1.03
Monitor Controller
TYPICAL APPLICATION CIRCUIT
Crystal Oscillator
NRES Pin and 3.3V Regulator
VDD=3.3v
Weltrend Semiconductor, Inc.
Page 47
WT61P4 v1.03
Monitor Controller
PWM Output
Hsync, Vsync and DDC Interface Protection
+5V
WT61P4
+5V
47K
47K
220
VIN
VSYNC
HIN
HSYNC
220
100P
470P
5.1V
+5V
47K
+5V
10K
150
SCL1
SCL
SDA1
SDA
150
5.1V
Weltrend Semiconductor, Inc.
Page 48