芯美电子 Preliminary EUP7182 50mA Low-Noise Ultra Low-Dropout CMOS Regulator with Fault Indicator DESCRIPTION FEATURE The EUP7182 low-noise, low-dropout, linear regulator operates from a 2.5V to 5.5V input and is guaranteed to deliver 50mA. The EUP7182 is stable with small 1µF ceramic capacitor. Its performance suits battery powered applications because of its shutdown mode (60 nA typ), low quiescent current (110µA typ), and LDO voltage (25mV typ). The low dropout voltage allows for more utilization of a battery’s available energy by operating closer to its end-of-life voltage. An output fault-detection circuit indicates loss of regulation. The EUP7182 is available in MSOP package with 1.8V, 2.5v, 2.8V, 3V and 3.3V versions. z z z z z z z z z z z z 2.5V to 5.5V Input Range 50mA Guaranteed Output Current 60dB PSRR at 1kHz 50µV RMS Output Voltage Noise (10Hz to 100kHz) 25mV Dropout at 50mA Low 110µA No-Load Supply Current ≤ 1µA Shutdown Current Fast Start-up Time Stable With 1µF Ceramic Output Capacitors Thermal Shutdown and Short-Circuit Protection Fault Indicator RoHS Compliant and 100% Lead (Pb)-Free APPLICATIONS z z z z Wireless Handsets DSP Core Power Battery Powered Electronics Portable Information Appliances Block Diagram Figure1. DS7182 Ver 0.1 Oct.2007 1 联系电话：１５９９９６４４５７９ ８３１５１７１５ 芯美电子 Preliminary EUP7182 Typical Application Circuit Figure2. Fixed Voltage LDO Regulator Pin Configurations Package Type Pin Configurations SOT23-6 Pin Description PIN PIN VIN 1 Input voltage of the LDO GND 2 Common Ground SHDN 3 FAULT 4 CC 5 SHDN places the entire device in shutdown mode when held low. Fault output. A high-impedance, open-drain output. If the circuit is out of regulation, FAULT goes low. In shutdown, this pin is high Impedance. Connect to GND if unused Compensation capacitor for noise reduction VOUT 6 Output voltage of the LDO DS7182 Ver 0.1 Oct.2007 DESCRIPTION 2 联系电话：１５９９９６４４５７９ ８３１５１７１５ 芯美电子 Preliminary EUP7182 Ordering Information Order Number Package Type Marking Operating Temperature range EUP7182-18VIR1 SOT23-6 mDxxxx -40°C to 85°C EUP7182-25VIR1 SOT23-6 mBxxxx -40°C to 85°C EUP7182-28VIR1 SOT23-6 mExxxx -40°C to 85°C EUP7182-30VIR1 SOT23-6 mGxxxx -40°C to 85°C EUP7182-33VIR1 SOT23-6 mHxxxx -40°C to 85°C EUP7182 □ □ □ □ □ □ Lead Free Code 1: Lead Free 0: Lead Packing R: Tape & Reel Operating temperature range I: Industry Standard C: Commercial Package Type V: SOT23 Output Voltage 18: 1.8V 25: 2.5V 28: 2.8V 30: 3.0V 33: 3.3V DS7182 Ver 0.1 Oct.2007 3 联系电话：１５９９９６４４５７９ ８３１５１７１５ 芯美电子 EUP7182 Preliminary Absolute Maximum Ratings VIN, VOUT, V SHDN , VCC, V FAULT ------------------------------------------------------------ -0.3V to 6V Fault Sink Current --------------------------------------------------------------------------------20mA Storage Temperature Range ------------------------------------------------------------- -65°C to 160°C Junction Temperature (TJ) -----------------------------------------------------------------------150°C Lead Temperature (10 sec.) ------------------------------------------------------------------------260°C Electrical Characteristics Unless otherwise specified, all limits guaranteed for VIN= VO +0.5V, VSHDN=VIN, CIN=COUT=1µF, CCC=10nF, TJ =25°C. (Boldface limits apply for the operating temperature extremes: -40°C and 85°C) Symbol Parameter VIN Input Voltage ∆ VO Output Voltage Tolerance IO Maximum Output Current Output Current Limit Supply Current Shutdown Supply Current ILIMIT IQ VDO ∆ VO Conditions 100µA ≤ IOUT ≤ 50mA VIN=VO+0.5V, Average DC Current Rating 75 110 0.06 VO =0V, SHDN =GND IOUT =1mA Dropout Voltage IOUT =50mA IOUT = 1mA, (VO +0.5V) ≤ VI ≤ 5.5V 100µA ≤ IOUT ≤ 50mA IOUT =10mA, 10Hz ≤ f ≤ 100kHz VIH,(VO+0.5V) ≤ VI ≤ 5.5V Line Regulation Output Voltage Noise EUP7182 Typ Max. 2.5 -2 -3 50 IOUT=0mA Load Regulation en Min 5.5 +2 +3 100 100 200 1 0.4 -0.1 25 50 0.05 0.1 Unit V % of VOUT(NOM) mA mA µA µA mV %/V 0.002 %/mA 50 µVRMS 2 V VSHDN SHDN Input Threshold ISHDN SHDN Input Bias Current SHDN =GND or IN 0.1 100 nA FAULT Detection Voltage VO ≥ 2.5V, IOUT =50mA 40 70 mV FAULT Output Low Voltage ISINK=2mA 0.13 0.25 V FAULT =3.6V, SHDN =0V 0.1 100 nA V FAULT VIL,(VO+0.5V) ≤ VI ≤ 5.5V I FAULT FAULT Off-Leakage Current TSD Thermal Shutdown Temperature 160 Thermal Shutdown Hysteresis TON Start-Up Time DS7182 Ver 0.1 Oct.2007 0.4 20 VO at 90% of Final Value 80 4 联系电话：１５９９９６４４５７９ ８３１５１７１５ °C µs 芯美电子 Application Information Noise Bypass Capacitor Connecting a 33nF capacitor between the CBYPASS pin and ground significantly reduces noise on the regulator output. This cap is connected directly to a high impedance node in the bandgap reference circuit. Any significant loading on this node will cause a change on the regulated output voltage. For this reason, DC leakage current through this pin must be kept as low as possible for best output voltage accuracy. The types of capacitors best suited for the noise bypass capacitor are ceramic and film. Unlike many other LDO’s , addition of a noise reduction capacitor does not effect the load transient response of the device. However, it does affect start-up time. The smaller the capacitance value, the quicker the start-up time. External Capacitors Like any low-dropout regulator, the EUP7182 requires external capacitors for regulator stability. The EUP7182 is specifically designed for portable applications requiring minimum board space and smallest components. These capacitors must be correctly selected for good performance. Input Capacitor A minimum input capacitance of 1µF is required between the EUP7182 input pin and ground (the amount of the capacitance may be increased without limit).This capacitor must be located a distance of not more than 1cm from the input pin and returned to a clean analog ground. 1µF ceramic capacitor are fine for most end use applications. If a tantalum capacitor is used at the input, it must be guaranteed by the manufacturer to have a surge current rating sufficient for the application. Power Dissipation and Junction Temperature Specified regulator operation is assured to a junction temperature of 125°C; the maximum junction temperature should be restricted to 125°C under normal operating conditions. This restriction limits the power dissipation the regulator can handle in any given application. To ensure the junction temperature is within acceptable limits, calculate the maximum allowable dissipation, PD(max), and the actual dissipation, PD, which must be less than or equal to PD(max) The maximum-power-dissipation limit is determined using the following equation: No-Load Stability The EUP7182 will remain stable and in regulation with no external load. This is specially important in CMOS RAM keep-alive applications. Output Capacitance The EUP7182 is specifically designed to employ ceramic output capacitors as low as 2.2µF. Ceramic capacitors below 10µF offer significant cost and space savings, along with high frequency noise filtering. Higher values and other types and of capacitor may be used, but their equivalent series resistance (ESR) should be maintained below 0.5Ω. Ceramic capacitor of the value required by the EUP7182 are available in the following dielectric types: Z5U, Y5V, X5R, and X7R. The Z5U and Y5V types exhibit a 50% or more drop in capacitance value as their temperature increase from 25°C, an important consideration. The X5R generally maintain their capacitance value within ± 20%. The X7R type are desirable for their tighter tolerance of 10% over temperature. DS7182 Ver 0.1 Oct.2007 EUP7182 Preliminary T max − T A = J D(max) R P θJA Where: TJmax is the maximum allowable junction temperature. RθJA is the thermal resistance junction-to-ambient for the package TA is the ambient temperature. The regulator dissipation is calculated using: PD=(VI-VO) × IO Power dissipation resulting from quiescent current is negligible. Excessive power dissipation triggers the thermal protection circuit. 5 联系电话：１５９９９６４４５７９ ８３１５１７１５ 芯美电子 Preliminary EUP7182 Fault Detection The EUP7182 provides a FAULT pin that goes low during out of regulation conditions like current limit and thermal shutdown, or when it approaches dropout. The latter monitors the input-to-output voltage differential and compares it against a threshold that is slightly above the dropout voltage. This threshold also tracks the dropout voltage as it varies with load current. Refer to Fault Detect vs. Load Current curve in the typical characteristics section. The FAULT pin requires a pull-up resistor since it is an open-drain output. This resistor should be large in value to reduce energy drain. A100kΩ pull-up resistor works well for most applications. Shutdown The EUP7182 goes into sleep mode when the SHDN pin is in a logic low condition. During this condition, the pass transistor, error amplifier, and bandgap are turned off, reducing the supply current to 60nA typical. The SHDN pin may be directly tied to VIN to keep the part on. Fast Start-up The EUP7182 provides fast start-up time for better system efficiency. The start-up speed is maintained when using the optional noise bypass capacitor. DS7182 Ver 0.1 Oct.2007 6 联系电话：１５９９９６４４５７９ ８３１５１７１５ 芯美电子 EUP7182 Preliminary Packaging Information SOT23-6 SYMBOLS A A1 b D E1 e E L DS7182 Ver 0.1 Oct.2007 MILLIMETERS MIN. MAX. 1.45 0.00 0.15 0.30 0.50 2.90 1.60 0.95 2.60 3.00 0.30 0.60 INCHES MIN. 0.000 0.012 MAX. 0.057 0.006 0.020 0.114 0.063 0.037 0.102 0.012 0.118 0.024 7 联系电话：１５９９９６４４５７９ ８３１５１７１５