ETC NTP8000

NTP-8010
High Performance, High Fidelity Power
Driver Integrated Full Digital Audio Amplifier
Datasheet
Revision 1.0
Power Driver Integrated Full Digital Audio Amplifier
General Description
NTP-8010
Features
The NTP-8010 is a single chip full digital audio
amplifier including power stage for stereo amplifier
system. NTP-8010 is integrated with versatile digital
audio signal processing functions, high-performance,
high-fidelity fully digital PWM modulator and two
high-power full bridge MOSFET power stages.
The NTP-8010 receives digital serial audio data with
sampling frequency from 8KHz to 192KHz. It
delivers 2 x 10 watt in stereo mode without heat sink.
The NTP-8010 has mixer and Bi-Quad filters which
can be used to implement the essential audio signal
processing functions like loudness control, loud
speaker response compensation and parametric
equalizers.
All the functions of the NTP-8010 can be controlled
2
by internal register values via I C host interface bus.










Package
2 CH Stereo (10W x 2 BTL)
Wide Operating Supply Voltage Range
(4.5V to 16V)
Floating Point Operation
16 Programmable Bi-Quad Filters
 Speaker Compensation
 DC Cut, LPF, HPF
 Parametric Equalizer
100dB Dynamic Range
Enhanced Dynamic Range Control
Adaptive Loudness Compensation
Loudness Control
Protection Circuit
 OCP(Over Current Protection)
 OTP(Over Temperature Protection)
 UVP(Under Voltage Protection)
High Efficiency
CLK_IN
GND_IO
AD
RESET
BST1A
PGND1A
PGND1A
OUT1A
OUT1A
PVDD1A
PVDD1A
PGND1B
PVDD1B
OUT1B
56
55
54
53
52
51
50
49
48
47
46
45
44
43
Applications
VDD_IO
1
42
OUT1B
DGND_PLL
2
41
PGND1B
AGND_PLL
3
40
PGND1B
LF
4
39
BST1B
AVDD_PLL
5
38
VDR1B
DVDD_PLL
6
37
VDR1A
GND
7
36
AGND1
DGND
8
35
AGND2
NTP-8010
22
23
24
25
26
27
28
OUT2B
PVDD2B
PVDD2B
PVDD2A
PVDD2A
OUT2A
OUT2A
OUT2B
29
21
14
PGND2B
PGND2A
SCL
20
30
PGND2B
13
19
PGND2A
SDA
BST2B
BST2A
31
18
32
12
/FAULT
11
BCK
17
WCK
MONITOR_2
VDR2A
16
VDR2B
15
34
33
MONITOR_1
9
10
MORITOR_0
DVDD
SDATA



PDP TV or LCD TV
Docking Station
Mini-Component Audio Solution
Ordering Information
Product ID
Package Type
Pin
Size
NTP-8010
MLF
56
8 x 8mm
( 56 pin MLF 8mm x 8mm Package )
NeoFidelity, Inc. #1901, Ace High-End Tower 2, 222-14, Guro-dong, Guro-gu, Seoul 152-848 Korea,
Phone +82-2-6340-1000, Fax +82-2-6675-1109, Email [email protected], Web www.neofidelity.com
Disclaimer
NeoFidelity, Inc. reserves the right to make changes without notice in the product described in this datasheet including circuits, software and ICs,
described herein for the purpose of improvement of design and performance. NeoFidelity, Inc. assumes no responsibilities and liabilities for the use of
the product, conveys no license under any patent or copyright, and makes no warranties that the product is free from patent or copyright infringement,
unless otherwise specified.
Copyright ⓒ NeoFidelity, Inc.
Document Number: DS8010 Rev 1.0
Page 2
2009-10-30
Power Driver Integrated Full Digital Audio Amplifier
NTP-8010
Table of Contents
1. BLOCK DIAGRAM ..................................................................................................................................................... 4
2. PIN ASSIGNMENTS .................................................................................................................................................. 4
3. PIN DESCRIPTIONS .................................................................................................................................................. 5
4. CHARACTERISTICS AND SPECIFICATIONS .......................................................................................................... 7
4.1. Absolute Maximum Ratings ................................................................................................................................... 7
4.2. Recommended Operating Conditions ................................................................................................................... 7
4.3. DC Electrical Characteristics ................................................................................................................................. 7
4.4. Performance Specification ..................................................................................................................................... 8
4.5. Switching Characteristics – I2C Control ................................................................................................................ 8
4.6. Switching Characteristics – Audio Interface .......................................................................................................... 8
5. I2C BUS OF NTP-8010 ............................................................................................................................................ 10
5.1. General Description of I2C Bus ........................................................................................................................... 10
5.1.1. Writing Operation .............................................................................................................................................. 11
5.1.2. Reading Operation ........................................................................................................................................... 12
5.1.3. I2C Glitch Filter................................................................................................................................................. 12
6. CLOCK, RESET & CONTROL ................................................................................................................................. 13
6.1. System Clock ...................................................................................................................................................... 13
6.2. Power On Sequence ........................................................................................................................................... 13
6.3. Reset ................................................................................................................................................................... 13
7. AUDIO INPUT .......................................................................................................................................................... 14
7.1. I2S and Serial Audio Interface ............................................................................................................................. 14
8. MIXER ...................................................................................................................................................................... 16
9. PRE-PROCESSING ................................................................................................................................................. 17
9.1. Adaptive Loudness Compensation ...................................................................................................................... 17
9.2. Bi-Quad Filter Chain ............................................................................................................................................ 17
9.3. Loudness Control ................................................................................................................................................ 18
10. VOLUME & DYNAMIC RANGE CONTROL ............................................................................................................ 19
10.1. Master Volume Control ...................................................................................................................................... 19
10.2. Channel Volume Control ................................................................................................................................... 19
10.3. Master Volume Fine Control .............................................................................................................................. 19
10.4. Master Volume Override .................................................................................................................................... 19
10.5. Mute and Soft Volume Change.......................................................................................................................... 19
10.6. Auto Mute .......................................................................................................................................................... 20
10.7. Dynamic Range Control .................................................................................................................................... 20
10.8. Power Meter ...................................................................................................................................................... 20
11. OUTPUT INTERFACE.............................................................................................................................................. 21
11.1. Output Configuration.......................................................................................................................................... 21
11.2. AM Interface Relief Mode .................................................................................................................................. 21
11.3. PWM Output Mapper ......................................................................................................................................... 21
11.4. Switching Output Mode...................................................................................................................................... 21
11.5. Soft start ............................................................................................................................................................ 22
12. TYPICAL APPLICATION SCHEMATICS ................................................................................................................. 23
13. APPENDIX ............................................................................................................................................................... 24
A.
B.
C.
Configuration Register Summary........................................................................................................................ 24
Configuration Resister Value Reference ............................................................................................................. 36
Outline and Mechanical Data.............................................................................................................................. 40
Copyright ⓒ NeoFidelity, Inc.
Document Number: DS8010 Rev 1.0
Page 3
2009-10-30
Power Driver Integrated Full Digital Audio Amplifier
NTP-8010
1. BLOCK DIAGRAM
SDATA
BCK
L
Digital
Audio
Interface
WCK
MIXER
PLL
SCL
SDA
I2C
Interface
Volume
Control
L
Biquad Filter
R
MCLK
Adaptive
Loudness
Compensation
L
R
1A
1B
Mute
R
Loudness
Control
2A
2B
DRC
Full
Bridge
Power
FET
Output
Protection
Logic
Control
Register
OUT1A
OUT1B
OUT2A
OUT2B
FAULT
MONITOR0
MONITOR1
MONITOR2
Monitoring
Logic
Figure 1. NTP-8010 Block Diagram
CLK_IN
GND_IO
AD
RESET
BST1A
PGND1A
PGND1A
OUT1A
OUT1A
PVDD1A
PVDD1A
PGND1B
PVDD1B
OUT1B
56
55
54
53
52
51
50
49
48
47
46
45
44
43
2. PIN ASSIGNMENTS
VDD_IO
1
42
OUT1B
DGND_PLL
2
41
PGND1B
AGND_PLL
3
40
PGND1B
LF
4
39
BST1B
AVDD_PLL
5
38
VDR1B
DVDD_PLL
6
37
VDR1A
GND
7
36
AGND1
DGND
8
35
AGND2
DVDD
9
34
VDR2B
SDATA
10
33
VDR2A
WCK
11
32
BST2A
BCK
12
31
PGND2A
SDA
13
30
PGND2A
SCL
14
29
OUT2A
15
16
17
18
19
20
21
22
23
24
25
26
27
28
MORITOR_0
MONITOR_1
MONITOR_2
/FAULT
BST2B
PGND2B
PGND2B
OUT2B
OUT2B
PVDD2B
PVDD2B
PVDD2A
PVDD2A
OUT2A
NTP-8010
Figure 2. NTP-8010 Pin Assignments
Copyright ⓒ NeoFidelity, Inc.
Document Number: DS8010 Rev 1.0
Page 4
2009-10-30
Power Driver Integrated Full Digital Audio Amplifier
NTP-8010
3. PIN DESCRIPTIONS
PIN
NAME
TYPE
DESCRIPTION
1
VDD_IO
P
Power supply for digital interface I/O, 3.3V
2
DGND_PLL
P
Ground for PLL digital block
3
AGND_PLL
P
Ground for PLL analog block
4
LF
O
External PLL loop filter
5
AVDD_PLL
P
Power supply for PLL analog block, 1.8V
6
DVDD_PLL
P
Power supply for PLL digital block, 1.8V
7
GND
I
This pin should be connected to Ground
8
DGND
P
Ground for Core block
9
DVDD
P
Core Logic Power Supply, 1.8V
10
SDATA
I
I2S serial data input
11
WCK
I/O
I2S word clock
12
BCK
I/O
I2S bit clock
13
SDA
I/O
I2C data
14
SCL
I
I2C clock
15
MONITOR0
O
No Connection, monitoring signal out from Power Driver protection logic
16
MONITOR1
O
No Connection, monitoring signal out from processor block
17
MONITOR2
O
No Connection, monitoring signal out from processor block
18
/FAULT
I
Active low to reset internal power stage, Pull-up
19
BST2B
P
Bootstrap supply, external capacitor to OUT2B is required
20
PGND2B
P
Ground
21
PGND2B
P
Ground
22
OUT2B
O
Power stage PWM output 2B
23
OUT2B
O
Power stage PWM output 2B
24
PVDD2B
P
Power supply for PWM Power stage 2B
25
PVDD2B
P
Power supply for PWM Power stage 2B
26
PVDD2A
P
Power supply for PWM Power stage 2A
27
PVDD2A
P
Power supply for PWM Power stage 2A
28
OUT2A
O
Power stage PWM output 2A
29
OUT2A
O
Power stage PWM output 2A
30
PGND2A
P
Ground
31
PGND2A
P
Ground
32
BST2A
P
Bootstrap supply, external capacitor to OUT2A is required
33
VDR2A
P
Gate drive voltage regulator decoupling pin, capacitor to GND is required
34
VDR2B
P
Gate drive voltage regulator decoupling pin, capacitor to GND is required
35
AGND1
P
Ground
36
AGND2
P
Ground
37
VDR1A
P
Gate drive voltage regulator decoupling pin, capacitor to GND is required
38
VDR1B
P
Gate drive voltage regulator decoupling pin, capacitor to GND is required
39
BST1B
P
Bootstrap supply, external capacitor to OUT1B is required
40
PGND1B
P
Ground
41
PGND1B
P
Ground
42
OUT1B
O
Power stage PWM output 1B
Copyright ⓒ NeoFidelity, Inc.
Document Number: DS8010 Rev 1.0
Page 5
2009-10-30
Power Driver Integrated Full Digital Audio Amplifier
43
OUT1B
O
Power stage PWM output 1B
44
PVDD1B
P
Power supply for PWM Power stage 1B
45
PVDD1B
P
Power supply for PWM Power stage 1B
46
PVDD1A
P
Power supply for PWM Power stage 1A
47
PVDD1A
P
Power supply for PWM Power stage 1A
48
OUT1A
O
Power stage PWM output 1A
49
OUT1A
O
Power stage PWM output 1A
50
PGND1A
P
Ground
51
PGND1A
P
Ground
52
BST1A
P
Bootstrap supply, external capacitor to OUT1A is required
53
/RESET
I
Active low to reset NTP-8010, Schmitt trigger input
54
AD
I
I2C device address selection
55
GND_IO
P
Ground for digital interface I/O
CLK_I
I
System master clock, Schmitt trigger input
56
NTP-8010
P = Power Supply or Ground, I = Input, O = Output, I/O = Input / Output
Table 1. NTP-8010 Pin Description
Copyright ⓒ NeoFidelity, Inc.
Document Number: DS8010 Rev 1.0
Page 6
2009-10-30
Power Driver Integrated Full Digital Audio Amplifier
NTP-8010
4. CHARACTERISTICS AND SPECIFICATIONS
4.1. Absolute Maximum Ratings
Parameter
Reference
Rating
Unit
DVSS
-0.3 ~ 2.5
V
VDD_IO voltage
VSS_IO
-0.3 ~ 4.4
V
Logic Input voltage
VSS_IO
-0.3 ~ 5.5
V
Logic output voltage
VSS_IO
-0.3 ~ 4.4
V
PVDDXX voltage
PGNDXX
18.5
V
OUTXX voltage
PGNDXX
-0.3 ~ PVDDXX
V
BSTXX voltage
PGNDXX
26.5
V
VDRXX voltage
PGNDXX
8
V
Storage Temperature
Tstg
-55 ~ 150
C
Junction Temperature
Tj
150
C
Reference
Rating
Unit
DVSS
1.62 ~ 1.98
V
VDD_IO voltage
VSS_IO
3.0 ~ 3.6
V
PVDDXX voltage
PGNDXX
4.5 ~ 16
V
VDRXX voltage
PGNDXX
6
V
Tamb
-10 ~ 85
C
DVDD voltage
4.2. Recommended Operating Conditions
Parameter
DVDD voltage
Ambient Operating temperature
4.3. DC Electrical Characteristics
Parameter
Symbol
Condition
Min
Typ
Max
Unit
Logic Block (DVDD=1.8V, VDD_IO=3.3V, TA=+25C, unless otherwise specified.)
Input High Voltage
Vih
-
2.0
Input Low Voltage
Vil
-
-0.3
Threshold point
Schmitt trig. Low to High
threshold point
Schmitt trig. High to Low
threshold point
Vt
-
Vt+
-
1.4
2.0
V
Vt-
-
0.8
1.2
V
10
uA
Il
VDD_IO=MAX,
0V ≤ Vin ≤ 5.5V
40kΩ pull down
40
160
uA
40kΩ pull up
-160
-40
uA
0.4
V
Input Current
V
0.8
1.09
V
V
Output Low Voltage
Vol
Iol=2,4,…24mA
Output High Voltage
Voh
Ioh=-2,-4,…-24mA
2.4
Output Low Current
Iol
Vol=0.4V, 4mA
4.7
8.0
10
mA
Output High Current
Ioh
Voh=2.4V, 4mA
5.6
11.9
19
mA
V
Driver Block (PVDDXX=7.5V, TA=+25C, unless otherwise specified.)
OUT On Resistance
Rdson
PVDDXX=7.5V
0.4
Ω
Peak Current Limit
Thermal
Shutdown
Temperature
OCP
-
3.5
A
150
C
Copyright ⓒ NeoFidelity, Inc.
Document Number: DS8010 Rev 1.0
Page 7
2009-10-30
Power Driver Integrated Full Digital Audio Amplifier
NTP-8010
4.4. Performance Specification
Parameter
Condition
SNR
PSRR
Power
consumption
Typ
AES17, A-weighting filter
100
THD+N
Cross talk
Min
Max
Unit
dB
1W, 1kHz
0.01
%
Dolby standard
VRIPPLE=1Vrms,
Audio Input= -60dBFS
PVDD=16V, Output Power=10W@8Ω
70
dB
68
dB
TBD
W
PVDD=16V @8Ω
TBD
W
Peak Output Power
4.5. Switching Characteristics – I2C Control
Parameter
Symbol
Condition
Min
Max
Unit
-
400
kHz
I2C Control Port
SCL clock frequency
Fscl
Hold time for START condition
Thdsta
600
-
ns
Low period of the SCL clock
Tlow
1300
-
ns
High period of the SCL clock
Thigh
600
-
ns
Rise time of SDA and SCL signals
Trise
-
300
ns
Fall time of SDA and SCL signals
Tfall
-
300
ns
Tsusto
600
-
ns
Setup time for STOP condition
Trise
Tfall
SDA
Tlow
SCL
Thdsta
Thigh
Tsusto
2
Figure 3. I C Mode Timing
4.6. Switching Characteristics – Audio Interface
Parameters
Symbol
min
max
units
BCK high time
tbh
20
-
ns
BCK low time
tbl
20
-
ns
SDATA setup time before BCK rising edge
tds
10
-
ns
SDATA hold time after BCK rising edge
tdh
10
-
ns
WCK setup time before BCK rising edge
tws
20
-
ns
BCK rising edge before WCK edge
twh
20
-
ns
Copyright ⓒ NeoFidelity, Inc.
Document Number: DS8010 Rev 1.0
Page 8
2009-10-30
Power Driver Integrated Full Digital Audio Amplifier
NTP-8010
tbl
tb h
BCK
tw h
tw s
WCK
tds
tdh
S D A TA
Figure 4. Audio Interface Timing
Copyright ⓒ NeoFidelity, Inc.
Document Number: DS8010 Rev 1.0
Page 9
2009-10-30
Power Driver Integrated Full Digital Audio Amplifier
NTP-8010
5. I2C BUS OF NTP-8010
The NTP-8010 uses Inter IC Control (I2C) bus to communicate with host IC. Host IC can write or read
internal register of the NTP-8010 via I2C bus.
5.1. General Description of I2C Bus
I2C bus uses two signal lines – a serial clock line (SCL) and a serial data line (SDA). Because the SDA
line is open drain type port, both the NTP-8010 and host IC can control data signal without short-circuit.
This characteristic makes both transmitting/receiving of data and controlling of bus handshake
possible with only these two signal lines.
In I2C bus, a master device means the device which generates serial clock on the SCL. A slave device
means the device which receives serial clock. There can be many master and slave devices on an I2C
bus. But, when one master device works on the bus, the other master devices should not generate
signal on the lines. These unexpected interrupts can make other slave devices to fail to communicate
with the mater device.
The NTP-8010 supports only slave mode of I2C bus. So, the NTP-8010 always receives serial clock
from host IC. The slave mode is enough to write/read data to/from the NTP-8010.
Slave Address
R
SDA
0
1
0
1
0
1
Acknowledgment Signal
from NTP-8010
A
0
MSB
/A
LSB
W
SCL
1
2
3
4
5
6
7
8
A
9
1
S or Sr
2-8
0
Sr or P
START or Repeated
START Condition
Byte Complete
STOP or Repeated
START Condition
Figure 5. Basic signaling elements of I2C bus
If there are no communication on I2C bus, lines must keep in high state. I2C bus begins
communication with the start condition and ends communication with the stop condition. The start
condition can be generated by changing the SDA state high to low, during the SCL state remains in
high. The stop condition can be generated by changing the SDA state low to high during the SCL
remains in high state. Be aware that the stop condition always reset the internal status of I2C bus
control logic. Except these two conditions, the SDA may not change during the SCL in high state.
Otherwise, abnormal start or stop condition will be generated.
I2C bus transfers the MSB of a byte on 1st data slot and the LSB of a byte on 8th data slot. I2C bus
checks success or fail of transfer on every 1 byte transfer. The device which found an expected data
on SDA must generate acknowledgement (keep low on SDA) on 9th clock. If there is no
acknowledgement on 9th clock, the device which generated a data on SDA may stop transfer. The
NTP-8010 will generate acknowledgement for every successful data transfer of 1 byte in write mode.
But, in read mode, because data is generated by the NTP-8010, the NTP-8010 will not generate an
acknowledgement. In this case, on the contrary, the NTP-8010 will check SDA state on 9th clock that
the master device received a read data properly.
Because there can be many other slave device on the I2C bus, the master device sends a target slave
address on the 1st byte. 7 bits from 1st to 7th bit of 1st byte are used for the slave address. The NTP8010 will response with slave address 0101010 or 0101011. If the AD pin was on low state in low to
high transient of the RESET pin, the NTP-8010 will use 0101010 for a slave address. Else if the AD pin
was on high state in low to high transient of the RESET pin, the NTP-8010 will use 0101011 for a slave
address.
AD
I2C Address
0
0x54
1
0x56
2
Table 2. I C Address
Last 8th bit of the 1st byte is used to indicate whether the master device want to write or read data.
Copyright ⓒ NeoFidelity, Inc.
Document Number: DS8010 Rev 1.0
Page 10
2009-10-30
Power Driver Integrated Full Digital Audio Amplifier
NTP-8010
5.1.1. Writing Operation
When last 8th bit of the 1st byte is set to low state, the writing operation of I2C bus begins. The NTP8010 supports 3 kind of writing operations which presented on Figure 6.
The type presented on Figure 6-(a) is single byte write operation. “Sub address” on 2nd byte means
the internal register address of the NTP-8010. The “Data” on 3rd byte will be written into the internal
register address on “Sub address”. If stop condition is not generated, writing “data” on specific “sub
address” can be repeated like Figure 6-(b). “Data #n” will be written on “sub address #n”.
The type presented on Figure 6-(c) is single byte write operation under address auto increment mode.
The AIF on 1st bit of 2nd byte is the address auto increment flag. If SDA is set to high state on AIF
slots, the NTP-8010 write data continuously with register addresses which increased from initial “sub
address” for every byte; “Data #n” will be written on “sub address” + n – 1. The internal address will
cycle automatically.
(a)
S
Slave Address
W A AIF
Sub Address
A
Data
A P
Slave Address
W A AIF
Sub Address #1
A
Data #1
A AIF
Slave Address
W A AIF
Sub Address #1
A
Data #1
A
(b)
S
Sub Address #2
A
Data #2
A
P
(c)
S
Data #n
A P
Figure 6. Single Byte Write Mode Sequence
Figure 7-(a), Figure 7-(b), and Figure 7-(c) represent 4 byte writing operations. Register address
0x30~0x64 are used to configure Bi-Quad filter coefficients, ALC filter coefficients, Low Shelf BQ filter
coefficients, Loudness gains and DRC clip down gain. The data size of these coefficients and gains is
4 byte for each. So, The NTP-8010 receives 4 byte data for these 58 special addresses.
The difference between 4byte writing operation and single byte writing operation is only the size of
transferring data. So, after sending “Sub address”, 4 sequential bytes must be transferred from the
most significant byte to the least significant byte sequence. Please compare the data transfer size
between Figure 6 and Figure 7.
(a)
S
Slave Address
W A AIF
Sub Address
A
Slave Address
W A AIF
Sub Address #1
A
Data (Byte #4)
A
Data (Byte #3)
A
A
Data #1 (Byte #3)
A
Data (Byte #2)
A
Data (Byte #1)
A P
(b)
S
AIF
Sub Address #n
A
Data #n (Byte #4)
Data #1 (Byte #4)
A
Data #n (Byte #3)
A
Data #n (Byte #2)
Data #1 (Byte #2)
A
A
Data #n (Byte #1)
Data #1 (Byte #1)
A
A P
(c)
S
Slave Address
A
W A AIF
Data #n-1 (Byte #1)
Sub Address
A
A
Data #n (Byte #4)
Data #1 (Byte #4)
A
A
Data #n (Byte #3)
Data #1 (Byte #3)
A
A
Data #n (Byte #2)
Data #1 (Byte #2)
A
A
Data #n (Byte #1)
Data #1 (Byte #1)
A
A P
Figure 7. Byte Write Mode Sequences
The register addresses from 0x30 to 0x5C are used for the Bi-Quad filter coefficients. Each Bi-Quad
filter uses 5 coefficients. Any unexpected coefficient value changes on any part of 5 coefficients can
generate unstable Bi-Quad filter response. To prevent this problem, the NTP-8010 changes all of 5
coefficients simultaneously on the end of 5th coefficients download (address 0x34 or 0x39 or 0x3E or
0x43 or 0x48 or 0x4D or 0x52 or 0x57 or 0x5C).
Copyright ⓒ NeoFidelity, Inc.
Document Number: DS8010 Rev 1.0
Page 11
2009-10-30
Power Driver Integrated Full Digital Audio Amplifier
NTP-8010
5.1.2. Reading Operation
(a)
S
Slave Address
W A AIF
Sub Address
A Sr
Slave Address
R A
Data
N P
Slave Address
W A AIF
Sub Address
A Sr
Slave Address
R A
Data
A
(b)
S
Data
N P
Figure 8. Read Mode Sequence
Figure 8-(a) represents single byte reading operation from the NTP-8010. To read data from the NTP8010, generate start condition to start transfer. After then, send “slave address” with write mode flag
and send the register address to read on “sub address”. By regenerating start condition(Sr) again and
transferring “slave address” with read mode flag, reading operation begins. The NTP-8010 will
generate data on SDA signal synchronizing with serial clocks on the SCL. Because the SDA signal
generated from the NTP-8010, the master device must generate ACK on 9th slot to confirm that the
master received read 1 byte successfully. However, if this is just one byte reading operation, NAK (not
acknowledged) signal must be generated. Then stop condition must be generated to end transfer.
When AIF set to high on sub address like Figure 8-(b), data will be read continuously with register
addresses which are increased from initial “sub address” for every byte. To continue reading operation
in this case, the master must generate ACK signal on every 9th slot to confirm that master received 1
byte successfully. Otherwise, reading operation will be terminated. To end address auto incrementing
reading operation, generate NAK on 9th slot and generate stop condition.
Note) NTP-8010 does not support multi-byte reading operation.
5.1.3. I2C Glitch Filter
To clean out the threats of noise in today’s high-speed-board system, the NTP-8010 has a glitch
elimination filter on the I2C ports. Glitches in the transmission lines of the I2C port can be safely
removed with this function. Please refer to the register 0x20.
Copyright ⓒ NeoFidelity, Inc.
Document Number: DS8010 Rev 1.0
Page 12
2009-10-30
Power Driver Integrated Full Digital Audio Amplifier
NTP-8010
6. CLOCK, RESET & CONTROL
6.1. System Clock
The internal system clock of the NTP-8010 is generated from external master clock by PLL. The NTP8010 supports external master clock frequency from 2.048 MHz to 24.576MHz. For proper operation,
PLL should be set correctly according to master clock frequency (Address 0x1D).
6.2. Power On Sequence
NTP-8010 uses 1.8V for core logic blocks (DVDD) and 3.3V for I/O pads (VDD_IO). The core logic
blocks become stable state at approximately 0.6V while I/O pads become active around 2V. If VDD_IO
become more than 1.8V before DVDD become 0.6V, some unexpected pop noise can be generated
on PWM output.
In typical systems, 1.8V is generated from 3.3V power lines with typical LDO regulator. In this case,
1.8V will track the voltage of 3.3V and there will be no pop noise on PWM output.
However, in the cases of LDO regulator have UVP(under voltage protection) functions or 3.3V / 1.8V
power is generated separately, user have to give attention on power-on sequence of 1.8V and 3.3V.
3.3V
I/O supply
voltage
(VDD_IO)
1.8V
T1
0V
1.8V
core logic
supply 0.6V
voltage
(DVDD)
T2
0V
3.3V
RESET
0V
T3
CAUTION !! T2 <= T1, T3 >> 0.1uS
Figure 9. Power On Sequence
6.3. Reset
When hardware /RESET pin is set to low state, the NTP-8010 is brought into the reset state to bring
up the actions as follow.
1) Each control register resets to the default value.
2) All the internal registers, multipliers, adders, counters, and etc. are cleared to zero.
3) All of the output pins keep low state as long as the /RESET is active.
The /RESET pin should left in low sate more than 0.1usec. It takes about 7µs after reset pin is
remained low state to finish the above operations as shown in Figure 10.
>0.1usec
Reset
Copyright ⓒ NeoFidelity, Inc.
Document Number: DS8010 Rev 1.0
~7us
Initialization
Figure 10. Reset Timing
Normal Operation
Page 13
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Power Driver Integrated Full Digital Audio Amplifier
NTP-8010
7. AUDIO INPUT
7.1. I2S and Serial Audio Interface
NTP-8010 receives audio data through digital audio interface. There are 2 different formats generally
used in digital audio interface - the Inter-IC Sound (I2S) Interface and General Serial Audio Interface
(GSA). These two interfaces have some common features.
These interfaces use 2 clock lines and 1 data line to transfer audio data. One of these clock lines is the
WCK. A period of the WCK is same with sampling period of audio data. This property enables the
clock receiving device to synchronize data word-wise transmitting or receiving timing with clock
generating device. Another functional aspect of the WCK is indication of current channel. Basically, low
state of the WCK indicates 1st channel or left channel, and high state of the WCK means 2nd channel
or right channel. However, this channel definition can be changed easily by register setting.
The other clock line is BCK. This clock line used to synchronize bit-wise timing. The number of clock
for one WCK period can be selected on BCK of register address 0x01.
NTP-8010 can work as a master or a slave on bus. When NTP-8010 works as master, WCK and BCK
will be generated by NTP-8010 from internal system clock. In slave mode, NTP-8010 receives WCK
and BCK from external source. When NTP-8010 is in master mode, user has to set FSM of register
address 0x00 for proper clock frequency generation.
The name of data transfer line is SDATA. The data being synchronized with the BCK must be loaded
on this line. NTP-8010 read data on rising edge of the BCK. NTP-8010 reads data from defined bit
range of WCK period. The bit range is selected by interface type.
The bit range for I2S is predefined. GSA interface can select bit range with LRJ, MLF and BS of
register address 0x01. Please refer to Figure 11.
Copyright ⓒ NeoFidelity, Inc.
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2009-10-30
Power Driver Integrated Full Digital Audio Amplifier
NTP-8010
1/Fs
WCK (I/O)
BCK (I/O)
LEFT CHANNEL
SDATA ( I )
X
X
0
1
RIGHT CHANNEL
n-1 n
X
X
MSB
X
0
1
LSB
n-1 n
X
MSB
X
X
X
n
X
n
n-1 n
X
LSB
I2S
1/Fs
WCK (I/O)
BCK (I/O)
LEFT CHANNEL
SDATA ( I )
X
0
1
n-1 n
RIGHT CHANNEL
X
MSB
X
0
1
LSB
n-1 n
X
MSB
LSB
GSA, Left Justified, MSB first
1/Fs
WCK (I/O)
BCK (I/O)
LEFT CHANNEL
SDATA ( I )
X
0
1
RIGHT CHANNEL
n-1 n
X
LSB
X
0
1
MSB
n-1 n
X
LSB
MSB
GSA, Left Justified, LSB first
1/Fs
WCK (I/O)
BCK (I/O)
LEFT CHANNEL
SDATA ( I )
X
X
X
0
1
RIGHT CHANNEL
n-1 n
X
MSB
X
0
1
LSB
MSB
LSB
GSA, Right Justified, MSB first
1/Fs
WCK (I/O)
BCK (I/O)
LEFT CHANNEL
SDATA ( I )
X
X
X
0
1
n-1 n
LSB
RIGHT CHANNEL
X
X
MSB
0
1
n-1 n
LSB
X
MSB
GSA, Right Justified, LSB first
Figure 11. Serial audio interface format
Copyright ⓒ NeoFidelity, Inc.
Document Number: DS8010 Rev 1.0
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2009-10-30
Power Driver Integrated Full Digital Audio Amplifier
NTP-8010
8. MIXER
Channel mixer can be used in lots of application needs like pseudo stereo and etc. User can mix input
channels into each output channels with designated gains and polarity. Step size of mixer gain is
variable according to the gain level as shown below.
Volume Range (dB)
Step (dB)
+18 ~ +6
1
+5.5 ~ -5.5
0.5
-6 ~ -32
1
≤ 32
-∞
Table 3. Variable step mixing gain
In total, 4 mixing gain coefficients denoted as M00, M01, M10 and M11 are defined as shown in the
equation below. Each Mxx stores volume value in dB scale, and the number values versus gain in dB
are shown in the Appendix B. By default, each input channel connected to each output channel
directly; M00 and M11 are set as 0 dB in plus polarity, M01 and M10 are set as -∞ dB.
[Output Channels] = [Mixer Matrix] x [Input Channels]
CH1 OUT
CH2 OUT
=
M00
M01
M10
M11
.
CH1 IN
CH2 IN
Figure 12. Serial Mixer Matrix
In order to load mixer coefficients into internal memory, send the index value in the gain value table to
the register address 0x02 ~ 0x05. Each address matched to M00, M01, M10 and M11 sequentially.
Copyright ⓒ NeoFidelity, Inc.
Document Number: DS8010 Rev 1.0
Page 16
2009-10-30
Power Driver Integrated Full Digital Audio Amplifier
NTP-8010
9. PRE-PROCESSING
9.1. Adaptive Loudness Compensation
NTP-8010 supports Adaptive Loudness Compensation (ALC) function. This function makes the
identical input signal level without reducing the dynamic range.
The difference with the Dynamic Range Control (DRC) function described in Section 10.7 is as
follows; DRC sustains the signal level when volume is operating but ALC sustains the signal level
when volume is not operating – that means ALC sustains the signal level of the original input source.
Also, DRC operation is performed by peak detection scheme and ALC is performed by energy
detection scheme. ALC structure of NTP-8010 is shown in Figure 13.
Ch 1
Ch 2
Psycho-Acoustic
Compensation
Gain
Controller
Level
Detector
Figure 13. Adaptive Loudness Compensation Diagram
ALC may be used to compensate the signal level difference of different channels and different
programs in same channel in TV related product applications.
There is a Bi-Quad filter in the Psycho-Acoustic Compensation block. To download the filter
coefficients of this Bi-Quad, the five 32 bit coefficients should be downloaded to 0x58 ~ 0x5C. See the
system register Addresses 0x06~08, 0x2F, 0x58~5C in the Appendix A. The downloading method is
explained on Section 5.
9.2. Bi-Quad Filter Chain
The Bi-Quad filter means 2nd order IIR filter. NTP-8010 implemented a serial chain of Bi-Quad filters
with proprietary floating point operation schemes. The Bi-Quad filter chains can be used in various
purposes; loudness control, parametric EQ, loud-speaker EQ, DC cut and etc. The Bi-Quad filter
structure is shown in Figure 14.
b0
x
Z-1
Z-1
+
b1
a1
x
x
b2
a2
x
x
Z-1
Z-1
Figure 14. Bi-Quad Filter Structure
Copyright ⓒ NeoFidelity, Inc.
Document Number: DS8010 Rev 1.0
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Power Driver Integrated Full Digital Audio Amplifier
NTP-8010
BQ1
1
BQ2
0
1
BQ3
0
0
BQ1
1
1
BQ4
0
0
BQ2
1
BQ5
0
0
BQ3
1
0
0
BQ4
1
1
1
0
BQ5
1
L13
L12
L11
Eight Bi-Quad filters are linked serially for one channel. The Bi-Quad filters can be configured
differently for each one and for each channel. Especially for loudness control, as shown in Figure 15,
last 3 filters have different structure from first 5 filters.
BQ6
BQ7
BQ8
1
1
1
0
0
0
0
0
0
1
1
1
BQ6
BQ7
BQ8
L23
L22
L21
Figure 15. Bi-Quad Filter Chain
Filter coefficients are 32-bit floating point numbers and can be downloaded thru I2C interface. To
download Bi-Quad filter coefficients to NTP-8010, select download channel by using CH flag in register
Address 0x2F first. And then write actual coefficient values to 40 register Addresses, from 0x30 to
0x57.
Address 0x30~34 designates 1st Bi-Quad(BQ1) coefficients and means coefficients b0, b1, b2, a1, a2
in sequence. Address 0x35~39 designates 2nd Bi-Quad(BQ2), and so on. The enable/disable
operation of these Bi-Quad filters can be made by using BQF flag in register Addresses 0x2B~2E.
Address
0x2F =
0x01
Address
0x2F =
0x02
0x30 ~
0x34
0x35 ~
0x39
0x3A ~
0x3E
0x3F ~
0x43
0x44 ~
0x48
0x49 ~
0x4D
0x4E ~
0x52
0x53 ~
0x57
BQ1 of
CH1
BQ2 of
CH1
BQ3 of
CH1
BQ4 of
CH1
BQ5 of
CH1
BQ6 of
CH1
BQ7 of
CH1
BQ8 of
CH1
BQ1 of
CH2
BQ2 of
CH2
BQ3 of
CH2
BQ4 of
CH2
BQ5 of
CH2
BQ6 of
CH2
BQ7 of
CH2
BQ8 of
CH2
0x58 ~
0x5C
ALC
gain
Table 4. Bi-Quad Filter Chain
9.3. Loudness Control
NTP-8010 provides loudness control function using Bi-Quad filter chains. Loudness control means the
compensation of frequency characteristics in low volume level to fit the acoustic characteristics of
human ears.
There are 3 Bi-Quad filters for loudness gain in each channel. To download loudness gain of each BiQuad, page flag register 0x2F should be set as in the case of downloading the filter coefficients.
When the filter coefficients to download are same for each of Bi-Quad of ch1 and ch2, then user can
set the register 0x2F as 0x03
0x62
0x63
0x64
loudness gains of CH1 (0x2F = 0x01 case)
L11
L12
L13
loudness gains of CH2 (0x2F = 0x02 case)
L21
L22
L23
Table 5. Loudness Gain
Copyright ⓒ NeoFidelity, Inc.
Document Number: DS8010 Rev 1.0
Page 18
2009-10-30
Power Driver Integrated Full Digital Audio Amplifier
NTP-8010
10. VOLUME & DYNAMIC RANGE CONTROL
Master and channel volumes of the NTP-8010 are independently controlled and softly changed. The
system register Address 0x0E is the master volume control that affects all 2 channels simultaneously
and the Address 0x0F and 0x10 correspond to the channel volume control register from 1 to 2
respectively.
The possible maximum of signal boost is +48.4375dB using master volume fine control because the
master volume varies the gain of input signal independent from a channel volume, and a clipping might
occur preventing overflow error if the input signal magnitude is large enough when the combined
volume setting is higher than 0dB at the same time.
10.1. Master Volume Control
By setting volume control register (address 0x0E), master volume is controlled between -infinity and
+24dB with changing step size as follows. For details on the master volume setting, see the register
value table shown in Appendix B.
Step
Range
0.5 dB
+24 ~ -100 dB
10dB
-100 ~ -150 dB
Table 6. Level dependent master volume steps
10.2. Channel Volume Control
By setting volume control registers (address 0x0F, 0x10), channel volumes are independently
controlled between infinity and +24dB with changing step size as described below, and in the
Appendix B, exact values for channel volume setting are described.
Step
Range
0.5 dB
+24 ~ -100 dB
10dB
-100 ~ -150 dB
Table 7. Level dependent Channel volume steps
10.3. Master Volume Fine Control
Fine control for master volume is possible (+0.0625dB step up to maximum +0.4375dB boost). Refer
the system register Address 0x0D in the Appendix A.
10.4. Master Volume Override
By setting the master volume override flag on each channel, the master volume is not applied to the
configured channels. See the system register Address 0x11 in the Appendix A.
10.5. Mute and Soft Volume Change
The NTP-8010 enters mute state by setting soft mute flag of register Address 0x0B. Soft mute is
implemented so that the volume gradually increases or decreases when mute is turned off or on
respectively. Also the soft mute speed and soft volume change speed rates are programmable.
Designers can minimize the pop noise by controlling the soft mute speed and volume change intervals.
Refer SMC flag of register Address 0x0C and SVI flag of register Address 0x12.
Copyright ⓒ NeoFidelity, Inc.
Document Number: DS8010 Rev 1.0
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Power Driver Integrated Full Digital Audio Amplifier
NTP-8010
10.6. Auto Mute
The NTP-8010 can mute the sound automatically when the level of input audio signal is lower than
register controllable threshold value. The mute can be achieved with soft mute or PWM switching with
50 % duty ratio or PWM switching off.
Auto-mute is supported for internal channels 1~2 after 2x2 mixer block. Refer register Address 0x13.
10.7. Dynamic Range Control
NTP-8010 adopted a new scheme for dynamic range control, which comprises a high band DRC, a
low band DRC, and a post DRC. The input data is filtered by HPF and LPF, and then processed by HDRC and L-DRC respectively. Two processed results are merged and followed by post DRC, which
produces the output data with the fully controlled dynamic range. For detailed setting of the DRC
registers, please refer to the system register addresses in Table 8
Figure 16. Block diagram of dynamic range control.
Address
0x2F =
0x04
0x30 ~
0x34
0x35 ~
0x39
0x3A ~
0x3E
0x3F ~
0x43
0x44 ~
0x48
0x49 ~
0x4D
0x62
0x63
0x64
0x65
HPF1
of
H-DRC
HPF2 of
H-DRC
LPF1 of
L-DRC
LPF2 of
L-DRC
Att. time
control
BQ of
L-DRC
Att. Time
control
BQ of HDRC
RELEASE
_LOW
RELEAS
E_HIGH
BAND
_GAIN
_LOW
BAND_
GAIN_HI
GH
Table 8. Register map for dynamic range control
10.8. Power Meter
The power meter measures signal’s energy of internal, send value of energy through register address
0x6F and always operates without on/off control.
Because audio signals swing very rapidly in process of time, user can use power meter gain to get
stable value of energy. The more power meter gain approaches to maximum value, the more value of
energy changes slowly.
Power meter gain is 32-bit floating point numbers and can be downloaded thru I2C interface. To
download power meter gain, page flag register 0x2F should be set 0x01 or 0x02. And then write gain
value to 0x65 register address.
Copyright ⓒ NeoFidelity, Inc.
Document Number: DS8010 Rev 1.0
Page 20
2009-10-30
Power Driver Integrated Full Digital Audio Amplifier
NTP-8010
11. OUTPUT INTERFACE
11.1. Output Configuration
The output of NTP-8010 has various options. To produce proper output signal, register 0x14~0x18
should be set to appropriate values.
11.2. AM Interface Relief Mode
The NTP-8010 has AM interference reduction mode. In this mode SNR performance of NTP-8010 can
be degrade to 90 dB and the PWM switching frequency is spread to 384kHz ~ 768kHz.
11.3. PWM Output Mapper
Any internal channel that procedures PWM output can be assigned to any PWM output hardware port
(or pin) by mapping output port register. This feature is very helpful for the hardware designer because
it can relieve difficulties in the power stage signal routing and channel assignment if the output channel
order is fixed. See the system register address 0x15~0x16 in the Appendix A.
11.4. Switching Output Mode
There are two selectable switching signal output modes called AD and BD mode in NTP-8010.
The difference among these output modes is the relative signal pattern relationship between PWM
OUTxA and PWM OUTxB for the channel x.
The selection of output mode is dependent upon the topology of the output stage within NTP-8010,
and the design target and policy. AD mode can be applied to both half bridge and full bridge output
stage.
BD mode can be used for full bridge output stage only. MD flag of register address 0x18 set the output
mode.
AD Mode
BD Mode
Output A
Output B
Figure 17. PWM Output Mode
AD asynchronous pair means the normal AD mode PWM output. In other words, A output and B output
of each PWM output pair are mutually complement. In the case of AD synchronous pair, A output and
B output is perfectly identical, not in complement relation. That is useful in some special case including
single-ended power stage design.
Copyright ⓒ NeoFidelity, Inc.
Document Number: DS8010 Rev 1.0
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Power Driver Integrated Full Digital Audio Amplifier
NTP-8010
11.5. Soft start
The soft_start reduce pop noises by control rapidly increased energy of PWM.
To begin soft_start operartion PWM soft_start enable register(0x2A : PSE) shoud be set to high, and
then PWM switching on/off register(0x14 : POE) shoud be set to low. Duty rate of PWM output
increases from 127:1(Low:High) to 50:50(Low:High). Step repeat time register (0x2A : SRT) means
repeat number of PWM output in one duty sector. Soft_start operartion applied 17 repeat time is
shown in the Figure18.
HIGH
PSE
LOW
HIGH
POF
LOW
44.48us
HIGH
pwm_a
LOW
384kHz
(2.6μs)
HIGH
LOW
pwm_b
HIGH
180˚
LOW
17
17
1
20.3ns
127
(2.58us)
2
40.6ns
126
(2.56us)
Figure 18 Soft start operation timing
Copyright ⓒ NeoFidelity, Inc.
Document Number: DS8010 Rev 1.0
Page 22
2009-10-30
Power Driver Integrated Full Digital Audio Amplifier
NTP-8010
12. TYPICAL APPLICATION SCHEMATICS
Copyright ⓒ NeoFidelity, Inc.
Document Number: DS8010 Rev 1.0
Page 23
2009-10-30
Power Driver Integrated Full Digital Audio Amplifier
NTP-8010
13.APPENDIX
A. Configuration Register Summary
Addr 0x00: Audio Input Format
Bit
7
6
5
Name
X
X
X
Name
INS
Description
Input format
FSM
Sampling
Frequency
in Master mode IIS
4
Value
b’00
b’01
b’10
b’11
b’000
b’001
b’010
b’011
b’100
b’101
b’110
b’111
Description
Serial data justify
MLF
Serial bit order
BS
Serial bit size
BCKS
Bit clock size select
Value
b’0
b’1
b’0
b’1
b’00
b’01
b’10
b’11
b’00
b’01
b’10
Description
Mixer gain
[
4
Value
b’0000000
~b’1111111
Mixer_ch1_output
Mixer_ch2_output
1
0
INS
3
BS
2
Ref.
1
MLF
0
LRJ
Meaning
Left justify
Right justify
MSB first
LSB first
24 bit
20 bit
18 bit
16 bit
64 BCK/WCK
48 BCK/WCK
32 BCK/WCK
Addr 0x02~0x05: Mixer Gain
Bit
7
6
5
Name
X
Name
MG
2
Meaning
2
I S, slave mode
2
I S, master mode
General serial audio, slave mode
General serial audio, master mode
48 kHz
8 kHz
16 kHz
32 kHz
12 kHz
24 kHz
96 kHz
192 kHz
Addr 0x01: General Serial Audio Format
Bit
7
6
5
4
Name
X
X
BCKS
Name
LRJ
3
FSM
] = [
Ref.
3
2
MG
1
0
Meaning
Mixer gain (refer to gain table)
0x02
0x03
0x04
0x05
] ● [
I2S_ch1_input
I2S_ch2_input
Ref.
]
Mixer equation
[
Mixer_ch1_output
Mixer_ch2_output
] = [
0dB(0x4E)
-∞dB(0x00)
-∞dB(0x00)
0dB(0x4E)
] ● [
I2S_ch1_input
I2S_ch2_input
Reset default
Copyright ⓒ NeoFidelity, Inc.
Document Number: DS8010 Rev 1.0
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]
Power Driver Integrated Full Digital Audio Amplifier
Addr 0x06: ALC Control 0
Bit
7
6
Name
LB
5
4
NTP-8010
3
DTHR
2
Name
DTHR
Description
Don’t’ care region
THR control
Value
b’0000
~b’1010
Meaning
-120 dB ~ -60 dB with -6 dB step
LB
Lower Bound
for Up condition
relative scale
b’0000
~b’1101
0 dB ~ -12 dB with 1dB step
Addr 0x07: ALC Control 1
Bit
7
6
5
Name
X
X
APR
4
CC
Name
CC
Description
C control
Value
b’00000
~b’11111
Meaning
0 dB ~ 31 dB with 1 dB step
APR
ALC enable
b’0
b’1
ALC off
ALC on
Addr 0x08: ALC Control 2
Bit
7
6
5
Name
X
X
C
Name
A
Description
ALC attack rate
C
ALC release rate
Value
b’000
~b’111
b’000
~b’111
4
3
3
2
2
A
1
0
Ref.
1
0
Ref.
1
0
Meaning
Attack Time (See attack and release rate
tables.)
Release rate (See attack and release rate
tables.)
Ref.
Value of Compression rate :
Register time to decrease –3 dB
000
14.7 msec
001
7.3 msec
010
3.6 msec
011
1.8 msec
100
0.9 msec
101
0.4 msec
110
0.2 msec
111
0.1 msec
Table 9. ALC Attack Time Table
Value of Rising time to increase 6dB
Register fs = 96,000
011
11 sec
010
5.4 sec
001
3.6 sec
000
2.8 sec
111
1.4 sec
110
0.6 sec
101
0.4 sec
Table 10. ALC Release Rate Table
Copyright ⓒ NeoFidelity, Inc.
Document Number: DS8010 Rev 1.0
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2009-10-30
Power Driver Integrated Full Digital Audio Amplifier
Addr 0x09: DRC Control 0
Bit
7
6
5
Name
CTS
Name
CPR
Description
DRC enable
CTS
DRC threshold
Value
b’0
b’1
b’0000000
~b’1111111
Addr 0x0A: DRC Control 1
Bit
7
6
5
Name
X
X
C1C
Name
A1C
Description
DRC attack time
Value
b’000
~b’111
C1C
DRC release rate
b’000
~b’111
Value of Register
011
010
001
000
111
110
101
NTP-8010
4
3
2
1
0
CPR
Meaning
Dynamic Range Compression off
Dynamic Range Compression on
-57 ~ 12dB unsigned 7-bit DRC
threshold for 1 band mode.
In 2 band mode, it will control the
threshold of low band.
Refer to DRC threshold value table for
threshold values.
Ref.
4
0
3
2
A1C
1
Meaning
Attack time control for 1 band mode. In 2
band mode, it will control the attack time
of low band. (See attack time table
below.)
Release rate control for 1 band mode. In
2 band mode, it will control the release
rate for low band. (See release rate time
table below.)
Ref.
Attack time
24 msec
14 msec
6.4 msec
3.2 msec
1.6 msec
0.8 msec
0.4 msec
Table 11. DRC Attack Time Table
Rising rate to increase
6dB, fs = 96,000
011
2.7 sec
010
1.4 sec
001
1.0 sec
000
0.7 sec
111
0.45 sec
110
0.2 sec
101
0.12sec
100
0.035sec
Table 12. DRC Release Rate Table
Value of Register
Copyright ⓒ NeoFidelity, Inc.
Document Number: DS8010 Rev 1.0
Page 26
2009-10-30
Power Driver Integrated Full Digital Audio Amplifier
Addr 0x0B: Soft-mute Control 0
Bit
7
6
5
Name
X
X
X
Name
SMn
Description
Softmute
Description
Soft mute
speed control
4
X
Value
b’0
b’1
Addr 0x0C: Soft-mute Control 1
Bit
7
6
5
Name
X
X
X
Name
SMC
NTP-8010
Value
b’00
b’01
b’10
b’11
4
X
Description
Master volume
fine control
Value
b’000
~b’111
Description
Volume control
Name
MVOn
Description
Value
Master
volume b’0
override on/off
b’1
Addr 0x12: Soft Volume Control
Bit
7
6
5
Name
X
X
X
Name
SVI
Description
Soft volume change
Change
Copyright ⓒ NeoFidelity, Inc.
Document Number: DS8010 Rev 1.0
Value
b’00
b’01
b’10
b’11
0
SM1
Ref.
3
X
0
2
X
1
SMC
3
X
2
MVFC
Ref.
1
0
Meaning
0 dB ~ 0.5 dB with 0.0625 dB step
Value
b’00000000
~b’11111111
Addr 0x11: Master Volume Override
Bit
7
6
5
Name
X
X
X
1
SM2
Meaning
increase for channel n
decrease for channel n
Addr 0x0E~0x10: Master Volume & CH 1/2 Volume
Bit
7
6
5
4
Name
VOL
Name
VOL
2
X
Meaning
42 / 46msec(at 96 / 88.2kHz)
85 / 92msec
21 / 23msec
0 msec(Hard change)
Addr 0x0D: Master Volume Fine Control
Bit
7
6
5
4
Name
X
X
X
X
Name
MVFC
3
X
4
X
3
2
Ref.
1
0
Meaning
See volume control register tables.
Reset default is 0 (0x00) ( = − dB)for
Master and 207 (0xCF) for Channel
3
X
2
X
1
MVO2
Ref.
0
MVO1
Meaning
Master volume is effective for channel n
Master volume is ineffective for channel n
Ref.
4
X
0
3
X
2
X
Meaning
Medium speed
High speed
Low speed
soft volume change disable
1
SVI
Ref.
Page 27
2009-10-30
Power Driver Integrated Full Digital Audio Amplifier
NTP-8010
Addr 0x13: Auto-mute Control
Bit
7
6
5
Name
EAMC
II
4
Name
Meaning
AT
II
EAMC
Description
Auto-mute
detection threshold
Auto-mute
response time
Effect of Auto-mute
condition
Value
b’0000
~b’1111
b’00
b’01
b’10
b’11
b’00
b’01
b’10
b’11
Description
Switching output
On/off control
Value
b’0
b’1
OPM1B
Description
Value
b’00
Select source
channel for PWM b’01
output port 1A
b’10
b’11
Select source
b’00
channel for PWM b’01
output port 1B
b’10
b’11
Description
Select source
channel for
PWM output port 2A
OPM2B
Select source
channel for
PWM output port 2B
Copyright ⓒ NeoFidelity, Inc.
Document Number: DS8010 Rev 1.0
Value
b’00
b’01
b’10
b’11
b’00
b’01
b’10
b’11
0
5 msec
50 msec
500 sec
2 sec
Auto mute disable(No-Effect)
Channel Soft Mute
Continue switching if auto-mute
Stop switching if auto-mute
3
X
2
X
1
POF2
0
POF1
Meaning
Channel n PWM switching on
Channel n PWM switching off
2
Ref.
1
OPM1A
Meaning
PWM1A is connected to PWM port 1A
PWM1B is connected to PWM port 1A
PWM2A is connected to PWM port 1A
PWM2B is connected to PWM port 1A
PWM1A is connected to PWM port 1B
PWM1B is connected to PWM port 1B
PWM2A is connected to PWM port 1B
PWM2B is connected to PWM port 1B
Addr 0x16: PWM Output Port Control for PWM 2A&2B
Bit
7
6
5
4
3
Name
X
X
X
X
OPM2B
Name
OPM2A
1
Ref.
Addr 0x15: PWM Output Port Control for PWM 1A&1B
Bit
7
6
5
4
3
Name
X
X
X
X
OPM1B
Name
OPM1A
2
Unsigned integer between 0 and 15
Addr 0x14: PWM Switching On/Off Control
Bit
7
6
5
4
Name
X
X
X
X
Name
POFn
3
AT
2
Ref.
1
OPM2A
Meaning
PWM1A is connected to PWM port 2A
PWM1B is connected to PWM port 2A
PWM2A is connected to PWM port 2A
PWM2B is connected to PWM port 2A
PWM1A is connected to PWM port 2B
PWM1B is connected to PWM port 2B
PWM2A is connected to PWM port 2B
PWM2B is connected to PWM port 2B
0
0
Ref.
Page 28
2009-10-30
Power Driver Integrated Full Digital Audio Amplifier
NTP-8010
Addr 0x17: Prescaler Value Control
Bit
7
6
5
Name
PS
4
Name
PS
Meaning
208 (0xD0)default
Description
Prescaler value
Value
b’00000000
~b’11111111
Addr 0x18: Miscellaneous PWM Control
Bit
7
6
5
4
Name
X
X
X
X
Name
MD
Description
PWM output mode
AHL
A-out state
When switching off
B-out state
when switching off
3
BHL
2
1
0
Ref.
2
AHL
1
MD
0
Meaning
AD mode with asynchronous signal pair
AD mode with synchronous signal pair
BD mode
AM Interference mode
Low
High
Low
High
Ref.
Addr 0x19: PWM_MASK Control 0
Bit
7
6
5
Name
X
X
X
4
X
0
Name
PWMM
Description
PWM
register
Meaning
PWM MASK output is low. (reset default)
FPMLD
Permanent
PWM_MASK
Low disable flag
FAULT disable
BHL
SRD
Value
b’00
b’01
b’10
b’11
b’0
b’1
b’0
b’1
3
Value
MASK b’10
otherwise
b’0
b’1
b’0
b’1
3
SRD
2
FPMLD
1
PWMM
Ref.
PWM MASK output is high.
No effect
Reset the
auto_PWM_MASK_restore_counter to 0
FAULT is effect for PROTECT
FAULT is ineffective for PROTECT
Addr 0x1A ~ 0x1B : Reserved
Copyright ⓒ NeoFidelity, Inc.
Document Number: DS8010 Rev 1.0
Page 29
2009-10-30
Power Driver Integrated Full Digital Audio Amplifier
Addr 0x1C: PWM_MASK Control 3
Bit
7
6
5
Name
IR
AVRCT
Name
PHT
Description
PWM_MASK Low
Hold Time
AVRCT
Auto PWM_MASK
Restore Counter
Threshold
IRC
Auto PWM_MASK
Restore
Interval
Ratio Control
Value
b’000
b’001
b’010
b’011
b’100
b’101
b’000
b’001
b’010
b’011
b’100
b’101
b’110
b’111
b’00
b’01
NTP-8010
4
Description
Master
Frequency
Clock
2
PHT
1
Meaning
0.5 msec Hold Time
1 msec Hold Time
2 msec Hold Time
4 msec Hold Time (Default)
8 msec Hold Time
16msec Hold Time
2
5 (Default)
10
15
20
25
30
Infinity
2 (Default)
4
Addr 0x1D: Master Clock Frequency Control
Bit
7
6
5
4
Name
X
X
X
X
Name
MCF
3
3
X
2
X
Ref.
1
MCF
Value
b’00
Meaning
12.288 MHz
b’01
b’10
b’11
24.576 MHz
18.432 MHz
User defined frequency. Required to set
address 0x1E and address 0x1F first
Master Clock Frequency
Address 0x1E
2.048MHz
0x80
3.072 MHz
0x80
4.096 MHz
0x80
6.144 MHz
0x80
8.192MHz
0xC0
16.384MHz
0xC0
Table 13. User defined master clock frequency
0
0
Ref.
Address 0x1F
0x5E
0x3E
0x2E
0x1E
0x2E
0x16
Caution 1) Register values different from those on the table are forbidden.
Caution 2) Writing values on Address 0x1E and 0x1F with MCF user defined frequency mode can
make system unstable. Address 0x1E and 0x1F must be configured before MCF is set as user defined
frequency.
Copyright ⓒ NeoFidelity, Inc.
Document Number: DS8010 Rev 1.0
Page 30
2009-10-30
Power Driver Integrated Full Digital Audio Amplifier
Addr 0x20: I2C Glitch filter
Bit
7
6
5
Name
DUR
Name
GFO
DUR
Description
Glitch filter
enable/disable
glitch width
NTP-8010
4
Value
b’0
b’1
b’0000000
~b’1111111
3
2
1
0
GFO
Meaning
Glitch filter on
Bypass
minimum pulse width = DUR * 20 ns
reset default = 16 * 20 ns (DUR default =
b’0001111)
Ref.
Addr 0x21: Reserved
Addr 0x22: ALC Control 3
Bit
7
6
Name
X
X
Name
ABE
Description
ABS enable
5
X
4
X
Value
b’0
b’1
Meaning
Disable ABS multiplier on ALC
Enable ABS multiplier on ALC
Addr 0x23: DRC Control 2
Bit
7
6
5
Name
X
X
BM
Name
CAS
Description
QMF mode / BQ
mode select
Threshold
parameter select bit
Value
b’0
b’1
b’0
b’1
RSB
Release parameter
select bit
b’0
b’1
ASB
Attack
parameter
select bit
b’0
b’1
BM
Band mode enable
b’0
b’1
TSB
4
ASB
3
X
3
RSB
2
X
2
TSB
1
X
0
ABE
Ref.
1
CAS
0
X
Meaning
QMF mode
BQ mode
Uses Threshold parameters in Table
Uses Threshold parameters from external
loading
Uses Release parameters in Table
Uses Release parameters from external
loading
Uses Attack parameters in Table
Uses Attack parameters from external
loading
Band mode 1
Band mode 2
Ref.
Addr 0x24: Reserved
Copyright ⓒ NeoFidelity, Inc.
Document Number: DS8010 Rev 1.0
Page 31
2009-10-30
Power Driver Integrated Full Digital Audio Amplifier
NTP-8010
Addr 0x25: DRC Control 0_H
Bit
7
6
5
Name
CTS_H
Name
CPR_H
CTS_H
Description
DRC enable for
high band
DRC threshold for
high band
4
Value
b’0
b’1
b’0000000
~
b’1111111
Addr 0x26: DRC Control 1_H
Bit
7
6
5
Name
X
X
C1C_H
Name
A1C_H
Description
DRC attack time
(high band)
Value
b’000
b’111
C1C_H
DRC release time
(high band)
b’000
b’111
Addr 0x27: DRC Control 3
Bit
7
6
Name
X
X
Name
DLL
Description
Delay line length
CTS_3
Description
DRC enable for
post-band
DRC threshold for
post- band
C1C_3
Description
DRC attack time
(post-DRC)
DRC release time
(post-DRC)
Copyright ⓒ NeoFidelity, Inc.
Document Number: DS8010 Rev 1.0
3
1
2
A1C_H
0
CPR_H
1
0
Meaning
~ Attack time control for high band.
It has effect only in band mode 2.
(See attack time table in Addr 0x0A)
~ Release time control for High band.
It has effect only in band mode 2.
(See Release rate table in Addr 0x0A)
5
X
4
DLL
Value
b’00000~
b’10100
Meaning
Delay line length. 0~20(decimal)
4
Value
b’0
b’1
b’0000000
~
b’1111111
Addr 0x29 : DRC Control 1_3
Bit
7
6
5
Name
X
X
C1C_3
Name
A1C_3
2
Meaning
Ref.
Dynamic Range Compression off
Dynamic Range Compression on
-57 ~ 12dB unsigned 7-bit DRC threshold
for high band.
It has effect only in band mode 2.
Refer to DRC threshold value table for
threshold values.
4
Addr 0x28: DRC Control0_3
Bit
7
6
5
Name
CTS_3
Name
CPR_3
3
3
3
2
2
Ref.
1
0
Ref.
1
0
CPR_3
Meaning
Dynamic Range Compression off
Dynamic Range Compression on
-57 ~ 12dB unsigned 7-bit DRC threshold
Refer to DRC threshold value table.
4
3
Value
Meaning
b’000 ~ Attack time
b’111
b’000 ~ Release rate
b’111
2
A1C_3
1
Ref.
0
Ref.
Page 32
2009-10-30
Power Driver Integrated Full Digital Audio Amplifier
Address 0x2A: PWM Soft start
Bit
7
6
5
Name
PSE
SRT
Name
PSE
SRT
Description
PWM soft start
Enable
Step Repeat Time
Value
b’0
b’1
b’000000
~
b’111111
NTP-8010
4
3
BQ2
BQ3
BQ4
BQ5
Description
On/off Bi-Quad 1
of ch. n (= ch. 1,2)
On/off Bi-Quad 2
of ch. n (= ch. 1,2)
On/off Bi-Quad 3
of ch. n (= ch. 1,2)
On/off Bi-Quad 4
of ch. n (= ch. 1,2)
On/off Bi-Quad 5
of ch. n (= ch. 1,2)
Value
b’0
b’1
b’0
b’1
b’0
b’1
b’0
b’1
b’0
b’1
2
BQ3
Description
On/off Bi-Quad 6
of ch. n (= ch. 1,2)
BQ7
On/off Bi-Quad 7
of ch. n (= ch. 1,2)
BQ8
On/off Bi-Quad 8
of ch. n (= ch. 1,2)
Value
b’00
b’01
b’10
b’00
b’01
b’10
b’00
b’01
b’10
CH2
DRC
Description
Coefficient write
enable/disable for
ch1
Coefficient write
enable/disable for
ch2
Coefficient write
enable/disable for
Enhance DRC
Copyright ⓒ NeoFidelity, Inc.
Document Number: DS8010 Rev 1.0
1
BQ2
2
DRC
Ref.
1
0
BQ6
Ref.
1
CH2
0
CH1
Value
b’0
b’1
Meaning
Disable coefficient write for ch1
Enable coefficient write for ch1
b’0
b’1
Disable coefficient write for ch2
Enable coefficient write for ch2
b’0
Disable coefficient write for Enhanced
DRC
Enable coefficient write for Enhanced DRC
b’1
Ref.
0
BQ1
Meaning
Bypass Bi-Quad 6 of channel n
Enable Bi-Quad 6 of channel n
Enable Bi-Quad 6 as Loudness Filter
Bypass Bi-Quad 7 of channel n
Enable Bi-Quad 7 of channel n
Enable Bi-Quad 7 as Loudness Filter
Bypass Bi-Quad 8 of channel n
Enable Bi-Quad 8 of channel n
Enable Bi-Quad 8 as Loudness Filter
Addr 0x2F: Bi-Quad Filter Control 2 for CH1/CH2
Bit
7
6
5
4
3
Name
X
X
X
X
X
Name
CH1
0
Meaning
Bypass Bi-Quad 1 of channel n
Enable Bi-Quad 1 of channel n
Bypass Bi-Quad 2 of channel n
Enable Bi-Quad 2 of channel n
Bypass Bi-Quad 3 of channel n
Enable Bi-Quad 3 of channel n
Bypass Bi-Quad 4 of channel n
Enable Bi-Quad 4 of channel n
Bypass Bi-Quad 5 of channel n
Enable Bi-Quad 5 of channel n
Addr 0x2D~0x2E: Bi-Quad Filter Control 1 for CH1/CH2
Bit
7
6
5
4
3
2
Name
X
BQ8
BQ7
Name
BQ6
1
Meaning
Disable
Enable (Default)
The repeat time of each step (default : 16
– means repeat 17 times)
Addr 0x2B~0x2C: Bi-Quad Filter Control 0 for CH1/CH2
Bit
7
6
5
4
3
Name
X
X
X
BQ5
BQ4
Name
BQ1
2
Ref.
address
0x30
~0x65
one time,
one
channel
address
0x30~0x65
Page 33
2009-10-30
Power Driver Integrated Full Digital Audio Amplifier
NTP-8010
Addr 0x30~0x57: Bi-Quad Filter Coefficient of Ch 1&2, DRC_QMF_BQ, ATTACK_LOW,
ATTACK_HIGH
Addr 0x58~0x5C: ALC Filter Coefficient
32-bit floating point
Addr 0x5D~0x61: reserved
32-bit floating point
Addr 0x62~0x64: Loudness Gain for BQ 6,7,8 of Ch 1& 2, RELEASE_LOW, RELEASE_HIGH,
BAND_GAIN_LOW
32-bit floating point
Addr 0x65: BAND_GAIN_HIGH, Power Meter Gain
32-bit floating point
Addr 0x67: Modulation Index & NS-Type Control
Bit
7
6
5
4
3
Name
X
X
X
M0
Name
MD12
0
Ref.
Addr 0x68: PWM Control 6
Bit
7
6
5
Name
ARED
4
0
Name
ARED
Meaning
0 default
M0
Description
Aout Rising Edge
Delay
Value
b’11
b’10
b’01
b’00
b’0
b’1
b’00
b’01
b’10
b’11
1
MD12
Meaning
Minimum pulse width = 2
Minimum pulse width = 4
Minimum pulse width = 6
Minimum pulse width = 8
Type 1
Type 2
No left shift on dither value = Dither off
1bit left shift on dither value
2bit left shift on dither value
3bit left shift on dither value
NT
Description
Modulation index
control by Minimum
pulse width for Ch
1&2
Noise shaping Type
for Ch 1&2
Dither Position
Selector
2
NT
Value
unsigned
Addr 0x69: PWM Control 7
Bit
7
6
5
Name
AFED
4
Name
AFED
Meaning
0 default
Description
Aout Falling Edge
Delay
Value
unsigned
Addr 0x6A: PWM Control 8
Bit
7
6
5
Name
BRED
4
Name
BRED
Meaning
0 default
Description
Bout Rising Edge
Delay
Value
unsigned
Addr 0x6B: PWM Control 9
Bit
7
6
5
Copyright ⓒ NeoFidelity, Inc.
Document Number: DS8010 Rev 1.0
4
3
2
1
Ref.
3
2
1
0
Ref.
3
2
1
0
Ref.
3
2
1
0
Page 34
2009-10-30
Power Driver Integrated Full Digital Audio Amplifier
Name
BFED
Name
BFED
Description
Bout falling Edge
Delay
Value
unsigned
NTP-8010
Meaning
0 default
Ref.
Addr 0x6C~0x6E: Reserved
Addr 0x6F: Power Meter (read-only)
Bit
7
6
5
Name
PSE
SRT
Name
PSE
SRT
Description
PWM soft start
Enable
Step Repeat Time
Value
b’0
b’1
b’000000
~
b’111111
4
ULCK
LSRC
MPW
FSI
Description
Permanent
PWM_MASK
Indication flag
Sampled PLL
Unlock error
ASRC lock status
MCK/WCK
Ratio error
Sampling
Frequency
Information
Value
b’0
b’1
b’0
b’1
b’0
b’1
b’0
b’1
b’0000
b’0001
b’0010
b’0011
b’0100
b’0101
b’0110
b’0111
b’1000
b’1001
b’1010
b’1011
2
1
0
Meaning
Disable
Enable (Default)
The repeat time of each step (default : 16
– means repeat 17 times)
Addr 0x70: System Error Status (Read-only)
Bit
7
6
5
4
Name
FSI
Name
PPM
3
3
MPW
2
LSRC
Meaning
1
ULCK
Ref.
0
PPM
Ref.
Indicated that PWM_MASK is
in Permanent LOW state
PLL is locked state
PLL is unlocked state
ASRC is unlocked state.
ASRC is locked state.
Ratio is incorrect
Ratio is correct
8kHz
11.025kHz
12kHz
16kHz
22.05kHz
24 kHz
32 kHz
44.1 kHz
48 kHz
88.2 kHz
96 kHz
192 kHz
Addr 0x7F: Chip ID 0x8A
Copyright ⓒ NeoFidelity, Inc.
Document Number: DS8010 Rev 1.0
Page 35
2009-10-30
Power Driver Integrated Full Digital Audio Amplifier
NTP-8010
B. Configuration Resister Value Reference
Master & Channel Volume
Index
FF
FE
FD
FC
FB
FA
F9
F8
F7
F6
F5
F4
F3
F2
F1
F0
EF
EE
ED
EC
EB
EA
E9
E8
E7
E6
E5
E4
E3
E2
E1
E0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
dB
24
23.5
23
22.5
22
21.5
21
20.5
20
19.5
19
18.5
18
17.5
17
16.5
16
15.5
15
14.5
14
13.5
13
12.5
12
11.5
11
10.5
10
9.5
9
8.5
8
7.5
7
6.5
6
5.5
5
4.5
4
3.5
3
Index
D4
D3
D2
D1
D0
CF
CE
CD
CC
CB
CA
C9
C8
C7
C6
C5
C4
C3
C2
C1
C0
BF
BE
BD
BC
BB
BA
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
AF
AE
AD
AC
AB
AA
dB
2.5
2
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
-3
-3.5
-4
-4.5
-5
-5.5
-6
-6.5
-7
-7.5
-8
-8.5
-9
-9.5
-10
-10.5
-11
-11.5
-12
-12.5
-13
-13.5
-14
-14.5
-15
-15.5
-16
-16.5
-17
-17.5
-18
-18.5
Copyright ⓒ NeoFidelity, Inc.
Document Number: DS8010 Rev 1.0
Index
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
9F
9E
9D
9C
9B
9A
99
98
97
96
95
94
93
92
91
90
8F
8E
8D
8C
8B
8A
89
88
87
86
85
84
83
82
81
80
7F
dB
-19
-19.5
-20
-20.5
-21
-21.5
-22
-22.5
-23
-23.5
-24
-24.5
-25
-25.5
-26
-26.5
-27
-27.5
-28
-28.5
-29
-29.5
-30
-30.5
-31
-31.5
-32
-32.5
-33
-33.5
-34
-34.5
-35
-35.5
-36
-36.5
-37
-37.5
-38
-38.5
-39
-39.5
-40
Index
7E
7D
7C
7B
7A
79
78
77
76
75
74
73
72
71
70
6F
6E
6D
6C
6B
6A
69
68
67
66
65
64
63
62
61
60
5F
5E
5D
5C
5B
5A
59
58
57
56
55
54
dB
-40.5
-41
-41.5
-42
-42.5
-43
-43.5
-44
-44.5
-45
-45.5
-46
-46.5
-47
-47.5
-48
-48.5
-49
-49.5
-50
-50.5
-51
-51.5
-52
-52.5
-53
-53.5
-54
-54.5
-55
-55.5
-56
-56.5
-57
-57.5
-58
-58.5
-59
-59.5
-60
-60.5
-61
-61.5
Index
53
52
51
50
4F
4E
4D
4C
4B
4A
49
48
47
46
45
44
43
42
41
40
3F
3E
3D
3C
3B
3A
39
38
37
36
35
34
33
32
31
30
2F
2E
2D
2C
2B
2A
29
dB
-62
-62.5
-63
-63.5
-64
-64.5
-65
-65.5
-66
-66.5
-67
-67.5
-68
-68.5
-69
-69.5
-70
-70.5
-71
-71.5
-72
-72.5
-73
-73.5
-74
-74.5
-75
-75.5
-76
-76.5
-77
-77.5
-78
-78.5
-79
-79.5
-80
-80.5
-81
-81.5
-82
-82.5
-83
Index
28
27
26
25
24
23
22
21
20
1F
1E
1D
1C
1B
1A
19
18
17
16
15
14
13
12
11
10
0F
0E
0D
0C
0B
0A
9
8
7
6
5
4
3
2
1
0
dB
-83.5
-84
-84.5
-85
-85.5
-86
-86.5
-87
-87.5
-88
-88.5
-89
-89.5
-90
-90.5
-91
-91.5
-92
-92.5
-93
-93.5
-94
-94.5
-95
-95.5
-96
-96.5
-97
-97.5
-98
-98.5
-99
-99.5
-100
-110
-120
-130
-140
-150
-150
-150
Page 36
2009-10-30
Power Driver Integrated Full Digital Audio Amplifier
NTP-8010
Mixer Gain & Polarity
Index
Polarity
dB
Index
Polarity
dB
Index
Polarity
dB
Index
Polarity
dB
7E
+
18
7D
-
18
3E
+
-4
3D
-
-4
7C
+
17
7B
-
17
3C
+
-4.5
3B
-
-4.5
7A
+
16
79
-
16
3A
+
-5
39
-
-5
78
+
15
77
-
15
38
+
-5.5
37
-
-5.5
76
+
14
75
-
14
36
+
-6
35
-
-6
74
+
13
73
-
13
34
+
-7
33
-
-7
72
+
12
71
-
12
32
+
-8
31
-
-8
70
+
11
6F
-
11
30
+
-9
2F
-
-9
6E
+
10
6D
-
10
2E
+
-10
2D
-
-10
6C
+
9
6B
-
9
2C
+
-11
2B
-
-11
6A
+
8
69
-
8
2A
+
-12
29
-
-12
68
+
7
67
-
7
28
+
-13
27
-
-13
66
+
6
65
-
6
26
+
-14
25
-
-14
64
+
5.5
63
-
5.5
24
+
-15
23
-
-15
62
+
5
61
-
5
22
+
-16
21
-
-16
60
+
4.5
5F
-
4.5
20
+
-17
1F
-
-17
5E
+
4
5D
-
4
1E
+
-18
1D
-
-18
5C
+
3.5
5B
-
3.5
1C
+
-19
1B
-
-19
5A
+
3
59
-
3
1A
+
-20
19
-
-20
58
+
2.5
57
-
2.5
18
+
-21
17
-
-21
56
+
2
55
-
2
16
+
-22
15
-
-22
54
+
1.5
53
-
1.5
14
+
-23
13
-
-23
52
+
1
51
-
1
12
+
-24
11
-
-24
50
+
0.5
4F
-
0.5
10
+
-25
0F
-
-25
4E
+
0
4D
-
0
0E
+
-26
0D
-
-26
4C
+
-0.5
4B
-
-0.5
0C
+
-27
0B
-
-27
4A
+
-1
49
-
-1
0A
+
-28
09
-
-28
48
+
-1.5
47
-
-1.5
08
+
-29
07
-
-29
46
+
-2
45
-
-2
06
+
-30
05
-
-30
44
+
-2.5
43
-
-2.5
04
+
-31
03
-
-31
42
+
-3
41
-
-3
02
+
-32
01
-
-32
40
+
-3.5
3F
-
-3.5
00
+
-150
Copyright ⓒ NeoFidelity, Inc.
Document Number: DS8010 Rev 1.0
Page 37
2009-10-30
Power Driver Integrated Full Digital Audio Amplifier
NTP-8010
Dynamic Range Control Threshold
dB
Value
dB
Value
dB
Value
dB
Value
-57
FF
-5.5
BF
-2.3
7F
0.9
3F
-54
FD
-5.4
BD
-2.2
7D
1
3D
-51
FB
-5.3
BB
-2.1
7B
1.25
3B
-48
F9
-5.2
B9
-2
79
1.5
39
-45
F7
-5.1
B7
-1.9
77
1.75
37
-42
F5
-5
B5
-1.8
75
2
35
-39
F3
-4.9
B3
-1.7
73
2.25
33
-36
F1
-4.8
B1
-1.6
71
2.5
31
-33
EF
-4.7
AF
-1.5
6F
2.75
2F
-30
ED
-4.6
AD
-1.4
6D
3
2D
-27
EB
-4.5
AB
-1.3
6B
3.25
2B
-24
E9
-4.4
A9
-1.2
69
3.5
29
-21
E7
-4.3
A7
-1.1
67
3.75
27
-18
E5
-4.2
A5
-1
65
4
25
-15
E3
-4.1
A3
-0.9
63
4.25
23
-12
E1
-4
A1
-0.8
61
4.5
21
-11.5
DF
-3.9
9F
-0.7
5F
4.75
1F
-11
DD
-3.8
9D
-0.6
5D
5
1D
-10.5
DB
-3.7
9B
-0.5
5B
5.5
1B
-10
D9
-3.6
99
-0.4
59
6
19
-9.5
D7
-3.5
97
-0.3
57
6.5
17
-9
D5
-3.4
95
-0.2
55
7
15
-8.5
D3
-3.3
93
-0.1
53
7.5
13
-8
D1
-3.2
91
0
51
8
11
-7.5
CF
-3.1
8F
0.1
4F
8.5
0F
-7
CD
-3
8D
0.2
4D
9
0D
-6.5
CB
-2.9
8B
0.3
4B
9.5
0B
-6
C9
-2.8
89
0.4
49
10
09
-5.9
C7
-2.7
87
0.5
47
10.5
07
-5.8
C5
-2.6
85
0.6
45
11
05
-5.7
C3
-2.5
83
0.7
43
11.5
03
-5.6
C1
-2.4
81
0.8
41
12
01
※ CPR bit = 1
Copyright ⓒ NeoFidelity, Inc.
Document Number: DS8010 Rev 1.0
Page 38
2009-10-30
Power Driver Integrated Full Digital Audio Amplifier
NTP-8010
Auto Mute Detection Threshold Table
Name
AT
Description
Auto-mute
Detection
threshold
Value
dB
0000
-126
0001
-120
0010
-114
0011
-108
0100
-102
0101
-96
0110
-90
0111
-84
1000
-78
1001
-72
1010
-66
1011
-60
1100
-54
1101
-48
1110
-42
1111
Auto-mute
※ Do not use value 1111.
Copyright ⓒ NeoFidelity, Inc.
Document Number: DS8010 Rev 1.0
Page 39
2009-10-30
Power Driver Integrated Full Digital Audio Amplifier
NTP-8010
C. Outline and Mechanical Data
Copyright ⓒ NeoFidelity, Inc.
Document Number: DS8010 Rev 1.0
Page 40
2009-10-30
Power Driver Integrated Full Digital Audio Amplifier
Copyright ⓒ NeoFidelity, Inc.
Document Number: DS8010 Rev 1.0
NTP-8010
Page 41
2009-10-30