ETC DS3232M

19-6247; Rev 0; 3/12
DS3232M
±5ppm、内置SRAM的I2C实时时钟
概述
特性
DS3232M是低成本、超高精度I2C实时时钟(RTC)，带有
236字节电池备份SRAM。该器件集成了电池输入，当器件
主电源断电时可保持精确计时。集成微机电系统(MEMS)
振荡电路保持器件的长期精确度，并减少了生产线的元件
数量。
S-40°C至+85°C温度范围内，计时精度保持在±5ppm
(±0.432秒/天)
RTC提供秒、分、时、星期、日期、月和年信息。少于31
天的月份，自动调整月末日期，包括闰年修正。时钟格式
可以是24小时或带AM/PM指示的12小时格式。提供两个
可设置的日历闹钟和一路1Hz输出。地址与数据通过I2C双
向总线串口传输。高精度、经过温度补偿的电压基准和比
较器电路用来监测VCC状态，检测电源故障，提供复位输
出，并在必要时自动切换到备份电源。另外，RST监测引
脚可以作为产生微处理器复位的按键输入，详细信息请参
考方框图 。
S低功耗
应用
S236字节电池备份用户SRAM
S为连续计时提供电池备份
S功能兼容于DS3232
S完整的时钟日历，包括秒、分、时、星期、日期、月和
年，并提供有效期到2100年的闰年补偿
S两个日历闹钟
S1Hz和32.768kHz输出
S复位输出和按键去抖输入
S高速(400kHz) I2C兼容串行总线
S+2.3V至+4.5V电源电压
S精度为±3°C的数字温度传感器
电表
S-40°C至+85°C工作温度范围
工业应用
S8引脚SO (150 mil)封装
S通过美国保险商实验室协会(UL)认证
定购信息在数据资料的最后给出。
典型工作电路
VCC
VCC
SCL
I/O PORT
SDA
DS3232M
INT/SQW
32KHZ
INTERRUPTS
CPU
PUSHBUTTON
RESET
RST
VBAT
相关型号以及配合该器件使用的推荐产品，请参见：china.maxim-ic.com/DS3232M.related。
注意：该器件某些版本的规格可能与发布的规格不同，会以勘误表的形式给出。通过不同销售渠道可能同时获得器件的多个版本。欲了解器件勘误表信
息，请点击：china.maxim-ic.com/errata。
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本文是英文数据资料的译文，文中可能存在翻译上的不准确或错误。如需进一步确认，请在您的设计中参考英文资料。
有关价格、供货及订购信息，请联络Maxim亚洲销售中心：10800 852 1249 (北中国区)，10800 152 1249 (南中国区)，
或访问Maxim的中文网站：china.maxim-ic.com。
DS3232M
±5ppm、内置SRAM的I2C实时时钟
Absolute Maximum Ratings
Lead Temperature (soldering, 10s).................................+260NC
Soldering Temperature (reflow).......................................+260NC
Voltage Range on Any Pin Relative to GND.........-0.3V to +6.0V
Operating Temperature Range........................... -40NC to +85NC
Storage Temperature Range............................. -55NC to +125NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
(TA = -40NC to +85NC, unless otherwise noted.) (Note 1)
PARAMETER
MIN
TYP
MAX
VCC
2.3
3.3
4.5
VBAT
2.3
3.0
4.5
Logic 1
VIH
0.7 x
VCC
VCC +
0.3
V
Logic 0
VIL
-0.3
0.3 x
VCC
V
Supply Voltage
SYMBOL
CONDITIONS
UNITS
V
Electrical Characteristics—Frequency and Timekeeping
(VCC or VBAT = +3.3V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = +3.3V, VBAT = +3.0V, and
TA = +25NC, unless otherwise noted.) (Note 1)
PARAMETER
1Hz Frequency Tolerance
SYMBOL
Df/fOUT
CONDITIONS
MIN
TYP
Measured over R 10s interval
MAX
UNITS
Q5
ppm
1Hz Frequency Stability vs. VCC
Voltage
Df/V
Timekeeping Accuracy
tKA
Q0.432
Seconds/
Day
Df/fOUT
Q2.5
%
32kHz Frequency Tolerance
ppm/V
Q1
DC Electrical Characteristics—General
(VCC = +2.3V to +4.5V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = +3.3V, VBAT = +3.0V, and
TA = +25NC, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Active Supply Current
(I2C Active)
ICCA
(Note 2)
125
250
µA
Standby Supply Current
(I2C Inactive)
ICCS
(Notes 2, 3)
100
175
µA
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DS3232M
±5ppm、内置SRAM的I2C实时时钟
DC Electrical Characteristics—General (continued)
(VCC = +2.3V to +4.5V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = +3.3V, VBAT = +3.0V, and
TA = +25NC, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
Temperature Conversion Current
(I2C Inactive)
ICCSCONV
CONDITIONS
MIN
2.45
TYP
MAX
UNITS
200
350
µA
2.575
2.70
V
Power-Fail Voltage
VPF
Logic 0 Output
(32KHZ, INT/SQW, SDA)
VOL
IOL = 3mA
0.4
V
Logic 0 Output (RST)
VOL
IOL = 1mA
0.4
V
Logic 1 Output (32KHZ)
VOH
Active supply > 3.3V, IOH = -1mA
2.0
Active supply > 2.7V, IOH = -0.75mA
Active supply > 2.3V, IOH = -0.14mA
2.0
V
2.0
Output Leakage
(32KHZ, INT/SQW, SDA)
ILO
-0.1
+0.1
µA
Input Leakage (SCL)
ILI
-0.1
+0.1
µA
IOL
RST I/O Leakage
VBAT Leakage
IBATLKG
Temperature Accuracy
TEMPACC
-200
TA = +25NC
-100
VCC or VBAT = +3.3V
25
+10
µA
+100
nA
Q3
NC
Temperature Conversion Time
tCONV
10
ms
Pushbutton Debounce
PBDB
250
ms
Reset Active Time
tRST
Oscillator Stop Flag (OSF) Delay
tOSF
250
(Note 4)
25
ms
100
ms
DC Electrical Characteristics—VBAT Current Consumption
(VCC = 0V, VBAT = +2.3V to +4.5V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = 0V, VBAT = +3.0V, and
TA = +25NC, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Active Battery Current
(I2C Active)
IBATA
(Note 2)
25
75
µA
Timekeeping Battery Current
(I2C Inactive)
IBATT
EN32KHZ = 0, INTCN = 1 (Note 2)
1.8
3.0
µA
200
350
µA
100
nA
Temperature Conversion Current
(I2C Inactive)
IBATTC
Data Retention Current
(Oscillator Stopped and I2C
Inactive)
IBATDR
TA = +25NC
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DS3232M
±5ppm、内置SRAM的I2C实时时钟
AC Electrical Characteristics—Power Switch
(TA = -40NC to +85NC, unless otherwise noted.) (Note 1, Figure 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VCC Fall Time, VPFMAX to
VPFMIN
tVCCF
300
Fs
VCC Rise Time, VPFMIN to
VPFMAX
tVCCR
0
Fs
Recovery at Power-Up
tREC
(Note 5)
250
300
ms
AC Electrical Characteristics—I2C Interface
(VCC or VBAT = +2.3V to +4.5V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = +3.3V, VBAT = +3.0V, and
TA = +25NC, unless otherwise noted.) (Notes 1, 6, Figure 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
400
kHz
SCL Clock Frequency
fSCL
0
Bus Free Time Between STOP
and START Conditions
tBUF
1.3
Fs
Hold Time (Repeated) START
Condition
tHD:STA
0.6
Fs
Low Period of SCL
tLOW
1.3
Fs
High Period of SCL
tHIGH
0.6
Fs
Data Hold Time
tHD:DAT
0
Data Set-Up Time
tSU:DAT
100
ns
START Set-Up Time
tSU:STA
0.6
Fs
0.9
Fs
SDA and SCL Rise Time
tR
(Note 7)
20 +
0.1CB
300
ns
SDA and SCL Fall Time
tF
(Note 7)
20 +
0.1CB
300
ns
STOP Set-Up Time
SDA, SCL Input Capacitance
0.6
tSU:STO
CBIN
(Note 8)
Fs
10
pF
Note 1: Limits are 100% tested at TA = +25°C and TA = +85°C. Limits over the operating temperature range and relevant supply
voltage range are guaranteed by design and characterization. Typical values are not guaranteed.
Note 2: Includes the temperature conversion current (averaged).
Note 3: Does not include RST leakage if VCC < VPF.
Note 4: The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set.
Note 5: The state of RST does not affect the I2C interface or RTC functions.
Note 6: Interface timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with standard mode
I2C timing.
Note 7: CB = total capacitance of one bus line in picofarads.
Note 8: Guaranteed by design and not 100% production tested.
����������������������������������������������������������������� Maxim Integrated Products 4
DS3232M
±5ppm、内置SRAM的I2C实时时钟
时序图
SDA
tBUF
tF
tLOW
tHD:STA
tSP
SCL
tHD:STA
tHIGH
tR
tHD:DAT
STOP
START
tSU:STA
tSU:STO
tSU:DAT
REPEATED
START
NOTE: TIMING IS REFERENCED TO VILMAX AND VIHMIN.
图1. I2C时序
tVCCF
tVCCR
VPFMAX
VPFMIN
VCC
tREC
RST
图2. 电源开关时序
RST
PBDB
tRST
图3. 按钮复位时序
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DS3232M
±5ppm、内置SRAM的I2C实时时钟
典型工作特性
(TA = +25°C, unless otherwise noted.)
TA = +85°C
120
100
80
TA = +25°C
2.8
DS3232M toc02
1.5
TA = +25°C
0.5
3.8
2.8
3.3
3.8
4.3
0
1
2
3
4
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
OUTPUT CURRENT (mA)
INT/SQW OUTPUT VOLTAGE
vs. OUTPUT CURRENT
POWER-SUPPLY CURRENT
vs. SCL FREQUENCY
THERMOMETER ERROR
vs. TEMPERATURE
170
DS3232M toc04
0.5
VCC = 2.7V
0.3
0.2
0.1
EN32KHZ = 0,
SDA = INACTIVE
160
150
SUPPLY CURRENT (µA)
0.4
4.0V
140
130
3.0V
120
110
100
90
2.6V
80
2
4
6
OUTPUT CURRENT (mA)
8
10
5
5
VCC = 3.3V
4
3
2
1
0
-1
-2
-3
-4
70
0
0
0.2
0
2.3
4.3
0.3
0.1
TA = -40°C
3.3
0.4
DS3232M toc06
2.3
2.0
1.0
VPF TA = -40°C
40
TA = +85°C
VCC = 2.45V
0.5
THERMOMETER ERROR (°C)
60
OUTPUT VOLTAGE (V)
2.5
0.6
OUTPUT VOLTAGE (V)
140
VCC = 0V,
EN32KHZ = 0,
INTCN = 1
DS3232M toc05
SUPPLY CURRENT (µA)
160
BATTERY CURRENT (µA)
VBAT = 2.3V,
EN32KHZ = 0,
INTCN = 1
180
3.0
DS3232M toc01
200
RST OUTPUT VOLTAGE
vs. OUTPUT CURRENT
BATTERY CURRENT
vs. BATTERY VOLTAGE
DS3232M toc03
POWER-SUPPLY CURRENT
vs. POWER-SUPPLY VOLTAGE
-5
0
100
200
300
SCL FREQUENCY (kHz)
400
-40
-10
20
50
80
TEMPERATURE (°C)
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DS3232M
±5ppm、内置SRAM的I2C实时时钟
典型工作特性(续)
(TA = +25°C, unless otherwise noted.)
4
2
0
-2
-4
4
2
0
-2
-4
3
2
1
0
-1
-2
-6
-6
-3
-8
-8
-4
-10
-5
-10
5
10
15
20
25
5
10
15
20
25
5
10
15
20
25
TIME (MINUTES)
1Hz FREQUENCY ERROR
(10s THERMAL UPDATES
MEASURED EVERY SECOND)
1Hz FREQUENCY ERROR
(1s THERMAL UPDATES
MEASURED EVERY SECOND)
TIMEKEEPING ACCURACY
vs. TEMPERATURE
0
-2
-4
6
4
2
0
-2
-4
-6
-6
-8
-8
-10
10
15
20
TIME (SECONDS)
25
30
DS3232M ACCURACY
0
-50
TYPICAL 20ppm
CRYSTAL,
UNCOMPENSATED
-100
-150
-200
-10
5
50
FREQUENCY EROR (ppm)
FREQUENCY ERROR (ppm)
2
VBAT = 3.3V,
VCC = 0V,
TA = +25°C
8
30
DS3232M toc12
10
DS3232M toc10
4
0
0
30
TIME (MINUTES)
VBAT = 3.3V,
VCC = 0V,
TA = +25°C
6
0
TIME (SECONDS)
10
8
30
DS3232M toc11
0
FREQUENCY ERROR (ppm)
6
VCC = 3.3V,
TA = +25°C
4
FREQUENCY ERROR (ppm)
FREQUENCY ERROR (ppm)
FREQUENCY ERROR (ppm)
6
VCC = 3.3V,
TA = +25°C
8
5
DS3232M toc08
VCC = 3.3V,
TA = +25°C
8
10
DS3232M toc07
10
1Hz FREQUENCY ERROR
(DELTA FROM T0)
1Hz FREQUENCY ERROR
(MEASURED EVERY SECOND)
DS3232M toc09
1Hz FREQUENCY ERROR
(MEASURED EVERY SECOND)
0
5
10
15
20
TIME (SECONDS)
25
30
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
����������������������������������������������������������������� Maxim Integrated Products 7
DS3232M
±5ppm、内置SRAM的I2C实时时钟
引脚配置
TOP VIEW
32KHZ
1
VCC
2
INT/SQW
RST
+
8 SCL
7
SDA
3
6
VBAT
4
5
GND
DS3232M
SO
引脚说明
引脚
名称
功能
1
32KHZ
32.768kHz输出(推挽输出，50%占空比)。使能条件下(EN32KHZ = 1)，32kHz输出在VCC上电时提供有效输
出；如果在电池供电时使能(BB32KHZ = 1)，输出则在VBAT上电时提供有效输出。禁止条件下，输出被强制为
低电平。如果不使用该功能，可以将该引脚浮空。
2
VCC
主电源直流电源引脚。该引脚应使用0.1μF至1.0μF电容进行去耦，不用时将其接地。
INT/
SQW
低电平有效中断或1Hz方波输出。该漏极开路输出引脚要求外接上拉电阻，上拉电阻连接到4.5V或低于4.5V
的电源电压。如不使用该引脚，可保持开路。该多功能引脚的功能由控制寄存器(0Eh)的INTCN位决定。当
INTCN设定为0时，引脚输出1Hz方波；当INTCN设定为1时，计时寄存器与任一闹钟寄存器相匹配时都会触发
INT/SQW引脚(如果使能闹钟功能)。由于首次上电时INTCN位设定为1，因此，该引脚的缺省设置为中断输出
并禁止闹钟功能。
4
RST
低电平有效复位引脚，该引脚为漏极开路输入/输出。引脚指示VCC相对于VPF指标的状态。如果VCC下降到低于
VPF，RST引脚被拉低；若VCC超过VPF并持续tRST时间，RST引脚通过内部上拉电阻拉至高电平。低电平有效、
漏极开路输出还具有去抖动按钮输入，该引脚可由按钮复位请求触发。引脚内部通过标称值为50kΩ (RPU)的上
拉电阻连接至VCC，无需外接上拉电阻。如果禁止晶体振荡器，tREC被屏蔽，RST立即进入高电平。
5
GND
地。
6
VBAT
备用电源输入。器件将VBAT输入作为主电源时，该引脚应使用0.1μF至1.0μF的低泄漏电容进行去耦。器件将
VBAT输入用作备用电源时，无需使用电容。如果不使用VBAT，则将该引脚接地。器件经过UL认证，在使用锂电
池时，可防止反向充电，更多信息请参考china.maxim-ic.com/qa/info/ul。
7
SDA
串行数据输入/输出。该引脚为I2C串口的数据输入/输出。此漏极开路引脚要求外接上拉电阻。上拉电压可高达
4.5V，与VCC电压无关。
8
SCL
串行时钟输入，该引脚为I2C串口的时钟输入，用于同步串口数据传输。上拉电压可高达4.5V，与VCC电压无关。
3
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DS3232M
±5ppm、内置SRAM的I2C实时时钟
方框图
*SELECTED
POWER
P
DS3232M
32KHZ
DIVIDER
N
INT/SQW
1Hz
TIME-BASE
RESONATOR
VBAT
VCC
POWER
CONTROL*
INTERRUPT
OR 1Hz
SELECT
N
DIGITAL
ADJUSTMENT
RST
TEMP
SENSOR
N
FACTORY TRIM
GND
SDA
SCL
I2C
INTERFACE
CONTROL AND STATUS
REGISTERS
SRAM
详细说明
DS3232M串行实时时钟(RTC)由内部带温度补偿的微机电
系统(MEMS)谐振槽路驱动。振荡器提供稳定、精确的参
考时钟，在-40°C至+85°C温度范围内，RTC的精度保持在
±0.432秒/天之内。RTC为低功耗时钟/日历，提供两个可
编程日历闹钟。INT/SQW提供由闹钟条件决定的中断信号
或者1Hz方波。时钟/日历提供秒、分、时、星期、日期、
月和年信息，少于31天的月份，将自动调整月末的日期，
并包括闰年补偿。时钟可工作在24小时或带AM/PM指示
CLOCK/CALENDAR
WITH ALARM
的12小时格式。内部寄存器通过I2C总线接口访问，温补
电压基准和比较器电路用于监测VCC电平，以检测电源故
障，并在必要时自动切换至备用电源。RST引脚提供外部
按钮输入功能，并可用于指示电源故障。另外，器件还提
供了236字节电池备份的通用SRAM。
工作原理
方框图 给出了该器件的主要组成部分，在以下章节中将对
每个主要模块分别说明。
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DS3232M
±5ppm、内置SRAM的I2C实时时钟
高精度时基
+3.3V
VCC
VBAT
高精度时基由温度传感器、振荡器和数字调节控制逻辑电
路组成。控制器读取片内温度传感器的输出，通过调节最
终的1Hz输出以保持所要求的精度。器件在工厂经过校准，
能够在整个工作温度范围内保持极高精度。采用VCC为器
件供电时，每秒钟进行一次校准。采用VBAT为器件供电
时，每10秒钟进行一次校准，以节省电能。1Hz时基无需
频繁校准，这不会影响器件的长期计时精度。器件还具有
一个老化补偿寄存器，能够在工厂校准值上增加一个补偿
常数(正或负)。
电源配置
图4. 单电源(VCC)供电
DS3232M可以配置为采用单电源(VCC或VBAT)或双电源供
电，双电源配置下提供一个备用电源，在未连接系统主电
源时保持计时电路正常工作。
VCC
VBAT
图4所示为VCC供电下的单电源配置，其中VBAT输入接地。
当VCC < VPF时，触发RST输出(低电平有效)。每秒钟执行
一次温度转换。
图5所示为VBAT供电下的单电源配置，其中VCC输入接地。
RST输出被禁止，并通过内部上拉电阻连接至地。每10秒
钟执行一次温度转换。
图6所示为双电源配置，系统正常工作时采用VCC供电，
VBAT用作备用电源。该配置下，带温度补偿的电压基准
和比较器电路监测VCC电压，并提供电源选择。当VCC高
于VPF时，器件由VCC供电；当VCC低于VPF但高于VBAT时，
该器件由VCC供电；当VCC低于VPF并低于VBAT时，器件由
VBAT供电(见表1)。
图5. 单电源(VBAT)供电
+3.3V
当VCC < VPF时，触发RST输出(低电平有效)。选择VCC作
为电源时，每秒钟执行一次温度转换；选择VBAT作为电源
时，每10秒钟执行一次温度转换。
VCC
VBAT
图6. 双电源供电
���������������������������������������������������������������� Maxim Integrated Products 10
DS3232M
±5ppm、内置SRAM的I2C实时时钟
表1. 电源控制
CONFIGURATION
CONDITION
VCC Only
(Figure 4)
VCC > VPF
VCC < VPF
VBAT Only
(Figure 5)
EOSC = 1
Dual Supply
(Figure 6)
EOSC = 0
VCC > VPF
VCC < VPF
I/O ACTIVE
I/O INACTIVE
ICCA
ICCS
Disabled (Low)
IBATDR
ICCA
VCC > VBAT
VCC < VBAT
Active (Low)
IBATT
IBATA
ICCS
ICCA
IBATA
为了保护电池，VBAT首次加到器件上时，振荡器在VCC超出
VPF之前，或者向器件写入一个有效的I2C地址之前并不启
动。典型的振荡器启动时间在1秒以内。在VCC加电后或者
有效的I2C地址写入后大约2秒钟，器件会测量一次温度，
并使用计算的修正值校准振荡器。一旦振荡器运行起来，
只要电源(VCC或者VBAT)有效，就会一直保持运行状态，器
件也将持续测量温度并校准振荡器频率。VCC电源首次上
电或向器件写入一个有效的I2C地址时(如果VBAT加电)，时
间和日期寄存器被复位至01/01/00 01 00:00:00 (DD/MM/
YY DOW HH:MM:SS)。
VBAT供电
不同工作模式具有不同的VBAT电流。当器件采用VBAT供
电并且串口处于工作状态时，将消耗电池电流IBATA。串
口禁止时，电池电流为保持计时状态的电流IBATT (其中包
括温度转换消耗的平均电流IBATTC)。温度转换消耗的电流
IBATTC源于系统必须能够承受周期性的较大脉冲电流，同
时还需保持有效的电压值。数据保持电流IBATDR是振荡器
停止(EOSC = 1)时的器件电流。在不必保留时间和日期信
VCC > VBAT
VCC < VBAT
RST
Inactive (High)
Inactive (High)
ICCS
IBATT
Active (Low)
息时(例如，产品在交付给客户之前)，该模式有助于降低
对电池的要求。
按钮复位功能
器件提供连接至RST输入/输出引脚的按钮控制功能。若器
件不在复位周期，会连续监测RST信号的下降沿。一旦检
测到一个边沿跳变，器件将通过拉低RST完成开关去抖。
内部定时器计时结束(PBDB)后，器件将继续监测RST信号。
如果信号依旧保持低电平，器件则继续监测信号以检测上
升沿。一旦检测到按钮被释放，器件将强制RST引脚为低
电平并保持tRST时间。RST还用来指示电源故障，当VCC低
于VPF时，会产生内部电源故障报警信号，并强制拉低RST
引 脚。 当VCC超 过VPF电 平 时，RST引 脚 保 持 低 电 平 大 约
250ms (tREC)，使供电电源稳定下来。如果在VCC加载时振
荡器没有工作，将会跳过tREC，RST立刻变为高电平。无
论通过按钮或电源失效检测拉低RST输出，都不会影响器
件的内部工作。RST输出和手动复位监测功能仅在VCC供
电时有效。
���������������������������������������������������������������� Maxim Integrated Products 11
DS3232M
±5ppm、内置SRAM的I2C实时时钟
实时时钟(RTC)
带温度补偿的振荡器提供1Hz信号时，RTC可产生秒、分、
时、星期、日期、月和年信息。少于31天的月份，将自动
调整月末日期，其中包括闰年修正。时钟可工作在24小时
或带AM/PM指示的12小时格式。时钟提供两个可编程日
历闹钟。可以使能INT/SQW产生由闹钟条件决定的中断信
号或者1Hz方波信号，功能选择由控制寄存器中的INTCN
位控制。
I2C接口
只要VCC或VBAT处于有效供电电压范围，即可访问I2C接
口。如果与该器件连接的微控制器由于VCC掉电或其它因
素复位，有可能造成微控制器与该器件的I2C通信不同步，
例如：微控制器在从该器件读数据时发生复位。当微控制
器复位时，通过在SDA达到高电平之前触发SCL，可以将
器件的I2C接口置于已知状态。此时，微控制器应该在SCL
为高电平时将SDA拉低，产生一个START条件。
SRAM
DS3232M提供236字节电池备份、可读/写的通用存储器，
I2C地址范围为14h-FFh。只要VCC或VBAT电压大于最低工
作电压，即可对SRAM进行读、写操作。
地址映射表
表2给出了该器件计时寄存器的地址映射表。在多字节访
问过程中，当地址指针到达寄存器空间的末尾(12h)时，将
会返回到地址00h。在I2C的START条件下或者地址指针递
增到地址00h时，当前的时间会传送给辅助寄存器。在时
钟继续运行的同时，可从辅助寄存器读取时间信息。这样
在读操作期间发生主寄存器更新时，可以避免重新读取寄
存器。
时钟和日历
可以通过读取适当的寄存器字节获得时钟和日历信息，表2
给出了RTC寄存器的配置说明。通过写入适当的寄存器字
节来设定或者初始化时钟和日历数据。时钟和日历寄存器
的内容采用二-十进制编码(BCD)格式，器件可以运行于12
小时或者24小时模式。小时寄存器的第6位定义为12小时
或24小时模式选择位。该位为高时，选择12小时模式。在
12小时模式下，第5位为AM/PM指示位，逻辑高时为PM。
在24小时模式下，第5位为20小时位(20至23小时)。当年
寄存器由99溢出至00时，会转换世纪位(月寄存器的第7
位)。星期寄存器在午夜时递增，对应的星期值由用户定义，
但是该值必须连续(即，如果1等于星期日，那么2等于星期
一，依次类推)。不合逻辑的时间和日期输入会导致不确定
的操作。读取或写入时间和日期寄存器时，辅助缓存器用
于防止内部寄存器更新时可能出现的错误。读取时间和日
期寄存器时，辅助缓存器在任何I2C START条件下或者寄
存器指针返回到零时与内部寄存器同步。时间信息从这些
辅助寄存器读取，此时时钟继续保持运行状态。这样在读
操作期间发生主寄存器更新时可以避免重新读取寄存器。
任何时候写秒寄存器时，倒计时链都会复位。在该器件应
答后进行写传输操作。一旦倒计时链复位，为避免翻转问
题，必须在1秒钟之内写入剩余的时间和日期寄存器。
���������������������������������������������������������������� Maxim Integrated Products 12
DS3232M
±5ppm、内置SRAM的I2C实时时钟
表2. 计时寄存器
ADDRESS
BIT 7
MSB
00h
0
10 Seconds
01h
0
10 Minutes
02h
0
12/24
20
Hours
03h
0
0
0
04h
0
0
BIT 6
BIT 5
AM/PM
05h
Century
BIT 3
BIT 2
RANGE
Seconds
Seconds
00–59
Minutes
Minutes
00–59
Hour
Hours
1–12 +
AM/PM
00–23
Day
1–7
10
Hours
0
0
Day
Date
10
Month
0
BIT 1
BIT 0
LSB
FUNCTION
10 Date
0
06h
BIT 4
Date
01–31
Month
Month/Century
01–12 +
Century
Year
Year
00–99
10 Year
07h
A1M1
10 Seconds
Seconds
Alarm 1
Seconds
00–59
08h
A1M2
10 Minutes
Minutes
Alarm 1
Minutes
00–59
09h
A1M3
12/24
Hour
Alarm 1 Hours
1–12 +
AM/PM
00–23
0Ah
A1M4
DY/DT
0Bh
A2M2
0Ch
A2M3
12/24
0Dh
A2M4
DY/DT
0Eh
BBSQW
0Fh
EOSC
OSF
BB32KHZ
10h
SIGN
DATA
AM/PM
20
Hours
10
Hours
Day
Alarm 1 Day
1–7
Date
Alarm 1 Date
1–31
Minutes
Alarm 2
Minutes
00–59
Hour
Alarm 2 Hours
1–12 +
AM/PM
00–23
10 Date
10 Minutes
AM/PM
20
Hours
10
Hours
10 Date
CONV
Day
Alarm 2 Day
1–7
Date
Alarm 2 Date
1–31
Control
—
NA
NA
INTCN
A2IE
A1IE
0
0
EN32KHZ
BSY
A2F
A1F
Status
—
DATA
DATA
DATA
DATA
DATA
DATA
Aging Offset
—
—
—
11h
SIGN
DATA
DATA
DATA
DATA
DATA
DATA
DATA
Temperature
MSB
12h
DATA
DATA
0
0
0
0
0
0
Temperature
LSB
13h
SWRST
0
0
0
0
0
0
0
Test
—
14h–FFh
X
X
X
X
X
X
X
X
SRAM
00h–FFh
注：除非另有说明，初次上电时的寄存器状态未做定义。
���������������������������������������������������������������� Maxim Integrated Products 13
DS3232M
±5ppm、内置SRAM的I2C实时时钟
闹钟
该器件包含两个星期/日期闹钟。闹钟1可通过写入寄存器
07h至0Ah来设定，闹钟2可通过写入寄存器0Bh至0Dh来
设定，参见表2。可对闹钟进行编程(通过控制寄存器的闹
钟使能位和INTCN位)，从而在闹钟匹配条件下触发INT/
SQW输出。每个星期/日期闹钟寄存器的第7位是屏蔽位
(表2)。当每个闹钟的屏蔽位均为逻辑0时，闹钟只有在计
时寄存器中的值与存储于星期/日期闹钟寄存器的对应值相
匹配时才会发生中断。闹钟也可以编程为每秒、分、时、
星期或日期重复触发中断，表3给出了可能的设置。如果
不按照表中配置，会导致不合逻辑的操作。DY/DT位(闹钟
星期/日期寄存器的第6位)用于控制存储于寄存器第0位至
第5位的闹钟值是反映星期几还是月份中的日期。如果DY/
DT设为逻辑0，闹钟将是与月份日期匹配的结果。如果DY/
DT设为逻辑1，闹钟则是与星期几匹配的结果。当RTC寄
存器值与闹钟寄存器的设定值相匹配时，相应的闹钟标志
位A1F或A2F置为逻辑1。如果对应的闹钟中断使能A1IE或
A2IE位也设定为逻辑1，并且INTCN位设定为逻辑1时，闹
钟条件将会触发INT/SQW信号。在时间和日期寄存器每秒
更新时都会检测匹配情况。
表3. 闹钟屏蔽位
DY/DT
ALARM 1 REGISTER MASK BITS (BIT 7)
ALARM RATE
A1M4
A1M3
A1M2
A1M1
X
1
1
1
1
Alarm once a second
X
1
1
1
0
Alarm when seconds match
X
1
1
0
0
Alarm when minutes and seconds match
X
1
0
0
0
Alarm when hours, minutes, and seconds match
0
0
0
0
0
Alarm when date, hours, minutes, and seconds match
1
0
0
0
0
Alarm when day, hours, minutes, and seconds match
DY/DT
ALARM 2 REGISTER MASK BITS (BIT 7)
ALARM RATE
A2M4
A2M3
A2M2
X
1
1
1
Alarm once per minute (00 seconds of every minute)
X
1
1
0
Alarm when minutes match
X
1
0
0
Alarm when hours and minutes match
0
0
0
0
Alarm when date, hours, and minutes match
1
0
0
0
Alarm when day, hours, and minutes match
���������������������������������������������������������������� Maxim Integrated Products 14
DS3232M
±5ppm、内置SRAM的I2C实时时钟
控制寄存器(0Eh)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
EOSC
0
BBSQW
CONV
NA
NA
INTCN
A2IE
A1IE
0
0
1
1
1
0
0
BIT 7
EOSC：使能振荡器。设定为逻辑0时，启动振荡器。设定为逻辑1时，在器件电源切换至VBAT时振荡器停止。初次上
电时，该位清零(逻辑0)。当该器件由VCC供电时，振荡器与EOSC位的状态无关，始终保持运行状态。当振荡器被
禁止时，所有寄存器数据处于静态。
BIT 6
BBSQW：电池备份的方波使能。设定为逻辑1，并且当INTCN = 0、VCC < VPF时，该位使能1Hz方波输出。当
BBSQW设定为逻辑0时，若VCC降至VPF以下，则INT/SQW引脚变为高阻态。初次上电时，该位被禁止(逻辑0)。
BIT 5
CONV：转换温度。该位设定为1时，强制温度传感器将温度转换成数字码，并执行温度补偿算法以更新振荡器的
精度。器件执行温度补偿算法的速度无法达到每秒钟一次，由用户启动的温度转换不会影响内部更新周期。CONV
位从写入开始直到温度转换完成期间一直保持为1，转换完后CONV和BSY均变为0。在监视用户启动转换的状态时
应该使用CONV位。详细信息请参见图7。
BITS 4:3
NA：没有操作。这些位不影响器件工作，可以设置为0或1。
BIT 2
INTCN：中断控制。该位控制INT/SQW输出信号。INTCN设定为0时，INT/SQW引脚输出1Hz方波。INTCN设定为1
时，若计时寄存器与任一个闹钟寄存器相匹配，则会触发INT/SQW输出(如果也使能闹钟的话)。相应的闹钟标志总
是置位，而与INTCN位的状态无关。初次上电时，INTCN位设定为逻辑1。
BIT 1
A2IE：闹钟2中断使能。该位设定为逻辑1时，允许状态寄存器中的闹钟2标志位(A2F)触发INT/SQW信号(当INTCN
= 1时)。当A2IE位设定为0或者INTCN设定为0时，A2F位不启动中断信号。初次上电时，A2IE位被禁止(逻辑0)。
BIT 0
A1IE：闹钟1中断使能。该位设定为逻辑1时，允许状态寄存器中的闹钟1标志位(A1F)触发INT/SQW信号(当INTCN
= 1时)。当A1IE位设定为0或者INTCN设定为0时，A1F位不启动中断信号。初次上电时，A1IE位被禁止(逻辑0)。
���������������������������������������������������������������� Maxim Integrated Products 15
DS3232M
±5ppm、内置SRAM的I2C实时时钟
VCC POWERED
INTERNAL 1Hz
CLOCK
BSY
CONV
THE USER SETS THE CONV BIT
THE DEVICE CLEARS THE CONV BIT
AFTER THE TEMPERATURE CONVERSION
HAS COMPLETED
BSY IS HIGH DURING
THE TEMPERATURE CONVERSION
VBAT POWERED
10 SECONDS
INTERNAL 1Hz
CLOCK
BSY
CONV
THE USER SETS THE CONV BIT
THE DEVICE CLEARS THE CONV BIT
AFTER THE TEMPERATURE CONVERSION
HAS COMPLETED
图7. CONV控制位和BSY状态位的工作情况
���������������������������������������������������������������� Maxim Integrated Products 16
DS3232M
±5ppm、内置SRAM的I2C实时时钟
状态寄存器(0Fh)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
OSF
BB32KHZ
0
0
EN32KHZ
BSY
A2F
A1F
1
1
0
0
1
X
X
X
BIT 7
OSF：振荡器停止标志。该位为逻辑1表示振荡器现在停止工作，或者曾经停止工作，可用于判定计时数据的有效
性。无论何时振荡器停止工作，该位均置为逻辑1。该位保持为逻辑1，直到写入逻辑0清除。以下情况能够造成OSF
置位：
1) 初次上电。
2) VCC与VBAT上的电压都不足以支持振荡器工作。
3) 在电池备份模式下，EOSC位关闭。
4) 影响振荡器的外部因素(即噪声、泄漏等)。
BIT 6
BB32KHZ：电池备份32kHz输出(BB32KHZ)，当器件由VBAT供电时，该位用于使能32kHz时钟输出(EN32KHZ位使能
条件下，提供32kHz时钟输出)。如果BB32KHZ = 0，VBAT供电时将强制32kHz输出为低电平。
BITS 5:4
未使用(0)。这些位没有意义，读操作时固定为0。
BIT 3
EN32KHZ：使能32.768kHz输出。该位控制32KHZ输出的使能和禁止。设定为逻辑0时，32KHZ输出变为高阻态。初
始化上电时，该位为逻辑1，使能32KHZ输出，如果振荡器使能，则产生32.768kHz方波信号。
BIT 2
BSY：忙。该位表示器件正在执行温度转换功能。温度传感器的转换控制信号使该位置为逻辑1；当器件完成温度转
换后，该位清零。详细信息请参见方框图。
BIT 1
A2F：闹钟2标志。闹钟2标志位为逻辑1时表示时间与闹钟2寄存器匹配。如果A2IE位为逻辑1，并且INTCN位设定为逻
辑1，则触发INT/SQW引脚。写入逻辑0时A2F位清零。该位仅能写入逻辑0，试图写入逻辑1的操作不改变原逻辑值。
BIT 0
A1F：闹钟1标志。闹钟1标志位为逻辑1时表示时间与闹钟1寄存器匹配。如果A1IE位为逻辑1，并且INTCN位设定为逻
辑1，则触发INT/SQW引脚。写入逻辑0时A1F位清零。该位仅能写入逻辑0，试图写入逻辑1的操作不改变原逻辑值。
���������������������������������������������������������������� Maxim Integrated Products 17
DS3232M
±5ppm、内置SRAM的I2C实时时钟
老化补偿寄存器(10h)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SIGN
DATA
DATA
DATA
DATA
DATA
DATA
DATA
0
0
0
0
0
0
0
0
老化补偿寄存器用于在工厂设定的时基校准值上增加或减去一个用户提供的数值。如果只是要求达到电气特性表中规定的精度，则
不需要使用老化补偿寄存器。
老化补偿值采用2的补码形式，第7位为符号(SIGN)位。一个LSB通常对应于0.12ppm的频率变化。在整个工作温度范围内，每个LSB
对应的频率变化(ppm)相同。正补偿值会减慢时基，而负补偿值会加快时基。
温度寄存器(11h至12h)
温度寄存器(高字节 = 11h)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SIGN
DATA
DATA
DATA
DATA
DATA
DATA
DATA
0
0
0
0
0
0
0
0
温度寄存器(低字节 = 12h)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DATA
DATA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
温度值采用10位编码表示，具有0.25°C的分辨率，访问地址为11h和12h。温度编码为2的补码格式。高8位(整数部分)位于地址11h，
低2位(小数部分)位于地址12h。例如，00011001 01b = +25.25°C。上电复位后，寄存器的缺省温度值设定为0°C，控制器启动温度
转换。在VCC初次上电或VBAT供电下首次进行I2C通信时，开始读取温度值，之后每秒(采用VCC供电)或每10秒(采用VBAT供电)读取一
次。每次由用户启动的转换结束后都会更新温度寄存器，温度寄存器是只读的。
���������������������������������������������������������������� Maxim Integrated Products 18
DS3232M
±5ppm、内置SRAM的I2C实时时钟
测试寄存器(13h)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
NAME:
SWRST
0
0
0
0
0
0
BIT 0
0
POR*:
0
0
0
0
0
0
0
0
*POR定义为器件首次上电(VBAT或VCC)。
该寄存器用于工厂测试，6:0位锁存并始终读取为零。对6:0位进行写操作时，不会影响器件的工作状态。如果SWRST位置于逻辑1，
器件将立即复位内部所有逻辑电路和寄存器(SRAM除外)，使它们处于工厂默认的POR状态。
收到承载SWRST指令的数据字节后，器件在随后的应答时隙内复位；由于复位操作，将产生NACK条件(图8所示)。I/O主机应通过标
准的STOP指令终止I/O操作(第28个SCL时钟)，SWRST位自动清零。
SLAVE ACKs
SDA
1
1
0
1
0
0
SLAVE ADDRESS
0
0
0
R/W
0
0
1
0
NACK DURING SWRST
0
1
1
1
REGISTER ADDRESS
0
0
0
0
0
0
0
DATA
SCL
图8. 软件复位I/O
SRAM (14h至FFh)
NAME:
POR*:
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
*POR定义为器件首次上电(VBAT或VCC)。
���������������������������������������������������������������� Maxim Integrated Products 19
DS3232M
±5ppm、内置SRAM的I2C实时时钟
I2C串口工作原理
I2C从地址
器件的从地址字节为D0h。发送到器件的第一个字节包括
器件识别位、器件地址和R/W位(图9)。I2C主机发送的器件
地址必须与分配给器件的地址相匹配。
I2C定义
下列术语常用于I2C数据传输的说明。
主机器件：主机器件用于控制总线上的从机器件。主机
器件产生SCL时钟脉冲以及START和STOP条件。
从机器件：从机器件按照主机的请求发送、接收数据。
总线空闲或不忙：在STOP和START条件之间，SDA和
SCL都无效且处于逻辑高电平状态。当总线空闲时，从
器件通常启动低功耗模式。
START条件：主机产生START条件启动一次新的与从
机之间的数据传输。SCL保持高电平期间，SDA由高电
平到低电平的跳变将产生一个START条件，实际时序如
图1所示。
STOP条件：主机产生STOP条件以终止与从机之间的
数据传输。SCL保持高电平期间，SDA由低电平到高电
平的跳变将产生一个STOP条件，实际时序如图1所示。
LSB
MSB
1
1
0
DEVICE
IDENTIFIER
图9. I2C从机地址字节
1
0
0
0
R/W
READ/
WRITE BIT
重复START条件：在一次数据传输结束后，主机可以
采用重复START条件指示在当前数据传输后将立即启
动一次新的数据传输。读操作期间，重复START条件
通常表示对一个特定存储地址启动一次数据传输。重复
START条件的产生方式与普通START条件相同，实际
时序如图1所示。
写位：SDA的跳变只能发生在SCL的低电平期间。在整
个SCL脉冲为高电平以及所要求的建立、保持时间内(见
图1)，SDA上的数据必须保持有效且不变。在SCL上升
沿，数据移入器件。
读位：写操作结束后，主机应在读位期间释放SDA总
线，并在SCL的下一个上升沿之前保持适当的建立时间
(见图1)。在前一个SCL脉冲的下降沿，器件将每一位数
据通过SDA移出，并在当前SCL脉冲的上升沿保持数据
位有效。注意，由主机产生所有SCL时钟，包括从从机
读取数据位的时钟。
应答(ACK和NACK)：应答(ACK)或非应答(NACK)通常
在字节传输的第9位发送。接收数据的器件(读操作期
间的主机或写操作期间的从机)在第9位期间发送0进行
ACK。器件在第9位期间发送1，以NACK响应。ACK和
NACK的时序与其它位的写操作相同。ACK应答器件已
经收到的数据，NACK用于终止读过程或表示器件没有
收到数据。
写字节：写字节操作包括主机传送到从机的8位信息(最
高有效位在前)和从机发送给主机的1位应答。主机按照
写位定义完成8位数据的发送，按照读位定义读取应答。
读字节：读字节操作包括从机向主机发送的8位信息和
主机发送给从机的1位ACK或NACK。主机按照读位定
义读取从机向主机发送的8位信息(最高有效位在前)，
主机按照写位定义发送ACK，以继续接收其它数据字
节。主机应在读取最后一个字节后发送NACK，终止通
信，使从机将SDA的控制权交还给主机。
���������������������������������������������������������������� Maxim Integrated Products 20
DS3232M
±5ppm、内置SRAM的I2C实时时钟
从机地址字节：I2C总线的每个从机将对START条件之
后发送的从机地址字节进行响应。从机地址字节包含
7位高有效位从机地址和最低有效位R/W位。器件的
从机地址为D0h，用户不能修改该地址。R/W = 0时
(为D0h)，表示主机将向从机写入数据；R/W = 1时(为
D1h)，主机将从从机读取数据。如果写入错误的从机
地址，器件将判定主机与其它I2C器件通信，并在下一
次发送START条件之前忽略通信操作。
I2C通信
I2C通信举例请参见图10。
向从机写入单个字节：主机必须产生START条件、写从
机地址字节(R/W = 0)、写存储器地址、写数据字节并
产生STOP条件。注意，主机必须在整个字节写操作期
间读取从机发送的应答位。
向从机写入多个字节：为了向从机写入多个字节，主机
应产生START条件、写从机地址字节(R/W = 0)、写存
储器地址、写入多个数据字节并产生STOP条件。
存储器地址：I2C写操作期间，主机必须发送存储器地
址以确定从机存储数据的位置。写操作期间，存储器地
址始终为从机地址字节之后发送的第二个字节。
从从机读取单个字节：与写操作中利用指定的存储器地
址字节定义数据写入的位置不同，读操作地址对应于存
TYPICAL I2C WRITE TRANSACTION
MSB
START
1
LSB
1
0
1
0
0
0
R/W
MSB
SLAVE
ACK
b7
LSB
b6
READ/
WRITE
SLAVE
ADDRESS
b5
b4
b3
b2
b1
b0
MSB
SLAVE
ACK
b7
LSB
b6
b5
b4
REGISTER ADDRESS
b3
b2
b1
b0
SLAVE
ACK
STOP
DATA
EXAMPLE I2C TRANSACTIONS
D0h
A) SINGLE BYTE WRITE
-WRITE CONTROL REGISTER
TO 44h
START
B) SINGLE BYTE READ
-READ CONTROL REGISTER
START 1 1 0 1 0 0 0 0
11010000
D0h
0Eh
SLAVE
00001110
ACK
0Eh
SLAVE
SLAVE
00001110
ACK
ACK
D0h
C) MULTIBYTE WRITE
-WRITE DATE REGISTER
TO "02" AND MONTH
REGISTER TO "11"
D) MULTIBYTE READ
-READ ALARM 2 HOURS
AND DATE VALUES
START 1 1 0 1 0 0 0 0
04h
SLAVE
ACK
00000100
SLAVE
ACK
00001100
D0h
START 1 1 0 1 0 0 0 0
44h
SLAVE
01000100
ACK
SLAVE
ACK
STOP
D1h
REPEATED
START
DATA
11010001
00000010
SLAVE
ACK
REPEATED
START
SLAVE
ACK
00010001
SLAVE
ACK
SLAVE
ACK
VALUE
D1h
0Ch
VALUE
MASTER
NACK
STOP
11h
02h
SLAVE
ACK
SLAVE
ACK
11010001
STOP
DATA
DATA
MASTER
ACK
VALUE
MASTER
NACK
STOP
图10. I2C传输
���������������������������������������������������������������� Maxim Integrated Products 21
DS3232M
±5ppm、内置SRAM的I2C实时时钟
储器地址计数器的当前位置。为了从从机读取单个字
节，主机发送START条件，写从机地址字节(R/W = 1)，
然后读取数据字节并以NACK指示终止传输，然后产生
STOP条件。由于实际应用中，无法要求主机跟踪存储
器地址计数器，因此应在读操作时修改地址计数器。
读操作时的地址计数器修改：可以采用空的写操作将地
址计数器指向一个特定值。为此，主机可以产生一个
START条件，写从机地址字节(R/W = 0)，写入需要读
取数据的存储器地址，产生一次重复START条件，写
从机地址字节(R/W = 1)，读取数据并以ACK或NACK响
应，最后发送STOP条件。采用重复START条件指定起
始存储器位置的读操作示例，请参见图6。
从从机读取多个字节：可以通过读操作在一次数据传输
过程中读取多个字节。从从机读取多个字节时，主机在
终止传输之前，如果需要继续读取另一个字节，只需简
单地发出ACK以应答数据字节。主机读取最后一个字节
后，必须发出NACK指示终止传输，然后产生STOP条件。
应用信息
RST也为漏极开路输出，但引脚内部提供了上拉至VCC的
50kΩ电阻(RPU)，无需外接上拉电阻。
SDA和SCL上拉电阻
SDA为漏极开路输出，需要外接上拉电阻，以实现逻辑高
电平。
由于器件不使用时钟扩展功能，因此SCL可以连接具有漏
极开路输出(带上拉电阻)或CMOS输出驱动器(推挽输出)的
主机。
电池充电保护
器件具有Maxim的冗余电池充电保护电路，可防止对任何
外部电池充电。
定购信息
PART
TEMP RANGE
DS3232MZ+
-40NC to +85NC
+表示无铅(Pb)/符合RoHS标准的封装。
如果在电池供电期间无需进行通信，可以省去VBAT去耦电容。
使用漏极开路输出
INT/SQW为漏极开路输出，因此需要外接上拉电阻，以实
现逻辑高电平。上拉电阻值通常在1kΩ至10MΩ之间。
8 SO
封装信息
电源去耦
使用DS3232M时，为获得最佳工作性能，采用0.1μF和/或
1.0μF电容对VCC和/或VBAT电源进行去耦。尽可能采用高
质量的表贴陶瓷电容。表贴元件可减小引线电感、提高性
能，陶瓷电容具有较好的高频响应，适用于去耦应用。
PIN-PACKAGE
如需最近的封装外形信息和焊盘布局(占位面积)，请查询china.
maxim-ic.com/packages。请注意，封装编码中的
“+”
、“#”或
“-”仅表示RoHS状态。封装图中可能包含不同的尾缀字符，但
封装图只与封装有关，与RoHS状态无关。
封装类型
封装编码
外形编号
焊盘布局编号
8 SO
S8MK+1
21-0041
90-0096
���������������������������������������������������������������� Maxim Integrated Products 22
DS3232M
±5ppm、内置SRAM的I2C实时时钟
修订历史
修订号
修订日期
0
3/12
说明
修改页
—
最初版本。
Maxim北京办事处
北京8328信箱 邮政编码100083
免费电话：800 810 0310
电话：010-6211 5199
传真：010-6211 5299
Maxim不对Maxim产品以外的任何电路使用负责，也不提供其专利许可。Maxim保留在任何时间、没有任何通报的前提下修改产品资料和规格的权利。电气
特性表中列出的参数值(最小值和最大值)均经过设计验证，数据资料其它章节引用的参数值供设计人员参考。
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2012 Maxim Integrated Products 23
Maxim是Maxim Integrated Products，Inc.的注册商标。
DS3232M ±5ppm、内置SRAM的I²C实时时钟 - 概述
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Maxim > 产品 > 实时时钟(RTC) > DS3232M
Maxim > 产品 > 时钟、定时器和计数器 > DS3232M
DS3232M
±5ppm、内置SRAM的I²C实时时钟
具有最小封装尺寸的内置存储器、温度补偿MEMS RTC
概述 技术文档 定购信息 相关产品 用户说明 (0) 所有内容 状况
数据资料
状况：生产中。
提供更新的英文版数据资料
下载 Rev. 1 (PDF, 1.9MB)
英文
概述
E-Mail
中文
DS3232M是低成本、超高精度I²C实时时钟(RTC)，带有236字节电池备份SRAM。该器件集成了电池输入，当器
件主电源断电时可保持精确计时。集成微机电系统(MEMS)振荡电路保持器件的长期精确度，并减少了生产线的元
件数量。
下载 Rev. 0 (PDF, 1.7MB)
E-Mail
RTC提供秒、分、时、星期、日期、月和年信息。少于31天的月份，自动调整月末日期，包括闰年修正。时钟格
式可以是24小时或带AM/PM指示的12小时格式。提供两个可设置的日历闹钟和一路1Hz输出。地址与数据通
过I²C双向总线串口传输。高精度、经过温度补偿的电压基准和比较器电路用来监测VCC状态，检测电源故障，提
供复位输出，并在必要时自动切换到备份电源。另外，/RST监测引脚可以作为产生微处理器复位的按键输入，详
细信息请参考数据资料中的方框图。
关键特性
-40°C至+85°C温度范围内，计时精度保持在±5ppm
(±0.432秒/天)
236字节电池备份用户SRAM
为连续计时提供电池备份
低功耗
功能兼容于DS3232
完整的时钟日历，包括秒、分、时、星期、日期、月和年，
并提供有效期到2100年的闰年补偿
两个日历闹钟
1Hz和32.768kHz输出
复位输出和按键去抖输入
高速(400kHz) I²C兼容串行总线
+2.3V至+4.5V电源电压
精度为±3°C的数字温度传感器
-40°C至+85°C工作温度范围
8引脚SO (150 mil)封装
通过美国保险商实验室协会(UL)认证
应用/使用
楼宇自动化
High-Definition Video Security
Industrial Application
电表
关键特性:
Timekeeping & Real-Time Clocks
Part Number
Date/
Time
Format
Interface
V SUPPLY
(V)
hh =
sec/100
DS3232M NEW!
YY-MMDD/
HH:MM:SS
Time
Keeping
Current
(nA)
Memory
Type
Memory
Size
(Bytes)
Time
of Day
Alarms
Integrated
Resonator
typ
I2 C
2.3 to 4.5
查看所有Timekeeping & Real-Time Clocks (89)
http://china.maxim-ic.com/datasheet/index.mvp/id/7684[2012-08-16 7:59:39]
1800
Budgetary Price
See Notes
NV
SRAM
236
2
MEMs
$3.32 @1k
DS3232M ±5ppm、内置SRAM的I²C实时时钟 - 概述
Pricing Notes:
This pricing is BUDGETARY, for comparing similar parts. Prices are in U.S. dollars and subject to change. Quantity pricing may vary substantially and international prices may
differ due to local duties, taxes, fees, and exchange rates. For volume-specific prices and delivery, please see the price and availability page or contact an authorized
distributor.
图表
Typical Operating Circuit
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参考文献： 19- 6247 Rev. 1; 2012- 08- 15
本页最后一次更新: 2012- 08- 15
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© 2012 Maxim Integrated Products版权所有
http://china.maxim-ic.com/datasheet/index.mvp/id/7684[2012-08-16 7:59:39]
19-6247; Rev 1; 8/12
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
General Description
The DS3232M is a low-cost, extremely accurate, I2C
real-time clock (RTC) with 236 bytes of battery-backed
SRAM. The device incorporates a battery input and
maintains accurate timekeeping when main power to the
device is interrupted. The integration of the microelectromechanical systems (MEMS) resonator enhances the
long-term accuracy of the device and reduces the piecepart count in a manufacturing line.
The RTC maintains seconds, minutes, hours, day, date,
month, and year information. The date at the end of the
month is automatically adjusted for months with fewer
than 31 days, including corrections for leap year. The
clock operates in either the 24-hour or 12-hour format
with an AM/PM indicator. Two programmable time-of-day
alarms and a 1Hz output are provided. Address and data
are transferred serially through an I2C bidirectional bus.
A precision temperature-compensated voltage reference
and comparator circuit monitors the status of VCC to
detect power failures, to provide a reset output, and to
automatically switch to the backup supply when necessary. Additionally, the RST pin is monitored as a pushbutton input for generating a microprocessor reset. See the
Block Diagram for more details.
Applications
Features
STimekeeping Accuracy ±5ppm (±0.432 Second/
Day) from -40NC to +85NC
S236 Bytes of Battery-Backed User SRAM
SBattery Backup for Continuous Timekeeping
SLow Power Consumption
SFunctionally Compatible to DS3232
SComplete Clock Calendar Functionality Including
Seconds, Minutes, Hours, Day, Date, Month, and
Year with Leap Year Compensation Up to Year
2100
STwo Time-of-Day Alarms
S1Hz and 32.768kHz Outputs
SReset Output and Pushbutton Input with
Debounce
SFast (400kHz) I2C-Compatible Serial Bus
S+2.3V to +4.5V Supply Voltage
SDigital Temp Sensor with ±3NC Accuracy
S-40NC to +85NC Temperature Range
S8-Pin SO (150 mils) Package
SUnderwriters Laboratories (UL) Recognized
Typical Operating Circuit
Power Meters
Industrial Applications
VCC
VCC
Ordering Information appears at end of data sheet.
SCL
I/O PORT
SDA
DS3232M
INT/SQW
32KHZ
INTERRUPTS
CPU
PUSHBUTTON
RESET
RST
VBAT
For related parts and recommended products to use with this part, refer to: www.maxim-ic.com/DS3232M.related
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may
be simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata.
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to GND.........-0.3V to +6.0V
Operating Temperature Range........................... -40NC to +85NC
Storage Temperature Range............................. -55NC to +125NC
Lead Temperature (soldering, 10s).................................+300NC
Soldering Temperature (reflow).......................................+260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(TA = -40NC to +85NC, unless otherwise noted.) (Note 1)
PARAMETER
MIN
TYP
MAX
VCC
2.3
3.3
4.5
VBAT
2.3
3.0
4.5
Logic 1
VIH
0.7 x
VCC
VCC +
0.3
V
Logic 0
VIL
-0.3
0.3 x
VCC
V
Supply Voltage
SYMBOL
CONDITIONS
UNITS
V
ELECTRICAL CHARACTERISTICS—FREQUENCY AND TIMEKEEPING
(VCC or VBAT = +3.3V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = +3.3V, VBAT = +3.0V, and
TA = +25NC, unless otherwise noted.) (Note 1)
PARAMETER
1Hz Frequency Tolerance
SYMBOL
Df/fOUT
CONDITIONS
MIN
TYP
Measured over R 10s interval
MAX
UNITS
Q5
ppm
1Hz Frequency Stability vs. VCC
Voltage
Df/V
Timekeeping Accuracy
tKA
Q0.432
Seconds/
Day
Df/fOUT
Q2.5
%
32kHz Frequency Tolerance
ppm/V
Q1
DC ELECTRICAL CHARACTERISTICS—GENERAL
(VCC = +2.3V to +4.5V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = +3.3V, VBAT = +3.0V, and
TA = +25NC, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Active Supply Current
(I2C Active)
ICCA
(Note 2)
125
250
µA
Standby Supply Current
(I2C Inactive)
ICCS
(Notes 2, 3)
100
175
µA
2
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
DC ELECTRICAL CHARACTERISTICS—GENERAL (continued)
(VCC = +2.3V to +4.5V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = +3.3V, VBAT = +3.0V, and
TA = +25NC, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
Temperature Conversion Current
(I2C Inactive)
ICCSCONV
CONDITIONS
MIN
2.45
TYP
MAX
UNITS
200
350
µA
2.575
2.70
V
Power-Fail Voltage
VPF
Logic 0 Output
(32KHZ, INT/SQW, SDA)
VOL
IOL = 3mA
0.4
V
Logic 0 Output (RST)
VOL
IOL = 1mA
0.4
V
Logic 1 Output (32KHZ)
VOH
Active supply > 3.3V, IOH = -1mA
2.0
Active supply > 2.7V, IOH = -0.75mA
Active supply > 2.3V, IOH = -0.14mA
2.0
V
2.0
Output Leakage
(32KHZ, INT/SQW, SDA)
ILO
-0.1
+0.1
µA
Input Leakage (SCL)
ILI
-0.1
+0.1
µA
+10
µA
+100
nA
RST I/O Leakage
VBAT Leakage
Temperature Accuracy
IOL
IBATLKG
TEMPACC
-200
-100
TA = +25NC
VCC or VBAT = +3.3V
25
Q3
NC
Temperature Conversion Time
tCONV
10
ms
Pushbutton Debounce
PBDB
250
ms
Reset Active Time
tRST
Oscillator Stop Flag (OSF) Delay
tOSF
250
(Note 4)
25
ms
100
ms
DC ELECTRICAL CHARACTERISTICS—VBAT CURRENT CONSUMPTION
(VCC = 0V, VBAT = +2.3V to +4.5V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = 0V, VBAT = +3.0V, and
TA = +25NC, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Active Battery Current
(I2C Active)
IBATA
(Note 2)
25
75
µA
Timekeeping Battery Current
(I2C Inactive)
IBATT
EN32KHZ = 0, INTCN = 1 (Note 2)
1.8
3.0
µA
200
350
µA
100
nA
Temperature Conversion Current
(I2C Inactive)
IBATTC
Data Retention Current
(Oscillator Stopped and I2C
Inactive)
IBATDR
TA = +25NC
3
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
AC ELECTRICAL CHARACTERISTICS—POWER SWITCH
(TA = -40NC to +85NC, unless otherwise noted.) (Note 1, Figure 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VCC Fall Time, VPFMAX to
VPFMIN
tVCCF
300
Fs
VCC Rise Time, VPFMIN to
VPFMAX
tVCCR
0
Fs
Recovery at Power-Up
tREC
(Note 5)
250
300
ms
AC ELECTRICAL CHARACTERISTICS—I2C INTERFACE
(VCC or VBAT = +2.3V to +4.5V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = +3.3V, VBAT = +3.0V, and
TA = +25NC, unless otherwise noted.) (Notes 1, 6, Figure 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
400
kHz
SCL Clock Frequency
fSCL
0
Bus Free Time Between STOP
and START Conditions
tBUF
1.3
Fs
Hold Time (Repeated) START
Condition
tHD:STA
0.6
Fs
Low Period of SCL
tLOW
1.3
Fs
High Period of SCL
tHIGH
0.6
Fs
Data Hold Time
tHD:DAT
0
Data Set-Up Time
tSU:DAT
100
ns
START Set-Up Time
tSU:STA
0.6
Fs
SDA and SCL Rise Time
tR
(Note 7)
20 +
0.1CB
300
ns
SDA and SCL Fall Time
tF
(Note 7)
20 +
0.1CB
300
ns
STOP Set-Up Time
SDA, SCL Input Capacitance
tSU:STO
CBIN
0.9
0.6
(Note 8)
Fs
Fs
10
pF
Note 1: Limits are 100% tested at TA = +25°C and TA = +85°C. Limits over the operating temperature range and relevant supply
voltage range are guaranteed by design and characterization. Typical values are not guaranteed.
Note 2: Includes the temperature conversion current (averaged).
Note 3: Does not include RST leakage if VCC < VPF.
Note 4: The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set.
Note 5: The state of RST does not affect the I2C interface or RTC functions.
Note 6: Interface timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with standard mode
I2C timing.
Note 7: CB = total capacitance of one bus line in picofarads.
Note 8: Guaranteed by design and not 100% production tested.
4
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
Timing Diagrams
SDA
tBUF
tF
tLOW
tHD:STA
tSP
SCL
tHD:STA
tHIGH
tR
tHD:DAT
STOP
START
tSU:STA
tSU:STO
tSU:DAT
REPEATED
START
NOTE: TIMING IS REFERENCED TO VILMAX AND VIHMIN.
Figure 1. I2C Timing
tVCCF
tVCCR
VPFMAX
VPFMIN
VCC
tREC
RST
Figure 2. Power Switch Timing
RST
PBDB
tRST
Figure 3. Pushbutton Reset Timing
5
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
TA = +85°C
120
100
80
TA = +25°C
2.8
DS3232M toc02
1.5
TA = +25°C
0.5
3.8
2.8
3.3
3.8
4.3
0
1
2
3
4
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
OUTPUT CURRENT (mA)
INT/SQW OUTPUT VOLTAGE
vs. OUTPUT CURRENT
POWER-SUPPLY CURRENT
vs. SCL FREQUENCY
THERMOMETER ERROR
vs. TEMPERATURE
170
DS3232M toc04
0.5
VCC = 2.7V
0.3
0.2
0.1
EN32KHZ = 0,
SDA = INACTIVE
160
150
SUPPLY CURRENT (µA)
0.4
4.0V
140
130
3.0V
120
110
100
90
2.6V
80
2
4
6
OUTPUT CURRENT (mA)
8
10
5
5
VCC = 3.3V
4
3
2
1
0
-1
-2
-3
-4
70
0
0
0.2
0
2.3
4.3
0.3
0.1
TA = -40°C
3.3
0.4
DS3232M toc06
2.3
2.0
1.0
VPF TA = -40°C
40
TA = +85°C
VCC = 2.45V
0.5
THERMOMETER ERROR (°C)
60
OUTPUT VOLTAGE (V)
2.5
0.6
OUTPUT VOLTAGE (V)
140
VCC = 0V,
EN32KHZ = 0,
INTCN = 1
DS3232M toc05
SUPPLY CURRENT (µA)
160
BATTERY CURRENT (µA)
VBAT = 2.3V,
EN32KHZ = 0,
INTCN = 1
180
3.0
DS3232M toc01
200
RST OUTPUT VOLTAGE
vs. OUTPUT CURRENT
BATTERY CURRENT
vs. BATTERY VOLTAGE
DS3232M toc03
POWER-SUPPLY CURRENT
vs. POWER-SUPPLY VOLTAGE
-5
0
100
200
300
SCL FREQUENCY (kHz)
400
-40
-10
20
50
80
TEMPERATURE (°C)
6
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
4
2
0
-2
-4
4
2
0
-2
-4
3
2
1
0
-1
-2
-6
-6
-3
-8
-8
-4
-10
-5
-10
5
10
15
20
25
5
10
15
20
25
5
10
15
20
25
TIME (MINUTES)
1Hz FREQUENCY ERROR
(10s THERMAL UPDATES
MEASURED EVERY SECOND)
1Hz FREQUENCY ERROR
(1s THERMAL UPDATES
MEASURED EVERY SECOND)
TIMEKEEPING ACCURACY
vs. TEMPERATURE
0
-2
-4
6
4
2
0
-2
-4
-6
-6
-8
-8
-10
10
15
20
TIME (SECONDS)
25
30
DS3232M ACCURACY
0
-50
TYPICAL 20ppm
CRYSTAL,
UNCOMPENSATED
-100
-150
-200
-10
5
50
FREQUENCY EROR (ppm)
FREQUENCY ERROR (ppm)
2
VBAT = 3.3V,
VCC = 0V,
TA = +25°C
8
30
DS3232M toc12
10
DS3232M toc10
4
0
0
30
TIME (MINUTES)
VBAT = 3.3V,
VCC = 0V,
TA = +25°C
6
0
TIME (SECONDS)
10
8
30
DS3232M toc11
0
FREQUENCY ERROR (ppm)
6
VCC = 3.3V,
TA = +25°C
4
FREQUENCY ERROR (ppm)
FREQUENCY ERROR (ppm)
FREQUENCY ERROR (ppm)
6
VCC = 3.3V,
TA = +25°C
8
5
DS3232M toc08
VCC = 3.3V,
TA = +25°C
8
10
DS3232M toc07
10
1Hz FREQUENCY ERROR
(DELTA FROM T0)
1Hz FREQUENCY ERROR
(MEASURED EVERY SECOND)
DS3232M toc09
1Hz FREQUENCY ERROR
(MEASURED EVERY SECOND)
0
5
10
15
20
TIME (SECONDS)
25
30
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
7
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
Pin Configuration
TOP VIEW
32KHZ
1
VCC
2
INT/SQW
RST
+
8 SCL
7
SDA
3
6
VBAT
4
5
GND
DS3232M
SO
Pin Description
PIN
NAME
FUNCTION
32.768KHZ Output (Push-Pull Output, 50% Duty Cycle). If enabled (EN32KHZ = 1), the 32kHz output is
active on VCC. If enabled for battery operation (BB32KHZ = 1), the output is also active on VBAT. When
disabled, the output is forced low. This pin can be left unconnected if not used.
1
32KHZ
2
VCC
DC Power Pin for Primary Power Supply. This pin should be decoupled using a 0.1FF to 1.0FF capacitor.
Connect to ground if not used.
INT/
SQW
Active-Low Interrupt or 1Hz Square-Wave Output. This open-drain pin requires an external pullup resistor
connected to a supply at 4.5V or less. It can be left open if not used. This multifunction pin is determined
by the state of the INTCN bit in the Control register (0Eh). When INTCN is set to logic 0, this pin outputs
a 1Hz square wave. When INTCN is set to logic 1, a match between the timekeeping registers and either
of the alarm registers activates the INT/SQW pin (if the alarm is enabled). Because the INTCN bit is set to
logic 1 when power is first applied, the pin defaults to an interrupt output with alarms disabled.
4
RST
Active-Low Reset. This pin is an open-drain input/output. It indicates the status of VCC relative to the VPF
specification. As VCC falls below VPF, the RST pin is driven low. When VCC exceeds VPF, for tRST, the
RST pin is pulled high by the internal pullup resistor. The active-low, open-drain output is combined with
a debounced pushbutton input function. This pin can be activated by a pushbutton reset request. It has
an internal 50kI (RPU) nominal value pullup resistor to VCC. No external pullup resistors should be connected. If the oscillator is disabled, tREC is bypassed and RST immediately goes high.
5
GND
Ground
6
VBAT
Backup Power-Supply Input. When using the device with the VBAT input as the primary power source, this
pin should be decoupled using a 0.1FF to 1.0FF low-leakage capacitor. When using the device with the VBAT
input as the backup power source, the capacitor is not required. If VBAT is not used, connect to ground. The
device is UL recognized to ensure against reverse charging when used with a primary lithium battery. Go to
www.maxim-ic.com/qa/info/ul for more information.
7
SDA
Serial-Data Input/Output. This pin is the data input/output for the I2C serial interface. This open-drain pin
requires an external pullup resistor. The pullup voltage can be up to 4.5V, regardless of the voltage on VCC.
8
SCL
Serial-Clock Input. This pin is the clock input for the I2C serial interface and is used to synchronize data
movement on the serial interface. The pullup voltage can be up to 4.5V, regardless of the voltage on VCC.
3
8
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
Block Diagram
*SELECTED
POWER
P
DS3232M
DIVIDER
32KHZ
N
INT/SQW
1Hz
TIME-BASE
RESONATOR
VBAT
VCC
POWER
CONTROL*
INTERRUPT
OR 1Hz
SELECT
N
DIGITAL
ADJUSTMENT
RST
TEMP
SENSOR
N
FACTORY TRIM
GND
SDA
SCL
I2C
INTERFACE
CONTROL AND STATUS
REGISTERS
SRAM
Detailed Description
The DS3232M is a serial real-time clock (RTC) driven by
an internal, temperature-compensated, microelectromechanical systems (MEMS) resonator. The oscillator provides a stable and accurate reference clock and maintains the RTC to within Q0.432 seconds-per-day accuracy from -40NC to +85NC. The RTC is a low-power clock/
calendar with two programmable time-of-day alarms. INT/
SQW provides either an interrupt signal due to alarm
conditions or a 1Hz square wave. The clock/calendar
provides seconds, minutes, hours, day, date, month, and
year information. The date at the end of the month is automatically adjusted for months with fewer than 31 days,
including corrections for leap year. The clock operates in
CLOCK/CALENDAR
WITH ALARM
either the 24-hour or 12-hour format with an AM/PM indicator. The internal registers are accessible though an I2C
bus interface. A temperature-compensated voltage reference and comparator circuit monitors the level of VCC to
detect power failures and to automatically switch to the
backup supply when necessary. The RST pin provides
an external pushbutton function and acts as an indicator of a power-fail event. Also available are 236 bytes of
general-purpose battery-backed SRAM.
Operation
The Block Diagram shows the device’s main elements.
Each of the major blocks is described separately in the
following sections.
9
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
High-Accuracy Time Base
+3.3V
VCC
VBAT
Figure 4. Single Supply (VCC Only)
VCC
Power-Supply Configurations
VBAT
Figure 5. Single Supply (VBAT Only)
+3.3V
VCC
VBAT
Figure 6. Dual Power Supply
The temperature sensor, oscillator, and digital adjustment controller logic form the highly accurate time base.
The controller reads the output of the on-board temperature sensor and adjusts the final 1Hz output to maintain
the required accuracy. The device is trimmed at the
factory to maintain a tight accuracy over the operating
temperature range. When the device is powered by VCC,
the adjustment occurs once a second. When the device
is powered by VBAT, the adjustment occurs once every
10s to conserve power. Adjusting the 1Hz time base less
often does not affect the device’s long-term timekeeping
accuracy. The device also contains an Aging Offset register that allows a constant offset (positive or negative) to
be added to the factory-trimmed adjustment value.
The DS3232M can be configured to operate on a single
power supply (using either VCC or VBAT) or in a dualsupply configuration, which provides a backup supply
source to keep the timekeeping circuits alive during
absence of primary system power.
Figure 4 illustrates a single-supply configuration using
VCC only, with the VBAT input grounded. When VCC < VPF,
the RST output is asserted (active low). Temperature conversions are executed once per second.
Figure 5 illustrates a single-supply configuration using
VBAT only, with the VCC input grounded. The RST output
is disabled and is held at ground through the connection
of the internal pullup resistor. Temperature conversions
are executed once every 10s.
Figure 6 illustrates a dual-supply configuration, using
the VCC supply for normal system operation and the
VBAT supply for backup power. In this configuration, the
power-selection function is provided by a temperaturecompensated voltage reference and a comparator circuit
that monitors the VCC level. When VCC is greater than
VPF, the device is powered by VCC. When VCC is less
than VPF but greater than VBAT, the device is powered
by VCC. If VCC is less than VPF and is less than VBAT, the
device is powered by VBAT (see Table 1).
When VCC < VPF, the RST output is asserted (active
low). When VCC is the presently selected power source,
temperature conversions are executed once per second.
When VBAT is the presently selected power source, temperature conversions are executed once every 10s.
10
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
Table 1. Power Control
CONFIGURATION
CONDITION
VCC Only
(Figure 4)
VCC > VPF
VCC < VPF
VBAT Only
(Figure 5)
Dual Supply
(Figure 6)
EOSC = 0
EOSC = 1
VCC > VPF
VCC < VPF
I/O ACTIVE
I/O INACTIVE
ICCA
ICCS
Disabled (Low)
IBATDR
ICCA
VCC > VBAT
VCC < VBAT
Active (Low)
IBATT
IBATA
ICCS
ICCA
IBATA
To preserve the battery, the first time VBAT is applied
to the device the oscillator does not start up until VCC
exceeds VPF or until a valid I2C address is written to
the device. Typical oscillator startup time is less than
1s. Approximately 2s after VCC is applied, or a valid
I2C address is written, the device makes a temperature
measurement and applies the calculated correction to
the oscillator. Once the oscillator is running, it continues
to run as long as a valid power source is available (VCC
or VBAT), and the device continues to measure the temperature and correct the oscillator frequency. On the first
application of VCC power, or (if VBAT powered) when a
valid I2C address is written to the device, the time and
date registers are reset to 01/01/00 01 00:00:00 (DD/MM/
YY DOW HH:MM:SS).
VBAT Operation
There are several modes of operation that affect the
amount of VBAT current that is drawn. While the device
is powered by VBAT and the serial interface is active,
the active battery current IBATA is drawn. When the
serial interface is inactive, the timekeeping current IBATT
(which includes the averaged temperature-conversion
current IBATTC) is used. The temperature-conversion
current IBATTC is specified since the system must be
able to support the periodic higher current pulse and
still maintain a valid voltage level. The data-retention
current IBATDR is the current drawn by the device when
VCC > VBAT
VCC < VBAT
RST
Inactive (High)
Inactive (High)
ICCS
IBATT
Active (Low)
the oscillator is stopped (EOSC = 1). This mode can be
used to minimize battery requirements for periods when
maintaining time and date information is not necessary,
e.g., while the end system is waiting to be shipped to a
customer.
Pushbutton Reset Function
The device provides for a pushbutton switch to be connected to the RST input/output pin. When the device is
not in a reset cycle, it continuously monitors RST for a
low-going edge. If an edge transition is detected, the
device debounces the switch by pulling RST low. After
the internal timer has expired (PBDB), the device continues to monitor the RST line. If the line is still low, the
device continuously monitors the line looking for a rising
edge. Upon detecting release, the device forces RST
low and holds it low for tRST. RST is also used to indicate a power-fail condition. When VCC is lower than VPF,
an internal power-fail signal is generated, which forces
RST low. When VCC returns to a level above VPF, RST
is held low for approximately 250ms (tREC) to allow the
power supply to stabilize. If the oscillator is not running
when VCC is applied, tREC is bypassed and RST immediately goes high. Assertion of the RST output, whether
by pushbutton or power-fail detection, does not affect
the device’s internal operation. RST output operation and
pushbutton monitoring are only available if VCC power is
available.
11
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
Real-Time Clock (RTC)
With the 1Hz source from the temperature-compensated
oscillator, the RTC provides seconds, minutes, hours,
day, date, month, and year information. The date at the
end of the month is automatically adjusted for months
with fewer than 31 days, including corrections for leap
year. The clock operates in either the 24-hour or the
12-hour format with an AM/PM indicator. The clock provides two programmable time-of-day alarms. INT/SQW
can be enabled to generate either an interrupt due to an
alarm condition or a 1Hz square wave. This selection is
controlled by the INTCN bit in the Control register.
I2C Interface
2
The I C interface is accessible whenever either VCC or
VBAT is at a valid level. If a microcontroller connected
to the device resets because of a loss of VCC or other
event, it is possible that the microcontroller and device’s
I2C communications could become unsynchronized,
e.g., the microcontroller resets while reading data from
the device. When the microcontroller resets, the device’s
I2C interface can be placed into a known state by toggling SCL until SDA is observed to be at a high level. At
that point the microcontroller should pull SDA low while
SCL is high, generating a START condition.
SRAM
The DS3232M provides 236 bytes of general-purpose
battery-backed read/write memory. The I2C address
ranges from 14h–FFh. The SRAM can be written or read
whenever VCC or VBAT is greater than the minimum operating voltage.
Address Map
Table 2 shows the address map for the device’s timekeeping registers. During a multibyte access, when
the address pointer reaches the end of the register
space (12h), it wraps around to location 00h. On an
I2C START or address pointer incrementing to location
00h, the current time is transferred to a second set of
registers. The time information is read from these secondary registers, while the clock can continue to run.
This eliminates the need to reread the registers in case
the main registers update during a read.
Clock and Calendar
The time and calendar information is obtained by reading
the appropriate register bytes. Table 2 shows the RTC
registers. The time and calendar data are set or initialized
by writing the appropriate register bytes. The contents of
the time and calendar registers are in the binary-coded
decimal (BCD) format. The device can be run in either
12-hour or 24-hour mode. Bit 6 of the Hours register is
defined as the 12-hour or 24-hour mode select bit. When
high, the 12-hour mode is selected. In the 12-hour mode,
bit 5 is the AM/PM bit with logic-high being PM. In the
24-hour mode, bit 5 is the 20-hour bit (20–23 hours).
The century bit (bit 7 of the Month register) is toggled
when the Years register overflows from 99 to 00. The
day-of-week register increments at midnight. Values that
correspond to the day of week are user-defined but must
be sequential (i.e., if 1 equals Sunday, then 2 equals
Monday, and so on). Illogical time and date entries result
in undefined operation. When reading or writing the time
and date registers, secondary buffers are used to prevent
errors when the internal registers update. When reading
the time and date registers, the secondary buffers are
synchronized to the internal registers on any I2C START
and when the register pointer rolls over to zero. The time
information is read from these secondary registers, while
the clock continues to run. This eliminates the need to
reread the registers in case the main registers update
during a read. The countdown chain is reset whenever
the seconds register is written. Write transfers occur on
the acknowledge from the device. Once the countdown
chain is reset, to avoid rollover issues the remaining time
and date registers must be written within 1s.
12
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
Table 2. Timekeeping Registers
ADDRESS
BIT 7
MSB
00h
0
10 Seconds
01h
0
10 Minutes
02h
0
12/24
20
Hours
03h
0
0
0
04h
0
0
05h
Century
0
BIT 6
BIT 5
AM/PM
06h
BIT 4
BIT 3
BIT 2
0
RANGE
Seconds
Seconds
00–59
Minutes
Minutes
00–59
Hour
Hours
1–12 +
AM/PM
00–23
0
Day
1–7
Date
Day
Date
01–31
Month
Month/Century
01–12 +
Century
Year
Year
00–99
10 Date
10
Month
0
BIT 0
LSB
FUNCTION
10
Hours
BIT 1
10 Year
07h
A1M1
10 Seconds
Seconds
Alarm 1
Seconds
00–59
08h
A1M2
10 Minutes
Minutes
Alarm 1
Minutes
00–59
Hour
Alarm 1 Hours
1–12 +
AM/PM
00–23
AM/PM
10
Hours
09h
A1M3
12/24
0Ah
A1M4
DY/DT
0Bh
A2M2
0Ch
A2M3
12/24
0Dh
A2M4
DY/DT
0Eh
EOSC
OSF
BBSQW
CONV
NA
NA
INTCN
A2IE
0Fh
BB32KHZ
0
0
EN32KHZ
BSY
A2F
10h
SIGN
DATA
DATA
DATA
DATA
DATA
DATA
20
Hours
Day
Alarm 1 Day
1–7
Date
Alarm 1 Date
1–31
Minutes
Alarm 2
Minutes
00–59
Hour
Alarm 2 Hours
1–12 +
AM/PM
00–23
10 Date
10 Minutes
AM/PM
20
Hours
10
Hours
10 Date
Day
Alarm 2 Day
1–7
Date
Alarm 2 Date
1–31
A1IE
Control
—
A1F
Status
—
DATA
Aging Offset
—
—
—
11h
SIGN
DATA
DATA
DATA
DATA
DATA
DATA
DATA
Temperature
MSB
12h
DATA
DATA
0
0
0
0
0
0
Temperature
LSB
13h
SWRST
0
0
0
0
0
0
0
Test
—
14h–FFh
X
X
X
X
X
X
X
X
SRAM
00h–FFh
Note: Unless otherwise specified, the registers’ state is not defined when power is first applied.
13
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
Alarms
The device contains two time-of-day/date alarms.
Alarm 1 can be set by writing to registers 07h–0Ah.
Alarm 2 can be set by writing to registers 0Bh–0Dh.
See Table 2. The alarms can be programmed (by the
alarm enable and INTCN bits in the Control register)
to activate the INT/SQW output on an alarm match
condition. Bit 7 of each of the time-of-day/date alarm
registers are mask bits (Table 2). When all the mask
bits for each alarm are logic 0, an alarm only occurs
when the values in the timekeeping registers match the
corresponding values stored in the time-of-day/date
alarm registers. The alarms can also be programmed
to repeat every second, minute, hour, day, or date.
Table 3 shows the possible settings. Configurations
not listed in the table result in illogical operation. The
DY/DT bits (bit 6 of the alarm day/date registers) control whether the alarm value stored in bits 0–5 of that
register reflects the day of the week or the date of the
month. If DY/DT is written to logic 0, the alarm is the
result of a match with date of the month. If DY/DT is
written to logic 1, the alarm is the result of a match
with day of the week. When the RTC register values
match alarm register settings, the corresponding alarm
flag A1F or A2F bit is set to logic 1. If the corresponding alarm interrupt enable A1IE or A2IE bit is also set
to logic 1, the alarm condition activates the INT/SQW
signal if the INTCN bit is set to logic 1. The match is
tested on the once-per-second update of the time and
date registers.
Table 3. Alarm Mask Bits
DY/DT
ALARM 1 REGISTER MASK BITS (BIT 7)
ALARM RATE
A1M4
A1M3
A1M2
A1M1
X
1
1
1
1
Alarm once a second
X
1
1
1
0
Alarm when seconds match
X
1
1
0
0
Alarm when minutes and seconds match
X
1
0
0
0
Alarm when hours, minutes, and seconds match
0
0
0
0
0
Alarm when date, hours, minutes, and seconds match
1
0
0
0
0
Alarm when day, hours, minutes, and seconds match
DY/DT
ALARM 2 REGISTER MASK BITS (BIT 7)
ALARM RATE
A2M4
A2M3
A2M2
X
1
1
1
Alarm once per minute (00 seconds of every minute)
X
1
1
0
Alarm when minutes match
X
1
0
0
Alarm when hours and minutes match
0
0
0
0
Alarm when date, hours, and minutes match
1
0
0
0
Alarm when day, hours, and minutes match
14
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
Control Register (0Eh)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
EOSC
0
BBSQW
CONV
NA
NA
INTCN
A2IE
A1IE
0
0
1
1
1
0
0
BIT 7
EOSC: Enable oscillator. When set to logic 0, the oscillator is started. When set to logic 1, the oscillator is
stopped when the device switches to VBAT. This bit is clear (logic 0) when power is first applied. When the
device is powered by VCC, the oscillator is always on regardless of the status of the EOSC bit. When the oscillator is disabled, all register data is static.
BIT 6
BBSQW: Battery-backed square-wave enable. When set to logic 1 with INTCN = 0 and VCC < VPF, this bit
enables the 1Hz square wave. When BBSQW is logic 0, INT/SQW goes high impedance when VCC falls below
VPF. This bit is disabled (logic 0) when power is first applied.
BIT 5
CONV: Convert temperature. Setting this bit to 1 forces the temperature sensor to convert the temperature
into digital code and execute the temperature compensate algorithm to update the oscillator’s accuracy. The
device cannot be forced to execute the temperature-compensate algorithm faster than once per second. A
user-initiated temperature conversion does not affect the internal update cycle. The CONV bit remains at a 1
from the time it is written until the temperature conversion is completed, at which time both CONV and BSY go
to 0. The CONV bit should be used when monitoring the status of a user-initiated conversion. See Figure 7 for
more details.
BITS 4:3
NA: Not applicable. These bits have no affect on the device and can be set to either 0 or 1.
BIT 2
INTCN: Interrupt control. This bit controls the INT/SQW output signal. When the INTCN bit is set to logic 0, a
1Hz square wave is output on INT/SQW. When the INTCN bit is set to logic 1, a match between the timekeeping registers and either of the alarm registers activates the INT/SQW output (if the alarm is also enabled). The
corresponding alarm flag is always set regardless of the state of the INTCN bit. The INTCN bit is set to a logic
1 when power is first applied.
BIT 1
A2IE: Alarm 2 interrupt enable. When set to logic 1, this bit permits the alarm 2 flag (A2F) bit in the status register to assert INT/SQW (when INTCN = 1). When the A2IE bit is set to logic 0 or INTCN is set to logic 0, the
A2F bit does not initiate an interrupt signal. The A2IE bit is disabled (logic 0) when power is first applied.
BIT 0
A1IE: Alarm 1 interrupt enable. When set to logic 1, this bit permits the alarm 1 flag (A1F) bit in the status register to assert INT/SQW (when INTCN = 1). When the A1IE bit is set to logic 0 or INTCN is set to logic 0, the
A1F bit does not initiate an interrupt signal. The A1IE bit is disabled (logic 0) when power is first applied.
15
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
VCC POWERED
INTERNAL 1Hz
CLOCK
BSY
CONV
THE USER SETS THE CONV BIT
THE DEVICE CLEARS THE CONV BIT
AFTER THE TEMPERATURE CONVERSION
HAS COMPLETED
BSY IS HIGH DURING
THE TEMPERATURE CONVERSION
VBAT POWERED
10 SECONDS
INTERNAL 1Hz
CLOCK
BSY
CONV
THE USER SETS THE CONV BIT
THE DEVICE CLEARS THE CONV BIT
AFTER THE TEMPERATURE CONVERSION
HAS COMPLETED
Figure 7. CONV Control Bit and BSY Status Bit Operation
16
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
Status Register (0Fh)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
OSF
BB32KHZ
0
0
EN32KHZ
BSY
A2F
A1F
1
1
0
0
1
X
X
X
BIT 7
OSF: Oscillator stop flag. A logic 1 in this bit indicates that the oscillator either is stopped or was stopped for
some period and could be used to judge the validity of the timekeeping data. This bit is set to logic 1 any time
that the oscillator stops. This bit remains at logic 1 until written to logic 0. The following are examples of
conditions that can cause the OSF bit to be set:
1) The first time power is applied.
2) The voltages present on both VCC and VBAT are insufficient to support the oscillator.
3) The EOSC bit is turned off in battery-backed mode.
4) External influences on the oscillator (i.e., noise, leakage, etc.).
BIT 6
BB32KHZ: Battery-backed 32kHz output (BB32KHZ). This bit enables the 32kHz output when the device is powered from VBAT (provided the 32kHz output is enabled with the EN32KHZ bit). If BB32KHZ = 0, the 32kHz output
is forced low when the device is powered by VBAT.
BITS 5:4
Unused (0). These bits have no meaning and are fixed at 0 when read.
BIT 3
EN32KHZ: Enabled 32.768kHz output. This bit enables and disables the 32KHZ output. When set to a logic 0,
the 32KHZ output is high impedance. On initial power-up, this bit is set to a logic 1 and the 32KHZ output is
enabled and produces a 32.768kHz square wave if the oscillator is enabled.
BIT 2
BSY: Busy. This bit indicates the device is busy executing temperature conversion function. It goes to logic 1
when the conversion signal to the temperature sensor is asserted, and then it is cleared when the device has
completed the temperature conversion. See the Block Diagram for more details.
BIT 1
A2F: Alarm 2 flag. A logic 1 in the alarm 2 flag bit indicates that the time matched the alarm 2 registers. If the
A2IE bit is logic 1 and the INTCN bit is set to logic 1, INT/SQW is also asserted. A2F is cleared when written to
logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value unchanged.
BIT 0
A1F: Alarm 1 flag. A logic 1 in the alarm 1 flag bit indicates that the time matched the alarm 1 registers. If the
A1IE bit is logic 1 and the INTCN bit is set to logic 1, INT/SQW is also asserted. A1F is cleared when written to
logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value unchanged.
17
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
Aging Offset Register (10h)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SIGN
DATA
DATA
DATA
DATA
DATA
DATA
DATA
0
0
0
0
0
0
0
0
The Aging Offset register takes a user-provided value to add to or subtract from the factory-trimmed value that adjusts the
accuracy of the time base. Use of the Aging Offset register is not needed to achieve the accuracy as defined in the Electrical
Characteristics tables.
The Aging Offset code is encoded in two’s complement, with bit 7 representing the SIGN bit. One LSB typically represents a
0.12ppm change in frequency. The change in ppm per LSB is the same over the operating temperature range. Positive offsets
slow the time base and negative offsets quicken the time base.
Temperature Registers (11h–12h)
Temperature Register (Upper Byte = 11h)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SIGN
DATA
DATA
DATA
DATA
DATA
DATA
DATA
0
0
0
0
0
0
0
0
Temperature Register (Lower Byte = 12h)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DATA
DATA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Temperature is represented as a 10-bit code with a resolution of 0.25°C and is accessible at location 11h and 12h. The temperature is encoded in two’s complement format. The upper 8 bits, the integer portion, are at location 11h and the lower 2 bits,
the fractional portion, are at location 12h. For example, 00011001 01b = +25.25°C. Upon power reset, the registers are set to
a default temperature of 0°C and the controller starts a temperature conversion. The temperature is read upon initial application of VCC or I2C access on VBAT and once every second afterwards with VCC power or once every 10s with VBAT power. The
Temperature registers are also updated after each user-initiated conversion and are read only.
18
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
Test Register (13h)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
NAME:
SWRST
0
0
0
0
0
0
0
POR*:
0
0
0
0
0
0
0
0
*POR is defined as the first application of power to the device, either VBAT or VCC.
This register is used for factory test. Bits 6:0 are locked and always read as zeros. Writing to bit locations 6:0 has no affect on the
device. If the SWRST bit is set to Logic 1, the device immediately resets all internal logic and registers (except the SRAM) to their
factory-default POR state.
The device reset occurs during the normal acknowledge time slot following the receipt of the data byte carrying that SWRST
instruction; a NACK occurs due to the resetting action (see Figure 8). The I/O master should terminate the I/O string with a normal STOP instruction (on the 28th SCL clock). The SWRST bit is automatically cleared to logic 0.
SLAVE ACKs
SDA
1
1
0
1
0
0
SLAVE ADDRESS
0
0
0
R/W
0
0
1
0
NACK DURING SWRST
0
1
1
1
REGISTER ADDRESS
0
0
0
0
0
0
0
DATA
SCL
Figure 8. Software Reset I/O Execution
SRAM (14h–FFh)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
NAME:
D7
D6
D5
D4
D3
D2
D1
D0
POR*:
X
X
X
X
X
X
X
X
*POR is defined as the first application of power to the device, either VBAT or VCC.
19
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
I2C Serial Port Operation
I2C Slave Address
The device’s slave address byte is D0h. The first byte
sent to the device includes the device identifier, device
address, and the R/W bit (Figure 9). The device address
sent by the I2C master must match the address assigned
to the device.
I2C Definitions
The following terminology is commonly used to describe
I2C data transfers.
Master Device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses and START and STOP conditions.
Slave Devices: Slave devices send and receive data
at the master’s request.
Bus Idle or Not Busy: Time between STOP and
START conditions when both SDA and SCL are inactive and in their logic-high states. When the bus is idle,
it often initiates a low-power mode for slave devices.
START Condition: A START condition is generated
by the master to initiate a new data transfer with a
slave. Transitioning SDA from high to low while SCL
remains high generates a START condition. See
Figure 1 for applicable timing.
STOP Condition: A STOP condition is generated
by the master to end a data transfer with a slave.
Transitioning SDA from low to high while SCL remains
high generates a STOP condition. See Figure 1 for
applicable timing.
Repeated START Condition: The master can use
a repeated START condition at the end of one data
transfer to indicate that it immediately initiates a new
data transfer following the current one. Repeated
STARTs are commonly used during read operations
to identify a specific memory address to begin a data
LSB
MSB
1
1
0
1
DEVICE
IDENTIFIER
Figure 9. I2C Slave Address Byte
0
0
0
R/W
READ/
WRITE BIT
transfer. A repeated START condition is issued identically to a normal START condition. See Figure 1 for
applicable timing.
Bit Write: Transitions of SDA must occur during
the low state of SCL. The data on SDA must remain
valid and unchanged during the entire high pulse of
SCL plus the setup and hold time requirements (see
Figure 1). Data is shifted into the device during the
rising edge of the SCL.
Bit Read: At the end of a write operation, the master
must release the SDA bus line for the proper amount
of setup time (see Figure 1) before the next rising
edge of SCL during a bit read. The device shifts out
each bit of data on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising
edge of the current SCL pulse. Remember that the
master generates all SCL clock pulses including when
it is reading bits from the slave.
Acknowledge (ACK and NACK): An acknowledge
(ACK) or not acknowledge (NACK) is always the ninth
bit transmitted during a byte transfer. The device
receiving data (the master during a read or the slave
during a write operation) performs an ACK by transmitting a 0 during the ninth bit. A device performs
a NACK by transmitting a 1 during the ninth bit.
Timing for the ACK and NACK is identical to all other
bit writes. An ACK is the acknowledgment that the
device is properly receiving data. A NACK is used to
terminate a read sequence or as an indication that the
device is not receiving data.
Byte Write: A byte write consists of 8 bits of information transferred from the master to the slave (most
significant bit first) plus a 1-bit acknowledgment from
the slave to the master. The 8 bits transmitted by the
master are done according to the bit write definition
and the acknowledgment is read using the bit read
definition.
Byte Read: A byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information
that are transferred (most significant bit first) from the
slave to the master are read by the master using the
bit read definition, and the master transmits an ACK
using the bit write definition to receive additional data
bytes. The master must NACK the last byte read to
terminate communication so the slave returns control
of SDA to the master.
20
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
Slave Address Byte: Each slave on the I2C bus
responds to a slave address byte sent immediately
following a START condition. The slave address byte
contains the slave address in the most significant 7
bits and the R/W bit in the least significant bit. The
device’s slave address is D0h and cannot be modified by the user. When the R/W bit is 0 (such as in
D0h), the master is indicating it writes data to the
slave. If R/W = 1 (D1h in this case), the master is
indicating it wants to read from the slave. If an incorrect slave address is written, the device assumes the
master is communicating with another I2C device and
ignore the communication until the next START condition is sent.
Memory Address: During an I2C write operation, the
master must transmit a memory address to identify
the memory location where the slave is to store the
data. The memory address is always the second byte
transmitted during a write operation following the
slave address byte.
I2C Communication
See Figure 10 for an I2C communication example.
Writing a Single Byte to a Slave: The master must
generate a START condition, write the slave address
byte (R/W = 0), write the memory address, write
the byte of data, and generate a STOP condition.
Remember the master must read the slave’s acknowledgment during all byte write operations.
Writing Multiple Bytes to a Slave: To write multiple
bytes to a slave, the master generates a START condition, writes the slave address byte (R/W = 0), writes
the starting memory address, writes multiple data
bytes, and generates a STOP condition.
Reading a Single Byte from a Slave: Unlike the write
operation that uses the specified memory address
byte to define where the data is to be written, the read
operation occurs at the present value of the memory
address counter. To read a single byte from the slave,
the master generates a START condition, writes the
TYPICAL I2C WRITE TRANSACTION
MSB
START
1
LSB
1
0
1
0
0
0
R/W
MSB
SLAVE
ACK
b7
LSB
b6
READ/
WRITE
SLAVE
ADDRESS
b5
b4
b3
b2
b1
b0
MSB
SLAVE
ACK
b7
LSB
b6
b5
b4
REGISTER ADDRESS
b3
b2
b1
b0
SLAVE
ACK
STOP
DATA
EXAMPLE I2C TRANSACTIONS
D0h
A) SINGLE BYTE WRITE
-WRITE CONTROL REGISTER
TO 44h
START
B) SINGLE BYTE READ
-READ CONTROL REGISTER
START 1 1 0 1 0 0 0 0
11010000
D0h
0Eh
SLAVE
00001110
ACK
0Eh
SLAVE
SLAVE
00001110
ACK
ACK
D0h
C) MULTIBYTE WRITE
-WRITE DATE REGISTER
TO "02" AND MONTH
REGISTER TO "11"
D) MULTIBYTE READ
-READ ALARM 2 HOURS
AND DATE VALUES
START 1 1 0 1 0 0 0 0
04h
SLAVE
ACK
00000100
SLAVE
ACK
00001100
D0h
START 1 1 0 1 0 0 0 0
44h
SLAVE
01000100
ACK
SLAVE
ACK
STOP
D1h
REPEATED
START
DATA
11010001
00000010
SLAVE
ACK
REPEATED
START
SLAVE
ACK
00010001
SLAVE
ACK
SLAVE
ACK
VALUE
D1h
0Ch
VALUE
MASTER
NACK
STOP
11h
02h
SLAVE
ACK
SLAVE
ACK
11010001
STOP
DATA
DATA
MASTER
ACK
VALUE
MASTER
NACK
STOP
Figure 10. I2C Transactions
21
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
slave address byte with R/W = 1, reads the data byte
with a NACK to indicate the end of the transfer, and
generates a STOP condition. However, since requiring the master to keep track of the memory address
counter is impractical, use the method for manipulating the address counter for reads.
Manipulating the Address Counter for Reads: A
dummy write cycle can be used to force the address
counter to a particular value. To do this the master generates a START condition, writes the slave
address byte (R/W = 0), writes the memory address
where it desires to read, generates a repeated START
condition, writes the slave address byte (R/W = 1),
reads data with ACK or NACK as applicable, and
generates a STOP condition. See Figure 6 for a read
example using the repeated START condition to
specify the starting memory location.
Reading Multiple Bytes from a Slave: The read
operation can be used to read multiple bytes with a
single transfer. When reading bytes from the slave,
the master simply ACKs the data byte if it desires to
read another byte before terminating the transaction.
After the master reads the last byte it must NACK to
indicate the end of the transfer and then it generates
a STOP condition.
Applications Information
Using Open-Drain Outputs
The INT/SQW output is open drain and requires an external pullup resistor to realize logic-high output level. Pullup
resistor values between 1kI and 10MI are typical.
The RST output is also open drain, but is provided with
an internal 50kI pullup resistor (RPU) to VCC. External
pullup resistors should not be added.
SDA and SCL Pullup Resistors
SDA is an open-drain output and requires an external
pullup resistor to realize a logic-high level.
Because the device does not use clock cycle stretching,
a master using either an open-drain output with a pullup
resistor or CMOS output driver (push-pull) could be used
for SCL.
Battery Charge Protection
The device contains Maxim’s redundant battery-charge
protection circuit to prevent any charging of the external
battery.
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
DS3232MZ+
-40NC to +85NC
8 SO
DS3232MZ/V+
-40NC to +85NC
8 SO
+Denotes a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive qualified part.
Power-Supply Decoupling
To achieve the best results when using the DS3232M,
decouple the VCC and/or VBAT power supplies with
0.1FF and/or 1.0FF capacitors. Use a high-quality,
ceramic, surface-mount capacitor if possible. Surfacemount components minimize lead inductance, which
improves performance, and ceramic capacitors tend to
have adequate high-frequency response for decoupling
applications.
If communications during battery operation are not
required, the VBAT decoupling capacitor can be omitted.
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
8 SO
S8MK+1
21-0041
90-0096
22
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
Revision History
REVISION
NUMBER
REVISION
DATE
0
3/12
Initial release
—
1
8/12
Added an automotive qualified part option to the Ordering Information table
22
DESCRIPTION
PAGES
CHANGED
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical
Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated Products, Inc. 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
© 2012
Maxim Integrated Products 23
Maxim is a registered trademark of Maxim Integrated Products, Inc.