February 2006 Revision 1.1 PC97551 Embedded Controller for Notebook Systems General Description bedded controller interface channels and to the BIOS flash. The Winbond PC97551 is an embedded controller (EC) for mainstream notebook applications. It includes a highly optimized set of functions, which provide a hardware/firmware partition that enables the implementation of flexible solutions; and its high-performance CPU core enables EC functionality to be extended via the firmware. Like other members of Winbond’s Advanced I/O family, the PC97551 is PC01 and ACPI compliant. The PC97551 incorporates National’s CompactRISC CR16B core (a high-performance 16-bit RISC processor), internal ROM and RAM memories, system support functions and a Bus Interface Unit (BIU) that directly interfaces with both external memory (such as flash) and I/O devices. Outstanding Features ■ Host interface, based on Intel’s LPC Interface Specification Revision 1.1, August 2002 ■ PC2001 Rev 1.0, and ACPI 3.0 compliant ■ 16-bit RISC core, with 2 Mbytes address space, running at up to 20 MHz ■ Shared BIOS flash memory (external) System support functions include: watchdog, PWM, timers, interrupt control, General-Purpose I/O (GPIO) with internal keyboard matrix scanning, PS/2® Interface, SMBus® interface, analog-to-digital (ADC) and digital-to-analog (DAC) converters for battery charging circuitry, system monitoring and analog controls. ■ 92 GPIO ports (including keyboard scanning) with a variety of wake-up events ■ JTAG-based debugger interface ■ Software and hardware controlled clock throttling and extremely low current consumption in Idle mode The PC97551 interfaces with the host via an LPC interface that provides the host with access to the Keyboard and em- ■ 176-pin LQFP and FBGA packages System Block Diagram South Bridge Keyboard Mouse Touch Touch Pad Point Display PWBTN SuperI/O LPC ECSCI Sleep ON PWUREQ State Control SMI Lid Switch Brightness Contrast On/Off Internal Keyboard 4x PS/2 Keyboard Scan TPM PCI PCI Devices & Boards Wake-Up Enable PWM PC97551 Switch Pad and LEDs Power Switch Beep Development JTAG System Control and Status Embedded Controller for Notebook Systems Speaker Shared Flash Memory EC Firmware, System BIOS Tacho Local Bus Drv Drv Drv. Voltage Current CPU AC Detect ON and Switch Control © 2006 Winbond Electronics Corporation Voltage Temp. Input Port Control Direct CD Player 2x SMBus Output Port Expansion GPIOs Power Supply Charger Battery Fans Temperature Voltage Current AC Adaptor Temp. Sensor E2PROM Docking www.winbond.com PC97551 Embedded Controller for Notebook Systems Product Brief PC97551 PC97551 Block Diagram LPC I/F Serial IRQ SMI Reset & Config Processing Unit CR16B Core DMA Core Bus Host Controlled Functions Memory I/F Functions LPC Bus I/F CR Access Bridge Shared mem. + Protection Bus Adapter RAM ROM BIU Internal Bus Peripherals Peripheral Bus KBC + PM Host I/F MSWC HFCG ICU Valid Battery + Oscillator PS/2 I/F Debugger I/F MIWU PMC CLK ACB (X2) GPIO KBSCAN Timer + WDG MFT16 (X2) PWM ADC USART DAC External Memory + I/O JTAG 32.768 KHz Features ■ Embedded Controller ■ CompactRISC CR16B Processing Unit - a 16-bit embedded RISC processor core (the “core”) ■ Internal Memory — Boot block for core code in 4 Kbytes of ROM — 4 Kbytes of on-chip RAM with contents protection — ROM and RAM both can hold code and data ■ ❏ Communicates with debugger via JTAG interface ❏ Hardware breakpoint support — DEV - Development mode ❏ Used in In-System Emulators (ISE) and Application Development Boards (ADB) Bus Interface Unit (BIU) supporting: — Up to 2 Mbytes for code and data — Provides two chip-selects for flash/ROM and SRAM devices — Provides one chip-select for I/O devices — 8- or 16-bit wide bus — Configurable wait states — Enhanced performance using fast read cycles ❏ Single-cycle, fast-read (word-aligned) ❏ Operation Modes — IRE - Normal operation mode — OBD - On-Board Development mode ❏ Used for development in the final system ■ Two-byte, burst-read (byte-aligned) — BIOS sharing with PC host — Host-core shared memory access protection ❏ Host-controlled with core override ❏ Communicates with debugger via JTAG interface ❏ On-chip ROM is replaced with off-chip SRAM ❏ Cycle-by-cycle compatible with IRE mode LPC System Interface — 8-bit I/O and 8-bit memory read and write cycles — 8-bit FWH read and write with wait-sync cycles — Bootable memory support — Base Address (BADDR) strap to determine the base address of the Index-Data register pair — Serial IRQ (SERIRQ) support — LPCPD and CLKRUN support ❏ 64-Kbyte and 8-Kbyte blocks with independent protection Core-Controlled Functions ❏ Hardware-protected boot zone for host code ■ — Download for on-board code updating ❏ Host-controlled via LPC ❏ — 31 maskable vectored interrupts — Enable and pending indication for each interrupt — General-purpose external interrupt inputs through MIWU Core-controlled via JTAG or serial port — External memory “power-down” mode www.winbond.com Interrupt Control Unit (ICU) — Non-maskable interrupt input (PFAIL) 2 Revision 1.1 (Continued) — Provides interrupt on system events (via MSWC) ❏ External modem ring on RI ■ ❏ IRQ from Keyboard, Mouse and PM channels ❏ Software-triggered event ❏ System ACPI sleep-state change ❏ Power Button mode change ❏ Legacy software “Off” command Multi-Input Wake-Up (MIWU) — Supports up to 20 wake-up inputs — Provides user-selectable trigger conditions ■ Two 16-bit Multi Function Timer (MFT16) modules; each module: — Contains two 16-bit timers — Supports Pulse Width Modulation (PWM), Capture and Counter ■ Timer and Watchdog (TWM) — 16-bit periodic interrupt timer with 30 µs resolution and 5-bit prescaler for system tick and periodic wake-up tasks — 8-bit watchdog timer ■ Pulse Width Modulation (PWM) Module — Eight outputs — 8/16-bit duty cycle resolution — 8/16-bit common input clock prescaler ■ Analog to Digital Converter (ADC) — Five voltage channels (four external and one internal), with 8-bit resolution — Sigma-delta technology for high noise rejection — Internal voltage reference — Provides wake-up on activity of external pins ❏ General-purpose wake-up inputs ❏ Power switch input ❏ Keyboard scan inputs — Generates wake-up event to Power Management Controller (PMC) — Generates interrupts to ICU ■ General-Purpose I/O (GPIO) — 92 port pins (including keyboard scanning) — I/O pins individually configured as input or output — Optional internal pull-up resistors on inputs — Special ports for internal keyboard matrix scanning ❏ 16 open-collector outputs ❏ — Every 100 ms, three of the five channels are measured ■ — 1 µs conversion time Eight Schmitt inputs with internal pull-ups Host-Core Interface Functions — Dedicated input for system On/Off switch — External GPIO expansion through the BIU I/O Expansion protocol ■ ■ ■ PS/2 Interface — Supports four external ports for: external keyboard, mouse and two additional pointing devices — Supports byte-level handling via hardware accelerator Host Bus Interface (HBI) — Comprises three host interface ports, typically used for KBC and ACPI EC channels: ❏ One 8042 KBC-standard, interface (legacy 6016, 6416). ❏ Two PM interface ports (legacy 6216, 6616 and 6816, 6C16). These provide ACPI Embedded Controller support with either “Shared” or “Private” interface (regarding SCI/SMI generation). — Generates IRQ (with Legacy support), SMI and SCI Two ACB Interface modules. Each module: — Is Intel SMBus and Philips I2C® compatible — Is SMBus master and slave — Detects four simultaneous slave addresses (two user-defined, broadcast and ARP) — Supports polling and interrupt controlled operation — Generates a wake-up event on detection of a Start Condition (while in Idle mode) — Has an optional internal pull-up on SDA and SCL pins ■ Digital to Analog Converter (DAC) — Four channels with 8-bit resolution — Rail-to-Rail output range, from AGND to AVCC — Provides Fast Gate A20 and Fast Keyboard Reset via firmware ■ Core Access to Host-Controlled Functions — Host-Core arbitration of function control — Host access blocked by the core via lock bits Universal Synchronous/Asynchronous Receiver-Transmitter (USART) — Supports full-duplex USART communication — Has programmable baud rate — Supports polling and interrupt controlled data transfer — Supports synchronous mode with either internal or external clock — Supports 9-bit Attention mode Revision 1.1 3 www.winbond.com PC97551 Features