LTC4150 Coulomb Counter/ Battery Gas Gauge U DESCRIPTIO FEATURES ■ ■ ■ ■ ■ ■ ■ ■ The LTC®4150 measures battery depletion and charging in handheld PC and portable product applications. The device monitors current through an external sense resistor between the battery’s positive terminal and the battery’s load or charger. A voltage-to-frequency converter transforms the current sense voltage into a series of output pulses at the interrupt pin. These pulses correspond to a fixed quantity of charge flowing into or out of the battery. The part also indicates charge polarity as the battery is depleted or charged. Indicates Charge Quantity and Polarity ±50mV Sense Voltage Range Precision Timer Capacitor or Crystal Not Required 2.7V to 8.5V Operation High Side Sense 32.55Hz/V Charge Count Frequency 1.5µA Shutdown Current 10-Pin MSOP Package U APPLICATIO S ■ ■ ■ The LTC4150 is intended for 1-cell or 2-cell Li-Ion and 3-cell to 6-cell NiCd or NiMH applications. Battery Chargers Palmtop Computers and PDAs Cellular Telephones and Wireless Modems , LTC and LT are registered trademarks of Linear Technology Corporation. U TYPICAL APPLICATIO Integral Nonlinearity, % of Full Scale CHARGER RSENSE 0.5 LOAD + 0.4 4.7µF RL SENSE – SENSE + VDD CF+ 4.7µF CF– INT LTC4150 CLR POL GND CHG DISCHG µP SHDN 4150 TA01a ERROR (% FULL SCALE) 0.3 RL 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 –50 –25 0 25 CURRENT SENSE VOLTAGE (mV) 50 4150 TA01b 4150fa 1 LTC4150 U W W W ABSOLUTE AXI U RATI GS U W U PACKAGE/ORDER I FOR ATIO (Note 1) Supply Voltage (VDD) ...................................– 0.3V to 9V Input Voltage Range Digital Inputs (CLR, SHDN) ....... – 0.3V to (VDD + 0.3) SENSE –, SENSE + , CF –, CF + ........ – 0.3V to (VDD + 0.3) Output Voltage Range Digital Outputs (INT, POL) .......................– 0.3V to 9V Operating Temperature Range LTC4150CMS .......................................... 0°C to 70°C LTC4150IMS ..................................... –40°C TO 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER TOP VIEW SENSE + SENSE – CF+ CF– 10 9 8 7 6 1 2 3 4 SHDN 5 INT CLR VDD GND POL MS PACKAGE 10-LEAD PLASTIC MSOP LTC4150CMS LTC4150IMS MS PART MARKING TJMAX = 125°C, θJA = 160°C/W LTQW Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 2.7V and 8.5V unless otherwise noted. SYMBOL PARAMETER VIL Digital Input Low Voltage, CLR, SHDN VIH Digital Input High Voltage, CLR, SHDN VOL Digital Output Low Voltage, INT, POL ILEAK VOS CONDITIONS MIN TYP ● ● IOL = 1.6mA, VDD = 2.7V ● Digital Output Leakage Current, INT, POL VINT = VPOL = 8.5V ● Differential Offset Voltage (Note 4) VDD = 4.0V VSENSE Sense Voltage Differential Input Range SENSE + – SENSE – RIDR Average Differential Input Resistance, Across SENSE + and SENSE – VDD = 4.1V (Note 3) VUVLO Undervoltage Lockout Threshold VDD Rising V V 0.01 0.5 V 1 µA ● ±100 ±150 µV µV ● ±100 ±150 µV µV ● ±150 ±200 µV µV VDD + 0.06 V VDD = 2.7V to 8.5V Sense Voltage Common Mode Input Range UNITS 0.7 1.9 VDD = 8.0V VSENSE(CM) MAX ● VDD – 0.06 ● – 0.05 0.05 V 270 390 kΩ ● 2.5 2.7 V 115 80 140 100 µA µA 10 1.5 µA µA 33.1 33.3 Hz/V Hz/V 0 0.5 %/V ● – 0.03 0.03 %/ ºC ● – 0.4 – 0.5 0.4 0.5 % % 155 Power Supply Current IDD Supply Current, Operating VDD = 8.5V VDD = 2.7V ● ● IDD(SD) Supply Current, Shutdown VDD = 8.5V VDD = 2.7V ● ● VSENSE = 50mV to – 50mV, 2.7V ≤ VDD ≤ 8.5V ● AC Characteristics GVF ∆GVF(VDD) Voltage to Frequency Gain Gain Variation with Supply ∆GVF(TEMP) Gain Variation with Temperature INL 2.7V ≤ VDD ≤ 8.5V (Note 2) Integral Nonlinearity tCLR CLR Pulse Width to Reset INT, INT and CLR Not Connected Figure 2 tINT INT Low Time, INT Connected to CLR Figure 3, CL = 15pF ● 32.0 31.8 32.55 20 µs 1 µs 4150fa 2 LTC4150 ELECTRICAL CHARACTERISTICS Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: Guaranteed by design and not tested in production. Note 3: Measured at least 20ms after power on. Note 4: Tested in feedback loop to SENSE + and SENSE –. U W TYPICAL PERFOR A CE CHARACTERISTICS otherwise noted.) Voltage to Frequency Gain vs Temperature +1.00 +1.00 +0.75 +0.75 +0.50 +0.25 VSENSE = 25mV 0 VSENSE = 50mV –0.25 –0.50 –0.75 Operating IDD vs VDD 140 VSENSE = 50mV 120 +0.50 VDD = 2.7V +0.25 0 VDD = 8.5V 100 –0.25 80 –0.50 –0.75 –1.00 2 3 4 5 6 VDD (V) 7 8 –1.00 -50 9 60 -25 0 25 50 75 TEMPERATURE (°C) 100 4150 G01 125 400 VOL (mV) 4 2.60 IOL = 1.6mA 350 2.59 300 2.58 POL PIN 250 INT PIN 200 150 2 1 3 4 5 6 7 8 9 10 VDD (V) 4150 G04 6 7 VDD (V) 8 9 10 RISING EDGE 2.57 2.56 2.55 100 2.54 50 2.53 0 0 5 4 Undervoltage Lockout Threshold vs Temperature UVLO (V) 5 3 3 4150 G03 Digital Output Low Voltage vs VDD 6 2 2 4150 G02 Shutdown IDD vs VDD IDD (µA) IDD (µA) GVF ERROR (% OF TYPICAL) GVF ERROR (% OF TYPICAL) Voltage to Frequency Gain vs Supply Voltage (Specifications are at TA = 25°C, unless 2 3 4 5 6 VDD (V) 7 8 9 4150 G05 2.52 -50 -25 0 25 50 75 TEMPERATURE (°C) 100 125 4150 G06 4150fa 3 LTC4150 U U U PI FU CTIO S SENSE+ (Pin 1): Positive Sense Input. This is the noninverting current sense input. Connect SENSE+ to the load and charger side of the sense resistor. Full-scale current sense input is 50mV. SENSE+ must be within 60mV of VDD for proper operation. SENSE– (Pin 2): Negative Sense Input. This is the inverting current sense input. Connect SENSE– to the positive battery terminal side of the sense resistor. Full-scale current sense input is 50mV. SENSE– must be within 60mV of VDD for proper operation. CF+ (Pin 3): Filter Capacitor Positive Input. A capacitor connected between CF+ and CF– filters and averages noise and fast battery current variations. A 4.7µF value is recommended. If filtering is not desired, leave CF+ and CF– unconnected. CF– (Pin 4): Filter Capacitor Negative Input. A capacitor connected between CF+ and CF– filters and averages noise and fast battery current variations. A 4.7µF value is recommended. If filtering is not desired, leave CF+ and CF– unconnected. SHDN (Pin 5): Shutdown Digital Input. When asserted low, SHDN forces the LTC4150 into its low current consumption power-down mode and resets the part. In applications with logic supply VCC > VDD, a resistive divider must be used between SHDN and the logic which drives it. See the Applications Information section. POL (Pin 6): Battery Current Polarity Open-Drain Output. POL indicates the most recent battery current polarity when INT is high. A low state indicates the current is flowing out of the battery while high impedance means the current is going into the battery. POL latches its state when INT is asserted low. POL is an open-drain output and can be pulled up to any logic supply up to 9V. In shutdown, POL is high impedance. GND (Pin 7): Ground. Connect directly to the negative battery terminal. VDD (Pin 8): Positive Power Supply. Connect to the load and charger side of the sense resistor. SENSE+ also connects to VDD. VDD operating range is 2.7V to 8.5V. Bypass VDD with 4.7µF capacitor. CLR (Pin 9): Clear Interrupt Digital Input. When asserted low for more than 20µs, CLR resets INT high. Charge counting is unaffected. INT may be directly connected to CLR. In this case the LTC4150 will capture each assertion of INT and wait at least 1µs before resetting it. This ensures that INT pulses low for at least 1µs but gives automatic INT reset. In applications with a logic supply VCC > VDD, a resistive divider must be used between INT and CLR. See the Applications Information section. INT (Pin 10): Charge Count Interrupt Open-Drain Output. INT latches low every 1/(VSENSE • GVF) seconds and is reset by a low pulse at CLR. INT is an open-drain output and can be pulled up to any logic supply of up to 9V. In shutdown INT is high impedance. 4150fa 4 LTC4150 W BLOCK DIAGRA CHARGER LOAD VDD REFHI 1.7V S3 INT + SENSE + 100pF CF+ R – CLR CONTROL LOGIC AMPLIFIER + CF– Q COUNTER – 200k CF IBAT S S1 2k 200k RSENSE OFLOW/ UFLOW + UP/DN CHARGE POL POLARITY DETECTION DISCHARGE 200k 2k – SENSE – S2 REFLO 0.95V SHDN GND 4150 F01 Figure 1. Block Diagram W UW TI I G DIAGRA S CLR 50% 50% tCLR INT 50% 50% INT tINT 4150 F02 Figure 2. CLR Pulse Width to Reset INT, CLR and INT Not Connected 4150 F03 Figure 3. INT Minimum Pulse Width, CLR and INT Connected 4150fa 5 LTC4150 U OPERATIO Charge is the time integral of current. The LTC4150 measures battery current by monitoring the voltage developed across a sense resistor and then integrates this information in several stages to infer charge. The Block Diagram shows the stages described below. As each unit of charge passes into or out of the battery, the LTC4150 INT pin interrupts an external microcontroller and the POL pin reports the polarity of the charge unit. The external microcontroller then resets INT with the CLR input in preparation for the next interrupt issued by the LTC4150. The value of each charge unit is determined by the sense resistor value and the sense voltage to interupt frequency gain GVF of the LTC4150. Power-On and Start-Up Initialization When power is first applied to the LTC4150, all internal circuitry is reset. After an initialization interval, the LTC4150 begins counting charge. This interval depends on VDD and the voltage across the sense resistor but will be at least 5ms. It may take an additional 80ms for the LTC4150 to accurately track the sense voltage. An internal undervoltage lockout circuit monitors VDD and resets all circuitry when VDD falls below 2.5V. Asserting SHDN low also resets the LTC4150’s internal circuitry and reduces the supply current to 1.5µA. In this condition, POL and INT outputs are high impedance. The LTC4150 resumes counting after another initialization interval. Shutdown minimizes battery drain when both the charger and load are off. CHARGE COUNTING First, the current measurement is filtered by capacitor CF connected across pins CF+ and CF–. This averages fast changes in current arising from ripple, noise and spikes in the load or charging current. Second, the filter’s output is applied to an integrator with the amplifier and 100pF capacitor at its core. When the integrator output ramps to REFHI or REFLO levels, switches S1 and S2 reverse the ramp direction. By observing the condition of S1 and S2 and the ramp direction, polarity is determined. The integrating interval is trimmed to 600µs at 50mV full-scale sense voltage. Third, a counter is incremented or decremented every time the integrator changes ramp direction. The counter effectively increases integration time by a factor of 1024, greatly reducing microcontroller overhead required to service interrupts from the LTC4150. At each counter under or overflow, the INT output latches low, flagging a microcontroller. Simultaneously, the POL output is latched to indicate the polarity of the observed charge. With this information, the microcontroller can total the charge over long periods of time, developing an accurate estimate of the battery’s condition. Once the interrupt is recognized, the microcontroller resets INT with a low going pulse on CLR and awaits the next interrupt. Alternatively, INT can drive CLR. 4150fa 6 LTC4150 U W U U APPLICATIO S I FOR ATIO SENSE VOLTAGE INPUT AND FILTERS Coulomb Counting Since the overall integration time is set by internally trimming the LTC4150, no external timing capacitor or trimming is necessary. The only external component that affects the transfer function of interrupts per coulomb of charge is the sense resistor, RSENSE. The common mode range for the SENSE+ and SENSE– pins is VDD ±60mV, with a maximum differential voltage range of ±50mV. SENSE+ is normally tied to VDD, so there is no common mode issue when SENSE– operates within the 50mV differential limit relative to SENSE+. The LTC4150’s transfer function is quantified as a voltage to frequency gain GVF, where output frequency is the number of interrupts per second and input voltage is the differential drive VSENSE across SENSE+ and SENSE–. The number of interrupts per second will be: Choose RSENSE to provide 50mV drop at maximum charge or discharge current, whichever is greater. Calculate RSENSE from: RSENSE = 50mV IMAX f = GVF • ⏐VSENSE⏐ where VSENSE = IBATTERY • RSENSE The external filter capacitor CF operates against a total onchip resistance of 4k to form a lowpass filter that averages battery current and improves accuracy in the presence of noise, spikes and ripple. 4.7µF is recommended for general applications but can be extended to higher values as long as the capacitor’s leakage is low. A 10nA leakage is roughly equivalent to the input offset error of the integrator. Ceramic capacitors are suitable for this use. Switching regulators are a particular concern because they generate high levels of current ripple which may flow through the battery. The VDD and SENSE+ connection to the charger and load should be bypassed by at least 4.7µF at the LTC4150 if a switching regulator is present. The LTC4150 maintains high accuracy even when Burst Mode® switching regulators are used. Burst pulse “on” levels must be within the specified differential input voltage range of 50mV as measured at CF+ and CF–. To retain accurate charge information, the LTC4150 must remain enabled during Burst Mode operation. If the LTC4150 shuts down or VDD drops below 2.5V, the part resets and charge information is lost. (3) Therefore, f = GVF • ⏐IBATTERY • RSENSE⏐ (4) Since I • t = Q, coulombs of battery charge per INT pulse can be derived from Equation 4: (1) The sense input range is small (±50mV) to minimize the loss across RSENSE. To preserve accuracy, use Kelvin connections at RSENSE. (2) One INT = 1 Coulombs GVF • RSENSE (5) Battery capacity is most often expressed in ampere-hours. 1Ah = 3600 Coulombs (6) Combining Equations 5 and 6: 1 [Ah] (7) 1Ah = 3600 • GVF • RSENSE Interrupts (8) One INT = 3600 • GVF • RSENSE or The charge measurement may be further scaled within the microcontroller. However, the number of interrupts, coulombs or Ah all represent battery charge. The LTC4150’s transfer function is set only by the value of the sense resistor and the gain GVF. Once RSENSE is selected using Equation 1, the charge per interrupt can be determined from Equation 5 or 7. Note that RSENSE is not chosen to set the relationship between ampere-hours of battery charge and number of interrupts issued by the LTC4150. Rather, RSENSE is chosen to keep the maximum sense voltage equal to or less than the LTC4150’s 50mV full-scale sense input. Burst Mode is registered trademark of Linear Technology Corporation. 4150fa 7 LTC4150 U U W U APPLICATIO S I FOR ATIO INT, POL and CLR Interfacing to INT, POL, CLR and SHDN INT asserts low each time the LTC4150 measures a unit of charge. At the same time, POL is latched to indicate the polarity of the charge unit. The integrator and counter continue running, so the microcontroller must service and clear the interrupt before another unit of charge accumulates. Otherwise, one measurement will be lost. The time available between interrupts is the reciprocal of Equation 2: The LTC4150 operates directly from the battery, while in most cases the microcontroller supply comes from some separate, regulated source. This poses no problem for INT and POL because they are open-drain outputs and can be pulled up to any voltage 9V or less, regardless of the voltage applied to the LTC4150’s VDD. Time per INT Assertion = 1 GVF •⏐VSENSE⏐ (9) At 50mV full scale, the minimum time available is 596ms. To be conservative and accommodate for small, unexpected excursions above the 50mV sense voltage limit, the microcontroller should process the interrupt and polarity information and clear INT within 500ms. Toggling CLR low for at least 20µs resets INT high and unlatches POL. Since the LTC4150’s integrator and counter operate independently of the INT and POL latches, no charge information is lost during the latched period or while CLR is low. Charge/discharge information continues to accumulate during those intervals and accuracy is unaffected. Once cleared, INT idles in a high state and POL indicates real-time polarity of the battery current. POL high indicates charge flowing into the battery and low indicates charge flowing out. Indication of a polarity change requires at least: tPOL = 2 GVF • 1024 •⏐VSENSE⏐ (10) CLR and SHDN inputs require special attention. To drive them, the microcontroller or external logic must generate a minimum logic high level of 1.9V. The maximum input level for these pins is VDD + 0.3V. If the microcontroller’s supply is more than this, resistive dividers must be used on CLR and SHDN. The schematic in Figure 6 shows an application with INT driving CLR and microcontroller VCC > VDD. The resistive dividers on CLR and SHDN keep the voltages at these pins within the LTC4150’s VDD range. Choose R2 and R1 so that: (R1 + R2) ≥ 50RL 1.9 V ≤ R1 VCC ≤ VDD (Minimum) R1 + R2 RL > (VCC – 0.5) / 1.6mA (13) Equation 13 also applies to the selection of R3 and R4. The minimum VDD is the lowest supply to the LTC4150 when the battery powering it is at its lowest discharged voltage. When the battery is removed in any application, the CLR and SHDN inputs are unpredictable. INT and POL outputs may be erratic and should be ignored until after the battery is replaced. If desired, the simple logic of Figure 4 may be used to derive separate charge and discharge pulse trains from INT and POL. where VSENSE is the smallest sense voltage magnitude before and after the polarity change. Open-drain outputs POL and INT can sink IOL = 1.6mA at VOL = 0.5V. The minimum pull-up resistance for these pins should be: (12) INT CHARGE CLR LTC4150 DISCHARGE POL (11) where VCC is the logic supply voltage. Because speed isn’t an issue, pull-up resistors of 10k or higher are adequate. 4150 F04 Figure 4. Unravelling Polarity— Separate Charge and Discharge Outputs 4150fa 8 LTC4150 U U W U APPLICATIO S I FOR ATIO AUTOMATIC CHARGE COUNT INTERRUPT AND CLEAR In applications where a CLR pulse is unavailable, it’s easy to make the LTC4150 run autonomously, as shown in Figures 5 and 6. If the microcontroller VCC is less than or equal to the battery VDD, INT may be directly connected to CLR, as in Figure 5. The only requirement is that the microcontroller should be able to provide a high logic level of 1.9V to SHDN. If the microcontroller VCC is greater than the battery VDD, use Figure 6. The resistor dividers on CLR and SHDN keep the voltages at these pins within the LTC4150’s VDD range. Choose an RL value using Equation 11 and R1-R4 values using Equation 13. In either application, the LTC4150 will capture the first assertion of INT and wait at least 1µs before resetting it. This insures that INT pulses low for at least 1µs but gives automatic INT reset. POWER-DOWN SWITCH LOAD CL 47µF PROCESSOR VCC RL 1 SENSE + LTC4150 CLR RSENSE 2 2.7V TO 8.5V + BATTERY INT 3 CF 4.7µF 4 5 SENSE – VDD CF+ GND CF– SHDN POL RL 10 9 8 C2 4.7µF 7 µP 6 4150 F05 Figure 5. Application with INT Direct Drive of CLR and Separate Microprocessor Supply VCC ≤ VDD POWER-DOWN SWITCH LOAD PROCESSOR VCC RL 1 SENSE + 2 BATTERY VBATTERY < VCC INT LTC4150 CLR RSENSE + 3 CF 4.7µF 4 5 SENSE – VDD CF+ GND CF– SHDN POL CL 47µF RL 10 9 R2 8 C2 4.7µF 7 R1 µP 6 SHUTDOWN R4 R3 4150 F06 Figure 6. Application with INT Driving CLR and Separate Microprocessor Supply VCC > VDD 4150fa 9 LTC4150 U U W U APPLICATIO S I FOR ATIO PC BOARD LAYOUT SUGGESTIONS TO CHARGER Keep all traces as short as possible to minimize noise and inaccuracy. The supply bypass capacitor C2 should be placed close to the LTC4150. The 4.7µF filter capacitor CF should be placed close the CF+ and CF– pins and should be a low leakage, unpolarized type. Use a 4-wire Kelvin sense connection for the sense resistor, locating it close to the LTC4150 with short sense traces to the SENSE+ and SENSE– pins and longer force lines to the battery pack and powered load, see Figure 7. PIN 1 RSENSE LTC4150 4150 F07 TO BATTERY Figure 7. Kelvin Connection on SENSE Resistor U TYPICAL APPLICATIO S Figure 8 shows a typical application designed for a single cell lithium-ion battery and 500mA maximum load current. Use Equation 1 to calculate RSENSE = 0.05V / 0.5A = 0.1Ω. With RSENSE = 0.1Ω, Equation 7 shows that each interrupt corresponds to 0.085mAh. Equation 14, derived from Equation 2, gives the number of INT assertions for average battery current, IBATT, over a time, t, in seconds: INT Assertions = GVF • IBATT • RSENSE • t (14) Loading the battery so that 51.5mA is drawn from it over 600 seconds results in 100 INT assertions. For an 800mAh battery, this is (51.5mA • 1/6h) / 800mAh = 11% of the battery’s capacity. With a microcontroller supply = 5V, Equation 11 gives RL > 2.875k. The nearest standard value is 3k. From Equation 12, RL = 3k gives R1 + R2 equal to 150.5k. A single cell lithium-ion battery can discharge as low as 2.7V. From Equation 13, select R1 = 75k; the nearest standard value for R2 is 76.8k. Also from Equation 13, we choose R3 = 75k and R4 = 76.8k. POWER-DOWN SWITCH LOAD 5.0V 1 RSENSE 0.1Ω SINGLE-CELL Li-Ion 3.0V ~ 4.2V SENSE + INT LTC4150 CLR 2 3 + CF 4.7µF 4 5 SENSE – CF+ VDD GND CF– SHDN POL RL 3k RL 3k 10 9 CL 47µF R2 76.8k 8 C2 4.7µF 7 R1 75k µP 6 SHUTDOWN R4 76.8k R3 75k 4150 F08 Figure 8. Typical Application, Single Cell Lithium-Ion Battery 4150fa 10 LTC4150 U PACKAGE DESCRIPTIO MS Package 10-Lead Plastic MSOP (Reference LTC DWG # 05-08-1661) 0.889 ± 0.127 (.035 ± .005) 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 0.50 0.305 ± 0.038 (.0197) (.0120 ± .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) 0.497 ± 0.076 (.0196 ± .003) REF 10 9 8 7 6 3.00 ± 0.102 (.118 ± .004) (NOTE 4) 4.90 ± 0.152 (.193 ± .006) DETAIL “A” 0° – 6° TYP GAUGE PLANE 1 2 3 4 5 0.53 ± 0.152 (.021 ± .006) DETAIL “A” 0.86 (.034) REF 1.10 (.043) MAX 0.18 (.007) SEATING PLANE 0.17 – 0.27 (.007 – .011) TYP 0.50 (.0197) BSC 0.127 ± 0.076 (.005 ± .003) MSOP (MS) 0603 NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 4150fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 11 LTC4150 U TYPICAL APPLICATIO S CHARGER LOAD SENSE + 1.2Ω 1.1Ω INT CD40110B LTC4150 CLR 100mΩ SENSE – CD40110B + CD40110B SENSE RESISTANCE = 0.0852Ω IMAX = 588mA 10,000 PULSES = 1Ah CD40110B CD40110B 4150 F09 Figure 9. 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