4-Channel, 12-/10-/8-Bit ADC with I2C-Compatible Interface in 8-Lead SOT-23 AD7991/AD7995/AD7999 FEATURES FUNCTIONAL BLOCK DIAGRAM VDD 12-/10-/8-bit ADCs with fast conversion time: 1 μs typical 4 analog input channels/3 analog input channels with reference input Specified for VDD of 2.7 V to 5.5 V Sequencer operation Temperature range: −40°C to +125°C I2C-compatible serial interface supports standard, fast, and high speed modes 2 versions allow 2 I2C addresses Low power consumption Shutdown mode: 1 μA maximum 8-lead SOT-23 package VIN0 VIN1 VIN2 I/P MUX 12-/10-/8-BIT SAR ADC T/H VIN3/VREF AD7991/AD7995/AD7999 GND APPLICATIONS SCL SDA 06461-001 CONTROL LOGIC AND I2C INTERFACE Figure 1. System monitoring Battery-powered systems Data acquisition Medical instruments GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7991/AD7995/AD7999 are 12-/10-/8-bit, low power, successive approximation ADCs with an I2C®-compatible interface. Each part operates from a single 2.7 V to 5.5 V power supply and features a 1 μs conversion time. The track-and-hold amplifier allows each part to handle input frequencies of up to 14 MHz, and a multiplexer allows taking samples from four channels. 1. Each AD7991/AD7995/AD7999 provides a 2-wire serial interface compatible with I2C interfaces. The AD7991 and AD7995 come in two versions and each version has an individual I2C address. This allows two of the same devices to be connected to the same I2C bus. Both versions support standard, fast, and high speed I2C interface modes. The AD7999 comes in one version. The AD7991/AD7995/AD7999 normally remain in a shutdown state, powering up only for conversions. The conversion process is controlled by a command mode, during which each I2C read operation initiates a conversion and returns the result over the I2C bus. 2. 3. 4. 5. Four single-ended analog input channels, or three singleended analog input channels and one reference input channel. I2C-compatible serial interface. Standard, fast, and high speed modes. Automatic shutdown. Reference derived from the power supply or external reference. 8-lead SOT-23 package. Table 1. Related Devices Device AD7998 AD7997 AD7994 AD7993 AD7992 Resolution 12 10 12 10 12 Input Channels 8 8 4 4 2 When four channels are used as analog inputs, the reference for the part is taken from VDD; this allows the widest dynamic input range to the ADC. Therefore, the analog input range to the ADC is 0 V to VDD. An external reference, applied through the VIN3/VREF input, can also be used with this part. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007–2009 Analog Devices, Inc. All rights reserved. AD7991/AD7995/AD7999 TABLE OF CONTENTS Features .............................................................................................. 1 Converter Operation.................................................................. 17 Applications ....................................................................................... 1 Typical Connection Diagram ................................................... 18 Functional Block Diagram .............................................................. 1 Analog Input ............................................................................... 18 General Description ......................................................................... 1 Internal Register Structure ............................................................ 20 Product Highlights ........................................................................... 1 Configuration Register .............................................................. 20 Revision History ............................................................................... 2 Sample Delay and Bit Trial Delay ............................................. 21 Specifications..................................................................................... 3 Conversion Result Register ....................................................... 21 AD7991 .......................................................................................... 3 Serial Interface ................................................................................ 22 AD7995 .......................................................................................... 5 Serial Bus Address ...................................................................... 22 AD7999 .......................................................................................... 7 Writing to the AD7991/AD7995/AD7999 .................................. 23 I C Timing Specifications ............................................................ 9 Reading from the AD7991/AD7995/AD7999 ............................ 24 Absolute Maximum Ratings.......................................................... 11 ESD Caution ................................................................................ 11 Placing the AD7991/AD7995/AD7999 into High Speed Mode ................................................................................. 25 Pin Configuration and Function Descriptions ........................... 12 Mode of Operation ......................................................................... 26 Typical Performance Characteristics ........................................... 13 Outline Dimensions ....................................................................... 27 Terminology .................................................................................... 16 Ordering Guide .......................................................................... 27 2 Theory of Operation ...................................................................... 17 REVISION HISTORY 10/09—Rev. 0 to Rev. A Changes to Table 3 ............................................................................ 5 Changes to Table 4 ............................................................................ 7 Updated Ordering Guide ............................................................... 27 12/07—Revision 0: Initial Version Rev. A | Page 2 of 28 AD7991/AD7995/AD7999 SPECIFICATIONS AD7991 1 The temperature range of the Y version is −40°C to +125°C. Unless otherwise noted, VDD = 2.7 V to 5.5 V, VREF = 2.5 V, fSCL = 3.4 MHz, and TA = TMIN to TMAX. Table 2. Parameter DYNAMIC PERFORMANCE 2, 3 Signal-to-Noise and Distortion (SINAD) 4 Signal-to-Noise Ratio (SNR)4 Total Harmonic Distortion (THD)4 Peak Harmonic or Spurious Noise (SFDR)4 Intermodulation Distortion (IMD)4 Min Y Version Typ Max 69.5 70 70 71 −75.5 −77.5 −92 −88 −90 14 1.5 ±1 ±0.5 REFERENCE INPUT VREF Input Voltage Range DC Leakage Current VREF Input Capacitance Input Impedance dB dB dB dB dB dB dB MHz MHz 12 Differential Nonlinearity4 Offset Error4 Offset Error Matching Offset Temperature Drift Gain Error4 Gain Error Matching Gain Temperature Drift ANALOG INPUT Input Voltage Range DC Leakage Current Input Capacitance Test Conditions/Comments See the Sample Delay and Bit Trial Delay section, fIN = 10 kHz sine wave for fSCL from 1.7 MHz to 3.4 MHz fIN = 1 kHz sine wave for fSCL up to 400 kHz fa = 11 kHz, fb = 9 kHz for fSCL from 1.7 MHz to 3.4 MHz fa = 5.4 kHz, fb = 4.6 kHz for fSCL up to 400 kHz Second-Order Terms Third-Order Terms Channel-to-Channel Isolation4 Full-Power Bandwidth4 DC ACCURACY2, 5 Resolution Integral Nonlinearity4 Unit ±0.9 ±0.5 ±1 ±5 ±0.5 4.43 ±2 ±0.7 0.69 0 VREF ±1 Bits LSB LSB LSB LSB LSB LSB ppm/°C LSB LSB ppm/°C 34 V μA pF 4 pF 35 5 pF pF 1.2 VDD ±1 5 35 69 Rev. A | Page 3 of 28 V μA pF pF kΩ fIN = 10 kHz @ 3 dB @ 0.1 dB Guaranteed no missed codes to 12 bits VREF = VIN3/VREF or VDD Channel 0 to Channel 2—during acquisition phase Channel 0 to Channel 2—outside acquisition phase Channel 3—during acquisition phase Channel 3—outside acquisition phase Outside conversion phase During conversion phase AD7991/AD7995/AD7999 Parameter LOGIC INPUTS (SDA, SCL) Input High Voltage, VINH Y Version Typ Max Min 0.7 (VDD) 0.9 (VDD) Input Low Voltage, VINL Input Leakage Current, IIN Input Capacitance, CIN 6 Input Hysteresis, VHYST LOGIC OUTPUTS (OPEN DRAIN) Output Low Voltage, VOL 0.3 (VDD) 0.1 (VDD) ±1 10 0.1 (VDD) 0.4 0.6 ±1 10 Straight (natural) binary 18 × (1/fSCL) Floating-State Leakage Current Floating-State Output Capacitance6 Output Coding THROUGHPUT RATE Unit Test Conditions/Comments V V V V μA pF V VDD = 2.7 V to 5.5 V VDD = 2.35 V to 2.7 V VDD = 2.7 V to 5.5 V VDD = 2.35 V to 2.7 V VIN = 0 V or VDD V V μA pF ISINK = 3 mA ISINK = 6 mA fSCL ≤ 1.7 MHz; see the Serial Interface section fSCL > 1.7 MHz; see the Serial Interface section VREF = VDD; for fSCL = 3.4 MHz, clock stretching is implemented 17.5 × (1/fSCL) + 2 μs POWER REQUIREMENTS2 VDD IDD ADC Operating, Interface Active (Fully Operational) Power-Down, Interface Active 7 Power-Down, Interface Inactive7 Power Dissipation ADC Operating, Interface Active (Fully Operational) Power-Down, Interface Active7 Power-Down, Interface Inactive7 2.7 5.5 V 0.09/0.25 mA Digital inputs = 0 V or VDD VDD = 3.3 V/5.5 V, 400 kHz fSCL 0.25/0.8 0.07/0.16 0.26/0.85 1/1.6 mA mA mA μA VDD = 3.3 V/5.5 V, 3.4 MHz fSCL VDD = 3.3 V/5.5 V, 400 kHz fSCL VDD = 3.3 V/5.5 V, 3.4 MHz fSCL VDD = 3.3 V/5.5 V 0.3/1.38 mW VDD = 3.3 V/5.5 V, 400 kHz fSCL 0.83/4.4 0.24/0.88 0.86/4.68 3.3/8.8 mW mW mW μW VDD = 3.3 V/5.5 V, 3.4 MHz fSCL VDD = 3.3 V/5.5 V, 400 kHz fSCL VDD = 3.3 V/5.5 V, 3.4 MHz fSCL VDD = 3.3 V/5.5 V 1 Functional from VDD = 2.35 V. Sample delay and bit trial delay enabled, t1 = t2 = 0.5/fSCL. 3 For fSCL up to 400 kHz, clock stretching is not implemented. Above fSCL = 400 kHz, clock stretching is implemented. 4 See the Terminology section. 5 For fSCL ≤ 1.7 MHz, clock stretching is not implemented; for fSCL > 1.7 MHz, clock stretching is implemented. 6 Guaranteed by initial characterization. 7 See the Reading from the AD7991/AD7995/AD7999 section. 2 Rev. A | Page 4 of 28 AD7991/AD7995/AD7999 AD7995 1 The temperature range for the Y version is −40°C to +125°C. Unless otherwise noted, VDD = 2.7 V to 5.5 V, VREF = 2.5 V, fSCL = 3.4 MHz, and TA = TMIN to TMAX. Table 3. Parameter DYNAMIC PERFORMANCE 3 , 4 Min Signal-to-Noise and Distortion (SINAD) 5 Total Harmonic Distortion (THD)5 Peak Harmonic or Spurious Noise (SFDR)5 Intermodulation Distortion (IMD)5 REFERENCE INPUT VREF Input Voltage Range DC Leakage Current VREF Input Capacitance Input Impedance Min 61.5 61 Y Version Typ Max Unit Test Conditions/Comments See the Sample Delay and Bit Trial Delay section, fIN = 10 kHz sine wave for fSCL from 1.7 MHz to 3.4 MHz fIN = 1 kHz sine wave for fSCL up to 400 kHz dB −85 −75 dB −85 −76 dB fa = 11 kHz, fb = 9 kHz for fSCL from 1.7 MHz to 3.4 MHz fa = 5.4 kHz, fb = 4.6 kHz for fSCL up to 400 kHz Second-Order Terms Third-Order Terms Channel-to-Channel Isolation5 Full-Power Bandwidth5 DC ACCURACY3, 6 Resolution Integral Nonlinearity5 Differential Nonlinearity5 Offset Error5 Offset Error Matching Offset Temperature Drift Gain Error5 Gain Error Matching Gain Temperature Drift ANALOG INPUT Input Voltage Range DC Leakage Current Input Capacitance A Version 2 Typ Max −90 −86 −90 −90 −86 −90 dB dB dB fIN = 10 kHz 14 1.5 14 1.5 MHz MHz @ 3 dB @ 0.1 dB 10 10 ±0.4 ±0.4 ±0.4 ±0.4 ±1.5 ±0.2 ±1 ±0.04 4.13 ±0.15 ±0.06 0.50 0 4.13 ±0.5 ±0.25 0.50 VREF ±1 34 34 V μA pF 4 4 pF 35 5 35 5 pF pF 1.2 VDD ±1 5 35 69 0 VREF ±1 Bits LSB LSB LSB LSB ppm/°C LSB LSB ppm/°C 1.2 VDD ±1 5 35 69 Rev. A | Page 5 of 28 V μA pF pF kΩ Guaranteed no missed codes to 10 bits VREF = VIN3/VREF or VDD Channel 0 to Channel 2—during acquisition phase Channel 0 to Channel 2—outside acquisition phase Channel 3—during acquisition phase Channel 3—outside acquisition phase Outside conversion phase During conversion phase AD7991/AD7995/AD7999 Parameter LOGIC INPUTS (SDA, SCL) Input High Voltage, VINH Min 0.7 (VDD) Input Low Voltage, VINL Input Leakage Current, IIN Input Capacitance, CIN 7 Input Hysteresis, VHYST LOGIC OUTPUTS (OPEN DRAIN) Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance7 Output Coding THROUGHPUT RATE A Version 2 Typ Max Min Y Version Typ Max 0.7 (VDD) 0.9 (VDD) 0.3 (VDD) 0.3 (VDD) 0.1 (VDD) ±1 10 ±1 10 0.1 (VDD) 0.1 (VDD) Unit Test Conditions/Comments V V V V μA pF V VDD = 2.7 V to 5.5 V VDD = 2.35 V to 2.7 V VDD = 2.7 V to 5.5 V VDD = 2.35 V to 2.7 V VIN = 0 V or VDD ISINK = 3 mA ISINK = 6 mA 0.4 0.6 ±1 0.4 0.6 ±1 V V μA 10 10 pF Straight (natural) binary 18 × (1/fSCL) 17.5 × (1/fSCL) + 2 μs Straight (natural) binary 18 × (1/fSCL) 17.5 × (1/fSCL) + 2 μs fSCL ≤ 1.7 MHz; see the Serial Interface section fSCL > 1.7 MHz; see the Serial Interface section POWER REQUIREMENTS3 VDD IDD ADC Operating, Interface Active (Fully Operational) VREF = VDD; for fSCL = 3.4 MHz, clock stretching is implemented 2.7 5.5 5.5 V 0.09/0.25 mA Digital inputs = 0 V or VDD VDD = 3.3 V/5.5 V, 400 kHz fSCL 0.26 1 0.25/0.8 0.07/0.16 0.26/0.85 1/1.6 mA mA mA μA VDD = 3.3 V/5.5 V, 3.4 MHz fSCL VDD = 3.3 V/5.5 V, 400 kHz fSCL VDD = 3.3 V/5.5 V, 3.4 MHz fSCL VDD = 3.3 V/5.5 V 0.83 0.3/1.38 0.83/4.4 mW mW VDD = 3.3 V/5.5 V, 400 kHz fSCL VDD = 3.3 V/5.5 V, 3.4 MHz fSCL 0.86 3.3 0.24/0.88 0.86/4.68 3.3/8.8 mW mW μW VDD = 3.3 V/5.5 V, 400 kHz fSCL VDD = 3.3 V/5.5 V, 3.4 MHz fSCL VDD = 3.3 V/5.5 V 0.25 Power-Down, Interface Active 8 Power-Down, Interface Inactive8 Power Dissipation ADC Operating, Interface Active (Fully Operational) Power-Down, Interface Active8 Power-Down, Interface Inactive8 2.7 1 Functional from VDD = 2.35 V. A Version tested at VDD = 3.3 V and fSCL = 3.4 MHz. Functionality tested at fSCL = 400 kHz. Sample delay and bit trial delay enabled, t1 = t2 = 0.5/fSCL. 4 For fSCL up to 400 kHz, clock stretching is not implemented. Above fSCL = 400 kHz, clock stretching is implemented. 5 See the Terminology section. 6 For fSCL ≤ 1.7 MHz, clock stretching is not implemented; for fSCL > 1.7 MHz, clock stretching is implemented. 7 Guaranteed by initial characterization. 8 See the Reading from the AD7991/AD7995/AD7999 section. 2 3 Rev. A | Page 6 of 28 AD7991/AD7995/AD7999 AD7999 1 The temperature range for the Y version is −40°C to +125°C. Unless otherwise noted, VDD = 2.7 V to 5.5 V, VREF = 2.5 V, fSCL = 3.4 MHz, and TA = TMIN to TMAX. Table 4. Parameter DYNAMIC PERFORMANCE 3 , 4 Min Signal-to-Noise and Distortion (SINAD) 5 Total Harmonic Distortion (THD)5 Peak Harmonic or Spurious Noise (SFDR)5 Intermodulation Distortion (IMD)5 49.5 REFERENCE INPUT VREF Input Voltage Range DC Leakage Current VREF Input Capacitance Input Impedance Min Y Version Typ Max 49.5 Unit Test Conditions/Comments See the Sample Delay and Bit Trial Delay section, fIN = 10 kHz sine wave for fSCL from 1.7 MHz to 3.4 MHz fIN = 1 kHz sine wave for fSCL up to 400 kHz dB −65 −65 dB −65 −65 dB fa = 11 kHz, fb = 9 kHz for fSCL from 1.7 MHz to 3.4 MHz fa = 5.4 kHz, fb = 4.6 kHz for fSCL up to 400 kHz Second-Order Terms Third-Order Terms Channel-to-Channel Isolation5 Full-Power Bandwidth5 DC ACCURACY3, 6 Resolution Integral Nonlinearity5 Differential Nonlinearity5 Offset Error5 Offset Error Matching Offset Temperature Drift Gain Error5 Gain Error Matching Gain Temperature Drift ANALOG INPUT Input Voltage Range DC Leakage Current Input Capacitance A Version 2 Typ Max −83 −75 −90 −83 −75 −90 dB dB dB fIN = 10 kHz 14 1.5 14 1.5 MHz MHz @ 3 dB @ 0.1 dB 8 8 ±0.04 ±0.05 ±0.3 ±0.02 4.26 ±0.06 ±0.03 0.59 0 ±0.1 ±0.1 ±0.35 ±0.05 4.26 ±0.175 ±0.06 0.59 VREF ±1 0 34 4 35 5 1.2 34 4 35 5 VDD ±1 5 35 69 VREF ±1 1.2 VDD ±1 5 35 69 Rev. A | Page 7 of 28 Bits LSB LSB LSB LSB ppm/°C LSB LSB ppm/°C V μA pF pF pF pF V μA pF pF kΩ Guaranteed no missed codes to eight bits VREF = VIN3/VREF or VDD Channel 0 to Channel 2—during acquisition phase Channel 0 to Channel 2—outside acquisition phase Channel 3—during acquisition phase Channel 3—outside acquisition phase Outside conversion phase During conversion phase AD7991/AD7995/AD7999 Parameter LOGIC INPUTS (SDA, SCL) Input High Voltage, VINH Min 0.7 (VDD) Input Low Voltage, VINL Input Leakage Current, IIN Input Capacitance, CIN 7 Input Hysteresis, VHYST LOGIC OUTPUTS (OPEN DRAIN) Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance7 Output Coding THROUGHPUT RATE A Version 2 Typ Max Y Version Typ Max Min 0.7 (VDD) 0.9 (VDD) 0.3 (VDD) 0.3 (VDD) 0.1 (VDD) ±1 10 ±1 10 0.1 (VDD) 0.1 (VDD) Unit Test Conditions/Comments V V V V μA pF V VDD = 2.7 V to 5.5 V VDD = 2.35 V to 2.7 V VDD = 2.7 V to 5.5 V VDD = 2.35 V to 2.7 V VIN = 0 V or VDD ISINK = 3 mA ISINK = 6 mA 0.4 0.6 ±1 0.4 0.6 ±1 V V μA 10 10 pF Straight (natural) binary 18×(1/fSCL) 17.5×(1/fSCL) + 2 μs Straight (natural) binary 18×(1/fSCL) 17.5×(1/fSCL) + 2 μs fSCL ≤ 1.7 MHz; see the Serial Interface section fSCL > 1.7 MHz; see the Serial Interface section POWER REQUIREMENTS3 VDD IDD ADC Operating, Interface Active (Fully Operational) Power-Down, Interface Active 8 Power-Down , Interface Inactive8 Power Dissipation ADC Operating, Interface Active (Fully Operational) Power-Down, Interface Active8 Power-Down , Interface Inactive8 VREF = VDD; for fSCL = 3.4 MHz, clock stretching is implemented 2.7 5.5 2.7 5.5 V 0.25 0.09/0.25 0.25/0.8 mA mA Digital inputs = 0 V or VDD VDD = 3.3 V/5.5 V, 400 kHz fSCL VDD = 3.3 V/5.5 V, 3.4 MHz fSCL 0.26 1 0.07/0.16 0.26/0.85 1/1.6 mA mA μA VDD = 3.3 V/5.5 V, 400 kHz fSCL VDD = 3.3 V/5.5 V, 3.4 MHz fSCL VDD = 3.3 V/5.5 V 0.83 0.3/1.38 0.83/4.4 mW mW VDD = 3.3 V/5.5 V, 400 kHz fSCL VDD = 3.3 V/5.5 V, 3.4 MHz fSCL 0.86 3.3 0.24/0.88 0.86/4.68 3.3/8.8 mW mW μW VDD = 3.3 V/5.5 V, 400 kHz fSCL VDD = 3.3 V/5.5 V, 3.4 MHz fSCL VDD = 3.3 V/5.5 V 1 Functional from VDD = 2.35 V. A Version tested at VDD=3.3 V and fSCL= 3.4 MHz. Functionality tested at fSCL = 400 kHz. 3 Sample delay and bit trial delay enabled, t1 = t2 = 0.5/fSCL. 4 For fSCL up to 400 kHz, clock stretching is not implemented. Above fSCL = 400 kHz, clock stretching is implemented. 5 See the Terminology section. 6 For fSCL ≤ 1.7 MHz, clock stretching is not implemented; for fSCL > 1.7 MHz, clock stretching is implemented. 7 Guaranteed by initial characterization. 8 See the Reading from the AD7991/AD7995/AD7999 section. 2 Rev. A | Page 8 of 28 AD7991/AD7995/AD7999 I2C TIMING SPECIFICATIONS Guaranteed by initial characterization. All values were measured with the input filtering enabled. CB refers to the capacitive load on the bus line, with tr and tf measured between 0.3 VDD and 0.7 VDD (see Figure 2). Unless otherwise noted, VDD = 2.7 V to 5.5 V and TA = TMIN to TMAX. Table 5. Parameter fSCL 1 t11 t21 t31 t41, 2 t51 t61 t71 t81 t9 Conditions Standard mode Fast mode High speed mode CB = 100 pF maximum CB = 400 pF maximum Standard mode Fast mode High speed mode CB = 100 pF maximum CB = 400 pF maximum Standard mode Fast mode High speed mode CB = 100 pF maximum CB = 400 pF maximum Standard mode Fast mode High speed mode Standard mode Fast mode High Speed mode CB = 100 pF maximum CB = 400 pF maximum Standard mode Fast mode High Speed mode Standard mode Fast mode High speed mode Standard mode Fast mode Standard mode Fast mode High speed mode Standard mode Fast mode High speed mode CB = 100 pF maximum CB = 400 pF maximum Min Limit at tMIN, tMAX Typ Max 100 400 3.4 1.7 Unit kHz kHz 4 0.6 MHz MHz μs μs 60 120 4.7 1.3 ns ns μs μs 160 320 250 100 10 0 0 ns ns ns ns ns μs μs 0 0 4.7 0.6 160 4 0.6 160 4.7 1.3 4 0.6 160 3.45 0.9 70 3 150 20 + 0.1 CB 1000 300 ns ns μs μs ns μs μs ns μs μs μs μs ns ns ns 10 20 80 160 ns ns Rev. A | Page 9 of 28 Description Serial clock frequency tHIGH, SCL high time tLOW, SCL low time tSU;DAT, data setup time tHD;DAT, data hold time tSU;STA, setup time for a repeated start condition tHD;STA, hold time for a repeated start condition tBUF, bus-free time between a stop and a start condition tSU;STO, setup time for a stop condition tRDA, rise time of the SDA signal AD7991/AD7995/AD7999 Parameter t10 t11 t11A Conditions Standard mode Fast mode High speed mode CB = 100 pF maximum CB = 400 pF maximum Standard mode Fast mode High speed mode CB = 100 pF maximum CB = 400 pF maximum Standard mode Fast mode High speed mode CB = 100 pF maximum CB = 400 pF maximum Standard mode Fast mode High speed mode CB = 100 pF maximum CB = 400 pF maximum Fast mode High speed mode t12 tSP1 Limit at tMIN, tMAX Typ Max 300 20 + 0.1 CB 300 Min 10 20 Unit ns ns 80 160 1000 300 ns ns ns ns 40 80 1000 ns ns ns 20 + 0.1 CB 300 ns 10 20 20 + 0.1 CB 80 160 300 300 ns ns ns ns 10 20 0 0 40 80 50 10 ns ns ns ns μs 20 + 0.1 CB 10 20 tPOWER-UP 0.6 Description tFDA, fall time of the SDA signal tRCL, rise time of the SCL signal tRCL1, rise time of the SCL signal after a repeated start condition and after an acknowledge bit tFCL, fall time of the SCL signal Pulse width of the suppressed spike Power-up and acquisition time 1 Functionality is tested during production. A device must provide a data hold time for SDA in order to bridge the undefined region of the SCL falling edge. 3 For 3 V supplies, the maximum hold time with CB = 100 pF maximum is 100 ns maximum. 2 t11 t12 t2 t6 SCL t6 t4 t3 t5 t1 t8 t9 t10 SDA t7 P S S 06461-002 S = START CONDITION P = STOP CONDITION P Figure 2. 2-Wire Serial Interface Timing Diagram Rev. A | Page 10 of 28 AD7991/AD7995/AD7999 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 6. Parameter VDD to GND Analog Input Voltage to GND Reference Input Voltage to GND Digital Input Voltage to GND Digital Output Voltage to GND Input Current to Any Pin Except Supplies 1 Operating Temperature Ranges Industrial (Y Version) Temperature Range Storage Temperature Range Junction Temperature 8-Lead SOT-23 Package θJA Thermal Impedance θJC Thermal Impedance RoHS Compliant Temperature, Soldering Reflow ESD 1 Rating −0.3 V to 7 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to +7 V −0.3 V to VDD + 0.3 V ±10 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION −40°C to +125°C −65°C to +150°C 150°C 170°C/W 90°C/W 260 + 0°C 1 kV Transient currents of up to 100 mA do not cause SCR latch-up. Rev. A | Page 11 of 28 AD7991/AD7995/AD7999 SCL 1 SDA 2 VIN0 3 VIN1 4 AD7991/ AD7995/ AD7999 TOP VIEW (Not to Scale) 8 VDD 7 GND 6 VIN3/VREF 5 VIN2 06461-003 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3. SOT-23 Pin Configuration Table 7. Pin Function Descriptions Pin No. 1 2 3 4 5 6 Mnemonic SCL SDA VIN0 VIN1 VIN2 VIN3/VREF 7 GND 8 VDD Description Digital Input. Serial bus clock. External pull-up resistor required. Digital I/O. Serial bus bidirectional data. Open-drain output. External pull-up resistor required. Analog Input 1. Single-ended analog input channel. The input range is 0 V to VREF. Analog Input 2. Single-ended analog input channel. The input range is 0 V to VREF. Analog Input 3. Single-ended analog input channel. The input range is 0 V to VREF. Analog Input 4. Single-ended analog input channel. The input range is 0 V to VREF. Can also be used to input an external VREF signal. Analog Ground. Ground reference point for all circuitry on the AD7991/AD7995/AD7999. All analog input signals should be referred to this AGND voltage. Power Supply Input. The VDD range for the AD7991/AD7995/AD7999 is from 2.7 V to 5.5 V. Table 8. I2C Address Selection Part Number AD7991-0 AD7991-1 AD7995-0 AD7995-1 AD7999-1 I2C Address 010 1000 010 1001 010 1000 010 1001 010 1001 Rev. A | Page 12 of 28 AD7991/AD7995/AD7999 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 1.0 VDD = 2.7V VREF = 2.35V fSCL = 1.7MHz 0.8 0.6 0.4 0 –0.2 0.2 0 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 0 500 1000 1500 2000 2500 3000 3500 4000 CODE –1.0 1.2 NEGATIVE INL 1.7 2.2 2.7 3.2 3.7 4.2 4.7 REFERENCE VOLTAGE (V) Figure 4. DNL Error, VDD = 2.7 V, VREF = 2.35 V, fSCL = 1.7 MHz Without Clock Stretching 06461-033 INL ERROR (LSB) 0.2 –1.0 POSITIVE INL 0.4 06461-005 DNL ERROR (LSB) 0.6 0.8 Figure 7. INL Error vs. Reference Voltage , fSCL = 1.7 MHz Without Clock Stretching 1.0 1.0 VDD = 2.7V VREF = 2.35V fSCL = 1.7MHz 0.8 0.6 0.8 0.6 0.2 0 –0.2 –0.4 0.2 0 –0.4 –0.6 –0.8 –0.8 500 1000 1500 2000 2500 3000 3500 4000 CODE –1.0 1.2 06461-006 0 11.5 2.2 2.7 3.2 3.7 4.2 4.7 Figure 8. DNL Error vs. Reference Voltage, fSCL = 1.7 MHz Without Clock Stretching 74 ENOB VDD = 5V 1.7 REFERENCE VOLTAGE (V) Figure 5. INL Error, VDD = 2.7 V, VREF = 2.35 V, fSCL = 1.7 MHz Without Clock Stretching 12.0 NEGATIVE DNL –0.2 –0.6 –1.0 1.0 0.8 ENOB VDD = 3V 72 SINAD VDD = 5V 0.6 11.0 70 10.0 66 9.5 INL ERROR (LSB) 68 SINAD VDD = 3V 0.4 SINAD (dB) 10.5 0.2 0 –0.2 –0.4 64 9.0 –0.6 –0.8 8.0 60 0 1 2 3 4 5 6 REFERENCE VOLTAGE (V) Figure 6. ENOB/SINAD vs. Reference Voltage, fSCL = 1.7 MHz Without Clock Stretching –1.0 0 500 1000 1500 2000 2500 3000 3500 CODE Figure 9. INL Error, VDD = 5 V, VREF = 2.5 V, fSCL = 1.7 MHz Without Clock Stretching Rev. A | Page 13 of 28 4000 06461-013 VDD = 5V VREF = 2.5V fSCL = 1.7MHz 62 8.5 06461-036 ENOB (Bits) 0.4 06461-037 DNL ERROR (LSB) INL ERROR (LSB) POSITIVE DNL 0.4 AD7991/AD7995/AD7999 1.0 –70 fSCL = 1.7MHz 0.8 0.4 –80 0.2 VDD = 5V THD (dB) DNL ERROR (LSB) 0.6 0 –0.2 VDD = 3V –90 –0.4 –0.6 0 500 1000 1500 2000 2500 3000 3500 4000 CODE –100 06461-014 –1.0 1 Figure 13. THD vs. Input Frequency, VREF = 2.5 V, fSCL = 1.7 MHz Without Clock Stretching Figure 10. DNL Error, VDD = 5 V, VREF = 2.5 V, fSCL = 1.7 MHz Without Clock Stretching 800 96 +125°C +85°C +25°C –40°C 600 400 0 2 3 4 5 6 VDD (V) VDD = 3V 94 93 92 VDD = 5V 91 90 89 06461-035 200 95 VREF = VDD fSCL = 1.7MHz TEMPERATURE = T A 0 10 20 30 40 50 60 Figure 11. IDD Supply Current vs. Supply Voltage, fSCL = 1.7 MHz Without Clock Stretching, −40°C to +125°C 80 90 100 Figure 14. AD7991 Channel-to-Channel Isolation , fSCL = 1.7 MHz Without Clock Stretching 1000 0 fSCL = 3.4MHz +125°C +85°C +25°C –40°C 800 16384 POINT FFT fS = 22.5kSPS fSCL = 405kHz fIN = 5.13kHz SNR = 71.83dB SINAD = 71.39dB THD = –81.26dB SFDR = –93.71dB –20 –40 SINAD (dB) 600 400 –60 –80 200 0 2 3 4 5 6 VDD (V) –120 0 2 4 6 8 10 FREQUENCY (kHz) Figure 15. Dynamic Performance, fSCL = 405 kHz Without Clock Stretching, VDD = 5 V, Full-Scale Input, Seven-Term Blackman-Harris Window Figure 12. IDD Supply Current vs. Supply Voltage, f SCL = 3.4 MHz with Clock Stretching, −40°C to +125°C Rev. A | Page 14 of 28 06461-018 –100 06461-034 IDD (μA) 70 fNOISE (kHz) 06461-017 CHANNEL-TO-CHANNEL ISOLATION (dB) fSCL = 1.7MHz IDD (μA) 100 10 INPUT FREQUENCY (kHz) 06461-031 VDD = 5V VREF = 2.5V fSCL = 1.7MHz –0.8 AD7991/AD7995/AD7999 3 0 16384 POINT FFT fS = 95kSPS fSCL = 1.71MHz fIN = 10.13kHz SNR = 71.77dB SINAD = 71.45dB THD = –82.43dB SFDR = –95.02dB 2 –60 –80 VDD = 5V 1 –120 0 5 10 15 20 25 30 35 40 FREQUENCY (kHz) 45 Figure 16. Dynamic Performance, fSCL = 1.71 MHz Without Clock Stretching, VDD = 5 V, Full-Scale Input, Seven-Term Blackman-Harris Window 0 0 500 1000 1500 SCL FREQUENCY (kHz) Figure 17. Power vs. SCL Frequency, VREF = 2.5 V Rev. A | Page 15 of 28 06461-032 VDD = 3V –100 06461-019 SINAD (dB) –40 POWER (mW) –20 AD7991/AD7995/AD7999 TERMINOLOGY Signal-to-Noise and Distortion (SINAD) Ratio The measured ratio of signal-to-noise and distortion at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of the nonfundamental signals excluding dc, up to half the sampling frequency (fS/2). The ratio is dependent on the number of quantization levels in the digitization process: the more levels, the smaller the quantization noise. The theoretical SINAD ratio for an ideal N-bit converter with a sine wave input is given by Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB Therefore, SINAD is 49.92 dB for an 8-bit converter, 61.96 dB for a 10-bit converter, and 74 dB for a 12-bit converter. Total Harmonic Distortion (THD) The ratio of the rms sum of harmonics to the fundamental. For the AD7991/AD7995/AD7999, it is defined as THD (dB) = 20 log in frequency from the original sine waves, and the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of intermodulation distortion is, like the THD specification, the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals, expressed in decibels. Channel-to-Channel Isolation Channel-to-channel isolation is a measure of the level of crosstalk between any two channels. It is measured by applying a full-scale sine wave signal to all unselected input channels and then determining the degree to which the signal attenuates in the selected channel with a 10 kHz signal. The frequency of the signal in each of the unselected channels is increased from 2 kHz up to 92 kHz. Figure 14 shows the worst-case across all four channels for the AD7991. Full-Power Bandwidth The input frequency at which the amplitude of the reconstructed fundamental is reduced by 0.1 dB or 3 dB for a full-scale input. V2 2 + V3 2 + V4 2 + V5 2 + V6 2 V1 where: V1 is the rms amplitude of the fundamental. V2, V3, V4, V5, and V6 are the rms amplitudes of the second through sixth harmonics. Peak Harmonic or Spurious Noise The ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Typically, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, the largest harmonic may be a noise peak. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n equals 0. For example, second-order terms include (fa + fb) and (fa − fb), and third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb). The AD7991/AD7995/AD7999 are tested using the CCIF standard, where two input frequencies near the maximum input bandwidth are used. In this case, the second-order terms are usually distanced Integral Nonlinearity The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints are at zero scale (a point 1 LSB below the first code transition) and full scale (a point 1 LSB above the last code transition). Differential Nonlinearity The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Offset Error The deviation of the first code transition (00 … 000 to 00 … 001) from the ideal—that is, AGND + 1 LSB. Offset Error Match The difference in offset error between any two channels. Gain Error The deviation of the last code transition (111 … 110 to 111 … 111) from the ideal (that is, VREF − 1 LSB) after the offset error has been adjusted out. Gain Error Match The difference in gain error between any two channels. Rev. A | Page 16 of 28 AD7991/AD7995/AD7999 THEORY OF OPERATION The AD7991/AD7995/AD7999 provide the user with a 4-channel multiplexer, an on-chip track-and-hold, an ADC, and an I2Ccompatible serial interface, all housed in an 8-lead SOT-23 package that offers the user considerable space-saving advantages over alternative solutions. The AD7991/AD7995/AD7999 normally remains in a powerdown state while not converting. Therefore, when supplies are first applied, the part is in a power-down state. Power-up is initiated prior to a conversion, and the device returns to the power-down state upon completion of the conversion. This automatic powerdown feature allows the device to save power between conversions. This means any read or write operations across the I2C interface can occur while the device is in power-down. When the ADC starts a conversion, as shown in Figure 19, SW2 opens and SW1 moves to Position B, causing the comparator to become unbalanced. The input is disconnected when the conversion begins. The control logic and the capacitive DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC output code. Figure 20 shows the ADC transfer function. CAPACITIVE DAC A VIN B SW2 Figure 19. ADC Conversion Phase ADC Transfer Function The AD7991/AD7995/AD7999 are successive approximation ADCs built around a capacitive DAC. Figure 18 and Figure 19 show simplified schematics of the ADC during its acquisition and conversion phases, respectively. Figure 18 shows the ADC during its acquisition phase: SW2 is closed, SW1 is in Position A, the comparator is held in a balanced condition, and the sampling capacitor acquires the signal on VIN. The source driving the analog input needs to settle the analog input signal to within one LSB in 0.6 μs, which is equivalent to the duration of the power-up and acquisition time. The output coding of the AD7991/AD7995/AD7999 is straight binary. The designed code transitions occur at successive integer LSB values (that is, 1 LSB, 2 LSB, and so on). The LSB size for the AD7991/AD7995/AD7999 is VREF/4096, VREF/1024, and VREF/256, respectively. Figure 20 shows the ideal transfer characteristics for the AD7991/AD7995/AD7999. A COMPARATOR AGND AD7991 1 LSB = REF IN/4096 AD7995 1 LSB = REF IN/1024 AD7999 1 LSB = REF IN/256 AGND + 1 LSB 06461-020 B 011 ... 111 000 ... 010 000 ... 001 000 ... 000 CONTROL LOGIC SW1 111 ... 000 +REFIN – 1 LSB ANALOG INPUT 0V TO REFIN 06461-022 ADC CODE 111 ... 111 111 ... 110 CAPACITIVE DAC SW2 COMPARATOR AGND CONVERTER OPERATION VIN CONTROL LOGIC SW1 06461-021 The AD7991/AD7995/AD7999 are low power, 12-/10-/8-bit, single-supply, 4-channel ADCs. Each part can be operated from a single 2.35 V to 5.5 V supply. Figure 20. AD7991/AD7995/AD7999 Transfer Characteristics Figure 18. ADC Acquisition Phase Rev. A | Page 17 of 28 AD7991/AD7995/AD7999 TYPICAL CONNECTION DIAGRAM ANALOG INPUT Figure 22 shows the typical connection diagram for the AD7991/AD7995/AD7999. Figure 21 shows an equivalent circuit of the AD7991/AD7995/ AD7999 analog input structure. The two diodes, D1 and D2, provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signal does not exceed the supply rails by more than 300 mV. If the signal does exceed this level, the diodes become forward-biased and start conducting current into the substrate. Each diode can conduct a maximum current of 10 mA without causing irreversible damage to the part. The reference voltage can be taken from the supply voltage, VDD. However, the AD7991/AD7995/AD7999 can be configured to be a 3-channel device with the reference voltage applied to the VIN3/VREF pin. In this case, a 1 μF decoupling capacitor on the VIN3/VREF pin is recommended. SDA and SCL form the 2-wire I2C compatible interface. External pull-up resistors are required for both the SDA and SCL lines. VDD The AD7991-0/AD7995-0 and the AD7991-1/AD7995-1/ AD7999-1 support standard, fast, and high speed I2C interface modes. Both the -0 and -1 devices have independent I2C addresses, which allows the devices to connect to the same I2C bus without contention issues. D1 VIN C1 4pF + Figure 21. Equivalent Analog Input Circuit Capacitor C1 in Figure 21 is typically about 4 pF and can primarily be attributed to pin capacitance. Resistor R1 is a lumped component composed of the on resistance (RON) of both a track-and-hold switch and the input multiplexer. The total resistor is typically about 400 Ω. Capacitor C2, the ADC sampling capacitor, has a typical capacitance of 30 pF. 5V SUPPLY + RP VIN2 VIN3/VREF GND AD7991/ AD7995/ AD7999 RP 2-WIRE SERIAL INTERFACE SDA SCL MICROCONTROLLER/ MICROPROCESSOR 06461-024 VDD VIN1 D2 CONVERSION PHASE—SWITCH OPEN TRACK PHASE—SWITCH CLOSED 0.1µF VIN0 C2 30pF 06461-023 The part requires approximately 0.6 μs to wake up from powerdown and to acquire the analog input. Once the acquisition phase ends, the conversion phase starts and takes approximately 1 μs to complete. The AD7991/AD7995/AD7999 enters shutdown mode after each conversion, which is useful in applications where power consumption is a concern. 10µF R1 Figure 22. AD7991/AD7995/AD7999 Typical Connection Diagram Rev. A | Page 18 of 28 AD7991/AD7995/AD7999 VDD = 5V VREF = VDD TEMPERATURE = TA fSCL = 1.7MHz –20 –30 –40 –50 5.1kΩ –60 2kΩ –70 1.3kΩ –80 240Ω –90 56Ω –100 1 10 ANALOG INPUT FREQUENCY (kHz) 100 06461-025 When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum source impedance depends on the amount of THD that can be tolerated. THD increases as the source impedance increases and performance degrades. Figure 23 shows the THD vs. the analog input signal frequency for different source impedances at a supply voltage of 5 V. 0 –10 THD (dB) For ac applications, removing high frequency components from the analog input signal is recommended by use of an RC bandpass filter on the relevant analog input pin. In applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances significantly affect the ac performance of the ADC. This may necessitate the use of an input buffer amplifier. The choice of the op amp is a function of the particular application. Figure 23. THD vs. Analog Input Frequency for Various Source Impedances for VDD = 5 V, fSCL = 1.7 MHz Without Clock Stretching Rev. A | Page 19 of 28 AD7991/AD7995/AD7999 INTERNAL REGISTER STRUCTURE CONFIGURATION REGISTER The configuration register is an 8-bit write-only register that is used to set the operating modes of the AD7991/AD7995/AD7999. The bit functions are outlined in Table 10. A single-byte write is necessary when writing to the configuration register. D7 is the MSB. When the master writes to the AD7991/AD7995/AD7999, the first byte is written to the configuration register. Table 9. Configuration Register Bit Map and Default Settings at Power-Up D7 CH3 1 D6 CH2 1 D5 CH1 1 D4 CH0 1 D3 REF_SEL 0 D2 FLTR 0 D1 Bit trial delay 0 D0 Sample delay 0 Table 10. Bit Function Descriptions Bit D7 to D4 Mnemonic CH3 to CH0 D3 REF_SEL D2 FLTR D1 D0 Bit trial delay Sample delay Comment These four channel address bits select the analog input channel(s) to be converted. If a channel address bit (Bit D7 to Bit D4) is set to 1, a channel is selected for conversion. If more than one channel bit is set to 1, the AD7991/AD7995/AD7999 sequence through the selected channels, starting with the lowest channel. All unused channels should be set to 0. Table 11 shows how these four channel address bits are decoded. Prior to the device initiating a conversion, the channel(s) must be selected in the configuration register. This bit allows the user to select the supply voltage as the reference or choose to use an external reference. If this bit is 0, the supply is used as the reference, and the device acts as a 4-channel input part. If this bit is set to 1, an external reference must be used and applied to the VIN3/VREF pin, and the device acts as a 3-channel input part. The value written to this bit of the control register determines whether the filtering on SDA and SCL is enabled or bypassed. If this bit is set to 0, the filtering is enabled; if it set to 1, the filtering is bypassed. See the Sample Delay and Bit Trial Delay section. See the Sample Delay and Bit Trial Delay section. Table 11. Channel Selection D7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 D6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Analog Input Channel 1 No channel selected Convert on VIN0 Convert on VIN1 Sequence between VIN0 and VIN1 Convert on VIN2 Sequence between VIN0 and VIN2 Sequence between VIN1 and VIN2 Sequence among VIN0, VIN1, and VIN2 Convert on VIN3 Sequence between VIN0 and VIN3 Sequence between VIN1 and VIN3 Sequence among VIN0, VIN1, and VIN3 Sequence between VIN2 and VIN3 Sequence among VIN0, VIN2, and VIN3 Sequence among VIN1, VIN2, and VIN3 Sequence among VIN0, VIN1, VIN2, and VIN3 The AD7991/AD7995/AD7999 converts on the selected channel in the sequence in ascending order, starting with the lowest channel in the sequence. Rev. A | Page 20 of 28 AD7991/AD7995/AD7999 SAMPLE DELAY AND BIT TRIAL DELAY CONVERSION RESULT REGISTER 2 It is recommended that no I C bus activity occur while a conversion is taking place (see Figure 27 and the Placing the AD7991/AD7995/AD7999 into High Speed Mode section). However, if this is not always possible, then in order to maintain the performance of the ADC, Bits D0 and D1 in the configuration register are used to delay critical sample intervals and bit trials from occurring while there is activity on the I2C bus. This results in a quiet period for each bit decision. However, the sample delay protection may introduce excessive jitter, degrading the SNR for large signals above 300 Hz. For guaranteed ac performance, use of clock stretching is recommended. When Bit D0 and Bit D1 are both 0, the bit trial and sample interval delay mechanism is implemented. The default setting of D0 and D1 is 0. To turn off both delay mechanisms, set D0 and D1 to 1. The conversion result register is a 16-bit read-only register that stores the conversion result from the ADC in straight binary format. A 2-byte read is necessary to read data from this register. Table 12 shows the contents of the first byte to be read from AD7991/AD7995/AD7999, and Table 13 shows the contents of the second byte to be read. Each AD7991/AD7995/AD7999 conversion result consists of two leading 0s, two channel identifier bits, and the 12-/10-/8-bit data result. For the AD7995, the two LSBs (D1 and D0) of the second read contain two trailing 0s. For the AD7999, the four LSBs (D3, D2, D1, and D0) of the second read contain four trailing 0s. Table 12. Conversion Value Register (First Read) D15 Leading 0 D14 Leading 0 D13 CHID1 D12 CHID0 D11 MSB D10 B10 D9 B9 D8 B8 D3 B3/0 D2 B2/0 D1 B1/0 D0 B0/0 Table 13. Conversion Value Register (Second Read) D7 B7 D6 B6 D5 B5 D4 B4 Rev. A | Page 21 of 28 AD7991/AD7995/AD7999 SERIAL INTERFACE Control of the AD7991/AD7995/AD7999 is accomplished via the I2C-compatible serial bus. The AD7991/AD7995/AD7999 is connected to this bus as a slave device under the control of a master device, such as the processor. 4. Data is sent over the serial bus in sequences of nine clock pulses—eight bits of data followed by an acknowledge bit from the receiver of data. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period because a low-to-high transition when the clock is high may be interpreted as a stop signal. 5. When all data bytes have been read or written, stop conditions are established. In write mode, the master pulls the data line high during the 10th clock pulse to assert a stop condition. In read mode, the master device pulls the data line high during the low period before the ninth clock pulse. This is known as a no acknowledge. The master takes the data line low during the low period before the 10th clock pulse, and then high during the 10th clock pulse to assert a stop condition. 6. Any number of bytes of data can be transferred over the serial bus in one operation, but it is not possible to mix reads and writes in one operation because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation. SERIAL BUS ADDRESS Like all I2C-compatible devices, the AD7991/AD7995/AD7999 has a 7-bit serial address. The devices are available in two versions, the AD7991-0/AD7995-0 and the AD7991-1/AD7995-1/AD7999-1. Each version has a different address (see Table 8), which allows up to two AD7991/AD7995 devices to be connected to a single serial bus. AD7999 has only one version. The serial bus protocol operates as follows: 1. The master initiates a data transfer by establishing a start condition, defined as a high-to-low transition on the serial data line SDA while the serial clock line, SCL, remains high. This indicates that an address/data stream follows. 2. All slave peripherals connected to the serial bus respond to the start condition and shift in the next eight bits, consisting of a 7-bit address (MSB first) plus an R/W bit that determines the direction of the data transfer—that is, whether data is written to or read from the slave device. 3. The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit. All other devices on the bus remain idle while the selected device waits for data to be read from or written to it. If the R/W bit is set to 0, the master writes to the slave device. If the R/W bit is set to 1, the master reads from the slave device. Rev. A | Page 22 of 28 AD7991/AD7995/AD7999 WRITING TO THE AD7991/AD7995/AD7999 By default, each part operates in read-only mode and all four channels are selected as enabled in the configuration register. To write to the AD7991/AD7995/AD7999 configuration register, the user must first address the device. 1 The configuration register is an 8-bit register; therefore, only one byte of data can be written to this register. However, writing a single byte of data to this register consists of writing the serial bus write address, followed by the data byte written (see Figure 24). 9 1 9 SCL 0 1 0 1 0 0 A0 START BY MASTER R/W D7 D6 D5 D4 D3 D2 D1 ACK BY ADC ACK BY ADC FRAME 1 SERIAL BUS ADDRESS BYTE CONFIGURATION REGISTER BYTE Figure 24. Writing to the AD7991/AD7995/AD7999 Configuration Register Rev. A | Page 23 of 28 D0 STOP 06461-026 SDA AD7991/AD7995/AD7999 READING FROM THE AD7991/AD7995/AD7999 Reading data from the conversion result register is a 2-byte operation, as shown in Figure 25. Therefore, a read operation always involves two bytes. read operation and should not affect the read operation. The master reads back two bytes of data. On the ninth SCLK rising edge of the second byte, if the master sends an ACK, it keeps reading conversion results and the AD7991/AD7995/AD7999 powers up and performs a second conversion. If the master sends a NO ACK, the AD7991/AD7995/AD7999 does not power up on the ninth SCLK rising edge of the second byte. If a further conversion is required, the part converts on the next channel, as selected in the configuration register. See Table 11 for information about the channel selection. After the AD7991/AD7995/AD7999 have received a read address, any number of reads can be performed from the conversion result register. Following a start condition, the master writes the 7-bit address of the AD7991/AD7995/AD7999 and then sets R/W to 1. The AD7991/AD7995/AD7999 acknowledge this by pulling the SDA line low. They then output the conversion result over the I2C bus, preceded by four status bits. The status bits are two leading 0s followed by the channel identifier bits. For the AD7995 there are two trailing 0s, and for the AD7999 there are four trailing 0s. If the master sends a NO ACK on the ninth SCLK rising edge of the second byte, the conversion is finished and no further conversion is preformed. To put the part into full shutdown mode, the user should issue a stop condition to the AD7991/AD7995/AD7999. If the AD7991/ AD7995/AD7999 is not put into full shutdown mode, it will draw a few tens of microamperes from the supply. After the master has addressed the AD7991/AD7995/AD7999, the part begins to power up on the ninth SCLK rising edge. At the same time, the acquisition phase begins. When approximately 0.6 μs have elapsed, the acquisition phase ends. The input is sampled and a conversion begins. This is done in parallel to the 1 9 1 9 SCL 0 1 0 1 0 0 A0 0 R/W 0 ACK BY ADC START BY MASTER D11 D10 D9 D8 ACK BY MASTER CHID1 CHID0 FRAME 2 MOST SIGNIFICANT DATA BYTE FROM ADC FRAME 1 SERIAL BUS ADDRESS BYTE 1 9 SCL (CONTINUED) SDA (CONTINUED) D7 D6 D5 D4 D3 D2 D1 D0 NO ACK BY MASTER FRAME 3 LEAST SIGNIFICANT DATA BYTE FROM ADC Figure 25. Reading Two Bytes of Data from the AD7991Conversion Result Register Rev. A | Page 24 of 28 STOP BY MASTER 06461-027 SDA AD7991/AD7995/AD7999 PLACING THE AD7991/AD7995/AD7999 INTO HIGH SPEED MODE High speed mode communication commences after the master addresses all devices connected to the bus with the master code, 00001XXX, to indicate that a high speed mode transfer is to begin. No device connected to the bus is allowed to acknowledge the high speed master code; therefore, the code is followed by a NO ACK (see Figure 26). The master must then issue a repeated start, followed by the device address and an R/W bit. The selected device then acknowledges its address. All devices continue to operate in high speed mode until the master issues a stop condition. When the stop condition is issued, the devices return to fast mode. To guarantee performance above fSCL = 1.7 MHz, the user must perform clock stretching—that is, the clock must be held high—for 2 μs after the ninth clock rising edge (see Figure 27). Therefore, the clock must be held high for 2 μs after the device starts to power up (see the Reading from the AD7991/AD7995/AD7999 section). HIGH SPEED MODE FAST MODE 1 9 1 9 SCL 0 0 0 1 X X X 0 NO ACK START BY MASTER 1 1 0 0 0 Sr A0 ACK BY ADC HS MODE MASTER CODE SERIAL BUS ADDRESS BYTE 06461-028 0 SDA Figure 26. Placing the Part into High Speed Mode CLOCK HIGH TIME = 2µs 1 9 1 9 SCL 0 1 0 1 0 0 A0 0 R/W 0 ACK BY ADC START BY MASTER D11 D10 D9 D8 ACK BY MASTER CHID1 CHID0 FRAME 2 MOST SIGNIFICANT DATA BYTE FROM ADC FRAME 1 SERIAL BUS ADDRESS BYTE 1 9 SCL (CONTINUED) SDA (CONTINUED) D7 D6 D5 D4 D3 D2 D1 D0 NO ACK BY MASTER FRAME 3 LEAST SIGNIFICANT DATA BYTE FROM ADC Figure 27. Reading Two Bytes of Data from the Conversion Result Register in High Speed Mode for AD7991 Rev. A | Page 25 of 28 STOP BY MASTER 06461-030 SDA AD7991/AD7995/AD7999 MODE OF OPERATION The AD7991/AD7995/AD7999 powers up in shutdown mode. After the master addresses the AD7991/AD7995/AD7999 with the correct I2C address, the ADC acknowledges the address. In response, the AD7991/AD7995/AD7999 power up. During this wake up time, the AD7991/AD7995/AD7999 exit shutdown mode and begin to acquire the analog input (acquisition phase). By default, all channels are selected. Which channels are converted depends on the status of the channel bits in the configuration register. When the read address is acknowledged, the ADC outputs two bytes of conversion data. The first byte contains four status bits and the four MSBs of the conversion result. The status bits contain two leading 0s and two channel-identifier bits. After this first byte, the AD7991/AD7995/AD7999 outputs the 1 9 second byte of the conversion result. For the AD7991, this second byte contains the lower eight bits of conversion data. For the AD7995, this second byte contains six bits of conversion data plus two trailing 0s. For the AD7999, this second byte contains four bits of conversion data and four trailing 0s. The master then sends a NO ACK to the AD7991/AD7995/ AD7999, as long as no further reads are required. If the master instead sends an ACK to the AD7991/AD7995/AD7999, the ADC powers up and completes another conversion. When more than one channel bit has been set in the configuration register, this conversion is performed on the second channel in the selected sequence. If only one channel is selected, the ADC converts again on the selected channel. 1 9 9 SCL SDA 7-BIT ADDRESS R A FIRST DATA BYTE (MSB) ACK. BY ADC A SECOND DATA BYTE (LSB) ACK. BY MASTER Figure 28. Mode of Operation, Single-Channel Conversion Rev. A | Page 26 of 28 A Sr/P NO ACK. BY MASTER 06461-029 Sr AD7991/AD7995/AD7999 OUTLINE DIMENSIONS 3.00 2.90 2.80 1.70 1.60 1.50 8 7 6 5 1 2 3 4 3.00 2.80 2.60 PIN 1 INDICATOR 0.65 BSC 1.95 BSC 1.45 MAX 0.95 MIN 0.15 MAX 0.05 MIN 0.38 MAX 0.22 MIN 0.22 MAX 0.08 MIN SEATING PLANE 8° 4° 0° 0.60 BSC COMPLIANT TO JEDEC STANDARDS MO-178-BA 0.60 0.45 0.30 121608-A 1.30 1.15 0.90 Figure 29. 8-Lead Small Outline Transistor Package [SOT-23] (RJ-8) Dimensions shown in millimeters ORDERING GUIDE Model AD7991YRJZ-1RL 1 AD7991YRJZ-1500RL71 AD7991YRJZ-0RL1 AD7991YRJZ-0500RL71 AD7995YRJZ-1RL1 AD7995YRJZ-1500RL71 AD7995YRJZ-0RL1 AD7995YRJZ-0500RL71 AD7995ARJZ-0RL1 AD7999YRJZ-1RL1 AD7999YRJZ-1500RL71 AD7999ARJZ-1RL1 EVAL-AD7991EBZ1 1 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 Evaluation Board Z = RoHS Compliant Part. Rev. A | Page 27 of 28 Package Option RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 Branding C56 C56 C55 C55 C58 C58 C57 C57 C6Y C5B C5B C70 AD7991/AD7995/AD7999 NOTES ©2007–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06461-0-10/09(A) Rev. A | Page 28 of 28