AD AD1981B

a
®
AC ’97 SoundMAX Codec
AD1981B
FEATURES
AC ’97 2.3 COMPATIBLE FEATURES
S/PDIF Output, 20 Bits Data Format, Supporting
48 kHz and 44.1 kHz Sample Rates
Integrated Stereo Headphone Amplifier
Variable Sample Rate Audio
External Audio Power-Down Control
Greater than 90 dB Dynamic Range
Stereo Full-Duplex Codec
20-Bit PCM DAC
3 Analog Line-Level Stereo Inputs for
Line-In, AUX, and CD
Mono Line-Level Phone Input
Dual MIC Input with Built-In Programmable Preamp
High Quality CD Input with Ground Sense
Mono Output for Speakerphone or Internal Speaker
Power Management Support
48-Lead LQFP Package, Lead-Free Available
ENHANCED FEATURES
Stereo MIC Preamps Support
Built-In Digital Equalizer Function for Optimized
Speaker Sound
Full-Duplex Variable Sample Rates from 7040 Hz to
48 kHz with 1 Hz Resolution
Jack Sense Pins Provide Automatic Output Switching
Software Programmed VREFOUT Output for Biasing
Microphone and External Power Amp
Split Power Supplies: 3.3 V Digital and 5 V Analog
Multiple Codec Configuration Options
FUNCTIONAL BLOCK DIAGRAM
XTL_OUT XTL_IN SPDIF
VREF
VREFOUT
AD1981B
VOLTAGE
REFERENCE
G
MS
MIC PREAMP
CODEC CORE
G
MIC2
PCM L/R
ADC RATE
PHONE_IN
RECORD
SELECTOR
CD_L
CD_GND
SPDIF
TX
G
2CMIC
MIC1
CD
DIFF AMP
CD_R
AUX_L
G
M
16-BIT
⌺-⌬ ADC
G
M
16-BIT
⌺-⌬ ADC
PLL
ID0
ID1
AUX_R
LINE_IN_L
LINE_OUT_R
A
A
MZ
A
MZ
M
GA
GA
20-BIT
⌺-⌬ DAC
20-BIT
⌺-⌬ DAC
GA
GA
M
GA
M
M
M
GA
GA
GA
M
GA
G = GAIN
A = ATTENUATION
M = MUTE
Z = HIGH Z
PCM FRONT
DAC RATE
EQ
EQ
M
M
SYNC
BIT_CLK
EQ CORE STORAGE
M
OUTPUT SELECTOR
LINE_OUT_L
HP
GA
BYPASS
M
HP_OUT_L
M
16-BIT
⌺-⌬ ADC
BYPASS
A
M
MONO_OUT
16-BIT
⌺-⌬ ADC
MIX
G
M
AC '97 INTERFACE
G
RESET
ADC
AND
DAC
SLOT
LOGIC
LINE_IN_R
SDATA_OUT
SDATA_IN
AC '97
CONTROL
REGISTERS
M
M
HP_OUT_R
HP
M
A
M
ANALOG MIXING
CONTROL LOGIC
JS0
JS1
EAPD
EAPD
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
AD1981B–SPECIFICATIONS
STANDARD TEST CONDITIONS, UNLESS
OTHERWISE NOTED
Temperature
Digital Supply (DVDD)
Analog Supply (AVDD)
Sample Rate (FS)
Input Signal
Analog Output Pass Band
25°C
3.3 V
5.0 V
48 kHz
1008 Hz
20 Hz to 20 kHz
DAC Test Conditions
Calibrated
–3 dB Attenuation Relative to Full Scale
0 dB Input
10 kΩ Output Load (LINE_OUT)
32 Ω Output Load (HP_OUT)
ADC Test Conditions
Calibrated
0 dB Gain
Input –3.0 dB Relative to Full Scale
Parameter
Min
ANALOG INPUT
Input Voltage (RMS Values Assume Sine Wave Input)
LINE_IN, AUX, CD, PHONE_IN
Typ
1
2.83
0.1
0.283
1
2.83
20
5
MIC_IN with +20 dB Gain
MIC_IN with 0 dB Gain
Input Impedance1
Input Capacitance1
MASTER VOLUME
Step Size (0 dB to –46.5 dB): LINE_OUT_L, LINE_OUT_R
Output Attenuation Range1
Step Size (0 dB to –46.5 dB): MONO_OUT
Output Attenuation Range1
Step Size (0 dB to –46.5 dB): HP_OUT_R, HP_OUT_L
Output Attenuation Range Span1
Mute Attenuation of 0 dB Fundamental1
Max
Unit
7.5
V rms
V p-p
V rms
V p-p
V rms
V p-p
kΩ
pF
1.5
46.5
1.5
46.5
1.5
46.5
dB
dB
dB
dB
dB
dB
dB
1.5
22.5
dB
dB
90
90
dB
dB
1.5
dB
46.5
dB
80
PROGRAMMABLE GAIN AMPLIFIER—ADC
Step Size (0 dB to 22.5 dB)
PGA Gain Range
ANALOG MIXER—INPUT GAIN/AMPLIFIERS/ATTENUATORS
Signal-to-Noise Ratio (SNR)
CD to LINE_OUT
Other to LINE_OUT1
Step Size (+12 dB to –34.5 dB) (All Steps Tested):
MIC_IN, LINE_IN, CD, AUX, PHONE_IN, DAC
Input Gain/Attenuation Range:
MIC_IN, LINE_IN, CD, AUX, PHONE_IN, DAC
1
DIGITAL DECIMATION AND INTERPOLATION FILTERS
Pass Band
Pass-Band Ripple
Transition Band
Stop Band
Stop-Band Rejection
Group Delay
Group Delay Variation over Pass Band
–2–
0.4 fS
± 0.09
0.6 fS
0
0.4 fS
0.6 fS
–74
16/fS
0
Hz
dB
Hz
Hz
dB
sec
µs
REV. B
AD1981B
Parameter
ANALOG-TO-DIGITAL CONVERTERS
Resolution
Total Harmonic Distortion (THD)
Dynamic Range (–60 dB Input THD+N Referenced to Full Scale,
A-Weighted)
Signal-to-Intermodulation Distortion1 (CCIF Method)
ADC Crosstalk1
Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L)
Line_In to Other
Gain Error2 (Full-Scale Span Relative to Nominal Input Voltage)
Interchannel Gain Mismatch (Difference of Gain Errors)
ADC Offset Error1
DIGITAL-TO-ANALOG CONVERTERS
Resolution
Total Harmonic Distortion (THD) LINE_OUT
Total Harmonic Distortion (THD) HP_OUT
Dynamic Range (–60 dB Input THD+N Referenced to Full Scale,
A-Weighted)
Signal-to-Intermodulation Distortion1 (CCIF Method)
Gain Error2 (Output FS Voltage Relative to Nominal Output FS Voltage)
Interchannel Gain Mismatch (Difference of Gain Errors)
DAC Crosstalk1 (Input L, Zero R, Measure R_OUT; Input R,
Zero L, Measure L_OUT)
Total Audible Out-of-Band Energy1 (Measured from 0.6 fS to 20 kHz)
Min
Typ
80
16
–84
85
Bits
dB
dB
85
dB
–80
–100
85
ANALOG OUTPUT
Full-Scale Output Voltage; LINE_OUT and MONO_OUT
Output Impedance1
External Load Impedance1
Output Capacitance1
External Load Capacitance1
Full-Scale Output Voltage; HP_OUT (0 dB Gain)
External Load Impedance1
VREF
VREF_OUT (Programmable to 3.70 V Nominal)
VREF_OUT Current Drive
Mute Click (Muted Output Minus Unmuted Midscale DAC Output)
STATIC DIGITAL SPECIFICATIONS
High Level Input Voltage (VIH): Digital Inputs
Low Level Input Voltage (VIL)
High Level Output Voltage (VOH), IOH = 2 mA
Low Level Output Voltage (VOL), IOL = 2 mA
Input Leakage Current
Output Leakage Current
REV. B
–100
± 10
dB
%
dB
dB
± 0.7
–80
–40
dB
1
2.83
V rms
V p-p
Ω
kΩ
pF
pF
V rms
Ω
V
V
mA
mV
800
10
15
100
1
32
2.05
dB
dB
%
dB
mV
Bits
dB
dB
dB
2.25
2.25
2.45
5
±5
0.35 DVDD
0.9 DVDD
–3–
–80
± 10
± 0.5
±5
Unit
20
–85
–75
90
0.65 DVDD
POWER SUPPLY
Power Supply Range—Analog (AVDD)
Power Supply Range—Digital (DVDD)
Power Dissipation—5 V/3.3 V
Analog Supply Current—5 V (AVDD)
Digital Supply Current—3.3 V (DVDD)
Power Supply Rejection (100 mV p-p Signal @ 1 kHz)1
(At Both Analog and Digital Supply Pins, Both ADCs and DACs)
Max
–10
–10
0.1 DVDD
+10
+10
4.5
3.0
5.5
3.47
V
V
V
V
µA
µA
400
50
46
V
V
mW
mA
mA
40
dB
AD1981B
SPECIFICATIONS (continued)
Parameter
Min
Typ
Max
Unit
40
24.576
50
60
MHz
%
1
CLOCK SPECIFICATIONS
Input Clock Frequency
Recommended Clock Duty Cycle
NOTES
1
Guaranteed but not tested.
2
Measurements reflect main ADC.
Specifications subject to change without notice.
Parameter
Set Bits
DVDD Typ
AVDD Typ
Unit
POWER-DOWN STATES*
(Fully Active)
ADC
DAC
ADC + DAC
Mixer
ADC + Mixer
DAC + Mixer
ADC + DAC + Mixer
Standby
Headphone Standby
(No Bits Value)
PR0
PR1
PR1, PR0
PR2
PR2, PR0
PR2, PR1
PR2, PR1, PR0
PR5, PR4, PR3, PR2, PR1, PR0
PR6
42
36
29
12
42
36
29
12
0
42
51
45
35
28
24
18
9
1.5
0
44
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
*Values presented with V REFOUT not loaded.
Specifications subject to change without notice.
TIMING PARAMETERS
(Guaranteed over Operating Temperature Range)
Parameter
Symbol
RESET Active Low Pulsewidth
RESET Inactive to BIT_CLK Start-Up Delay
SYNC Active High Pulsewidth
SYNC Low Pulsewidth
SYNC Inactive to BIT_CLK Start-Up Delay
BIT_CLK Frequency
BIT_CLK Frequency Accuracy
BIT_CLK Period
BIT_CLK Output Jitter1, 2, 3
BIT_CLK High Pulsewidth
BIT_CLK Low Pulsewidth
SYNC Frequency
SYNC Period
Setup to Falling Edge of BIT_CLK
Hold from Falling Edge of BIT_CLK
BIT_CLK Rise Time
BIT_CLK Fall Time
SYNC Rise Time
SYNC Fall Time
SDATA_IN Rise Time
SDATA_IN Fall Time
SDATA_OUT Rise Time
SDATA_OUT Fall Time
End of Slot 2 to BIT_CLK, SDATA_IN Low
Setup to Trailing Edge of RESET
(Applies to SYNC, SDATA_OUT)
Rising Edge of RESET to Hi-Z Delay
Propagation Delay
RESET Rise Time
Output Valid Delay from Rising Edge of BIT_CLK to SDI Valid
tRST_LOW
tRST2CLK
tSYNC_HIGH
tSYNC_LOW
tSYNC2CLK
Min
Typ
1.0
6
6
6
6
6
6
6
6
1.0
25
15
50
15
ns
ns
ns
ns
ns
1.3
19.5
162.8
tCLK_PERIOD
tCLK_HIGH
tCLK_LOW
32.56
32.56
tSYNC_PERIOD
tSETUP
tHOLD
tRISECLK
tFALLCLK
tRISESYNC
tFALLSYNC
tRISEDIN
tFALLDIN
tRISEDOUT
tFALLDOUT
tS2_PDOWN
5
5
2
2
2
2
2
2
2
2
0
81.4
750
42
38
48.0
20.8
2.5
4
4
4
4
4
4
4
4
Unit
ms
ns
ms
µs
ns
MHz
ppm
ns
ps
ns
ns
kHz
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
162.8
12.288
tSETUP2RST
tOFF
Max
±1
2000
48.84
15
NOTES
1
Guaranteed but not tested.
2
Output jitter is directly dependent on crystal input jitter.
3
Maximum jitter specification for noncrystal operation only. Crystal operation maximum is much lower.
Specifications subject to change without notice.
–4–
REV. B
AD1981B
tRST2CLK
tRST_LOW
RESET
tTRI2ACTV
BIT_CLK
tTRI2ACTV
SDATA_IN
Figure 1. Cold Reset Timing (Codec Is Supplying the BIT_CLK Signal)
tSYNC_HIGH
tSYNC2CLK
SYNC
BIT_CLK
Figure 2. Warm Reset Timing
tCLK_LOW
BIT_CLK
tCLK_HIGH
tCLK_PERIOD
tSYNC_LOW
SYNC
tSYNC_HIGH
tSYNC_PERIOD
Figure 3. Clock Timing
BIT_CLK
tRISECLK
tFALLCLK
tRISESYNC
tFALLSYNC
tRISEDIN
tFALLDIN
tRISEDOUT
tFALLDOUT
SYNC
SDATA_IN
SDATA_OUT
Figure 4. Signal Rise and Fall Times
REV. B
–5–
AD1981B
SLOT 1
SLOT 2
WRITE TO
0x20
DATA
PR4
SYNC
BIT_CLK
SDATA_OUT
tS2_PDOWN
SDATA_IN
BIT_CLK NOT TO SCALE
Figure 5. AC-Link Low Power Mode Timing
tCO
tSETUP
BIT_CLK
VIH
VIL
SDATA_O
SDATA_I
VOH
SYNC
VOL
tHOLD
Figure 6. AC-Link Low Power Mode Timing, SYNC and BIT_CLK Chopped
RESET
SDATA_OUT
tSETUP2RST
SDATA_IN, BIT_CLK,
EAPD, SPDIF_OUT
AND DIGITAL I/O
Hi-Z
tOFF
Figure 7. ATE Test Mode
–6–
REV. B
AD1981B
ABSOLUTE MAXIMUM RATINGS *
ENVIRONMENTAL CONDITIONS *
(TA = 25°C, unless otherwise noted.)
Ambient Temperature Rating (LQFP Package)
TCASE = Case Temperature in °C
PD = Power Dissipation in W
JA Thermal Resistance (Junction to Ambient)
JC Thermal Resistance (Junction to Case)
Power Supplies
Digital (DVDD) . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +3.6 V
Analog (AVDD) . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6.0 V
Input Current (Except Supply Pins) . . . . . . . . . . . . . . ± 10 mA
Signals Pins
Digital Input Voltage . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V
Analog Input Voltage . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V
Ambient Temperature Range (Operating) . . . . . . . 0°C to 70°C
Package
␪JA
␪JC
LQFP
50.1°C/W
17.8°C/W
*All measurements per EIA-JESD51 with 2S2P test board per EIA-JESD51-7
*Stresses greater than those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option1
AD1981BJST
AD1981BJST-REEL
AD1981BJSTZ2
AD1981BJSTZ-REEL2
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
48-Lead LQFP (Tray)
48-Lead LQFP (Reel)
48-Lead LQFP (Tray)
48-Lead LQFP (Reel)
ST-48
ST-48
ST-48
ST-48
1
2
ST = Low Profile Quad Flatpack.
The AD1981BJSTZ is a lead-free environmentally friendly product. It is manufactured using the most up-to-date materials and processes. The coating on the leads of
each device is 100% pure tin electroplate. The device is suitable for lead-free applications and is able to withstand surface-mount soldering at up to 255 °C (± 5°C). In
addition, it is backward compatible with conventional tin-lead soldering processes. This means that the electroplated tin coating can be soldered with tin-lead solder
pastes at reflow temperatures of 220°C to 235°C.
HP_OUT_R
AVSS2
HP_OUT_L
AVDD2
MONO_OUT
41
40
39
38
37
AVSS3
44
AVDD3
ID0
45
NC
ID1
46
42
EAPD
47
43
SPDIF
48
PIN CONFIGURATION
48-Lead LQFP
DVDD1 1
36 LINE_OUT_R
XTL_IN 2
35 LINE_OUT_L
XTL_OUT 3
34 AVDD4
DVSS1 4
33 AVSS4
SDATA_OUT 5
32 AFILT4
BIT_CLK 6
AD1981B
DVSS2 7
TOP VIEW
(Not to Scale)
31 AFILT3
30 AFILT2
SDATA_IN 8
29 AFILT1
DVDD2 9
28 VREFOUT
27 VREF
SYNC 10
LINE_IN_R 24
LINE_IN_L 23
MIC2 22
MIC1 21
CD_R 20
CD_GND_REF 19
CD_L 18
JS0 17
JS1 16
NC = NO CONNECT
AUX_R 15
25 AVDD1
AUX_L 14
26 AVSS1
NC 12
PHONE_IN 13
RESET 11
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD1981B features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. B
–7–
AD1981B
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
I/O
Function
2
3
5
6
XTL_IN
XTL_OUT
SDATA_OUT
BIT_CLK
I
O
I
O/I
8
10
11
48
SDATA_IN
SYNC
RESET
SPDIF
O
I
I
O
Crystal Input (24.576 MHz) or External Clock Input.
Crystal Output.
AC-Link Serial Data Output, AD1981B Data Input Stream.
AC-Link Bit Clock Output (12.288 MHz) or Bit Clock Input if Secondary Mode
Selected.
AC-Link Serial Data Input, AD1981B Data Output Stream.
AC-Link Frame Sync.
AC-Link Reset, AD1981B Master Hardware Reset.
S/PDIF Output.
DIGITAL I/O
CHIP SELECTS (These pins can also be used to select an external clock. See Table IX.)
45
ID0
I
46
ID1
I
Chip Select Input 0 (Active Low). This pin can also be used as the chain input from
a secondary codec.
Chip Select Input 1 (Active Low).
JS0
JS1
EAPD
I
I
O
Jack Sense 0 Input.
Jack Sense 1 Input.
External Amp Power-Down Control.
13
14
15
18
19
20
21
PHONE_IN
AUX_L
AUX_R
CD_L
CD_GND_REF
CD_ R
MIC1
I
I
I
I
I
I
I
22
MIC2
I
23
24
35
36
37
39
41
LINE_IN_L
LINE_IN_R
LINE_OUT_L
LINE_OUT_R
MONO_OUT
HP_OUT_L
HP_OUT_R
I
I
O
O
O
O
O
Phone Input. Mono input from telephony subsystem speaker phone or handset.
Auxiliary Input Left Channel.
Auxiliary Input Right Channel.
CD Audio Left Channel.
CD Audio Analog Ground Reference for Differential CD Input.
CD Audio Right Channel.
Microphone 1 Input (Mono) or Left Channel when 2-Channel Mode
Selected (Stereo MIC).
Microphone 2 Input (Mono) or Right Channel when 2-Channel Mode
Selected (Stereo MIC).
Line In Left Channel.
Line In Right Channel.
Line Out (Front) Left Channel.
Line Out (Front) Right Channel.
Monaural Output to Telephony Subsystem Speakerphone.
Headphone Left Channel Output.
Headphone Right Channel Output.
JACK SENSE AND EAPD
17
16
47
ANALOG I/O
FILTER/REFERENCE (These signals are connected to resistors, capacitors, or specific voltages.)
27
28
29
30
31
32
VREF
VREFOUT
AFILT1
AFILT2
AFILT3
AFILT4
O
O
O
O
O
O
Voltage Reference Filter.
Voltage Reference Output 5 mA Drive (Intended for MIC Bias and Power Amp Bias).
Antialiasing Filter Capacitor—ADC Right Channel.
Antialiasing Filter Capacitor—ADC Left Channel.
Antialiasing Filter Capacitor—Mixer ADC Right Channel.
Antialiasing Filter Capacitor—Mixer ADC Left Channel.
I
I
I
I
I
I
I
I
I
I
I
I
Digital VDD 3.3 V.
Digital GND.
Digital GND.
Digital VDD 3.3 V.
Analog VDD 5.0 V.
Analog GND.
Analog VDD 5.0 V.
Analog GND.
Analog VDD 5.0 V.
Analog GND.
Analog VDD 5.0 V.
Analog GND.
POWER AND GROUND SIGNALS
1
4
7
9
25
26
38
40
43
44
34
33
DVDD1
DVSS1
DVSS2
DVDD2
AVDD1
AVSS1
AVDD2
AVSS2
AVDD3
AVSS3
AVDD4
AVSS4
NO CONNECTS
12
42
NC
NC
No Connect.
No Connect.
–8–
REV. B
AD1981B
Indexed Control Registers
Reg Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
00h
Reset
X
SE4
SE3
SE2
SE1
SE0
ID9
ID8
ID7
ID6
02h
Master Volume
MM
X
X
LMV4
LMV3
LMV2
LMV1 LMV0 RM*
X
04h
Headphones
Volume
HPM
X
X
LHV4
LHV3
LHV2
LHV1 LHV0 RM*
06h
ID5
ID4
ID3
ID2
ID1
ID0
X
RMV4 RMV3 RMV2 RMV1 RMV0
8000h
X
X
RHV4 RHV3 RHV2 RHV1 RHV0
8000h
8000h
MV2
MV1
MV0
0090h
Mono Volume
MVM
X
X
X
X
X
X
X
X
X
X
MV4
0Ch Phone Volume
PHM
X
X
X
X
X
X
X
X
X
X
PHV4 PHV3 PHV2 PHV1 PHV0
0Eh
MCM
X
X
X
X
X
X
X
X
M20
X
MCV4 MCV3 MCV2 MCV1 MCV0 8008h
MIC Volume
MV3
Default
8008h
10h
Line-In Volume
LVM
X
X
LLV4
LLV3
LLV2
LLV1 LLV0 RM*
X
X
RLV4 RLV3 RLV2 RLV1 RLV0
8808h
12h
CD Volume
CVM
X
X
LCV4
LCV3
LCV2
LCV1 LCV0 RM*
X
X
RCV4 RCV3 RCV2 RCV1 RCV0
8808h
16h
AUX Volume
AM
X
X
LAV4
LAV3
LAV2
LAV1 LAV0 RM*
X
X
RAV4 RAV3 RAV2 RAV1 RAV0
8808h
18h
PCM-Out Vol
OM
X
X
LOV4
LOV3
LOV2
LOV1 LOV0 RM*
X
X
ROV4 ROV3 ROV2 ROV1 ROV0
8808h
1Ah Record Select
X
X
X
X
X
LS2
LS1
X
X
X
X
0000h
1Ch Record Gain
IM
X
X
X
LIM3
LIM2
LIM1 LIM0 RM*
X
X
X
RIM3 RIM2 RIM1 RIM0
LS0
X
RS2
RS1
RS0
8000h
20h
General-Purpose
X
X
X
X
X
X
MIX
MS
LPBK X
X
X
X
X
X
X
0000h
26h
Power-Down
Ctrl/Stat
EAPD
PR6
PR5
PR4
PR3
PR2
PR1
PR0
X
X
X
X
REF
ANL
DAC
ADC
000Xh
28h
Ext’d Audio ID
IDC1
IDC0
X
X
REVC1 REVC0 AMAP X
X
X
DSA1 DSA0 X
SPDIF X
VRAS
X605h
X
X
X
X
X
X
SPSA1 SPSA0 X
SPDIF X
VRA
0000h
SRF8
SRF7
SRF6
SRF5
SRF2
SRF0
BB80h
2Ah Ext’d Audio Stat/ VFORCE X
Ctrl
SPCV
X
2Ch PCM Front
DAC Rate
SRF15
SRF14 SRF13
SRF12 SRF11 SRF10 SRF9
32h
SRA15
SRA14 SRA13
SRA12 SRA11 SRA10 SRA9 SRA8 SRA7 SRA6
SRA5 SRA4 SRA3 SRA2 SRA1 SRA0
BB80h
3Ah SPDIF Control
V
X
SPSR1
SPSR0 L
CC6
CC5
CC4
CC3
CC2
CC1
2000h
60h
EQM
MAD
LBEN
X
X
X
X
X
SYM
CHS
BCA5 BCA4 BCA3 BCA2 BCA1 BCA0
8080h
0000h
PCM L/R
ADC Rate
EQ CTRL
X
SRF4
CC0
SRF3
PRE
SRF1
COPY /AUD PRO
62h
EQ DATA
CFD15
CFD14 CFD13
CFD12 CFD11 CFD10 CFD9 CFD8 CFD7 CFD6
CFD5 CFD4 CFD3 CFD2 CFD1 CFD0
64h
Mixer ADC,
Volume
MXM
X
X
X
LMG3 LMG2 LMG1 LMG0 RM*
X
X
X
RMG3 RMG2 RMG1 RMG0 8000h
72h
Jack Sense
X
X
X
JS
MT2
JS
MT1
JS0
TMR
JS1
MD
JS0
MD
JS1
ST
JS0
ST
74h
Serial
Configuration
SLOT
16
REGM REGM
2
1
X
X
INTS
X
SPAL SPDZ SPLNK 7001h
76h
Misc Control
Bits
DACZ
X
7Ch Vendor ID1
F7
7Eh
T7
Vendor ID2
JS
MT0
JS1
EQB
JS0
EQB
JS1
TMR
REGM X
0
X
X
CHEN X
M
SPLT
LODIS DAM
X
FMXE X
MAD
PD
2CMIC X
MAD
ST
VREF VREF MBG1 MBG0 0000h
H
D
F6
F5
F4
F3
F2
F1
F0
S7
S6
S4
S3
T6
T5
T4
T3
T2
T1
T0
REV7 REV6
S5
S2
JS1
INT
S1
JS0
INT
S0
REV5 REV4 REV3 REV2 REV1 REV0
0000h
4144h
5374h
NOTES
All registers not shown. Bits containing an X are assumed to be reserved.
Odd register addresses are aliased to the next lower even address.
Reserved registers should not be written.
Zeros should be written to reserved bits.
*For AC ’97 compatibility, Bit D7 (RM) is only available by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right
channels. If MSPLT is not set, RM bit has no effect.
REV. B
–9–
AD1981B
Reset Register (Index 00h)
Reg
No.
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
00h
Reset
X
SE4
SE3
SE2
SE1
SE0
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
0090h
NOTES
X in the above table is a wild card and has no effect on the value.
Writing any value to this register performs a register reset that causes all registers to revert to their default values (except 74h, which forces the serial configuration).
Reading this register returns the ID code of the part and a code for the type of 3D stereo enhancement.
ID[9:0] Identify Capability. The ID decodes the capabilities of AD1981B based on the following:
Bit
Function
AD1981B
ID0
ID1
ID2
ID3
ID4
ID5
ID6
ID7
ID8
ID9
Dedicated Mic PCM In Channel
Modem Line Codec Support
Bass and Treble Control
Simulated Stereo (Mono to Stereo)
Headphone Out Support
Loudness (Bass Boost) Support
18-Bit DAC Resolution
20-Bit DAC Resolution
18-Bit ADC Resolution
20-Bit ADC Resolution
0
0
0
0
1
0
0
1
0
0
SE[4:0] Stereo Enhancement. The AD1981B does not provide hardware 3D stereo enhancement (all bits are zeros).
Master Volume Register (Index 02h)
Reg
No.
02h
Name
D15
D14
Master
Volume
MM X
D13
D12
D11
D10
D9
D8
D7
D6
X
LMV4 LMV3 LMV2 LMV1 LMV0 RM* X
D5
D4
D3
D2
D1
D0
Default
X
RMV4 RMV3 RMV2 RMV1 RMV0 8000h
* For AC ‘97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right
channels. If MSPLT is not set, RM bit has no effect. All registers not shown and bits containing an X are assumed to be reserved.
Refer to Table I for examples. This register controls the Line_Out volume controls for both stereo channels and the mute bit. Each
volume subregister contains five bits, generating 32 volume levels with 31 steps of 1.5 dB each. Because AC ’97 defines 6-bit volume
registers, to maintain compatibility whenever the D5 or D13 bits are set to 1, their respective lower five volume bits are automatically
set to 1 by the codec logic. On readback, all lower five bits will read 1s whenever these bits are set to 1.
RMV[4:0]
Right Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from
0 dB to a maximum attenuation of 46.5 dB.
RM
Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately
from the MM bit. Otherwise, this bit will always read 0 and will have no effect when set to 1.
LMV[4:0]
Left Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from
0 dB to a maximum attenuation of 46.5 dB.
MM
Master Volume Mute. When this bit is set to 1, both the left and right channels are muted, unless the MSPLT
bit in Register 76h is set to 1, in which case this mute bit will affect only the left channel.
–10–
REV. B
AD1981B
Headphones Volume Register (Index 04h)
Reg
No. Name
D15
D14
04h Headphone HPM X
Volume
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
X
LHV
4
LHV
3
LHV
2
LHV
1
LHV
0
RM*
X
X
RHV
4
RHV
3
RHV
2
RHV
1
RHV
0
8000h
*For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right
channels. If MSPLT is not set, RM bit has no effect. All registers not shown and bits containing an X are assumed to be reserved.
Refer to Table I for examples. This register controls the headphone volume controls for both stereo channels and mute bit. Each
volume subregister contains five bits, generating 32 volume levels with 31 steps of 1.5 dB each. Because AC ’97 defines 6-bit volume
registers, to maintain compatibility, whenever the D5 or D13 bits are set to 1, their respective lower five volume bits are automatically set to 1 by the codec logic. On readback, all lower five bits will read 1s whenever these bits are set to 1.
RHV [4:0]
Right Headphone Volume Control. The least significant bit represents 1.5 dB. This register controls the output
from 0 dB to a maximum attenuation of 46.5 dB.
RM
Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately
from the HPM bit. Otherwise, this bit will always read 0 and will have no effect when set to 1.
LHV [4:0]
Left Headphone Volume Control. The least significant bit represents 1.5 dB. This register controls the output
from 0 dB to a maximum attenuation of 46.5 dB.
HPM
Headphones Volume Mute. When this bit is set to 1, both the left and right channels are muted, unless the
MSPLT bit in Register 76h is set to 1, in which case this mute bit will affect only the left channel.
Table I. Volume Settings for Master and Headphone
Control Bits
Master Volume (02h) and Headphone Volume (04h)
Reg. 76h
MSPLT*
Left Channel Volume D[13:8]
Right Channel Volume D[5:0]
D15 WRITE
READBACK Function
D7*
WRITE READBACK
Function
0
0
00 0000
00 0000
0 dB Gain
x
00 0000
00 0000
0 dB Gain
0
0
00 1111
00 1111
–22.5 dB Gain
x
00 1111
00 1111
–22.5 dB Gain
0
0
01 1111
01 1111
–46.5 dB Gain
x
01 1111
01 1111
–46.5 dB Gain
0
0
1x xxxx
01 1111
–46.5 dB Gain
x
1x xxxx
01 1111
–46.5 dB Gain
0
1
xx xxxx
xx xxxx
– dB Gain, Muted
x
xx xxxx
xx xxxx
– dB Gain, Muted
1
0
1x xxxx
01 1111
–46.5 dB Gain
1
xx xxxx
xx xxxx
– dB Gain, Right
Only Muted
1
1
xx xxxx
xx xxxx
– dB Gain, Left Only Muted
0
xx xxxx
xx xxxx
–46.5 dB Gain
1
1
xx xxxx
xx xxxx
– dB Gain, Left Muted
1
xx xxxx
xx xxxx
– dB Gain, Right
Muted
*For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right
channels. If MSPLT is not set, RM bit has no effect.
X in the above table is a wild card and has no effect on the value.
REV. B
–11–
AD1981B
Mono Volume Register (Index 06h)
Reg
No. Name
06h
D15
Mono Volume MVM
D14 D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
X
X
X
X
X
X
X
X
X
MV4
MV3
MV2
MV1
MV0
8000h
X
All registers not shown and bits containing an X are assumed to be reserved.
Refer to Table II for examples. This register controls the mono output volume and mute bit. The volume register contains five bits,
generating 32 volume levels with 31 steps of 1.5 dB each. Because AC ’97 defines 6-bit volume registers, to maintain compatibility,
whenever the D5 bit is set to 1, their respective lower five volume bits are automatically set to 1 by the codec logic. On readback, all
lower five bits will read 1s whenever this bit is set to 1.
MV[4:0]
Mono Volume Control. The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a
maximum attenuation of 46.5 dB.
MVM
Mono Volume Mute. When this bit is set to 1, the channel is muted.
Table II. Volume Settings for Mono
Control Bits D[4:0] for Mono (06h)
D15
WRITE
READBACK
Function
0
0
0
1
0000
0 1111
1 1111
x xxxx
0 0000
0 1111
1 1111
x xxxx
0 dB Gain
–22.5 dB Gain
–46.5 dB Gain
– dB Gain, Muted
x in the above table is a wild card and has no effect on the value.
Phone Volume Register (Index 0Ch)
Reg
No. Name
D15
D14 D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
0Ch Phone Volume
PHM
X
X
X
X
X
X
X
X
X
PHV4
PHV3
PHV2
PHV1 PHV0
X
D0
Default
8008h
All registers not shown and bits containing an X are assumed to be reserved. Refer to Table III for examples.
PHV[4:0]
Phone Volume. Allows setting the phone volume attenuator in 32 volume levels with 31 steps of 1.5 dB each. The
LSB represents 1.5 dB, and the gain range is +12 dB to –34.5 dB. The default value is 0 dB, with the mute bit enabled.
PHM
Phone Mute. When this bit is set to 1, the phone channel is muted.
All registers not shown and bits containing an X are assumed to be reserved. Refer to Table III for examples.
–12–
REV. B
AD1981B
MIC Volume Register (Index 0Eh)
Reg
No. Name
D15
0Eh MIC Volume
MCM X
D14 D13
X
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
X
X
X
X
X
X
M20
X
MCV4
MCV3
MCV2
MCV1 MCV0 8008h
All registers not shown and bits containing an X are assumed to be reserved. Refer to Table III for examples.
MCV[4:0]
MIC Volume Gain. Allows setting the phone volume attenuator in 32 volume levels with 31 steps of 1.5 dB
each. The LSB represents 1.5 dB, and the gain range is +12 dB to –34.5 dB. The default value is 0 dB, with the mute
bit enabled.
M20
MIC Gain Boost. This bit allows setting additional MIC gain to increase the microphone sensitivity. The nominal
gain boost by default is 20 dB; however, Bits D0 and D1 (MBG[1:0]) on the miscellaneous control bits register
(76h) allow changing the gain boost to 10 dB or 30 dB if necessary.
0 = Disabled; Gain = 0 dB
1 = Enabled; Default Gain = 20 dB (see Register 76h, Bits D0, D1)
MCM
MIC Mute. When this bit is set to 1, the MIC channel is muted.
Table III. Volume Settings for Phone and MIC
Control Bits D[4:0]
Phone (0Ch) and Mic (0Eh)
D15
WRITE
READBACK
Function
0
0
0
1
0 0000
0 1000
1 1111
x xxxx
0 0000
0 1000
1 1111
x xxxx
12 dB Gain
0 dB Gain
–34.5 dB Gain
– dB Gain, Muted
x in the above table is a wild card, and has no effect on the value.
Line-In Volume Register (Index 10h)
Reg
No. Name
D15
10h Line-In Volume LVM
D14 D13 D12
X
X
D11
LLV4 LLV3
D10
D9
D8
D7
D6
LLV2
LLV1 LLV0 RM* X
D5
D4
D3
D2
D1
D0
Default
X
RLV4
RLV3
RLV2 RLV1 RLV0 8808h
*For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right
channels. If MSPLT is not set, the RM bit has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table IV for examples.
RLV[4:0]
Line In Volume Right. Allows setting the line-in right channel attenuator in 32 volume levels. The LSB represents
1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
RM
Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately
from the LM bit. Otherwise, this bit will always read 0 and will have no effect when set to 1.
LLV[4:0]
Line In Volume Left. Allows setting the line in left channel attenuator in 32 volume levels. The LSB represents
1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
LVM
Line In Mute. When this bit is set to 1, both the left and right channels are muted unless the MSPLT bit in
Register 76h is set to 1, in which case this mute bit will affect only the left channel.
REV. B
–13–
AD1981B
CD Volume Register (Index 12h)
Reg
No. Name
D15
12h CD Volume
CVM X
D14 D13 D12
X
D11
D10
D9
D8
D7
D6
LCV4 LCV3 LCV2 LCV1 LCV0 RM* X
D5
D4
D3
D2
D1
D0
Default
X
RCV4
RCV3
RCV2 RCV1 RCV0 8808h
*For AC ’97 compatibility, Bit D7 (RM) is only available by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right
channels. If MSPLT is not set, the RM bit has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table IV for examples.
RCV[4:0]
Right CD Volume. Allows setting the CD right channel attenuator in 32 volume levels. The LSB represents 1.5 dB,
and the gain range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
RM
Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately
from the CVM bit. Otherwise, this bit will always read 0 and will have no affect when set to 1.
LCV[4:0]
Left CD Volume. Allows setting the CD left channel attenuator in 32 volume levels. The LSB represents 1.5 dB,
and the gain range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
CVM
CD Volume Mute. When this bit is set to 1, both the left and right channels are muted, unless the MSPLT bit in
Register 76h is set to 1, in which case this mute bit will affect only the left channel.
AUX Volume Register (Index 16h)
Reg
No. Name
D15
D14
D13 D12
16h
AM
X
X
AUX Volume
D11
D10
LAV4 LAV3 LAV2
D9
D8
D7
D6
LAV1 LAV0 RM* X
D5
D4
D3
D2
D1
D0
Default
X
RAV4
RAV3 RAV2 RAV1 RAV0 8808h
*For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right
channels. If MSPLT is not set, RM bit has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table IV for examples.
RAV[4:0]
Right AUX Volume. Allows setting the AUX right channel attenuator in 32 volume levels. The LSB represents 1.5 dB,
and the gain range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
RM
Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately
from the AM bit. Otherwise, this bit will always read 0 and will have no affect when set to 1.
LAV[4:0]
Left AUX Volume. Allows setting the AUX left channel attenuator in 32 volume levels. The LSB represents 1.5 dB,
and the gain range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
AM
AUX Mute. When this bit is set to 1, both the left and right channels are muted, unless the MSPLT bit in
Register 76h is set to 1, in which case this mute bit will affect only the left channel.
PCM-Out Volume Register (Index 18h)
Reg
No. Name
D15 D14 D13 D12
18h PCM-Out Volume OM X
X
D11
D10
LOV4 LOV3 LOV2
D9
D8
D7
D6
LOV1 LOV0 RM* X
D5
D4
D3
D2
D1
D0
Default
X
ROV4 ROV3 ROV2 ROV1 ROV0 8808h
*For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right
channels. If MSPLT is not set, RM bit has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table IV for examples.
ROV[4:0]
Right PCM Out Volume. Allows setting the PCM right channel attenuator in 32 volume levels. The LSB represents
1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
RM
Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately
from the OM bit. Otherwise, this bit will always read 0 and will have no effect when set to 1.
LOV[4:0]
Left PCM Out Volume. Allows setting the PCM left channel attenuator in 32 volume levels. The LSB represents
1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
OM
PCM Out Volume Mute. When this bit is set to 1, both the left and right channels are muted unless the MSPLT
bit in Register 76h is set to 1, in which case this mute bit will affect only the left channel.
–14–
REV. B
AD1981B
Table IV. Volume Settings for Line-In, CD Volume, AUX, and PCM-Out
Control Bits
Line-In (10h), CD (12h), AUX (16h), and PCM-Out (18h)
Reg. 76h
Left Channel Volume D[12:8]
Right Channel Volume D[4:0]
MSPLT* D15 WRITE READBACK Function
D7* WRITE
READBACK Function
0
0
0
0
1
0
0
0
1
0
0 0000
0 1000
1 1111
x xxxx
1 1111
0 0000
0 1000
1 1111
x xxxx
1 1111
12 dB Gain
0 dB Gain
34.5 dB Gain
– dB Gain, Muted
–34.5 dB Gain
x
x
x
x
1
0 0000
0 1000
1 1111
x xxxx
x xxxx
0 0000
0 1000
1 1111
x xxxx
x xxxx
1
1
x xxxx
x xxxx
1 1111
1 1111
1
1
x xxxx
x xxxx
– dB Gain,
0
Left Only Muted
– dB Gain, Left Muted 1
+12 dB Gain
0 dB Gain
–34.5 dB Gain
– dB Gain, Muted
– dB Gain,
Right Only Muted
–34.5 dB Gain
x xxxx
x xxxx
– dB Gain, Right Muted
*For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right
channels. If MSPLT is not set, RM bit has no effect.
x in the above table is a wild card and has no effect on the value.
Record Select Control Register (Index 1Ah)
Reg
No. Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
1Ah Record Select
X
X
X
X
X
LS2
LS1
LS0
X
X
X
X
X
RS2
RS1
RS0
0000h
All registers not shown and bits containing an X are assumed to be reserved. Used to select the record source independently for right and left. The default value is
0000h, which corresponds to MIC In. Refer to Table V for examples.
RS[2:0]
Right Record Select
LS[2:0]
Left Record Select
Table V. Settings for Record Select Control
REV. B
LS [10:8]
Left Record Source
RS [2:0]
Right Record Source
000
001
010
011
100
101
110
111
MIC
CD_L
Muted
AUX_L
LINE_IN_L
Stereo Mix (L)
Mono Mix
PHONE_IN
000
001
010
011
100
101
110
111
MIC
CD_R
Muted
AUX_R
LINE_IN_R
Stereo Mix (R)
Mono Mix
PHONE_IN
–15–
AD1981B
Record Gain Register (Index 1Ch)
Reg
No. Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
1Ch Record Gain
IM
X
X
X
LIM3
LIM2
LIM1
LIM0
RM* X
D6
D5
D4
D3
D2
X
X
RIM3 RIM2
D1
D0
Default
RIM1
RIM0 8000h
*For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right
channels. If MSPLT is not set, RM bit has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table VI for examples.
RIM[3:0]
Right Input Mixer Gain Control. Each LSB represents 1.5 dB, 0000 = 0 dB, and the gain range is 0 dB to 22.5 dB.
RM
Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately
from the IM bit. Otherwise, this bit will always read 0 and will have no affect when set to 1.
LIM[3:0]
Left Input Mixer Gain Control. Each LSB represents 1.5 dB, 0000 = 0 dB, and the gain range is 0 dB to 22.5 dB.
IM
Input Mute. When this bit is set to 1, both the left and right channels are muted, unless the MSPLT bit in
Register 76h is set to 1, in which case this mute bit will affect only the left channel.
Table VI. Settings for Record Gain Register
Control Bits
Record Gain (1Ch)
Reg. 76h
Left Channel Input Mixer D[11:8]
Right Channel Input Mixer D[3:0]
MSPLT* D15 WRITE
READBACK
Function
D7*
WRITE
READBACK Function
0
0
1111
1111
22.5 dB Gain
x
1111
1111
22.5 dB Gain
0
0
0000
0000
0 dB Gain
x
0000
0000
0 dB Gain
0
1
xxxx
xxxx
– dB Gain, Muted
x
xxxx
xxxx
– dB Gain, Muted
1
0
1111
1111
22.5 dB Gain
1
xxxx
xxxx
– dB Gain,
Right Only Muted
1
1
xxxx
xxxx
– dB Gain,
Left Only Muted
0
1111
1111
22.5 dB Gain
1
1
xxxx
xxxx
– dB Gain,
Left Muted
1
xxxx
xxxx
– dB Gain, Right Muted
*For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right
channels. If MSPLT is not set, RM bit has no effect.
x is a wild card and has no effect on the value.
General-Purpose Register (Index 20h)
Reg
No. Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
20h
X
X
X
X
X
X
MIX
MS
LPBK
X
X
X
X
X
X
X
0000h
General-Purpose
This register should be read before writing to generate a mask for only the bit(s) that need to be changed. All registers not shown and bits containing an X are assumed
to be reserved.
LPBK
Loopback Control. ADC/DAC Digital Loopback Mode.
0 = No Loopback (Default).
1 = Loopback PCM Digital Data from ADC Output to DAC.
MS
MIC Select. Selects mono MIC input.
0 = Select MIC1.
1 = Select MIC2.
See 2CMIC bit in Register 76h to enable stereo microphone recording.
MIX
Mono Output Select. Selects mono output audio source.
0 = Mixer mono output (reset default).
1 = MIC1 channel.
–16–
REV. B
AD1981B
Power-Down Control/Status Register (Index 26h)
Reg
No. Name
D15
D14
D13
D12
D11
D10 D9
D8
26h Power-Down Ctrl/Stat
EAPD
PR6
PR5
PR4
PR3
PR2 PR1
PR0 X
D7
D6
D5
D4
D3
D2
D1
D0
Default
X
X
X
REF
ANL
DAC
ADC
000Xh
The ready bits are read-only; writing to REF, ANL, DAC, ADC will have no effect. These bits indicate the status for the AD1981B subsections. If the bit is a 1, that
subsection is ready. Ready is defined as the subsection able to perform in its nominal state. All registers not shown and bits containing an X are assumed to be reserved.
ADC
ADC Sections Ready to Transmit Data.
DAC
DAC Sections Ready to Accept Data.
ANL
Analog Amplifiers, Attenuators, and Mixers Ready.
REF
Voltage References, VREF, and VREFOUT up to Nominal Level.
PR [6:0]
Codec Power-Down Modes. The first three bits are to be used individually rather than in combination with each
other. PR3 can be used in combination with PR2 or by itself. The mixer and reference cannot be powered down via
PR3 unless the ADCs and DACs are also powered down.
Nothing else can be powered up until the reference is up. PR5 has no effect unless all ADCs, DACs, and the ac-link
are powered down. The reference and the mixer can be either up or down, but all power-up sequences must be
allowed to run to completion before PR5 and PR4 are both set.
In multiple codec systems, the master codec’s PR5 and PR4 bits control the slave codec. PR5 is also effective in the
slave codec if the master’s PR5 bit is clear, but the PR4 bit has no effect except to enable or disable PR5.
EAPD
External Audio Power-Down Control. Controls the state of the EAPD pin.
EAPD = 0 sets the EAPD pin low, enabling an external power amplifier (reset default).
EAPD = 1 sets the EAPD pin high, shutting the external power amplifier off.
Power-Down State
Set Bits
PR [6:0]
ADCs and Input Mux Power-Down
PR0
[000 0001]
DACs Power-Down
PR1
[000 0010]
Analog Mixer Power-Down (VREF and VREFOUT On)
PR1, PR2
[000 0101]
Analog Mixer Power-Down (VREF and VREFOUT Off)
PR0, PR1, PR3
[000 1011]
AC-Link Interface Power-Down
PR4
[001 000]
Internal Clocks Disabled
PR0, PR1, PR4, PR5
[011 0011]
ADC and DAC Power-Down
PR0, PR1
[000 0011]
VREF Standby Mode
PR0, PR1, PR2, PR4, PR5
[011 0111]
Total Power-Down
PR0, PR1, PR2, PR3, PR4, PR5, PR6
[111 1111]
Headphone Amp Power-In Standby
PR6
[100 0000]
Extended Audio ID Register (Index 28h)
Reg
No. Name
D15
D14
D13 D12 D11
28h Ext’d Audio ID IDC1 IDC0 X
X
REVC1
D10
D9
D8
D7
D6
D5
D4
D3 D2
REVC0
AMAP
X
X
X
DSA1
DSA0
X
D1 D0
SPDIF X
VRAS
Default
X605h
The Extended Audio ID Register identifies which extended audio features are supported. A nonzero Extended Audio ID value indicates that one or more of the
extended audio features are supported. All registers not shown and bits containing an X are assumed to be reserved.
REV. B
–17–
AD1981B
VRAS
Variable Rate PCM Audio Support (Read-Only). This bit returns a 1 when Read To indicates that the variable rate
PCM audio is supported.
SPDIF
SPDIF Support (Read-Only). This bit returns a 1 when Read To indicates that the SPDIF transmitter is supported
(IEC958).
This bit is also used to validate that the SPDIF transmitter output is actually enabled. The SPDIF bit is allowed to be
set high only if the SPDIF pin (48) is pulled down at power-up, enabling the codec transmitter logic. If the SPDIF
pin is floating or pulled high at power-up, the transmitter logic is disabled; therefore, this bit returns a low, indicating that the SPDIF transmitter is not available. This bit must always be read back to verify that the SPDIF transmitter
is actually enabled.
DSA[1,0]
DAC Slot Assignments (Read/Write) (Reset Default = 00).
00 DACs 1, 2 = 3 and 4.
01 DACs 1, 2 = 7 and 8.
10 DACs 1, 2 = 6 and 9.
11 Reserved.
AMAP
Slot DAC Mappings Based on Codec ID (Read-Only). This bit returns a 1 when read to indicate that slot/DAC
mappings based on the codec ID are supported.
REVC[1,0]
REVC[1,0] = 01 indicates codec is AC ’97 revision 2.2 compliant (Read-Only).
IDC[1:0]
Indicates Codec Configuration (Read-Only).
00 = Primary.
01, 10, 11 = Secondary.
Extended Audio Status and Control Register (Index 2Ah)
Reg
No. Name
D15
2Ah Ext’d Audio Stat/Ctrl VFORCE
D14 D13
D12
D11 D10
D9
D8
D7
D6
D5
X
X
X
X
X
X
X
SPSA1 SPSA0 X
X
SPCV
D4
D3 D2
D1 D0
SPDIF X
Default
VRA 0000h
All registers not shown and bits containing an X are assumed to be reserved. The Extended Audio Status and Control register is a read/write register that provides
status and control of the extended audio features.
VRA
Variable Rate Audio (Read/Write).
VRA = 0 sets fixed sample rate audio at 48 kHz (reset default).
VRA = 1 enables variable rate audio mode (enables sample rate registers and SLOTREQ signaling).
SPDIF
SPDIF Transmitter Subsystem Enable/Disable Bit (Read/Write).
SPDIF = 1 enables the SPDIF transmitter.
SPDIF = 0 disables the SPDIF transmitter (default).
This bit is also used to validate that the SPDIF transmitter output is actually enabled. The SPDIF bit is only allowed
to be set high if the SPDIF pin (48) is pulled down at power-up, enabling the codec transmitter logic. If the
SPDIF pin is floating or pulled high at power-up, the transmitter logic is disabled and this bit therefore returns a low,
indicating that the SPDIF transmitter is not available. This bit must always be read back to verify that the SPDIF
transmitter is actually enabled.
SPSA[1:0]
SPDIF Slot Assignment Bits (Read/Write). These bits control the SPDIF slot assignment and respective defaults,
depending on the codec ID configuration.
SPCV
SPDIF Configuration Valid (Read-Only). Indicates the status of the SPDIF transmitter subsystem, enabling the
driver to determine if the currently programmed SPDIF configuration is supported. SPCV is always valid, independent
of the SPDIF enable bit status.
SPCV = 0 indicates current SPDIF configuration (SPSA, SPSR, DAC slot rate, DRS) is not valid (not supported).
SPCV = 1 indicates current SPDIF configuration (SPSA, SPSR, DAC slot rate, DRS) is valid (is supported).
VFORCE
Validity Force Bit (Reset Default = 0).
When asserted, this bit forces the SPDIF stream validity flag (Bit 28 within each SPDIF L/R subframe) to be
controlled by the V bit (D15) in Register 3Ah (SPDIF control register).
VFORCE = 0 and V = 0; the Validity bit is managed by the codec error detection logic.
VFORCE = 0 and V = 1; the Validity bit is forced high, indicating subframe data is invalid.
VFORCE = 1 and V = 0; the Validity bit is forced low, indicating subframe data is valid.
VFORCE = 1 and V = 1; the Validity bit is forced high, indicating subframe data is invalid.
–18–
REV. B
AD1981B
AC ’97 2.2 AMAP Compliant Default SPDIF Slot Assignments
Codec ID
Function
SPSA = 00
SPSA = 01
SPSA = 10
SPSA = 11
00
00
00
01
01
10
10
11
2-Ch Primary w/SPDIF
4-Ch Primary w/SPDIF
6-Ch Primary w/SPDIF
+2-Ch Secondary w/SPDIF
+4-Ch Secondary w/SPDIF
+2-Ch Secondary w/SPDIF
+4-Ch Secondary w/SPDIF
+2-Ch Secondary w/SPDIF
3 and 4
3 and 4
3 and 4
3 and 4
3 and 4
3 and 4
3 and 4
3 and 4
7 and 8 (default)
7 and 8
7 and 8
7 and 8
7 and 8
7 and 8
7 and 8
7 and 8
6 and 9
6 and 9 (default)
6 and 9
6 and 9 (default)
6 and 9
6 and 9 (default)
6 and 9
6 and 9
10 and 11
10 and 11
10 and 11 (default)
10 and 11 (default)
10 and 11 (default)
10 and 11 (default)
PCM Front DAC Rate Register (Index 2Ch)
Reg
No. Name
D15
2Ch PCM Front
DAC Rate
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
SRF15 SRF14 SRF13 SRF12 SRF11 SRF10 SRF9 SRF8 SRF7 SRF6 SRF5 SRF4 SRF3 SRF2 SRF1 SRF0 BB80h
This read/write sample rate control register contains a 16-bit unsigned value, representing the rate of operation in Hz.
SR[15:0]
Sample Rate. The sampling frequency range is from 7 kHz (1B58h) to 48 kHz (BB80h) in 1 Hz increments.
If 0 is written to VRA, the sample rate is reset to 48k.
PCM ADC Rate Register (Index 32h)
Reg
No. Name
32h PCM L/R
ADC Rate
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SRA15 SRA14 SRA13 SRA12 SRA11 SRA10 SRA9 SRA8 SRA7 SRA6 SRA5 SRA4 SRA3 SRA2 SRA1 SRA0 BB80h
This read/write sample rate control register contains 16-bit unsigned value, representing the rate of operation in Hz.
SR[15:0]
REV. B
Default
Sample Rate. The sampling frequency range is from 7 kHz (1B58h) to 48 kHz (BB80h) in 1 Hz increments.
If 0 is written to VRA, the sample rate is reset to 48k.
–19–
AD1981B
SPDIF Control Register (Index 3Ah)
Reg
No. Name
3Ah SPDIF
Control
D15
D14
D13
D12
D11
D10
D9
D8
V
X
SPSR1
SPSR0
L
CC6
CC5 CC4
D7
D6
D5
D4
D3
D2
D1
D0
Default
CC3
CC2
CC1
CC0
PRE COPY /AUD PRO 2000h
Register 3Ah is a read/write register that controls SPDIF functionality and manages bit fields propagated as channel status (or subframe in the V case). With the
exception of V, this register should be written to only when the SPDIF transmitter is disabled (SPDIF bit in Register 2Ah is 0). This ensures that control and status
information start up correctly at the beginning of SPDIF transmission.
PRO
Professional. 1 indicates professional use of channel status.
0 indicates consumer.
/AUD
Non-Audio. 1 indicates data is non-PCM format.
0 data is PCM.
COPY
Copyright. 1 indicates copyright is asserted.
0 copyright is not asserted.
PRE
Pre-Emphasis. 1 indicates filter pre-emphasis is 50 µs/15 µs.
0 pre-emphasis is none.
CC[6:0]
Category Code. Programmed according to IEC standards, or as appropriate.
L
Generation Level. Programmed according to IEC standards, or as appropriate.
SPSR[1:0]
SPDIF Transmit Sample Rate.
SPSR[1:0] = 00 transmit sample rate = 44.1 kHz.
SPSR[1:0] = 01 Reserved.
SPSR[1:0] = 10 transmit sample rate = 48 kHz (reset default).
SPSR[1:0] = 11 not supported.
V
Validity. This bit affects the validity flag (Bit 28 transmitted in each SPDIF L/R subframe) and enables the
SPDIF transmitter to maintain connection during error or mute conditions.
V = 1 Each SPDIF subframe (L + R) has Bit 28 set to 1. This tags both samples as invalid.
V = 0 Each SPDIF subframe (L + R) has Bit 28 set to 0 for valid data and 1 for invalid data (error condition).
Note that when V = 0, asserting the VFORCE bit (D15) in Register 2Ah (Ext’d Audio Stat/Ctrl) will force the
Validity flag low, marking both samples as valid.
–20–
REV. B
AD1981B
EQ Control Register (Index 60h)
Reg
No. Name
D15
60h EQ CTRL EQM
D14
D13
D12
D11
D10
D9
D8
D7
D6
MAD
LBEN
X
X
X
X
X
X
SYM CHS
D5
D4
D3
BCA5 BCA4 BCA3
D2
D1
D0
Default
BCA2 BCA1 BCA0 8080h
Register 60h is a read/write register that controls the equalizer functionality and data setup. This register also contains the Biquad and Coefficient Address pointer,
which is used in conjunction with the EQ Data Register (78h) to set up the equalizer coefficients. The reset default disables the equalizer function until the coefficients
can be properly set up by the software and sets the Symmetry bit to allow equal coefficients for left and right channels. All registers not shown and bits containing an X
are assumed to be reserved.
BCA[5,0]
Biquad and Coefficient Address Pointer
biquad 0 coef a0 BCA[5,0] = 011011
biquad 0 coef a1 BCA[5,0] = 011010
biquad 0 coef a2 BCA[5,0] = 011001
biquad 0 coef b1 BCA[5,0] = 011101
biquad 0 coef b2 BCA[5,0] = 011100
biquad 1 coef a0 BCA[5,0] = 100000
biquad 1 coef a1 BCA[5,0] = 011111
biquad 1 coef a2 BCA[5,0] = 011110
biquad 1 coef b1 BCA[5,0] = 100010
biquad 1 coef b2 BCA[5,0] = 100001
biquad 2 coef a0 BCA[5,0] = 100101
biquad 2 coef a1 BCA[5,0] = 100100
biquad 2 coef a2 BCA[5,0] = 100011
biquad 2 coef b1 BCA[5,0] = 100111
biquad 2 coef b2 BCA[5,0] = 100110
biquad 3 coef a0 BCA[5,0] = 101010
biquad 3 coef a1 BCA[5,0] = 101001
biquad 3 coef a2 BCA[5,0] = 101000
biquad 3 coef b1 BCA[5,0] = 101100
biquad 3 coef b2 BCA[5,0] = 101011
biquad 4 coef a0 BCA[5,0] = 101111
biquad 4 coef a1 BCA[5,0] = 101110
biquad 4 coef a2 BCA[5,0] = 101101
biquad 4 coef b1 BCA[5,0] = 110001
biquad 4 coef b2 BCA[5,0] = 110000
biquad 5 coef a0 BCA[5,0] = 110100
biquad 5 coef a1 BCA[5,0] = 110011
biquad 5 coef a2 BCA[5,0] = 110010
biquad 5 coef b1 BCA[5,0] = 110110
biquad 5 coef b2 BCA[5,0] = 110101
biquad 6 coef a0 BCA[5,0] = 111001
biquad 6 coef a1 BCA[5,0] = 111000
biquad 6 coef a2 BCA[5,0] = 110111
biquad 6 coef b1 BCA[5,0] = 111011
biquad 6 coef b2 BCA[5,0] = 111010
CHS
Channel Select.
CHS = 0 selects left channel coefficients data block.
CHS = 1 selects right channel coefficients data block.
SYM
Symmetry. When set to 1, this bit indicates that the left and right channel coefficients are equal. This shortens
the coefficients’ setup sequence since only the left channel coefficients need to be addressed and set up (the right channel coefficients are fetched from the left channel memory).
MAD
LBEN
Mixer ADC Loopback Enable. Enables mixer ADC data to be summed into PCM stream.
0 = No loopback allowed (default).
1 = Enable loopback.
EQM
REV. B
Equalizer Mute. When set to 1, this bit disables the equalizer function (allows all data to pass through). The
reset default sets this bit to 1, disabling the equalizer function until the biquad coefficients can be properly set.
–21–
AD1981B
EQ Data Register (Index 62h)
Reg
No. Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
62h EQ DATA CFD15 CFD14 CFD13 CFD12 CFD11 CFD10 CFD9 CFD8 CFD7 CFD6 CFD5 CFD4 CFD3 CFD2 CFD1 CFD0 0000h
This read/write register is used to transfer EQ biquad coefficients into memory. The register data is transferred to, or retrieved from, the address pointed to by the
BCA bits in the EQ CNTRL Register (60h). Data will be written to memory only if the EQM bit (Register 60h, Bit 15) is asserted.
CFD[15:0]
Coefficient Data. The biquad coefficients are fixed point format values with 16 bits of resolution. The CFD15 bit is
the MSB, and the CFD0 bit is the LSB.
Mixer ADC, Input Gain Register (Index 64h)
Reg
No. Name
D15
64h Mixer
Volume
D14
MXM X
D13
D12
D11
D10
X
X
LMG3 LMG2
D9
D8
D7
D6
LMG1 LMG0 RM* X
D5
D4
D3
D2
D1
X
X
RMG3 RMG2 RMG1
D0
Default
RMG0 8000h
*For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right
channels. If MSPLT is not set, the RM bit has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table VII for examples.
RMG[3:0]
Right Mixer Gain Control. This register controls the gain into the mixer ADC from 0 dB to a maximum gain of
22.5 dB. The least significant bit represents 1.5 dB.
RM
Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately
from the MXM bit. Otherwise, this bit will always read 0 and will have no affect when set to 1.
LMG[3:0]
Left Mixer Gain Control. This register controls the gain into the mixer ADC, from 0 dB to a maximum gain of 22.5 dB.
The least significant bit represents 1.5 dB.
MXM
Mixer Gain Register Mute.
0 = Unmuted.
1 = Muted (reset default).
Table VII. Settings for Mixer ADC, Input Gain
Control Bits
Mixer ADC, Input Gain (64h)
Reg. 76h
Left Channel Mixer Gain D[11:8]
Right Channel Mixer Gain D[3:0]
MSPLT* D15 WRITE READBACK
Function
D7*
WRITE READBACK Function
0
0
1111
1111
22.5 dB Gain
x
1111
1111
22.5 dB Gain
0
0
0000
0000
0 dB Gain
x
0000
0000
0 dB Gain
0
1
xxxx
xxxx
– dB Gain, Muted
x
xxxx
xxxx
– dB Gain, Muted
1
0
1111
1111
22.5 dB Gain
1
xxxx
xxxx
– dB Gain,
Right Only Muted
1
1
xxxx
xxxx
– dB Gain, Left Only Muted 0
1111
1111
22.5 dB Gain
1
1
xxxx
xxxx
– dB Gain, Left Muted
xxxx
xxxx
– dB Gain,
Right Muted
1
*For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right
channels. If MSPLT is not set, RM bit has no effect.
x is a wild card and has no effect on the value.
–22–
REV. B
AD1981B
Jack Sense/Audio Interrupt/Status Register (Index 72h)
Reg
No. Name
D15 D14
D13 D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
72h Jack Sense
X
X
JS
MT1
JS
MT0
JS1
EQB
JS0
EQB
JS1
TMR
JS0
TMR
JS1
MD
JS0
MD
JS1
ST
JS0
ST
JS1
INT
JS0
INT
0000h
X
JS
MT2
All register bits are read/write except for JS0ST and JS1ST, which are read only. All registers not shown and bits containing an X are assumed to be reserved.
JS0INT
Indicates Pin JS0 Has Generated an Interrupt. Remains set until the software services JS0 interrupt, i.e., JS0 ISR
should clear this bit by writing a 0 to it. Note that the interrupt to the system is actually an OR combination of
this bit and JS1INT. Also note that the actual interrupt implementation is selected by the INTS bit (Register 76h).
It is also possible to generate a software system interrupt by writing a 1 to this bit.
JS1INT
Indicates Pin JS1 Has Generated an Interrupt. Remains set until the software services JS1 interrupt, i.e., JS1 ISR
should clear this bit by writing a 0 to it. See JS0INT description for additional details.
JS0ST
JS0 State. This bit always reports the logic state of JS0 pin.
JS1ST
JS1 State. This bit always reports the logic state of JS1 pin.
JS0MD
JS0 Mode. This bit selects the operation mode for the JS0 pin.
0 = Jack Sense mode (default).
1 = Interrupt mode.
JS1MD
JS1 Mode. This bit selects the operation mode for the JS1 pin.
0 = Jack Sense mode (default).
1 = Interrupt mode.
JS0TMR
JS0 Timer Enable. If this bit is set to a 1, JS0 must be high for greater than 278 ms to be recognized.
JS1TMR
JS1 Timer Enable. If this bit is set to a 1, JS1 must be high for greater than 278 ms to be recognized.
JS0EQB
JS0 EQ Bypass Enable. This bit enables JS0 to control the EQ bypass. When this bit is set to 1, JS0 = 1 will
cause the EQ to be bypassed.
JS1EQB
JS1 EQ Bypass Enable. This bit enables JS1 to control the EQ bypass. When this bit is set to 1, JS1 = 1 will
cause the EQ to be bypassed.
JSMT[2,0]
JS Mute Enable Selector. These three bits select and enable the Jack Sense muting action (see Table VIII).
REV. B
–23–
AD1981B
Table VIII. Jack Sense Mute Select–JSMT [2:0]
JS1
JS0
REF HEADPHONE LINE OUT
H.P.
JSMT2 JSMT1 JSMT0 OUT
LINE
OUT
MONO
OUT
0
1
2
3
OUT (0)
OUT (0)
IN (1)
IN (1)
OUT (0)
IN (1)
OUT (0)
IN (1)
0
0
0
0
0
0
0
0
0
0
0
0
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
JS0 and JS1 Ignored.
4
OUT (0)
OUT (0)
0
0
1
FMUTE
FMUTE
ACTIVE
JS0 No Mute Action;
JS1 Mutes Line_Out.
5
6
7
OUT (0)
IN (1)
IN (1)
IN (1)
OUT (0)
IN (1)
0
0
0
0
0
0
1
1
1
FMUTE
ACTIVE
ACTIVE
ACTIVE
FMUTE
FMUTE
ACTIVE
ACTIVE
ACTIVE
8
OUT (0)
OUT (0)
0
1
0
FMUTE
FMUTE
ACTIVE
9
10
11
OUT (0)
IN (1)
IN (1)
IN (1)
OUT (0)
IN (1)
0
0
0
1
1
1
0
0
0
FMUTE
ACTIVE
ACTIVE
ACTIVE
FMUTE
FMUTE
ACTIVE
FMUTE
FMUTE
12
13
14
15
OUT (0)
OUT (0)
IN (1)
IN (1)
OUT (0)
IN (1)
OUT (0)
IN (1)
0
0
0
0
1
1
1
1
1
1
1
1
**
**
**
**
**
**
**
**
**
**
**
**
** Reserved
16
OUT (0)
OUT (0)
1
0
0
FMUTE
FMUTE
ACTIVE
JS0 Mutes Mono;
JS1 No Mute Action.
17
18
19
OUT (0)
IN (1)
IN (1)
IN (1)
OUT (0)
IN (1)
1
1
1
0
0
0
0
0
0
FMUTE
ACTIVE
ACTIVE
ACTIVE
FMUTE
ACTIVE
FMUTE
ACTIVE
FMUTE
20
OUT (0)
OUT (0)
1
0
1
FMUTE
FMUTE
ACTIVE
21
22
23
OUT (0)
IN (1)
IN (1)
IN (1)
OUT (0)
IN (1)
1
1
1
0
0
0
1
1
1
FMUTE
ACTIVE
ACTIVE
ACTIVE
FMUTE
FMUTE
FMUTE
ACTIVE
FMUTE
24
OUT (0)
OUT (0)
1
1
0
FMUTE
FMUTE
ACTIVE
25
26
27
OUT (0)
IN (1)
IN (1)
IN (1)
OUT (0)
IN (1)
1
1
1
1
1
1
0
0
0
FMUTE
ACTIVE
ACTIVE
ACTIVE
FMUTE
FMUTE
FMUTE
FMUTE
FMUTE
28
29
30
31
OUT (0)
OUT (0)
IN (1)
IN (1)
OUT (0)
IN (1)
OUT (0)
IN (1)
1
1
1
1
1
1
1
1
1
1
1
1
**
**
**
**
**
**
**
**
**
**
**
**
NOTES
JS0 No Mute Action;
JS1 Mutes Mono and
Line_Out.
JS0 Mutes Mono;
JS1 Mutes Line_Out.
JS0 Mutes Mono;
JS1 Mutes Mono and
Line_Out.
** Reserved
FMUTE = Output is forced to mute independent of the respective volume register setting.
ACTIVE = Output is not muted and its status is dependent on the respective volume register setting.
OUT = Nothing plugged into the jack and therefore the JS status is low (via the load resistor pull-down).
IN = Jack has plug inserted and therefore the JS status is high (via the codec JS internal pull-up).
–24–
REV. B
AD1981B
Serial Configuration Register (Index 74h)
Reg
No. Name D15
D14
D13
D12
D11 D10 D9 D8
74h Serial SLOT16 REGM2 REGM1 REGM0 X
Configuration
X
X
D7 D6 D5 D4
CHEN X
X
X
D3 D2
INTS X
D1
D0
Default
SPAL SPDZ SPLNK 7001h
This register is not reset when the reset register (Register 00h) is written. All registers not shown and bits containing an X are assumed to be reserved.
SPLNK
SPDIF Link. This bit enables the SPDIF to link with the DAC for data requesting.
0 = SPDIF and DAC are not linked.
1 = SPDIF and DAC are linked and receive the same data requests (reset default).
SPDZ
SPDIF DACZ.
0 = Repeat last sample out of the SPDIF stream if FIFO underruns (reset default).
1 = Forces midscale sample out the SPDIF stream if FIFO underruns.
SPAL
SPDIF ADC Loop-Around.
0 = SPDIF transmitter is connected to the ac-link stream (reset default).
1 = SPDIF transmitter is connected to the digital ADC stream, not the ac-link.
INTS
Interrupt Mode Select. This bit selects the JS interrupt implementation path.
0 = Bit 0 SLOT 12 (modem interrupt).
1 = Slot 6 valid bit (MIC ADC interrupt).
CHEN
Chain Enable. This bit enables chaining of a slave codec SDATA_IN stream into the ID0 pin (Pin 45).
0 = Disable chaining (reset default).
1 = Enable chaining into ID0 pin.
REGM0
Master Codec Register Mask.
REGM1
Slave 1 Codec Register Mask.
REGM2
Slave 2 Codec Register Mask.
SLOT16
Enable 16-Bit Slot Mode. SLOT16 makes all ac-link slots 16 bits in length, formatted into 16 slots. This is a
preferred mode for DSP serial port interfacing.
Miscellaneous Control Bit Register (Index 76h)
Reg
No. Name
D15
D14 D13
76th Misc
DACZ X
Control Bits
D12
D11
D10 D9
MSPLT LODIS DAM X
D8 D7
FMXE X
D6
D5 D4
MADPD 2CMIC X
D3
D2
D1
D0
Default
MADST VREFH VREFD MBG1 MBG0 0000h
All registers not shown and bits containing an X are assumed to be reserved.
MBG[1:0]
MIC Boost Gain Change Register.
These two bits allow changing the MIC preamp gain from the nominal 20 dB gain.
Note: This gain setting takes affect only while Bit D6 (M20) on the MIC volume register (0Eh) is set to 1; otherwise,
the MIC boost block has a gain of 0 dB.
00 = 20 dB gain (reset default).
01 = 10 dB gain.
10 = 30 dB gain.
11 = Reserved.
VREFD
VREFOUT Disable. Disables VREFOUT, placing it into High Z Out mode. Note that this bit overrides the VREFH bit
selection (see below).
0 = VREFOUT pin is driven by the internal reference (reset default).
1 = VREFOUT pin is placed into High Z Out mode.
VREFH
VREFOUT High. Changes VREFOUT from 2.25 V to 3.70 V for MIC bias applications.
0 = VREFOUT pin is set to 2.25 V output (reset default).
1 = VREFOUT pin is set to 3.70 V output.
REV. B
–25–
AD1981B
MADST
Mixer ADC Status Bit. Indicates status of mixer digitizing ADC (left and right channels).
0 = Mixer ADC not ready.
1 = Mixer ADC ready.
2CMIC
2-Channel MIC Select. This bit enables simultaneous recording from MIC1 and MIC2 inputs for applications that
use a stereo microphone array. Note that this register works in conjunction with the MS bit in Register 20h.
0 = MIC1 or MIC2 (determined by MS bit) is routed to the record selector’s left and right MIC channels as well
as to the mixer (reset default).
1 = MIC1 is routed to the record selector’s left MIC channel and MIC2 is routed to the record selector’s
right MIC channel. Note that in this mode, the MS bit should be set low and MIC1 can still be enabled into the mixer.
MADPD
Mixer ADC Power Down. Controls power down for mixer digitizing ADC.
0 = Mixer ADC is powered on (default).
1 = Mixer ADC is powered down.
FMXE
Front DAC into Mixer Enable. Controls the front (main) DAC to mixer mute switches.
0 = Front DAC outputs are allowed to sum into the mixer (reset default).
1 = Front DAC outputs are muted into the mixer (blocked).
DAM
Digital Audio Mode. PCM DAC outputs bypass the analog mixer and are sent directly to the codec output.
LODIS
LINE_OUT Disable. Disables the LINE_OUT pins (L/R), placing them into High Z mode so that the assigned
output audio jack can be shared for input function (or other function).
0 = LINE_OUT pins have normal audio drive capability (reset default).
1 = LINE_OUT pins are placed into High Z mode.
MSPLT
Mute Split. Allows separate mute control bits for Master, Headphone, LINE_IN, CD, AUX, and PCM volume control
registers as well as record gain register.
0 = Both left and right channel mutes are controlled by Bit 15 in the respective registers (reset default).
1 = Bit 15 affects only the left channel mute and Bit 7 affects only the right channel mute.
DACZ
DAC Zero-Fill. Determines DAC data fill under starved conditions.
0 = DAC data is repeated when DACs are starved for data (reset default).
1 = DAC is zero-filled when DACs are starved for data.
Vendor ID Register (Index 7Ch–7Eh)
Reg
No. Name
D15
7Ch Vendor ID1 F7
D14 D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2 D1 D0 Default
F6
F4
F3
F2
F1
F0
S7
S6
S5
S4
S3
S2
F5
S1
S0
4144h
S[7:0] This register is ASCII encoded to A.
F[7:0] This register is ASCII encoded to D.
Reg
No. Name
D15 D14 D13 D12 D11 D10 D9 D8 D7
7Eh Vendor ID2 T7 T6
T5 T4 T3
T2
D6
D5
D4
D3
D2
D1
D0
Default
T1 T0 REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0 5374h
T[7:0] This register is ASCII encoded to S.
REV[7:0] Vendor specific revision number: The AD1981B assigns 74h to this field.
Table IX. Codec ID and External Clock Selection Table
ID1
ID0
Codec ID
Codec Clocking Source
1
1
(00) Primary
24.576 MHz
(Local Xtal or External into XTL_IN)
1
0
(01) Secondary
12.288 MHz
(External into BIT_CLK)
0
1
(00) Primary
48.000 MHz
(External into XTL_IN)
0
0
(00) Primary
14.31818 MHz
(External into XTL_IN)
Note that internally, the ID pins have weak pull-ups and are inverted.
–26–
REV. B
AD1981B
OUTLINE DIMENSIONS
48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
0.75
0.60
0.45
9.00 BSC
SQ
1.60
MAX
37
48
36
1
1.45
1.40
1.35
0.15
0.05
10ⴗ
6ⴗ
2ⴗ
SEATING
PLANE
PIN 1
SEATING
PLANE
7ⴗ
3.5ⴗ
0ⴗ
0.08 MAX
COPLANARITY
(PINS DOWN)
VIEW A
25
12
13
0.50
BSC
VIEW A
ROTATED 90ⴗ CCW
COMPLIANT TO JEDEC STANDARDS MS-026BBC
REV. B
7.00
BSC SQ
TOP VIEW
0.20
0.09
–27–
24
0.27
0.22
0.17
AD1981B
Revision History
Location
Page
6/03—Data Sheet changed from REV. A to REV. B.
Changes to ENVIRONMENTAL CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2/03—Data Sheet changed from REV. 0 to REV. A.
Changes to FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changes to TIMING PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Change to Figure 6 caption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
–28–
REV. B
C03091–0–6/03(B)
Changes to TIMING PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4