3 MSPS, 12-/10-/8-Bit ADCs in 6-Lead TSOT AD7276/AD7277/AD7278 FEATURES FUNCTIONAL BLOCK DIAGRAM VDD Throughput rate: 3 MSPS Specified for VDD of 2.35 V to 3.6 V Power consumption 12.6 mW at 3 MSPS with 3 V supplies Wide input bandwidth 70 dB SNR at 1 MHz input frequency Flexible power/serial clock speed management No pipeline delays High speed serial interface SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible Temperature range: −40°C to +125°C Power-down mode: 0.1 μA typical 6-lead TSOT package 8-lead MSOP package AD7476 and AD7476A pin-compatible VIN The conversion process and data acquisition are controlled using CS and the serial clock, allowing the devices to interface with microprocessors or DSPs. The input signal is sampled on the falling edge of CS, and the conversion is also initiated at this point. There are no pipeline delays associated with the part. The AD7276/AD7277/AD7278 use advanced design techniques to achieve very low power dissipation at high throughput rates. The reference for the part is taken internally from VDD. This allows the widest dynamic input range to the ADC; therefore, the analog input range for the part is 0 to VDD. The conversion rate is determined by the SCLK. 12-/10-/8-BIT SUCCESSIVE APPROXIMATION ADC AD7276/ AD7277/ AD7278 CONTROL LOGIC SCLK SDATA GND 04903-001 CS Figure 1. GENERAL DESCRIPTION The AD7276/AD7277/AD7278 are 12-/10-/8-bit, high speed, low power, successive approximation analog-to-digital converters (ADCs), respectively. The parts operate from a single 2.35 V to 3.6 V power supply and feature throughput rates of up to 3 MSPS. The parts contain a low noise, wide bandwidth trackand-hold amplifier that can handle input frequencies in excess of 55 MHz. T/H Table 1. Part Number AD7276 AD7277 AD7278 AD72741 AD72731 1 Resolution 12 10 8 12 10 Package 8-Lead MSOP 6-Lead TSOT 8-Lead MSOP 6-Lead TSOT 8-Lead MSOP 6-Lead TSOT 8-Lead MSOP 8-Lead TSOT 8-Lead MSOP 8-Lead TSOT Part contains external reference pin. PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. 6. 3 MSPS ADCs in a 6-lead TSOT package. AD7476/AD7477/AD7478 and AD7476A/AD7477A/ AD7478A pin-compatible. High throughput with low power consumption. Flexible power/serial clock speed management. This allows maximum power efficiency at low throughput rates. Reference derived from the power supply. No pipeline delay. The parts feature a standard successive approximation ADC with accurate control of the sampling instant via a CS input and once-off conversion control. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. 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AD7276/AD7277/AD7278 TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 16 General Description ......................................................................... 1 Circuit Information.................................................................... 16 Functional Block Diagram .............................................................. 1 Converter Operation.................................................................. 16 Product Highlights ........................................................................... 1 ADC Transfer Function............................................................. 16 Revision History ............................................................................... 2 Typical Connection Diagram ................................................... 16 Specifications..................................................................................... 3 Modes of Operation ................................................................... 18 AD7276 Specifications................................................................. 3 Power vs. Throughput Rate....................................................... 21 AD7277 Specifications................................................................. 5 Serial Interface ................................................................................ 22 AD7278 Specifications................................................................. 7 AD7278 in a 10 SCLK Cycle Serial Interface.......................... 24 Timing Specifications—AD7276/AD7277/AD7278 ............... 8 Microprocessor Interfacing....................................................... 24 Timing Examples........................................................................ 10 Application Hints ........................................................................... 25 Absolute Maximum Ratings.......................................................... 11 Grounding and Layout .............................................................. 25 ESD Caution................................................................................ 11 Evaluating Performance.............................................................. 25 Pin Configurations and Function Descriptions ......................... 12 Outline Dimensions ....................................................................... 26 Typical Performance Characteristics ........................................... 13 Ordering Guide .......................................................................... 27 Terminology .................................................................................... 15 REVISION HISTORY 5/11—Rev. B to Rev. C Changes to Figure 21...................................................................... 16 Changes to Ordering Guide .......................................................... 27 Changes to Endnote 5 .................................................................... 27 11/09—Rev. A to Rev. B Changes to Table 2............................................................................ 3 Changes to Table 3............................................................................ 5 Changes to Table 4............................................................................ 7 Changes to Ordering Guide .......................................................... 27 10/05—Rev. 0 to Rev. A Updated Format..................................................................Universal Changes to Table 2............................................................................ 3 Changes to Table 5............................................................................ 8 Changes to the Partial Power-Down Mode Section .................. 18 Changes to the Power vs. Throughput Rate Section.................. 21 Updated Outline Dimensions ....................................................... 26 Changes to Ordering Guide .......................................................... 26 7/05—Revision 0: Initial Version Rev. C | Page 2 of 28 AD7276/AD7277/AD7278 SPECIFICATIONS AD7276 SPECIFICATIONS VDD = 2.35 V to 3.6 V, B Grade and A Grade: fSCLK = 48 MHz, fSAMPLE = 3 MSPS, Y Grade: 1 fSCLK = 16 MHz, fSAMPLE = 1 MSPS, TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE Signal-to-Noise + Distortion (SINAD) 4 Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD)4 Peak Harmonic or Spurious Noise (SFDR)4 Intermodulation Distortion (IMD)4 Second-Order Terms Third-Order Terms Aperture Delay Aperture Jitter Full Power Bandwidth DC ACCURACY Resolution Integral Nonlinearity4 Differential Nonlinearity4 Offset Error4 Gain Error4 Total Unadjusted Error4 (TUE) ANALOG INPUT Input Voltage Ranges DC Leakage Current Input Capacitance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN 5 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance5 Output Coding A Grade 2, 3 B, Y Grade2,3 Unit 68 69 70 −73 −78 −80 68 69 70 −73 −78 −80 dB min dB min dB typ dB max dB typ dB typ −82 −82 5 18 55 8 −82 −82 5 18 55 8 dB typ dB typ ns typ ps typ MHz typ MHz typ 12 ±1.5 +1/−0.99 ±4 ±3.5 ±5 12 ±1 +1/−0.99 ±3 ±3.5 ±3.5 Bits LSB max LSB max LSB max LSB max LSB max 0 to VDD ±1 ±5.5 42 10 0 to VDD ±1 ±5.5 42 10 V μA max μA max pF typ pF typ 1.7 2 0.7 0.8 ±1 2 1.7 2 0.7 0.8 ±1 2 V min V min V max V max μA max pF typ VDD − 0.2 0.2 ±2.5 4.5 VDD − 0.2 V min 0.2 V max ±2.5 μA max 4.5 pF typ Straight (natural) binary Rev. C | Page 3 of 28 Test Conditions/Comments fIN = 1 MHz sine wave, B Grade fIN = 100 kHz sine wave, Y Grade fa = 1 MHz, fb = 0.97 MHz fa = 1 MHz, fb = 0.97 MHz @ 3 dB @ 0.1 dB Guaranteed no missed codes to 12 bits −40°C to +85°C 85°C to 125°C When in track When in hold 2.35 V ≤ VDD ≤ 2.7 V 2.7 V < VDD ≤ 3.6 V 2.35 V ≤ VDD ≤ 2.7 V 2.7 V < VDD ≤ 3.6 V Typically 10 nA, VIN = 0 V or VDD ISOURCE = 200 μA, VDD = 2.35 V to 3.6 V ISINK = 200 μA AD7276/AD7277/AD7278 Parameter CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time4 Throughput Rate POWER REQUIREMENTS VDD IDD Normal Mode (Static) Normal Mode (Operational) Partial Power-Down Mode (Static) Full Power-Down Mode (Static) Power Dissipation 6 Normal Mode (Operational) Partial Power-Down Full Power-Down A Grade 2, 3 B, Y Grade2,3 Unit Test Conditions/Comments 291 875 60 3 291 875 60 3 ns max ns max ns min MSPS max 14 SCLK cycles with SCLK at 48 MHz, B Grade 14 SCLK cycles with SCLK at 16 MHz, Y Grade 2.35/3.6 2.35/3.6 V min/max 1 5.5 2.5 4.2 1.6 34 2 10 1 5.5 2.5 4.2 1.6 34 2 10 mA typ mA max mA max mA typ mA typ μA typ μA max μA max −40°C to +85°C, typically 0.1 μA 85°C to 125°C 19.8 9 12.6 4.8 102 7.2 19.8 9 12.6 4.8 102 7.2 mW max mW max mW typ mW typ μW typ μW max VDD = 3.6 V, fSAMPLE = 3 MSPS, B Grade VDD = 3.6 V, fSAMPLE = 1 MSPS, Y Grade VDD = 3 V, fSAMPLE = 3 MSPS, B Grade VDD = 3 V, fSAMPLE = 1 MSPS, Y Grade VDD = 3 V VDD = 3.6 V, −40°C to +85°C 1 Y Grade specifications are guaranteed by characterization. Temperature range from −40°C to +125°C. Typical specifications are tested with VDD = 3 V and at 25°C. 4 See the Terminology section. 5 Guaranteed by characterization. 6 See the Power vs. Throughput Rate section. 2 3 Rev. C | Page 4 of 28 See the Serial Interface section Digital I/Ps 0 V or VDD VDD = 3.6 V, SCLK on or off VDD = 2.35 V to 3.6 V, fSAMPLE = 3 MSPS, B Grade VDD = 2.35 V to 3.6 V, fSAMPLE = 1 MSPS, Y Grade VDD = 3 V, fSAMPLE = 3 MSPS, B Grade VDD = 3 V, fSAMPLE = 1 MSPS, Y Grade AD7276/AD7277/AD7278 AD7277 SPECIFICATIONS VDD = 2.35 V to 3.6 V, fSCLK = 48 MHz, fSAMPLE = 3 MSPS, TA = TMIN to TMAX, unless otherwise noted. Table 3. Parameter DYNAMIC PERFORMANCE Signal-to-Noise + Distortion (SINAD) 3 Total Harmonic Distortion (THD)3 Peak Harmonic or Spurious Noise (SFDR)3 Intermodulation Distortion (IMD)3 Second-Order Terms Third-Order Terms Aperture Delay Aperture Jitter Full Power Bandwidth DC ACCURACY Resolution Integral Nonlinearity3 Differential Nonlinearity3 Offset Error3 Gain Error3 Total Unadjusted Error (TUE)3 ANALOG INPUT Input Voltage Ranges DC Leakage Current Input Capacitance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN 4 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance4 Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time3 Throughput Rate A Grade 1, 2 B Grade1, 2 Unit 60.5 −70 −76 −80 60.5 −1 −76 −80 dB min dB max dB typ dB typ −82 −82 5 18 74 10 −82 −82 5 18 74 10 dB typ dB typ ns typ ps typ MHz typ MHz typ 10 ±0.5 ±0.5 ±1.5 ±2 ±2.5 10 ±0.5 ±0.5 ±1 ±1.5 ±2.5 Bits LSB max LSB max LSB max LSB max LSB max 0 to VDD ±1 ±5.5 42 10 0 to VDD ±1 ±5.5 42 10 V μA max μA max pF typ pF typ 1.7 2 0.7 0.8 ±1 2 1.7 2 0.7 0.8 ±1 2 V min V min V max V max μA max pF typ VDD − 0.2 0.2 ±2.5 4.5 250 60 3.45 VDD − 0.2 V min 0.2 V max ±2.5 μA max 4.5 pF typ Straight (natural) binary 250 60 3.45 Rev. C | Page 5 of 28 ns max ns min MSPS max Test Conditions/Comments fIN = 1 MHz sine wave fa = 1 MHz, fb = 0.97 MHz fa = 1 MHz, fb = 0.97 MHz @ 3 dB @ 0.1 dB Guaranteed no missed codes to 10 bits −40°C to +85°C 85°C to 125°C When in track When in hold 2.35 V ≤ VDD ≤ 2.7 V 2.7 V < VDD ≤ 3.6 V 2.35 V ≤ VDD ≤ 2.7 V 2.7 V < VDD ≤ 3.6 V Typically 10 nA, VIN = 0 V or VDD ISOURCE = 200 μA, VDD = 2.35 V to 3.6 V ISINK = 200 μA 12 SCLK cycles with SCLK at 48 MHz SCLK at 48 MHz AD7276/AD7277/AD7278 Parameter POWER REQUIREMENTS VDD IDD Normal Mode (Static) Normal Mode (Operational) Partial Power-Down Mode (Static) Full Power-Down Mode (Static) Power Dissipation 5 Normal Mode (Operational) Partial Power-Down Full Power-Down A Grade 1, 2 B Grade1, 2 Unit 2.35/3.6 2.35/3.6 V min/max 0.6 5.5 3.5 34 2 10 0.6 5.5 3.5 34 2 10 mA typ mA max mA typ μA typ μA max μA max −40°C to +85°C, typically 0.1 μA 85°C to 125°C 19.8 10.5 102 7.2 19.8 10.5 102 7.2 mW max mW typ μW typ μW max VDD = 3.6 V, fSAMPLE = 3 MSPS VDD = 3 V VDD = 3 V VDD = 3.6 V, −40°C to +85°C 1 Temperature range from −40°C to +125°C. Typical specifications are tested with VDD = 3 V and at 25°C. 3 See the Terminology section. 4 Guaranteed by characterization. 5 See the Power vs. Throughput Rate section. 2 Rev. C | Page 6 of 28 Test Conditions/Comments Digital I/Ps 0 V or VDD VDD = 3.6 V, SCLK on or off VDD = 2.35 V to 3.6 V, fSAMPLE = 3 MSPS VDD = 3 V AD7276/AD7277/AD7278 AD7278 SPECIFICATIONS VDD = 2.35 V to 3.6 V, fSCLK = 48 MHz, fSAMPLE = 3 MSPS, TA = TMIN to TMAX, unless otherwise noted. Table 4. Parameter DYNAMIC PERFORMANCE Signal-to-Noise + Distortion (SINAD) 3 Total Harmonic Distortion (THD)3 Peak Harmonic or Spurious Noise (SFDR)3 Intermodulation Distortion (IMD)3 Second-Order Terms Third-Order Terms Aperture Delay Aperture Jitter Full Power Bandwidth Full Power Bandwidth DC ACCURACY Resolution Integral Nonlinearity3 Differential Nonlinearity3 Offset Error3 Gain Error3 Total Unadjusted Error (TUE)3 ANALOG INPUT Input Voltage Ranges DC Leakage Current Input Capacitance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN 4 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance4 Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time3 Throughput Rate A Grade 1, 2 B Grade1, 2 Unit 49 −66 −73 −69 49 −67 −73 −69 dB min dB max dB typ dB typ −76 −76 5 18 74 10 −76 −76 5 18 74 10 dB typ dB typ ns typ ps typ MHz typ MHz typ 8 ±0.2 ±0.3 ±0.9 ±1.2 ±1.5 8 ±0.2 ±0.3 ±0.5 ±1 ±1.5 Bits LSB max LSB max LSB max LSB max LSB max 0 to VDD ±1 ±5.5 42 10 0 to VDD ±1 ±5.5 42 10 V μA max μA max pF typ pF typ 1.7 2 0.7 0.8 ±1 2 1.7 2 0.7 0.8 ±1 2 V min V min V max V max μA max pF typ VDD − 0.2 0.2 ±2.5 4.5 208 60 4 VDD − 0.2 V min 0.2 V max ±2.5 μA max 4.5 pF typ Straight (natural) binary 208 60 4 Rev. C | Page 7 of 28 ns max ns min MSPS max Test Conditions/Comments fIN = 1 MHz sine wave fa = 1 MHz, fb = 0.97 MHz fa = 1 MHz, fb = 0.97 MHz @ 3 dB @ 0.1 dB Guaranteed no missed codes to 8 bits −40°C to +85°C 85°C to 125°C When in track When in hold 2.35 V ≤ VDD ≤ 2.7 V 2.7 V < VDD ≤ 3.6 V 2.35 V ≤ VDD ≤ 2.7 V 2.7 V < VDD ≤ 3.6 V ISOURCE = 200 μA, VDD = 2.35 V to 3.6 V ISINK = 200 μA 10 SCLK cycles with SCLK at 48 MHz SCLK at 48 MHz AD7276/AD7277/AD7278 Parameter POWER REQUIREMENTS VDD IDD Normal Mode (Static) Normal Mode (Operational) Partial Power-Down Mode (Static) Full Power-Down Mode (Static) Power Dissipation 5 Normal Mode (Operational) Partial Power-Down Full Power-Down A Grade 1, 2 B Grade1, 2 Unit 2.35/3.6 2.35/3.6 V min/max 0.5 5.5 3.5 34 2 10 0.5 5.5 3.5 34 2 10 mA typ mA max mA typ μA typ μA max μA max −40°C to +85°C, typically 0.1 μA +85°C to +125°C 19.8 10.5 102 7.2 19.8 10.5 102 7.2 mW max mW typ μW typ μW max VDD = 3.6 V, fSAMPLE = 3 MSPS VDD = 3 V VDD = 3 V VDD = 3.6 V, −40°C to +85°C Test Conditions/Comments Digital I/Ps = 0 V or VDD VDD = 3.6 V, SCLK on or off VDD = 2.35 V to 3.6 V, fSAMPLE = 3 MSPS VDD = 3 V 1 Temperature range from −40°C to +125°C. Typical specifications are tested with VDD = 3 V and at 25°C. 3 See the Terminology section. 4 Guaranteed by characterization. 5 See the Power vs. Throughput Rate section. 2 TIMING SPECIFICATIONS—AD7276/AD7277/AD7278 VDD = 2.35 V to 3.6 V, TA = TMIN to TMAX, unless otherwise noted. 1 Table 5. Parameter 2 fSCLK 3 tCONVERT tQUIET t1 t2 t3 5 t45 t5 t6 t75 t8 t9 TPOWER-UP 6 Limit at TMIN, TMAX 500 48 16 14 × tSCLK 12 × tSCLK 10 × tSCLK 4 Unit kHz min 4 MHz max MHz max 3 6 4 15 0.4 tSCLK 0.4 tSCLK 5 14 5 4.2 1 ns min ns min ns max ns max ns min ns min ns min ns max ns min ns max μs max ns min Description B grade Y grade AD7276 AD7277 AD7278 Minimum quiet time required between the bus relinquish and the start of the next conversion Minimum CS pulse width CS to SCLK setup time Delay from CS until SDATA three-state disabled Data access time after SCLK falling edge SCLK low pulse width SCLK high pulse width SCLK to data valid hold time SCLK falling edge to SDATA three-state SCLK falling edge to SDATA three-state CS rising edge to SDATA three-state Power-up time from full power-down 1 Sample tested during initial release to ensure compliance. All timing specifications given are with a 10 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. Guaranteed by characterization. All input signals are specified with tr = tf = 2 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. 3 Mark/space ratio for the SCLK input is 40/60 to 60/40. 4 Minimum fSCLK at which specifications are guaranteed. 5 The time required for the output to cross the VIH or VIL voltage. 6 See the Power-Up Times section. 2 Rev. C | Page 8 of 28 AD7276/AD7277/AD7278 t4 t8 SCLK VIL Figure 2. Access Time After SCLK Falling Edge Figure 4. SCLK Falling Edge SDATA Three-State t7 SCLK 04903-003 VIH SDATA VIL 1.4V SDATA Figure 3. Hold Time After SCLK Falling Edge Rev. C | Page 9 of 28 04903-004 VIH SDATA 04903-002 SCLK AD7276/AD7277/AD7278 This satisfies the requirement of 60 ns for tACQ. Figure 6 also shows that tACQ comprises 0.5(1/fSCLK) + t8 + tQUIET, where t8 = 14 ns max. This allows a value of 43 ns for tQUIET, satisfying the minimum requirement of 4 ns. TIMING EXAMPLES For the AD7276, if CS is brought high during the 14th SCLK rising edge after the two leading zeros and 12 bits of the conversion have been provided, the part can achieve the fastest throughput rate, 3 MSPS. If CS is brought high during the 16th SCLK rising edge after the two leading zeros and 12 bits of the conversion and two trailing zeros have been provided, a throughput rate of 2.97 MSPS is achievable. This is illustrated in the following two timing examples. Timing Example 2 The example in Figure 7 uses a 16 SCLK cycle, fSCLK = 48 MHz, and the throughput is 2.97 MSPS. This produces a cycle time of t2 + 12.5(1/fSCLK) + tACQ = 336 ns, where t2 = 6 ns minimum and tACQ = 70 ns. Figure 7 shows that tACQ comprises 2.5(1/fSCLK) + t8 + tQUIET, where t8 = 14 ns max. This satisfies the minimum requirement of 4 ns for tQUIET. Timing Example 1 In Figure 6, using a 14 SCLK cycle, fSCLK = 48 MHz and the throughput is 3 MSPS. This produces a cycle time of t2 + 12.5(1/fSCLK) + tACQ = 333 ns, where t2 = 6 ns minimum and tACQ = 67 ns. t1 CS SCLK 1 2 t6 3 4 t3 SDATA Z B 5 13 DB11 DB10 DB9 15 t5 t7 t4 ZERO 14 16 t8 tQUIET DB1 DB0 ZERO THREESTATE 2 LEADING ZEROS ZERO 2 TRAILING ZEROS THREE-STATE 04903-005 tCONVERT t2 1/THROUGHPUT Figure 5. AD7276 Serial Interface Timing Diagram t1 CS tCONVERT t2 1 2 3 4 t3 THREESTATE Z 5 t7 t4 ZERO DB11 DB10 13 14 t9 t5 DB9 DB1 tQUIET DB0 THREE-STATE 2 LEADING ZEROS 04903-034 SDATA B t6 SCLK 1/THROUGHPUT Figure 6. AD7276 Serial Interface Timing 14 SCLK Cycle t1 CS tCONVERT t2 B 1 2 3 4 5 12 13 14 15 16 t8 tQUIET tACQUISITION 12.5(1/fSCLK ) 1/THROUGHPUT Figure 7. AD7276 Serial Interface Timing 16 SCLK Cycle Rev. C | Page 10 of 28 04903-006 SCLK AD7276/AD7277/AD7278 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 6. Parameters VDD to GND Analog Input Voltage to GND Digital Input Voltage to GND Digital Output Voltage to GND Input Current to Any Pin Except Supplies 1 Operating Temperature Range Commercial (B grade) Storage Temperature Range Junction Temperature 6-Lead TSOT Package θJA Thermal Impedance θJC Thermal Impedance 8-Lead MSOP Package θJA Thermal Impedance θJC Thermal Impedance Lead Temperature Soldering Reflow (10 sec to 30 sec) Lead Temperature Soldering Reflow (10 sec to 30 sec) ESD 1 Ratings −0.3 V to +6 V −0.3 V to VDD + 0.3 V −0.3 V to +6 V −0.3 V to VDD + 0.3 V ±10 mA −40°C to +125°C −65°C to +150°C 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 230°C/W 92°C/W 205.9°C/W 43.74°C/W 255°C 260°C 1.5 kV Transient currents of up to 100 mA cause SCR latch-up. Rev. C | Page 11 of 28 AD7276/AD7277/AD7278 GND 2 AD7276/ AD7277/ AD7278 6 VDD 1 CS SDATA 2 5 SDATA TOP VIEW VIN 3 (Not to Scale) 4 SCLK CS 3 04903-007 VDD 1 NC 4 AD7276/ AD7277/ AD7278 TOP VIEW (Not to Scale) 8 VIN 7 GND 6 SCLK 5 NC NC = NO CONNECT Figure 8. 6-Lead TSOT Pin Configuration 04903-008 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 9. 8-Lead MSOP Pin Configuration Table 7. Pin Function Descriptions Pin No. 6-Lead TSOT 8-Lead MSOP 1 1 2 7 Mnemonic VDD GND 3 4 8 6 VIN SCLK 5 2 SDATA 6 3 CS 4, 5 NC Description Power Supply Input. The VDD range for the AD7276/AD7277/AD7278 is 2.35 V to 3.6 V. Analog Ground. Ground reference point for all circuitry on the AD7276/AD7277/AD7278. All analog input signals should be referred to this GND voltage. Analog Input. Single-ended analog input channel. The input range is 0 V to VDD. Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the conversion process of the AD7276/AD7277/AD7278. Data Out. Logic output. The conversion result from the AD7276/AD7277/AD7278 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7276 consists of two leading zeros followed by 12 bits of conversion data and two trailing zeros, provided MSB first. The data stream from the AD7277 consists of two leading zeros followed by 10 bits of conversion data and four trailing zeros, provided MSB first. The data stream from the AD7278 consists of two leading zeros followed by 8 bits of conversion data and six trailing zeros, provided MSB first. Chip Select. Active low logic input. This input provides the dual function of initiating conversion on the AD7276/AD7277/AD7278 and framing the serial data transfer. No Connect. Rev. C | Page 12 of 28 AD7276/AD7277/AD7278 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. 73.0 16,384 POINT FFT FSAMPLE = 3MSPS FIN = 1MHz SINAD = 71.2dB THD = –80.9dB SFDR = –82.4dB VDD = 3V –20 VDD = 3.6V 72.0 71.5 SNR (dB) SNR (dB) –40 72.5 –60 VDD = 3V 71.0 VDD = 2.35V 70.5 –80 70.0 –100 –120 0 04903-013 04903-009 69.5 69.0 100 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1000 Figure 13. AD7276 SNR vs. Analog Input Frequency at 3 MSPS for Various Supply Voltages, SCLK Frequency = 48 MHz Figure 10. AD7276 Dynamic Performance at 3 MSPS, Input Tone = 1 MHz –10 30,000 16,384 POINT FFT FSAMPLE = 3MSPS FIN = 1MHz SINAD = 61.6dB THD = –80.2dB SFDR = –83.4dB VDD = 3V –30 –40 30,000 CODES 25,000 NUMBER OF OCCURRENCES –20 –60 –70 –80 –90 20,000 15,000 10,000 –110 0 04903-016 04903-010 5,000 –100 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 2046 FREQUENCY (kHz) 2049 2050 Figure 14. Histogram of Codes for 30,000 Samples 72.5 –72 VDD = 3.6V 72.0 –74 71.5 –76 VDD = 2.35V 71.0 –78 VDD = 2.35V THD (dB) 70.0 2048 CODE Figure 11. AD7277 Dynamic Performance at 3 MSPS, Input Tone = 1 MHz 70.5 2047 VDD = 3V 69.5 VDD = 3V –80 –82 –84 69.0 VDD = 3.6V –86 04903-012 68.5 68.0 67.5 100 1000 –88 04903-017 SNR (dB) –50 SINAD (dB) 1500 INPUT FREQUENCY (kHz) FREQUENCY (kHz) –90 100 1500 INPUT FREQUENCY (kHz) 1000 INPUT FREQUENCY (kHz) Figure 12. AD7276 SINAD vs. Analog Input Frequency at 3 MSPS for Various Supply Voltages, SCLK Frequency = 48 MHz Figure 15. THD vs. Analog Input Frequency at 3 MSPS for Various Supply Voltages, SCLK Frequency = 48 MHz Rev. C | Page 13 of 28 1500 AD7276/AD7277/AD7278 1.0 –50 VDD = 3V 0.8 –55 0.6 DNL ERROR (LSB) RIN = 100Ω –60 THD (dB) –65 –70 RIN = 10Ω –75 0.4 0.2 0 –0.2 –0.4 –80 1000 04903-015 –90 100 –0.8 –1.0 1500 INPUT FREQUENCY (kHz) 1.0 VDD = 3V 0.6 0.2 0 –0.2 –0.4 –0.6 04903-011 INL ERROR (LSB) 0.4 –0.8 –1.0 0 500 1000 1500 2000 2500 3000 0 500 1000 1500 2000 2500 3000 CODE Figure 16. THD vs. Analog Input Frequency at 3 MSPS for Various Source Impedances, SCLK Frequency = 48 MHz, Supply Voltage = 3 V 0.8 04903-014 –0.6 RIN = 0Ω –85 3500 4000 CODE Figure 17. AD7276 INL Performance Rev. C | Page 14 of 28 Figure 18. AD7276 DNL Performance 3500 4000 AD7276/AD7277/AD7278 TERMINOLOGY Integral Nonlinearity The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. For the AD7276/ AD7277/AD7278, the endpoints of the transfer function are zero scale at 0.5 LSB below the first code transition and full scale at 0.5 LSB above the last code transition. Total Harmonic Distortion (THD) The ratio of the rms sum of harmonics to the fundamental. It is defined as: Differential Nonlinearity The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. where: V1 is the rms amplitude of the fundamental. V2, V3, V4, V5, and V6 are the rms amplitudes of the second through sixth harmonics. Offset Error The deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, that is, AGND + 0.5 LSB. Gain Error The deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal after adjusting for the offset error, that is, VREF − 1.5 LSB. Total Unadjusted Error A comprehensive specification that includes gain, linearity, and offset errors. Track-and-Hold Acquisition Time The time required after the conversion for the output of the track-and-hold amplifier to reach its final value within ±0.5 LSB. See the Serial Interface section for more details. Signal-to-Noise + Distortion Ratio (SINAD) The measured ratio of signal to noise plus distortion at the output of the ADC. The signal is the rms amplitude of the fundamental, and noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fS/2), including harmonics but excluding dc. The ratio is dependent on the number of quantization levels in the digitization process: the more levels, the smaller the quantization noise. For an ideal N-bit converter, the SINAD is defined as SINAD = 6.02 N + 1.76 dB According to this equation, the SINAD is 74 dB for a 12-bit converter and 62 dB for a 10-bit converter. However, various error sources in the ADC, including integral and differential nonlinearities and internal ac noise sources, cause the measured SINAD to be less than its theoretical value. THD (dB ) = 20 log V22 + V32 + V4 2 + V52 + V62 V1 Peak Harmonic or Spurious Noise The ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2, excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum; however, for ADCs with harmonics buried in the noise floor, it is determined by a noise peak. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, …. Intermodulation distortion terms are those for which neither m nor n are equal to zero. For example, the second-order terms include (fa + fb) and (fa − fb), and the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb). The AD7276/AD7277/AD7278 are tested using the CCIF standard in which two input frequencies are used (see fa and fb in the specifications). In this case, the second-order terms are usually distanced in frequency from the original sine waves, and the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The intermodulation distortion is calculated in a similar manner to the THD specification, that is, the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels. Aperture Delay The measured interval between the leading edge of the sampling clock and the point at which the ADC takes the sample. Aperture Jitter The sample-to-sample variation when the sample is taken. Rev. C | Page 15 of 28 AD7276/AD7277/AD7278 THEORY OF OPERATION CIRCUIT INFORMATION CHARGE REDISTRIBUTION DAC SW1 Figure 20. ADC Conversion Phase ADC TRANSFER FUNCTION The output coding of the AD7276/AD7277/AD7278 is straight binary. The designed code transitions occur midway between successive integer LSB values, such as 0.5 LSB and 1.5 LSB. The LSB size is VDD/4,096 for the AD7276, VDD/1,024 for the AD7277, and VDD/256 for the AD7278. The ideal transfer characteristic for the AD7276/AD7277/AD7278 is shown in Figure 21. ADC CODE 111...111 111...110 SAMPLING CAPACITOR B ACQUISITION PHASE VDD/2 SW2 COMPARATOR AGND CONTROL LOGIC 04903-019 SW1 111...000 011...111 1LSB = VREF /4096 (AD7276) 1LSB = VREF /1024 (AD7277) 1LSB = VREF /256 (AD7278) 000...010 000...001 000...000 0V 0.5LSB +VDD – 1.5LSB ANALOG INPUT Figure 21. AD7276/AD7277/AD7278 Transfer Characteristics TYPICAL CONNECTION DIAGRAM Figure 22 shows a typical connection diagram for the AD7276/ AD7277/AD7278. VREF is taken internally from VDD; therefore, VDD should be decoupled. This provides an analog input range of 0 V to VDD. The conversion result is output in a 16-bit word with two leading zeros followed by the 12-bit, 10-bit, or 8-bit result. The 12-bit result from the AD7276 is followed by two trailing zeros; the 10-bit and 8-bit results from the AD7277 and AD7278 are followed by four and six trailing zeros, respectively. CHARGE REDISTRIBUTION DAC A COMPARATOR VDD/2 CONVERTER OPERATION VIN CONTROL LOGIC SW2 AGND The AD7276/AD7277/AD7278 also feature a power-down option to save power between conversions. The power-down feature is implemented across the standard serial interface as described in the Modes of Operation section. The AD7276/AD7277/AD7278 are successive approximation ADCs that are based on a charge redistribution DAC. Figure 19 and Figure 20 show simplified schematics of the ADC. Figure 19 shows the ADC during its acquisition phase, where SW2 is closed, SW1 is in Position A, the comparator is held in a balanced condition, and the sampling capacitor acquires the signal on VIN. ACQUISITION PHASE B 04903-021 The AD7276/AD7277/AD7278 provide the user with an onchip track-and-hold ADC and a serial interface housed in a tiny 6-lead TSOT or an 8-lead MSOP package, which offers the user considerable space-saving advantages over alternative solutions. The serial clock input accesses data from the part and provides the clock source for the successive approximation ADC. The analog input range is 0 V to VDD. An external reference is not required for the ADC, and there is no reference on-chip. The reference for the AD7276/AD7277/AD7278 is derived from the power supply, resulting in the widest dynamic input range. SAMPLING CAPACITOR A VIN 04903-020 The AD7276/AD7277/AD7278 are fast, micropower, 12-/10-/ 8-bit, single-supply ADCs, respectively. The parts can be operated from a 2.35 V to 3.6 V supply. When operated from a supply voltage within this range, the AD7276/AD7277/AD7278 are capable of throughput rates of 3 MSPS when provided with a 48 MHz clock. Figure 19. ADC Acquisition Phase When the ADC starts a conversion, SW2 opens and SW1 moves to Position B, causing the comparator to become unbalanced (see Figure 20). The control logic and the charge redistribution DACs are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC output code. Alternatively, because the supply current required by the AD7276/ AD7277/AD7278 is so low, a precision reference can be used as the supply source for the AD7276/AD7277/AD7278. A REF19x voltage reference (REF193 for 3 V) can be used to supply the required voltage to the ADC (see Figure 22). This configuration is especially useful if the power supply is noisy or the system’s supply voltage is a value other than 3 V (for example, 5 V or 15 V). The REF19x outputs a steady voltage to the AD7276/AD7277/AD7278. If the low dropout REF193 is used, it must supply a current of typically 1 mA to the AD7276/AD7277/AD7278. When the ADC is converting at a rate of 3 MSPS, the REF193 must supply a maximum of 5 mA to the AD7276/AD7277/AD7278. Rev. C | Page 16 of 28 AD7276/AD7277/AD7278 3V 0.1µF 10µF VDD D1 VIN 5V SUPPLY REF193 1µF TANT Large source impedances significantly affect the ac performance of these ADCs and can necessitate the use of an input buffer amplifier. The AD8021 op amp is compatible with these devices; however, the choice of the op amp is a function of the particular application. C1 4pF 0.1µF R1 C2 D2 CONVERSION PHASE—SWITCH OPEN TRACK PHASE—SWITCH CLOSED 680nF VDD 0V TO VDD INPUT VIN 04903-023 The load regulation of the REF193 is typically 10 ppm/mA (REF193, VS = 5 V), which results in an error of 50 ppm (150 μV) for the 5 mA drawn from it. When VDD = 3 V from the REF193, it corresponds to an error of 0.204 LSB, 0.051 LSB, and 0.0128 LSB for the AD7276, AD7277, and AD7278, respectively. For applications where power consumption is of concern, use the power-down mode of the ADC and the sleep mode of the REF19x reference to improve power performance. See the Modes of Operation section. Figure 23. Equivalent Analog Input Circuit AD7276/ AD7277/ AD7278 SCLK SDATA CS DSP/ µC/µP SERIAL INTERFACE 04903-022 GND Figure 22. REF193 as Power Supply to the AD7276/AD7277/AD7278 Table 8 provides typical performance data with various references used as a VDD source with the same setup conditions. Table 8. AD7276 Performance (Various Voltage References IC) Reference Tied to VDD AD780 @ 3 V AD780 @ 2.5 V REF193 SNR Performance, 1 MHz Input 71.3 dB 70.1 dB 70.9 dB Analog Input Figure 23 shows an equivalent circuit of the analog input structure of the AD7276/AD7277/AD7278. The two diodes, D1 and D2, provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 300 mV. Signals exceeding this value cause these diodes to become forward biased and to start conducting current into the substrate. These diodes can conduct a maximum current of 10 mA without causing irreversible damage to the part. Capacitor C1 in Figure 23 is typically about 4 pF and can primarily be attributed to pin capacitance. Resistor R1 is a lumped component made up of the on resistance of a switch. This resistor is typically about 75 Ω. Capacitor C2 is the ADC sampling capacitor and has a capacitance of 4 pF typically when in hold mode and 32 pF typically when in track mode. For ac applications, removing high frequency components from the analog input signal is recommended by using a band-pass filter on the relevant analog input pin. In applications where the harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. When no amplifier is used to drive the analog input, the source impedance should be limited to a low value. The maximum source impedance depends on the amount of THD that can be tolerated. The THD increases as the source impedance increases and performance degrades. Figure 16 shows a graph of the THD vs. the analog input frequency for different source impedances when using a supply voltage of 3 V and sampling at a rate of 3 MSPS. Digital Inputs The digital inputs applied to the AD7276/AD7277/AD7278 are not limited by the maximum ratings that limit the analog inputs. Instead, the digital inputs applied to the AD7276/AD7277/ AD7278 can be 6 V and are not restricted by the VDD + 0.3 V limit of the analog inputs. For example, if the AD7276/AD7277/ AD7278 are operated with a VDD of 3 V, then 5 V logic levels can be used on the digital inputs. However, it is important to note that the data output on SDATA still has 3 V logic levels when VDD = 3 V. Another advantage of SCLK and CS not being restricted by the VDD + 0.3 V limit is that power supply sequencing issues are avoided. For example, unlike with the analog inputs, with the digital inputs, if CS or SCLK is applied before VDD, there is no risk of latch-up. Rev. C | Page 17 of 28 AD7276/AD7277/AD7278 MODES OF OPERATION The mode of operation of the AD7276/AD7277/AD7278 is selected by controlling the logic state of the CS signal during a conversion. There are three possible modes of operation: normal mode, partial power-down mode, and full power-down mode. The point at which CS is pulled high after the conversion has been initiated determines which power-down mode, if any, the device enters. Similarly, if the device is already in power-down mode, CS can control whether the device returns to normal operation or remains in power-down mode. These modes of operation are designed to provide flexible power management options, which can be chosen to optimize the power dissipation/ throughput rate ratio for different application requirements. Normal Mode This mode is intended for fastest throughput rate performance because the device remains fully powered at all times, eliminating worry about power-up times. Figure 24 shows the general diagram of AD7276/AD7277/AD7278 operation in this mode. The conversion is initiated on the falling edge of CS as described in the Serial Interface section. To ensure that the part remains fully powered up at all times, CS must remain low until at least 10 SCLK falling edges elapse after the falling edge of CS. If CS is brought high after the 10th SCLK falling edge but before the 16th SCLK falling edge, the part remains powered up, but the conversion is terminated and SDATA goes back into three-state. CS can idle high until the next conversion or low until CS returns high before the next conversion (effectively idling CS low). Once a data transfer is complete (SDATA has returned to threestate), another conversion can be initiated after the quiet time, tQUIET, has elapsed by bringing CS low again. Partial Power-Down Mode This mode is intended for use in applications where slower throughput rates are required. An example of this is when either the ADC is powered down between each conversion or a series of conversions is performed at a high throughput rate and then the ADC is powered down for a relatively long duration between these bursts of several conversions. When the AD7276/AD7277/ AD7278 are in partial power-down mode, all analog circuitry is powered down except the bias-generation circuit. To enter partial power-down mode, interrupt the conversion process by bringing CS high between the second and 10th falling edges of SCLK, as shown in Figure 25. Once CS is brought high in this window of SCLKs, the part enters partial power-down mode, the conversion that was initiated by the falling edge of CS is terminated, and SDATA goes back into three-state. If CS is brought high before the second SCLK falling edge, the part remains in normal mode and does not power down. This prevents accidental power-down due to glitches on the CS line. For the AD7276, a minimum of 14 serial clock cycles are required to complete the conversion and access the complete conversion result. For the AD7277 and AD7278, a minimum of 12 and 10 serial clock cycles are required to complete the conversion and to access the complete conversion result, respectively. AD7276/ AD7677/AD7278 CS 1 10 12 14 16 SDATA 04903-024 SCLK VALID DATA Figure 24. Normal Mode Operation CS 1 2 10 16 THREE-STATE SDATA Figure 25. Entering Partial Power-Down Mode Rev. C | Page 18 of 28 04903-025 SCLK AD7276/AD7277/AD7278 To exit this mode of operation and power up the AD7276/ AD7277/AD7278, users should perform a dummy conversion. On the falling edge of CS, the device begins to power up and continues to power up as long as CS is held low until after the falling edge of the 10th SCLK. The device is fully powered up once 16 SCLKs elapse; valid data results from the next conversion, as shown in Figure 26. If CS is brought high before the 10th falling edge of SCLK, the AD7276/AD7277/AD7278 go into full powerdown mode. Therefore, although the device can begin to power up on the falling edge of CS, it powers down on the rising edge of CS as long as this occurs before the 10th SCLK falling edge. If the AD7276/AD7277/AD7278 are already in partial powerdown mode and CS is brought high before the 10th falling edge of SCLK, the device enters full power-down mode. For more information on the power-up times associated with partial power-down mode in various configurations, see the Power-Up Times section. Full Power-Down Mode This mode is intended for use in applications where throughput rates slower than those in the partial power-down mode are required because power-up from a full power-down takes substantially longer than that from a partial power-down. This mode is suited to applications where a series of conversions performed at a relatively high throughput rate are followed by a long period of inactivity and thus, power down. When the AD7276/AD7277/AD7278 are in full power-down mode, all analog circuitry is powered down. To enter full powerdown mode, put the device into partial power-down mode by bringing CS high between the second and 10th falling edges of SCLK. In the next conversion cycle, interrupt the conversion process in the same way as shown in Figure 27 by bringing CS high before the 10th SCLK falling edge. Once CS is brought high in this window of SCLKs, the part powers down completely. Note that it is not necessary to complete the 16 SCLKs once CS is brought high to enter either of the power-down modes. Glitch protection is not available when entering full power-down mode. To exit full power-down mode and to power up the AD7276/ AD7277/AD7278, users should perform a dummy conversion, similar to when powering up from partial power-down mode. On the falling edge of CS, the device begins to power up and continues to power up as long as CS is held low until after the falling edge of the 10th SCLK. The required power-up time must elapse before a conversion can be initiated, as shown in Figure 28. See the Power-Up Times section for the power-up times associated with the AD7276/AD7277/AD7278. Power-Up Times The AD7276/AD7277/AD7278 have two power-down modes, partial power-down and full power-down, which are described in detail in the Modes of Operation section. This section deals with the power-up time required when coming out of either of these modes. To power up from partial power-down mode, one cycle is required. Therefore, with an SCLK frequency of up to 48 MHz, one dummy cycle is sufficient to allow the device to power up from partial power-down mode. Once the dummy cycle is complete, the ADC is fully powered up and the input signal is acquired properly. The quiet time, tQUIET, must still be allowed from the point where the bus goes back into three-state after the dummy conversion to the next falling edge of CS. To power up from full power-down, approximately 1 μs should be allowed from the falling edge of CS, shown in Figure 28 as tPOWER UP. Note that during power-up from partial power-down mode, the track-and-hold, which is in hold mode while the part is powered down, returns to track mode after the first SCLK edge, following the falling edge of CS. This is shown as Point A in Figure 26. When power supplies are first applied to the AD7276/AD7277/ AD7278, the ADC can power up in either of the power-down modes or in normal mode. Because of this, it is best to allow a dummy cycle to elapse to ensure that the part is fully powered up before attempting a valid conversion. Likewise, if the part is to be kept in partial power-down mode immediately after the supplies are applied, then two dummy cycles must be initiated. The first dummy cycle must hold CS low until after the 10th SCLK falling edge; in the second cycle, CS must be brought high between the second and 10th SCLK falling edges (see Figure 25). Alternatively, if the part is to be placed into full power-down mode when the supplies are applied, three dummy cycles must be initiated. The first dummy cycle must hold CS low until after the 10th SCLK falling edge; the second and third dummy cycles place the part into full power-down mode (see Figure 27). See the Modes of Operation section. Rev. C | Page 19 of 28 AD7276/AD7277/AD7278 THE PART IS FULLY POWERED UP, SEE THE POWERUP TIMES SECTION THE PART BEGINS TO POWER UP CS 1 10 16 1 16 SCLK SDATA INVALID DATA 04903-026 A VALID DATA Figure 26. Exiting Partial Power-Down Mode THE PART ENTERS PARTIAL POWER-DOWN THE PART BEGINS TO POWER UP THE PART ENTERS FULL POWER-DOWN CS 1 2 10 16 1 10 16 THREE-STATE INVALID DATA SDATA 04903-027 SCLK THREE-STATE VALID DATA Figure 27. Entering Full Power-Down Mode THE PART BEGINS TO POWER UP THE PART IS FULLY POWERED UP tPOWER UP CS 1 10 16 1 16 SDATA INVALID DATA VALID DATA Figure 28. Exiting Full Power-Down Mode Rev. C | Page 20 of 28 04903-028 SCLK AD7276/AD7277/AD7278 50MHz SCLK VARIABLE SCLK 04903-029 7.4 7.2 7.0 6.8 6.6 6.4 6.2 6.0 5.8 5.6 5.4 5.2 5.0 4.8 4.6 4.4 4.2 4.0 3.8 3.6 3.4 3.2 3.0 0 200 400 600 800 1000 1200 1400 1600 1800 2000 THROUGHPUT (kSPS) Figure 29. Power vs. Throughput Normal Mode 8.0 VDD = 3V 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 04903-035 POWER (mW) Figure 29 shows the power consumption of the device in normal mode, in which the part is never powered down. By using the power-down mode of the AD7276/AD7277/AD7278 when not performing a conversion, the average power consumption of the ADC decreases as the throughput rate decreases. Figure 30 shows that as the throughput rate is reduced, the device remains in its power-down state longer, and the average power consumption over time drops accordingly. For example, if the AD7276/AD7277/AD7278 are operated in continuous sampling mode with a throughput rate of 200 kSPS and an SCLK of 48 MHz (VDD = 3 V) and the devices are placed into powerdown mode between conversions, then the power consumption is calculated as follows. The power dissipation during normal operation is 12.6 mW (VDD = 3 V). If the power-up time is one dummy cycle, that is, 333 ns, and the remaining conversion time is 290 ns, then the AD7276/AD7277/AD7278 can be said to dissipate 12.6 mW for 623 ns during each conversion cycle. If the throughput rate is 200 kSPS, then the cycle time is 5 μs and the average power dissipated during each cycle is 623/5,000 × 12.6 mW = 1.56 mW. Figure 29 shows the power vs. throughput rate when using the partial power-down mode between conversions at 3 V. The power-down mode is intended for use with throughput rates of less than 600 kSPS, because at higher sampling rates, there is no power saving achieved by using the power-down mode. POWER (mW) POWER VS. THROUGHPUT RATE 0 200 400 600 800 1000 THROUGHPUT (kSPS) Figure 30. Power vs. Throughput Partial Power-Down Mode Rev. C | Page 21 of 28 AD7276/AD7277/AD7278 SERIAL INTERFACE Figure 31 through Figure 34 show the detailed timing diagrams for serial interfacing to the AD7276, AD7277, and AD7278. The serial clock provides the conversion clock and controls the transfer of information from the AD7276/AD7277/AD7278 during conversion. If 16 SCLKs are considered in the cycle, then the AD7278 clocks out six trailing zeros for the last six bits and SDATA returns to three-state on the 16th SCLK falling edge, as shown in Figure 34. If the user considers a 14 SCLK cycle serial interface for the AD7276/AD7277/AD7278, then CS must be brought high after the 14th SCLK falling edge. Then the last two trailing zeros are ignored, and SDATA goes back into three-state. In this case, the 3 MSPS throughput can be achieved by using a 48 MHz clock frequency. The CS signal initiates the data transfer and conversion process. The falling edge of CS puts the track-and-hold into hold mode and takes the bus out of three-state. The analog input is sampled and the conversion is initiated at this point. CS going low clocks out the first leading zero to be read by the microcontroller or DSP. The remaining data is then clocked out by subsequent SCLK falling edges, beginning with the second leading zero. Therefore, the first falling clock edge on the serial clock provides the first leading zero and clocks out the second leading zero. The final bit in the data transfer is valid on the 16th falling edge, because it is clocked out on the previous (15th) falling edge. For the AD7276, the conversion requires completing 14 SCLK cycles. Once 13 SCLK falling edges have elapsed, the track-andhold goes back into track mode on the next SCLK rising edge, as shown in Figure 31 at Point B. If the rising edge of CS occurs before 14 SCLKs have elapsed, the conversion is terminated and the SDATA line goes back into three-state. If 16 SCLKs are considered in the cycle, the last two bits are zeros and SDATA returns to three-state on the 16th SCLK falling edge, as shown in Figure 32. In applications with a slower SCLK, it is possible to read data on each SCLK rising edge. In such cases, the first falling edge of SCLK clocks out the second leading zero and can be read on the first rising edge. However, the first leading zero clocked out when CS goes low is missed if read within the first falling edge. The 15th falling edge of SCLK clocks out the last bit and can be read on the 15th rising SCLK edge. For the AD7277, the conversion requires completing 12 SCLK cycles. Once 11 SCLK falling edges elapse, the track-and-hold goes back into track mode on the next SCLK rising edge, as shown in Figure 33 at Point B. If the rising edge of CS occurs before 12 SCLKs elapse, the conversion is terminated and the SDATA line goes back into three-state. If 16 SCLKs are considered in the cycle, the AD7277 clocks out four trailing zeros for the last four bits and SDATA returns to three-state on the 16th SCLK falling edge, as shown in Figure 33. If CS goes low just after one SCLK falling edge elapses, then CS clocks out the first leading zero and can be read on the SCLK rising edge. The next SCLK falling edge clocks out the second leading zero and can be read on the following rising edge. For the AD7278, the conversion requires completing 10 SCLK cycles. Once 9 SCLK falling edges elapse, the track-and-hold goes back into track mode on the next rising edge. If the rising edge of CS occurs before 10 SCLKs elapse, the part enters powerdown mode. t1 CS tCONVERT 2 3 4 t3 SDATA THREESTATE B t6 1 Z 5 t4 ZERO DB11 DB10 DB9 13 t7 14 t9 t5 DB1 DB0 2 LEADING ZEROS 1/THROUGHPUT Figure 31. AD7276 Serial Interface Timing Diagram 14 SCLK Cycle Rev. C | Page 22 of 28 tQUIET THREE-STATE 04903-099 t2 SCLK AD7276/AD7277/AD7278 t1 CS tCONVERT t2 t6 2 3 t3 SDATA THREESTATE Z B 4 5 13 DB11 DB10 DB9 15 16 t5 t7 t4 ZERO 14 t8 tQUIET DB1 DB0 ZERO 2 LEADING ZEROS ZERO THREE-STATE 2 TRAILING ZEROS 04903-030 1 SCLK 1/THROUGHPUT Figure 32. AD7276 Serial Interface Timing Diagram 16 SCLK Cycle t1 CS tCONVERT t2 2 t3 THREESTATE Z 3 4 11 12 13 t5 t4 ZERO 10 DB9 14 15 16 t8 t7 DB8 DB1 2 LEADING ZEROS DB0 ZERO ZERO ZERO ZERO tQUIET THREE-STATE 4 TRAILING ZEROS 04903-031 SDATA t6 B 1 SCLK 1/THROUGHPUT Figure 33. AD7277 Serial Interface Timing Diagram t1 CS tCONVERT t2 t6 2 THREESTATE Z 4 ZERO B 8 9 10 11 t5 t4 t3 SDATA 3 DB7 14 15 16 t8 t7 DB6 DB1 DB0 tQUIET ZERO ZERO ZERO THREE-STATE 6 TRAILING ZEROS 2 LEADING ZEROS 04903-032 1 SCLK 1/THROUGHPUT Figure 34. AD7278 Serial Interface Timing Diagram t1 CS tCONVERT t6 1 SCLK 2 3 B 4 5 9 10 t8 SDATA THREESTATE Z ZERO DB7 DB6 tQUIET tACQ 8.5 (1/fSCLK ) DB5 DB1 DB0 2 LEADING ZEROS 1/THROUGHPUT Figure 35. AD7278 in a 10 SCLK Cycle Serial Interface Rev. C | Page 23 of 28 THREE-STATE 04903-033 t2 AD7276/AD7277/AD7278 AD7278 IN A 10 SCLK CYCLE SERIAL INTERFACE th For the AD7278, if CS is brought high during the 10 rising edge after the two leading zeros and eight bits of the conversion are provided, then the part can achieve a 4 MSPS throughput rate. For the AD7278, the track-and-hold goes back into track mode on the ninth rising edge. In this case, a fSCLK = 48 MHz and throughput of 4 MSPS result in a cycle time of t2 + 8.5(1/fSCLK) + tACQ = 250 ns, where t2 = 6 ns minimum and tACQ = 67 ns. This satisfies the requirement of 60 ns for tACQ. Figure 35 shows that tACQ comprises 0.5(1/fSCLK) + t8 + tQUIET, where t8 = 14 ns max. This allows a value of 43 ns for tQUIET, satisfying the minimum requirement of 4 ns. MICROPROCESSOR INTERFACING Setting RCKFE = 1 LRFS = 1 RFSR = 1 IRFS = 1 RLSBIT = 0 RDTYPE = 00 IRCLK = 1 RSPEN = 1 SLEN = 1111 The ADSP-BF53x family of DSPs interfaces directly to the AD7276/AD7277/AD7278 without requiring glue logic. The SPORT0 Receive Configuration 1 Register should be set up as outlined in Table 9. To implement the power-down modes, SLEN should be set to 1001 to issue an 8-bit SCLK burst. ADSP-BF53x* SPORT0 SCLK RCLK0 DOUT DR0PRI DIN RFS0 DT0 *ADDITIONAL PINS OMITTED FOR CLARITY 04903-098 CS Description Sample data with falling edge of RSCLK Active low frame signal Frame every word Internal RFS used Receive MSB first Zero fill Internal receive clock Receive enabled 16-bit data-word (or can be set to 1101 for 14-bit data-word) TFSR = RFSR = 1 AD7276/AD7277/AD7278-to-ADSP-BF53x AD7276/ AD7277/ AD7278* Table 9. The SPORT0 Receive Configuration 1 Register (SPORT0_RCR1) Figure 36. Interfacing with ADSP-BF53x Rev. C | Page 24 of 28 AD7276/AD7277/AD7278 APPLICATION HINTS GROUNDING AND LAYOUT The printed circuit board that houses the AD7276/AD7277/ AD7278 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This design facilitates using ground planes that can easily be separated. To provide optimum shielding for ground planes, a minimum etch technique is generally best. All AGND pins of the AD7276/ AD7277/AD7278 should be sunk into the AGND plane. Digital and analog ground planes should be joined in one place only. If the AD7276/AD7277/AD7278 are in a system where multiple devices require an AGND-to-DGND connection, the connection should still be made at only one point, a star ground point established as close as possible to the ground pin on the AD7276/AD7277/AD7278. Avoid running digital lines under the device because this couples noise onto the die. However, the analog ground plane should be allowed to run under the AD7276/AD7277/AD7278 to avoid noise coupling. The power supply lines to the AD7276/ AD7277/AD7278 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. To avoid radiating noise to other sections of the board, components with fast-switching signals, such as clocks, should be shielded with digital ground, and they should never be run near the analog inputs. Avoid crossover of digital and analog signals. To reduce the effects of feedthrough within the board, traces on opposite sides of the board should run at right angles to each other. A microstrip technique is by far the best method, but it is not always possible to use this approach with a doublesided board. In this technique, the component side of the board is dedicated to ground planes, and signals are placed on the solder side. Good decoupling is also important. All analog supplies should be decoupled with 10 μF ceramic capacitors in parallel with 0.1 μF capacitors to GND. To achieve the best results from these decoupling components, they must be placed as close as possible to the device, ideally right up against the device. The 0.1 μF capacitors should have low effective series resistance (ESR) and low effective series inductance (ESI), such as is typical of common ceramic or surface-mount types of capacitors. Capacitors with low ESR and low ESI provide a low impedance path to ground at high frequencies, which allow them to handle transient currents due to internal logic switching. EVALUATING PERFORMANCE The recommended layout for the AD7276/AD7277/AD7278 is outlined in the evaluation board documentation. The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from the PC via the evaluation board controller. To demonstrate/ evaluate the ac and dc performance of the AD7276/AD7277, the evaluation board controller can be used in conjunction with the AD7276/AD7277 evaluation board, as well as with many other Analog Devices evaluation boards ending in the CB designator, The software allows the user to perform ac (fast Fourier transform) and dc (histogram of codes) tests on the AD7276/ AD7277. The software and documentation are on a CD shipped with the evaluation board. Rev. C | Page 25 of 28 AD7276/AD7277/AD7278 OUTLINE DIMENSIONS 2.90 BSC 6 5 4 2.80 BSC 1.60 BSC 1 3 2 PIN 1 INDICATOR 0.95 BSC 1.90 BSC *0.90 0.87 0.84 0.20 0.08 *1.00 MAX 8° 4° 0° SEATING PLANE 0.50 0.30 0.60 0.45 0.30 102808-A 0.10 MAX *COMPLIANT TO JEDEC STANDARDS MO-193-AA WITH THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS. Figure 37. 6-Lead Thin Small Outline Transistor Package [TSOT] (UJ-6) Dimensions shown in millimeters 3.20 3.00 2.80 3.20 3.00 2.80 8 1 5.15 4.90 4.65 5 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.40 0.25 6° 0° 0.23 0.09 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 38. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters Rev. C | Page 26 of 28 0.80 0.55 0.40 100709-B 0.15 0.05 COPLANARITY 0.10 AD7276/AD7277/AD7278 ORDERING GUIDE Model 1 AD7276BRM AD7276BRMZ AD7276BRMZ-REEL AD7276BUJZ-REEL7 Notes AD7276BUJZ-500RL7 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Linearity Error (LSB) 2 ±1 max ±1 max ±1 max ±1 max −40°C to +125°C ±1 max AD7276YUJZ-500RL7 3 −40°C to +125°C ±1 max AD7276YUJZ-REEL7 3 −40°C to +125°C ±1 max AD7276ARMZ AD7276ARMZ-REEL AD7276AUJZ- 500RL7 −40°C to +125°C −40°C to +125°C −40°C to +125°C ±1.5 max ±1.5 max ±1.5 max AD7276AUJZ-REEL7 −40°C to +125°C ±1.5 max AD7277BRMZ AD7277BRMZ-REEL AD7277BUJZ-500RL7 −40°C to +125°C −40°C to +125°C −40°C to +125°C ±0.5 max ±0.5 max ±0.5 max AD7277BUJZ-REEL7 −40°C to +125°C ±0.5 max AD7277ARMZ AD7277ARMZ-RL AD7277AUJZ-500RL7 −40°C to +125°C −40°C to +125°C −40°C to +125°C ±0.5 max ±0.5 max ±0.5 max AD7277AUJZ-RL7 −40°C to +125°C ±0.5 max AD7278BRMZ AD7278BRMZ-REEL AD7278BUJZ-500RL7 −40°C to +125°C −40°C to +125°C −40°C to +125°C ±0.3 max ±0.3 max ±0.3 max AD7278BUJZ-REEL7 −40°C to +125°C ±0.3 max AD7278ARMZ AD7278ARMZ-RL AD7278AUJZ-500RL7 −40°C to +125°C −40°C to +125°C −40°C to +125°C ±0.3 max ±0.3 max ±0.3 max AD7278AUJZ-RL7 −40°C to +125°C ±0.3 max EVAL-AD7276CBZ EVAL-CONTROL BRD2 4 5 Package Description 8-Lead Mini Small Outline Package (MSOP) 8-Lead Mini Small Outline Package (MSOP) 8-Lead Mini Small Outline Package (MSOP) 6-Lead Thin Small Outline Transistor Package (TSOT) 6-Lead Thin Small Outline Transistor Package (TSOT) 6-Lead Thin Small Outline Transistor Package (TSOT) 6-Lead Thin Small Outline Transistor Package (TSOT) 8-Lead Mini Small Outline Package (MSOP) 8-Lead Mini Small Outline Package (MSOP) 6-Lead Thin Small Outline Transistor Package (TSOT) 6-Lead Thin Small Outline Transistor Package (TSOT) 8-Lead Mini Small Outline Package (MSOP) 8-Lead Mini Small Outline Package (MSOP) 6-Lead Thin Small Outline Transistor Package (TSOT) 6-Lead Thin Small Outline Transistor Package (TSOT) 8-Lead Mini Small Outline Package (MSOP) 8-Lead Mini Small Outline Package (MSOP) 6-Lead Thin Small Outline Transistor Package (TSOT) 6-Lead Thin Small Outline Transistor Package (TSOT) 8-Lead Mini Small Outline Package (MSOP) 8-Lead Mini Small Outline Package (MSOP) 6-Lead Thin Small Outline Transistor Package (TSOT) 6-Lead Thin Small Outline Transistor Package (TSOT) 8-Lead Mini Small Outline Package (MSOP) 8-Lead Mini Small Outline Package (MSOP) 6-Lead Thin Small Outline Transistor Package (TSOT) 6-Lead Thin Small Outline Transistor Package (TSOT) Evaluation Board Control Board 1 Package Option RM-8 RM-8 RM-8 UJ-6 Branding C1W C30 C30 C30 UJ-6 C30 UJ-6 C4W UJ-6 C4W RM-8 RM-8 UJ-6 C6S C6S C6S UJ-6 C6S RM-8 RM-8 UJ-6 C31 C31 C31 UJ-6 C31 RM-8 RM-8 UJ-6 C6T C6T C6T UJ-6 C6T RM-8 RM-8 UJ-6 C32 C32 C32 UJ-6 C32 RM-8 RM-8 UJ-6 C6U C6U C6U UJ-6 C6U Z = RoHS Compliant Part. Linearity error refers to integral nonlinearity. 3 Y Grade part, fSAMPLE = 1 MSPS. 4 This can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL board for evaluation/demonstration purposes. 5 This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards that end in a CB designator. To order a complete evaluation kit, the particular ADC evaluation board (such as EVAL-AD7276CBZ), the EVAL-CONTROL BRD2, and a 12 V transformer must be ordered. See the relevant evaluation board user guide for more information. 2 Rev. C | Page 27 of 28 AD7276/AD7277/AD7278 NOTES ©2005–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04903-0-5/11(C) Rev. C | Page 28 of 28