Final Electrical Specifications LTC1709-8/LTC1709-9 2-Phase, 5-Bit VID, Current Mode, High Efficiency, Synchronous Step-Down Switching Regulators U DESCRIPTIO FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Single Controller Operates Two Output Stages: Antiphase Reducing Required Input Capacitance and Power Supply Induced Noise Two 5-Bit Desktop VID Codes: LTC1709-8 For VRM8.4 (VOUT from 1.3V to 3.5V) LTC1709-9 For VRM9.0 (VOUT from 1.1V to 1.85V) Current Mode Control Ensures Best Current Sharing True Remote Sensing Differential Amplifier Power Good Output Indicator OPTI-LOOPTM Compensation Minimizes COUT Programmable Fixed Frequency: 150kHz to 300kHz ±1% Output Voltage Accuracy Wide VIN Range: 4V to 36V Operation Adjustable Soft-Start Current Ramping Internal Current Foldback and Short-Circuit Shutdown Overvoltage Soft Latch Eliminates Nuisance Trips Low Shutdown Current: 20µA Available in 36-Lead SSOP Package U APPLICATIO S ■ ■ ■ Workstations Internet Servers Large Memory Arrays DC Power Distribution Systems The LTC®1709-8/LTC1709-9 are 2-phase, VID programmable, synchronous step-down switching regulator controllers that drive two all N-channel external power MOSFET stages in a fixed frequency architecture. The 2-phase controller drives its two output stages out of phase at frequencies up to 300kHz to minimize the RMS ripple currents in both input and output capacitors. The 2-phase technique effectively multiplies the fundamental frequency by two, improving transient response while operating each channel at an optimum frequency for efficiency. Thermal design is also simplified. An internal differential amplifier provides true remote sensing of the regulated supply’s positive and negative output terminals as required for high current applications. The RUN/SS pin provides soft-start and optional timed, short-circuit shutdown. Current foldback limits MOSFET dissipation during short-circuit conditions when the overcurrent latchoff is disabled. OPTI-LOOP compensation allows the transient response to be optimized for a wide range of output capacitors and ESR values. The LTC1709-8/LTC1709-9 implement two different VID tables compliant with VRM8.4 and VRM9.0 respectively. , LTC and LT are registered trademarks of Linear Technology Corporation. OPTI-LOOP is a trademark of Linear Technology Corporation. U ■ May 2000 TYPICAL APPLICATIO + VIN RUN/SS 3.3k TG1 220pF LTC1709-8 ITH PGOOD VID0–VID4 0.002Ω 1µH SW1 S BG1 SENSE1 + SENSE1 – TG2 BOOST2 EAIN ATTENOUT BG2 VDIFFOUT INTVCC – SENSE2 + VOS + SENSE2 – 0.002Ω 0.47µF VOUT 1.3V TO 3.5V 40A 1µH SW2 ATTENIN VOS 0.47µF VIN 5V TO 28V PGND SGND 5 VID BITS S BOOST1 + 0.1µF 10µF 35V ×4 10µF + COUT 1000µF 4V ×2 17097 F01 Figure 1. High Current Dual Phase Step-Down Converter Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 1 LTC1709-8/LTC1709-9 U W W W ABSOLUTE AXI U RATI GS U W U PACKAGE/ORDER I FOR ATIO (Note 1) Input Supply Voltage (VIN).........................36V to – 0.3V Topside Driver Voltages (BOOST1,2) .........42V to – 0.3V Switch Voltage (SW1, 2) .............................36V to – 5 V SENSE1+, SENSE2 +, SENSE1–, SENSE2 – Voltages ........................ (1.1)INTVCC to – 0.3V EAIN, VOS+, VOS–, EXTVCC, INTVCC, RUN/SS, VBIAS, ATTENIN, ATTENOUT, PGOOD, VID0–VID4, Voltages ...................................7V to – 0.3V Boosted Driver Voltage (BOOST-SW) ..........7V to – 0.3V PLLFLTR, PLLIN, VDIFFOUT Voltages .... INTVCC to – 0.3V ITH Voltage ................................................2.7V to – 0.3V Peak Output Current <1µs(TGL1,2, BG1,2) ................ 3A INTVCC RMS Output Current ................................ 50mA Operating Ambient Temperature Range (Note 2) ................................................ – 40°C to 85°C Junction Temperature (Note 3) ............................. 125°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER TOP VIEW RUNN/SS 1 36 NC SENSE1 + 2 35 TG1 SENSE1 – 3 34 SW1 EAIN 4 33 BOOST1 PLLFLTR 5 32 VIN PLLIN 6 31 BG1 NC 7 30 EXTVCC ITH 8 29 INTVCC SGND 9 28 PGND VDIFFOUT 10 LTC1709EG-8 LTC1709EG-9 27 BG2 VOS – 11 26 BOOST2 VOS + 12 25 SW2 SENSE2 – 13 24 TG2 SENSE2 + 14 23 PGOOD ATTENOUT 15 22 VBIAS ATTENIN 16 21 VID4 VID0 17 20 VID3 VID1 18 19 VID2 G PACKAGE 36-LEAD PLASTIC SSOP TJMAX = 125°C, θJA = 85°C/W Consult factory for Military grade parts. ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VBIAS = 5V, VRUN/SS = 5V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Main Control Loop VEAIN Regulated Feedback Voltage ITH Voltage = 1.2V (Note 4) ● 0.792 0.800 0.808 VSENSEMAX Maximum Current Sense Threshold VSENSE – = 5V ● 62 75 88 mV IINEAIN Feedback Current (Note 4) –5 – 50 nA VLOADREG Output Voltage Load Regulation (Note 4) Measured in Servo Loop, ∆ITH Voltage: 1.2V to 0.7V Measured in Servo Loop, ∆ITH Voltage: 1.2V to 2V 0.1 – 0.1 0.5 – 0.5 % % ● ● V VREFLNREG Reference Voltage Line Regulation VIN = 3.6V to 30V (Note 4) VOVL Output Overvoltage Threshold Measured at VEAIN UVLO Undervoltage Lockout VIN Ramping Down gm Transconductance Amplifier gm ITH = 1.2V, Sink/Source 5µA (Note 4) 3 mmho gmOL Transconductance Amplifier Gain ITH = 1.2V, (gmxZL; No Ext Load) (Note 4) 1.5 V/mV IQ Input DC Supply Current Normal Mode Shutdown (Note 5) EXTVCC Tied to VOUT, VOUT = 5V VRUN/SS = 0V 470 20 IRUN/SS Soft-Start Charge Current VRUN/SS = 1.9V – 0.5 –1.2 VRUN/SS RUN/SS Pin ON Arming VRUN/SS Rising 1.0 1.5 2 ● 0.002 0.02 %/V 0.84 0.86 0.88 V 3 3.5 4 V 40 µA µA µA 1.9 V LTC1709-8/LTC1709-9 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VBIAS = 5V, VRUN/SS = 5V unless otherwise noted. SYMBOL PARAMETER CONDITIONS VRUN/SSLO RUN/SS Pin Latchoff Arming VRUN/SS Rising from 3V MIN ISCL RUN/SS Discharge Current Soft Short Condition VEAIN = 0.5V, VRUN/SS = 4.5V ISDLHO Shutdown Latch Disable Current VEAIN = 0.5V ISENSE Total Sense Pins Source Current Each Channel: VSENSE1 –, 2 – = VSENSE1+, 2 + = 0V – 85 – 60 µA DFMAX Maximum Duty Factor In Dropout 98 99.5 % TG1, 2 tr TG1, 2 tf Top Gate Transition Time: Rise Time Fall Time (Note 6) CLOAD = 3300pF CLOAD = 3300pF 30 40 90 90 ns ns BG1, 2 tr BG1, 2 tf Bottom Gate Transition Time: Rise Time Fall Time (Note 6) CLOAD = 3300pF CLOAD = 3300pF 30 20 90 90 ns ns TG/BG t1D Top Gate Off to Bottom Gate On Delay Synchronous Switch-On Delay Time CLOAD = 3300pF Each Driver (Note 6) 90 ns BG/TG t2D Bottom Gate Off to Top Gate On Delay Top Switch-On Delay Time CLOAD = 3300pF Each Driver (Note 6) 90 ns tON(MIN) Minimum On-Time Tested with a Square Wave (Note 7) 180 ns 0.5 TYP MAX UNITS 4.1 4.5 V 2 4 µA 1.6 5 µA Internal VCC Regulator VINTVCC Internal VCC Voltage 6V < VIN < 30V, VEXTVCC = 4V 4.8 VLDO INT INTVCC Load Regulation ICC = 0 to 20mA, VEXTVCC = 4V 0.2 1.0 % VLDO EXT EXTVCC Voltage Drop ICC = 20mA, VEXTVCC = 5V 80 160 mV VEXTVCC EXTVCC Switchover Voltage ICC = 20mA, EXTVCC Ramping Positive VLDOHYS EXTVCC Switchover Hysteresis ICC = 20mA, EXTVCC Ramping Negative ● 4.5 5.0 5.2 V 4.7 V 0.2 V VID Parameters VBIAS Operating Supply Voltage Range 2.7 RATTEN Resistance Between ATTENIN and ATTENOUT Pins LTC1709-8 LTC1709-9 ATTENERR Resistive Divider Error LTC1709-8: VID4 = 0; LTC1709-9 LTC1709-8: VID4 = 1 RPULLUP VID0–VID4 Pull-Up Resistance (Note 8) VIDTHLOW VID0–VID4 Logic Threshold Low VIDTHHIGH VID0–VID4 Logic Threshold High VIDLEAK VID0–VID4 Leakage 5.5 20 10 ● ● – 0.25 –0.35 V kΩ kΩ 0.25 0.35 40 % % kΩ 0.4 V 1 µA 1.6 V VBIAS < VID0–VID4 < 7V Oscillator and Phase-Locked Loop fNOM Nominal Frequency VPLLFLTR = 1.2V 190 220 250 kHz fLOW Lowest Frequency VPLLFLTR = 0V 120 140 160 kHz fHIGH Highest Frequency VPLLFLTR ≥ 2.4V 280 320 360 kHz RPLLIN PLLIN Input Resistance IPLLFLTR Phase Detector Output Current Sinking Capability Sourcing Capability RRELPHS Controller 2-Controller 1 Phase fPLLIN < fOSC fPLLIN > fOSC 50 kΩ – 15 15 µA µA 180 Deg 3 LTC1709-8/LTC1709-9 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VRUN/SS = 5V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 0.1 0.3 V ±1 µA PGOOD Output VPGL PGOOD Voltage Low IPGOOD = 2mA IPGOOD PGOOD Leakage Current VPGOOD = 5V VPG PGOOD Trip Level, Either Controller VEAIN with Respect to Set Output Voltage VEAIN Ramping Negative VEAIN Ramping Positive –6 6 – 7.5 7.5 – 9.5 9.5 % % 0.995 1 1.005 V/V Differential Amplifier/Op Amp Gain Block ADA Gain CMRRDA Common Mode Rejection Ratio 0V < VCM < 5V RIN Input Resistance Measured at VOS + Input 46 Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LTC1709EG is guaranteed to meet performance specifications from 0°C to 70°C. Specifications over the – 40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: LTC1709EG: TJ = TA + (PD • 85°C/W) Note 4: The LTC1709-8/LTC1709-9 are tested in a feedback loop that servos VITH to a specified voltage and measures the resultant VEAIN. 55 dB 80 kΩ Note 5: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See Applications Information. Note 6: Rise and fall times are measured using 10% and 90% levels. Delay times are measured using 50% levels. Note 7: The minimum on-time condition corresponds to the on inductor peak-to-peak ripple current ≥ 40% IMAX (see Minimum On-Time Considerations in the Applications Information section). Note 8: Each built-in pull-up resistor attached to the VID inputs also has a series diode to allow input voltages higher than the VIDVCC supply without damage or clamping (see the Applications Information section). U W TYPICAL PERFOR A CE CHARACTERISTICS Efficiency vs Output Current (Figure 12) Efficiency vs Output Current (Figure 12) Efficiency vs Output Current (Figure 12) 100 100 100 VOUT = 3.3V VEXTVCC = 5V IOUT = 20A VEXTVCC = 5V 80 80 VIN = 8V 60 VIN = 12V VIN = 20V 40 20 VOUT = 2V VEXTVCC = 0V FREQ = 200kHz 0 0.1 1 10 OUTPUT CURRENT (A) 100 170989 G01 4 VEXTVCC = 0V EFFICIENCY (%) EFFICIENCY (%) EFFICIENCY (%) VIN = 5V 60 40 20 0 0.1 90 80 VIN = 12V VOUT = 2V FREQ = 200kHz 70 1 10 OUTPUT CURRENT (A) 100 5 10 15 20 VIN (V) 170989 G02 170989 G03 LTC1709-8/LTC1709-9 U W TYPICAL PERFOR A CE CHARACTERISTICS Supply Current vs Input Voltage and Mode (Figure 12) 1000 5.05 INTVCC AND EXTVCC SWITCH VOLTAGE (V) 250 ON EXTVCC VOLTAGE DROP (mV) 800 SUPPLY CURRENT (µA) INTVCC and EXTVCC Switch Voltage vs Temperature EXTVCC Voltage Drop 600 400 200 200 150 100 50 SHUTDOWN 0 0 5 20 15 10 25 INPUT VOLTAGE (V) 30 0 35 0 10 30 20 CURRENT (mA) 40 170989 G04 50 4.95 4.90 4.85 4.80 4.70 – 50 – 25 100 125 Maximum Current Sense Threshold vs Percent of Nominal Output Voltage (Foldback) Maximum Current Sense Threshold vs Duty Factor 75 80 ILOAD = 1mA 70 60 4.8 4.7 50 VSENSE (mV) 4.9 VSENSE (mV) INTVCC VOLTAGE (V) 50 25 75 0 TEMPERATURE (°C) 170989 G06 5.0 25 4.6 50 40 30 20 4.5 10 0 4.4 0 5 20 15 25 10 INPUT VOLTAGE (V) 30 0 35 20 40 60 DUTY FACTOR (%) 80 Maximum Current Sense Threshold vs VRUN/SS (Soft-Start) 80 0 100 50 100 0 25 75 PERCENT ON NOMINAL OUTPUT VOLTAGE (%) 170989 G08 170989 G07 170989 G09 Current Sense Threshold vs ITH Voltage Maximum Current Sense Threshold vs Sense Common Mode Voltage 90 80 VSENSE(CM) = 1.6V 80 70 76 40 60 VSENSE (mV) VSENSE (mV) 60 VSENSE (mV) EXTVCC SWITCHOVER THRESHOLD 4.75 170989 G05 Internal 5V LDO Line Reg 5.1 INTVCC VOLTAGE 5.00 72 68 50 40 30 20 10 20 0 64 –10 –20 0 0 1 2 3 4 5 6 VRUN/SS (V) 170989 G10 60 0 1 3 4 2 COMMON MODE VOLTAGE (V) 5 170989 G11 –30 0 0.5 1 1.5 VITH (V) 2 2.5 170989 G12 5 LTC1709-8/LTC1709-9 U W TYPICAL PERFOR A CE CHARACTERISTICS Load Regulation 2.5 FCB = 0V VIN = 15V FIGURE 1 100 VOSENSE = 0.7V 2.0 –0.2 50 ISENSE (µA) –0.1 VITH (V) NORMALIZED VOUT (%) SENSE Pins Total Source Current VITH vs VRUN/SS 0.0 1.5 1.0 –0.3 0 –50 0.5 –0.4 0 1 3 2 LOAD CURRENT (A) 0 4 5 0 1 2 3 5 4 6 VRUN/SS (V) –100 2 0 4 1629 G14 1629 G13 Maximum Current Sense Threshold vs Temperature 1629 G15 RUN/SS Current vs Temperature 1.8 80 1.6 RUN/SS CURRENT (µA) VSENSE (mV) 78 76 74 72 1.4 1.2 1.0 0.8 0.6 0.4 0.2 70 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 0 –50 –25 0 25 50 75 TEMPERATURE (°C) 170989 G16 100 125 170989 G17 Soft-Start (Figure 12) Load Step (Figure 12) VITH 1V/DIV VOUT 50mV/DIV VOUT 2V/DIV VRUN/SS 2V/DIV IOUT 0/20A 100ms/DIV 6 170989 G18 6 VSENSE COMMON MODE VOLTAGE (V) 20µs/DIV 170989 G19 LTC1709-8/LTC1709-9 U W TYPICAL PERFOR A CE CHARACTERISTICS Current Sense Pin Input Current vs Temperature 10 VOUT = 5V 350 VFREQSET = 5V 33 31 29 27 50 25 0 75 TEMPERATURE (°C) 100 125 300 8 FREQUENCY (kHz) EXTVCC SWITCH RESISTANCE (Ω) CURRENT SENSE INPUT CURRENT (µA) 35 25 –50 –25 Oscillator Frequency vs Temperature EXTVCC Switch Resistance vs Temperature 6 4 VFREQSET = 0V 150 100 50 0 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 0 – 50 – 25 50 25 75 0 TEMPERATURE (°C) 100 125 170989 G22 170989 G21 Undervoltage Lockout vs Temperature Shutdown Latch Thresholds vs Temperature 4.5 SHUTDOWN LATCH THRESHOLDS (V) 3.50 UNDERVOLTAGE LOCKOUT (V) VFREQSET = OPEN 200 2 170989 G20 3.45 3.40 3.35 3.30 3.25 3.20 –50 –25 250 50 25 75 0 TEMPERATURE (°C) 100 125 170989 G23 LATCH ARMING 4.0 3.5 3.0 LATCHOFF THRESHOLD 2.5 2.0 1.5 1.0 0.5 0 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 125 170989 G24 U U U PI FU CTIO S RUN/SS (Pin 1): Combination of Soft-Start, Run Control Input and Short-Circuit Detection Timer. A capacitor to ground at this pin sets the ramp time to full current output. Forcing this pin below 0.8V causes the IC to shut down all internal circuitry. All functions are disabled in shutdown. SENSE1+, SENSE2+ (Pins 2,14): The (+) Input to Each Differential Current Comparator. The ITH pin voltage and built-in offsets between SENSE– and SENSE+ pins in conjunction with RSENSE set the current trip threshold. SENSE1–, SENSE2– (Pins 3, 13): The (–) Input to the Differential Current Comparators. EAIN (Pin 4): Input to the error amplifier that compares the feedback voltage to the internal 0.8V reference voltage. This pin is normally connected to a resistive divider from the output of the differential amplifier (DIFFOUT). PLLFLTR (Pin 5): The phase-locked loop’s lowpass filter is tied to this pin. Alternatively, this pin can be driven with an AC or DC voltage source to vary the frequency of the internal oscillator. 7 LTC1709-8/LTC1709-9 U U U PI FU CTIO S PLLIN (Pin 6): External Synchronization Input to Phase Detector. This pin is internally terminated to SGND with 50kΩ. The phase-locked loop will force the rising top gate signal of controller 1 to be synchronized with the rising edge of the PLLIN signal. NC (Pins 7, 36): Do not connect. ITH (Pin 8): Error Amplifier Output and Switching Regulator Compensation Point. Both current comparator’s thresholds increase with this control voltage. The normal voltage range of this pin is from 0V to 2.4V SGND (Pin 9): Signal Ground. This pin is common to both controllers. Route separately to the PGND pin. VDIFFOUT (Pin 10): Output of a Differential Amplifier. This pin provides true remote output voltage sensing. VDIFFOUT normally drives an external resistive divider that sets the output voltage. VOS–, VOS+ (Pins 11, 12): Inputs to an Operational Amplifier. Internal precision resistors capable of being electronically switched in or out can configure it as a differential amplifier or an uncommitted op amp. ATTENOUT (Pin 15): Voltage Feedback Signal Resistively Divided According to the VID Programming Code. ATTENIN (Pin 16): The Input to the VID Controlled Resistive Divider. VID0–VID4 (Pins 17,18, 19, 20, 21): VID Control Logic Input Pins. VBIAS (Pin 22): Supply Pin for the VID Control Circuit. PGOOD (Pin 23): Open-Drain Logic Output. PGOOD is pulled to ground when the voltage on the EAIN pin is not within ±7.5% of its set point. 8 TG2, TG1 (Pins 24, 35): High Current Gate Drives for Top N-Channel MOSFETS. These are the outputs of floating drivers with a voltage swing equal to INTVCC superimposed on the switch node voltage SW. SW2, SW1 (Pins 25, 34): Switch Node Connections to Inductors. Voltage swing at these pins is from a Schottky diode (external) voltage drop below ground to VIN. BOOST2, BOOST1 (Pins 26, 33): Bootstrapped Supplies to the Topside Floating Drivers. External capacitors are connected between the BOOST and SW pins, and Schottky diodes are connected between the BOOST and INTVCC pins. BG2, BG1 (Pins 27, 31): High Current Gate Drives for Bottom N-Channel MOSFETS. Voltage swing at these pins is from ground to INTVCC. PGND (Pin 28): Driver Power Ground. Connect to sources of bottom N-channel MOSFETS and the (–) terminals of CIN. INTVCC (Pin 29): Output of the Internal 5V Linear Low Dropout Regulator and the EXTVCC Switch. The driver and control circuits are powered from this voltage source. Decouple to power ground with a 1µF ceramic capacitor placed directly adjacent to the IC and minimum of 4.7µF additional tantalum or other low ESR capacitor. EXTVCC (Pin 30): External Power Input to an Internal Switch. This switch closes and supplies INTVCC, bypassing the internal low dropout regulator whenever EXTVCC is higher than 4.7V. See EXTVCC Connection in the Applications Information section. Do not exceed 7V on this pin and ensure VEXTVCC ≤ VIN. VIN (Pin 32): Main Supply Pin. Should be closely decoupled to the IC’s signal ground pin. LTC1709-8/LTC1709-9 W FU CTIO AL DIAGRA U U PLLIN INTVCC PHASE DET fIN 50k RLP DUPLICATE FOR SECOND CONTROLLER CHANNEL PLLLPF CLP OSCILLATOR DROP OUT DET CLK2 S Q R Q – CB TG TOP + CIN BOT SW FORCE BOT SWITCH LOGIC INTVCC BOT PGOOD DB BOOST CLK1 VIN BG PGND 0.86V + SHDN EAIN – + 0.74V I1 + A1 + L + 30k SENSE 0.86V 4(VFB) – VOS – – 30k SENSE RSENSE COUT + + SLOPE COMP + VOS INTVCC – – 45k 45k VOUT 2.4V DIFFOUT EAIN 0.80V VIN – EA + VREF VIN OV 4.7V EXTVCC + – 1.2µA 5V SHDN RST 4(VFB) INTVCC + 6V 0.86V ITH RUN SOFT START CC RC RUN/SS INTERNAL SUPPLY SGND + – 5V LDO REG 0.80V CSS ATTENIN 20k (LTC1709-8) 10k (LTC1709-9) 5-BIT VID DECODER ATTENOUT TYPICAL ALL VID PINS 40k R1 VID0 VID1 VID2 VID3 VID4 VBIAS 170989 FBD 9 LTC1709-8/LTC1709-9 U OPERATIO (Refer to Functional Diagram) Main Control Loop Low Current Operation The LTC1709 uses a constant frequency, current mode step-down architecture with inherent current sharing. During normal operation, the top MOSFET is turned on each cycle when the oscillator sets the RS latch, and turned off when the main current comparator, I1, resets the RS latch. The peak inductor current at which I 1 resets the RS latch is controlled by the voltage on the ITH pin, which is the output of the error amplifier EA. The differential amplifier, A1, produces a signal equal to the differential voltage sensed across the output capacitor but re-references it to the internal signal ground (SGND) reference. The EAIN pin receives a portion of this voltage feedback signal at the DIFFOUT as determined by VID logic input pins (VID0 to VID4) and is compared to the internal reference voltage by the EA. When the load current increases, it causes a slight decrease in the EAIN pin voltage relative to the 0.8V reference, which in turn causes the ITH voltage to increase until the average inductor current matches the new load current. After the top MOSFET has turned off, the bottom MOSFET is turned on for the rest of the period. The LTC1709 operates in a continuous, PWM control mode. The resulting operation at low output currents optimizes transient response at the expense of substantial negative inductor current during the latter part of the period. The level of ripple current is determined by the inductor value, input voltage, output voltage and frequency of operation. The top MOSFET drivers are biased from floating bootstrap capacitor CB, which normally is recharged during each off cycle through an external Schottky diode. When VIN decreases to a voltage close to VOUT, however, the loop may enter dropout and attempt to turn on the top MOSFET continuously. A dropout detector detects this condition and forces the top MOSFET to turn off for about 400ns every 10th cycle to recharge the bootstrap capacitor, CB. The main control loop is shut down by pulling Pin 1 (RUN/ SS) low. Releasing RUN/SS allows an internal 1.2µA current source to charge soft-start capacitor CSS. When CSS reaches 1.5V, the main control loop is enabled with the ITH voltage clamped at approximately 30% of its maximum value. As CSS continues to charge, ITH is gradually released allowing normal operation to resume. When the RUN/SS pin is low, all LTC1709 functions are shut down. If VOUT has not reached 70% of its nominal value when CSS has charged to 4.1V, an overcurrent latchoff can be invoked as described in the Applications Information section. 10 Frequency Synchronization The phase-locked loop allows the internal oscillator to be synchronized to an external source via the PLLIN pin. The output of the phase detector at the PLLFLTR pin is also the DC frequency control input of the oscillator that operates over a 140kHz to 310kHz range corresponding to a DC voltage input from 0V to 2.4V. When locked, the PLL aligns the turn on of the top MOSFET to the rising edge of the synchronizing signal. When PLLIN is left open, the PLLFLTR pin goes low, forcing the oscillator to minimum frequency. Input capacitance ESR requirements and efficiency losses are substantially reduced because the peak current drawn from the input capacitor is effectively divided by two and power loss is proportional to the RMS current squared. A two stage, single output voltage implementation can reduce input path power loss by 75% and radically reduce the required RMS current rating of the input capacitor(s). INTVCC/EXTVCC Power Power for the top and bottom MOSFET drivers and most of the IC circuitry is derived from INTVCC. When the EXTVCC pin is left open, an internal 5V low dropout regulator supplies INTVCC power. If the EXTVCC pin is taken above 4.7V, the 5V regulator is turned off and an internal switch is turned on connecting EXTVCC to INTVCC. This allows the INTVCC power to be derived from a high efficiency external source such as the output of the regulator itself or a secondary winding, as described in the Applications Information section. An external Schottky diode can be used to minimize the voltage drop from EXTVCC to INTVCC in applications requiring greater than the specified INTVCC current. Voltages up to 7V can be applied to EXTVCC for additional gate drive capability. LTC1709-8/LTC1709-9 U OPERATIO (Refer to Functional Diagram) Differential Amplifier This amplifier provides true differential output voltage sensing. Sensing both VOUT + and VOUT – benefits regulation in high current applications and/or applications having electrical interconnection losses. The AMPMD pin allows selection of internal, precision feedback resistors for high common mode rejection differencing applications, or direct access to the actual amplifier inputs without these internal feedback resistors for other applications. The AMPMD pin is grounded to connect the internal precision resistors in a unity-gain differencing application, or tied to the INTVCC pin to bypass the internal resistors and make the amplifier inputs directly available. The amplifier is a unity-gain stable, 2MHz gain bandwidth, >120dB open-loop gain design. The amplifier has an output slew rate of 5V/µs and is capable of driving capacitive loads with an output RMS current typically up to 35mA. The amplifier is not capable of sinking current and therefore must be resistively loaded to do so. Power Good (PGOOD) The PGOOD pin is connected to the drain of an internal MOSFET. The MOSFET turns on when the output voltage is not within ±7.5% of its nominal output level as determined by the feedback divider. When the output is within ±7.5% of its nominal value, the MOSFET is turned off within 10µs and the PGOOD pin should be pulled up by an external resistor to a source of up to 7V. Short-Circuit Detection The RUN/SS capacitor is used initially to limit the inrush current from the input power source. Once the controllers have been given time, as determined by the capacitor on the RUN/SS pin, to charge up the output capacitors and provide full-load current, the RUN/SS capacitor is then used as a short-circuit timeout circuit. If the output voltage falls to less than 70% of its nominal output voltage the RUN/SS capacitor begins discharging assuming that the output is in a severe overcurrent and/or short-circuit condition. If the condition lasts for a long enough period as determined by the size of the RUN/SS capacitor, the controller will be shut down until the RUN/SS pin voltage is recycled. This built-in latchoff can be overidden by providing a current >5µA at a compliance of 5V to the RUN/SS pin. This current shortens the soft-start period but also prevents net discharge of the RUN/SS capacitor during a severe overcurrent and/or short-circuit condition. Foldback current limiting is activated when the output voltage falls below 70% of its nominal level whether or not the short-circuit latchoff circuit is enabled. U W U U APPLICATIO S I FOR ATIO The basic LTC1709 application circuit is shown in Figure␣ 1 on the first page. External component selection begins with the selection of the inductor(s) based on ripple current requirements and continues with the RSENSE1, 2 resistor selection using the calculated peak inductor current and/or maximum current limit. Next, the power MOSFETs and D1 and D2 are selected. The operating frequency and the inductor are chosen based mainly on the amount of ripple current. Finally, CIN is selected for its ability to handle the input ripple current (that PolyPhaseTM operation minimizes) and COUT is chosen with low enough ESR to meet the output ripple voltage and load step specifications (also minimized with PolyPhase). Current mode architecture provides inherent current sharing between output stages. The circuit shown in Figure␣ 1 can be configured for operation up to an input voltage of 28V (limited by the external MOSFETs). RSENSE Selection For Output Current RSENSE1, 2 are chosen based on the required peak output current. The LTC1709 current comparator has a maximum threshold of 75mV/RSENSE and an input common mode range of SGND to 1.1(INTVCC). The current comparator threshold sets the peak inductor current, yielding a maximum average output current IMAX equal to the peak value less half the peak-to-peak ripple current, ∆IL. PolyPhase is a trademark of Linear Technology Corporation. 11 LTC1709-8/LTC1709-9 U W U U APPLICATIO S I FOR ATIO Allowing a margin for variations in the LTC1709 and external component values yields: RSENSE = 2(50mV/IMAX) Operating Frequency effect of inductor value on ripple current and low current operation must also be considered. The PolyPhase approach reduces both input and output ripple currents while optimizing individual output stages to run at a lower fundamental frequency, enhancing efficiency. The LTC1709 uses a constant frequency, phase-lockable architecture with the frequency determined by an internal capacitor. This capacitor is charged by a fixed current plus an additional current which is proportional to the voltage applied to the PLLFLTR pin. Refer to PhaseLocked Loop and Frequency Synchronization for additional information. The inductor value has a direct effect on ripple current. The inductor ripple current ∆IL per individual section, N, decreases with higher inductance or frequency and increases with higher VIN or VOUT: A graph for the voltage applied to the PLLFLTR pin vs frequency is given in Figure␣ 2. As the operating frequency is increased the gate charge losses will be higher, reducing efficiency (see Efficiency Considerations). The maximum switching frequency is approximately 310kHz. where f is the individual output stage operating frequency. PLLFLTR PIN VOLTAGE (V) 2.5 VOUT VOUT 1− fL VIN In a 2-phase converter, the net ripple current seen by the output capacitor is much smaller than the individual inductor ripple currents due to ripple cancellation. The details on how to calculate the net output ripple current can be found in Application Note 77. Figure 3 shows the net ripple current seen by the output capacitors for the 1- and 2- phase configurations. The output ripple current is plotted for a fixed output voltage as the duty factor is varied between 10% and 90% on the x-axis. The output ripple current is normalized against the inductor ripple current at zero duty factor. The graph can be used in place of tedious calculations, simplifying the design process. 2.0 1.5 1.0 0.5 0 120 ∆IL = 170 220 270 OPERATING FREQUENCY (kHz) 1.0 320 1709 F02 0.8 0.7 The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use of smaller inductor and capacitor values. So why would anyone ever choose to operate at lower frequencies with larger components? The answer is efficiency. A higher frequency generally results in lower efficiency because MOSFET gate charge and transition losses increase directly with frequency. In addition to this basic tradeoff, the 0.6 VO/fL Inductor Value Calculation and Output Ripple Current ∆IO(P-P) Figure 2. Operating Frequency vs VPLLFLTR 12 1-PHASE 2-PHASE 0.9 0.5 0.4 0.3 0.2 0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 DUTY FACTOR (VOUT/VIN) 0.8 0.9 1709 F03 Figure 3. Normalized Output Ripple Current vs Duty Factor [IRMS ≈ 0.3 (∆IO(P–P))] LTC1709-8/LTC1709-9 U W U U APPLICATIO S I FOR ATIO Accepting larger values of ∆IL allows the use of low inductances, but can result in higher output voltage ripple. A reasonable starting point for setting ripple current is ∆IL = 0.4(IOUT)/2, where IOUT is the total load current. Remember, the maximum ∆IL occurs at the maximum input voltage. The individual inductor ripple currents are determined by the inductor, input and output voltages. (see EXTVCC Pin Connection). Consequently, logic-level threshold MOSFETs must be used in most applications. The only exception is if low input voltage is expected (VIN < 5V); then, sublogic-level threshold MOSFETs (VGS(TH) < 1V) should be used. Pay close attention to the BVDSS specification for the MOSFETs as well; most of the logic-level MOSFETs are limited to 30V or less. Inductor Core Selection Selection criteria for the power MOSFETs include the “ON” resistance RDS(ON), reverse transfer capacitance CRSS, input voltage and maximum output current. When the LTC1709 is operating in continuous mode the duty factors for the top and bottom MOSFETs of each output stage are given by: Once the values for L1 and L2 are known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy, or Kool Mµ® cores. Actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard,” which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Molypermalloy (from Magnetics, Inc.) is a very good, low loss core material for toroids, but it is more expensive than ferrite. A reasonable compromise from the same manufacturer is Kool Mµ. Toroids are very space efficient, especially when you can use several layers of wire. Because they lack a bobbin, mounting is more difficult. However, designs for surface mount are available which do not increase the height significantly. Power MOSFET, D1 and D2 Selection Two external power MOSFETs must be selected for each controller with the LTC1709: one N-channel MOSFET for the top (main) switch, and one N-channel MOSFET for the bottom (synchronous) switch. The peak-to-peak drive levels are set by the INTVCC voltage. This voltage is typically 5V during start-up Main Switch Duty Cycle = VOUT VIN V –V Synchronous Switch Duty Cycle = IN OUT VIN The MOSFET power dissipations at maximum output current are given by: 2 I V PMAIN = OUT MAX 1 + δ RDS(ON) + VIN 2 2 I k VIN MAX CRSS f 2 ( ) ( ) ( )( ) 2 I V –V PSYNC = IN OUT MAX 1 + δ RDS(ON) VIN 2 ( ) where δ is the temperature dependency of RDS(ON) and k is a constant inversely related to the gate drive current. Both MOSFETs have I2R losses but the topside N-channel equation includes an additional term for transition losses, which peak at the highest input voltage. For VIN < 20V the high current efficiency generally improves with larger MOSFETs, while for VIN > 20V the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CRSS actual provides higher efficiency. The Kool Mµ is a registered trademark of Magnetics, Inc. 13 LTC1709-8/LTC1709-9 U W U U APPLICATIO S I FOR ATIO 0.5 DC LOAD CURRENT The term (1 + δ) is generally given for a MOSFET in the form of a normalized RDS(ON) vs temperature curve, but δ = 0.005/°C can be used as an approximation for low voltage MOSFETs. CRSS is usually specified in the MOSFET characteristics. The constant k = 1.7 can be used to estimate the contributions of the two terms in the main switch dissipation equation. 0.6 RMS INPUT RIPPLE CURRNET synchronous MOSFET losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. 0.4 1-PHASE 2-PHASE 0.3 0.2 0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 DUTY FACTOR (VOUT/VIN) 0.8 0.9 170989 F04 The Schottky diodes, D1 and D2 shown in Figure 1 conduct during the dead-time between the conduction of the two large power MOSFETs. This helps prevent the body diode of the bottom MOSFET from turning on, storing charge during the dead-time, and requiring a reverse recovery period which would reduce efficiency. A 1A to 3A Schottky (depending on output current) diode is generally a good compromise for both regions of operation due to the relatively small average current. Larger diodes result in additional transition losses due to their larger junction capacitance. CIN and COUT Selection In continuous mode, the source current of each top N-channel MOSFET is a square wave of duty cycle VOUT/ VIN. A low ESR input capacitor sized for the maximum RMS current must be used. The details of a closed form equation can be found in Application Note 77. Figure 4 shows the input capacitor ripple current for a 2-phase configuration with the output voltage fixed and input voltage varied. The input ripple current is normalized against the DC output current. The graph can be used in place of tedious calculations. The minimum input ripple current can be achieved when the input voltage is twice the output voltage In the graph of Figure 4, the 2-phase local maximum input RMS capacitor currents are reached when: VOUT 2k − 1 = 4 VIN where k = 1, 2 14 Figure 4. Normalized RMS Input Ripple Current vs Duty Factor for 1 and 2 Output Stages These worst-case conditions are commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturer’s ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. Always consult the capacitor manufacturer if there is any question. It is important to note that the efficiency loss is proportional to the input RMS current squared and therefore a 2-phase implementation results in 75% less power loss when compared to a single phase design. Battery/input protection fuse resistance (if used), PC board trace and connector resistance losses are also reduced by the reduction of the input ripple current in a 2-phase system. The required amount of input capacitance is further reduced by the factor, 2, due to the effective increase in the frequency of the current pulses. The selection of COUT is driven by the required effective series resistance (ESR). Typically once the ESR requirement has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirements. The steady state output ripple (∆VOUT) is determined by: 1 ∆VOUT ≈ ∆IRIPPLE ESR + 16 fCOUT LTC1709-8/LTC1709-9 U W U U APPLICATIO S I FOR ATIO Where f = operating frequency of each stage, COUT = output capacitance and ∆IRIPPLE = combined inductor ripple currents. The output ripple varies with input voltage since ∆IL is a function of input voltage. The output ripple will be less than 50mV at max VIN with ∆IL = 0.4IOUT(MAX)/2 assuming: COUT required ESR < 4(RSENSE) and COUT > 1/(16f)(RSENSE) The emergence of very low ESR capacitors in small, surface mount packages makes very physically small implementations possible. The ability to externally compensate the switching regulator loop using the I TH pin(OPTI-LOOP compensation) allows a much wider selection of output capacitor types. OPTI-LOOP compensation effectively removes constraints on output capacitor ESR. The impedance characteristics of each capacitor type are significantly different than an ideal capacitor and therefore require accurate modeling or bench evaluation during design. Manufacturers such as Nichicon, United Chemicon and Sanyo should be considered for high performance through-hole capacitors. The OS-CON semiconductor dielectric capacitor available from Sanyo and the Panasonic SP surface mount types have the lowest (ESR)(size) product of any aluminum electrolytic at a somewhat higher price. An additional ceramic capacitor in parallel with OS-CON type capacitors is recommended to reduce the inductance effects. In surface mount applications, multiple capacitors may have to be paralleled to meet the ESR or RMS current handling requirements of the application. Aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations. New special polymer surface mount capacitors offer very low ESR also but have much lower capacitive density per unit volume. In the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. Several excellent choices are the AVX TPS, AVX TPSV or the KEMET T510 series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. Other capacitor types include Sanyo OS-CON, Nichicon PL series and Sprague 595D series. Consult the manufacturer for other specific recommendations. A combination of capacitors will often result in maximizing performance and minimizing overall cost and size. INTVCC Regulator An internal P-channel low dropout regulator produces 5V at the INTVCC pin from the VIN supply pin. The INTVCC regulator powers the drivers and internal circuitry of the LTC1709. The INTVCC pin regulator can supply up to 50mA peak and must be bypassed to power ground with a minimum of 4.7µF tantalum or electrolytic capacitor. An additional 1µF ceramic capacitor placed very close to the IC is recommended due to the extremely high instantaneous currents required by the MOSFET gate drivers. High input voltage applications in which large MOSFETs are being driven at high frequencies may cause the maximum junction temperature rating for the LTC1709 to be exceeded. The supply current is dominated by the gate charge supply current, in addition to the current drawn from the differential amplifier output. The gate charge is dependent on operating frequency as discussed in the Efficiency Considerations section. The supply current can either be supplied by the internal 5V regulator or via the EXTVCC pin. When the voltage applied to the EXTVCC pin is less than 4.7V, all of the INTVCC load current is supplied by the internal 5V linear regulator. Power dissipation for the IC is higher in this case by (IIN)(VIN – INTVCC) and efficiency is lowered. The junction temperature can be estimated by using the equations given in Note 1 of the Electrical Characteristics. For example, the LTC1709 VIN current is limited to less than 24mA from a 24V supply: TJ = 70°C + (24mA)(24V)(85°C/W) = 119°C Use of the EXTVCC pin reduces the junction temperature to: TJ = 70°C + (24mA)(5V)(85°C/W) = 80.2°C The input supply current should be measured while the controller is operating in continuous mode at maximum VIN and the power dissipation calculated in order to prevent the maximum junction temperature from being exceeded. 15 LTC1709-8/LTC1709-9 U W U U APPLICATIO S I FOR ATIO EXTVCC Connection The LTC1709 contains an internal P-channel MOSFET switch connected between the EXTVCC and INTVCC pins. When the voltage applied to EXTVCC rises above 4.7V, the internal regulator is turned off and an internal switch closes, connecting the EXTVCC pin to the INTVCC pin thereby supplying internal and MOSFET gate driving power to the IC. The switch remains closed as long as the voltage applied to EXTVCC remains above 4.5V. This allows the MOSFET driver and control power to be derived from the output during normal operation (4.7V < VEXTVCC < 7V) and from the internal regulator when the output is out of regulation (start-up, short-circuit). Do not apply greater than 7V to the EXTVCC pin and ensure that EXTVCC < VIN + 0.3V when using the application circuits shown. If an external voltage source is applied to the EXTVCC pin when the VIN supply is not present, a diode can be placed in series with the LTC1709’s VIN pin and a Schottky diode between the EXTVCC and the VIN pin, to prevent current from backfeeding VIN. Significant efficiency gains can be realized by powering INTVCC from the output, since the VIN current resulting from the driver and control currents will be scaled by the ratio: (Duty Factor)/(Efficiency). For 5V regulators this means connecting the EXTVCC pin directly to VOUT. However, for 3.3V and other lower voltage regulators, additional circuitry is required to derive INTVCC power from the output. OPTIONAL EXTVCC CONNECTION 5V < VSEC < 7V + The following list summarizes the four possible connections for EXTVCC: 1. EXTVCC left open (or grounded). This will cause INTVCC to be powered from the internal 5V regulator resulting in a significant efficiency penalty at high input voltages. 2. EXTVCC connected directly to VOUT. This is the normal connection for a 5V regulator and provides the highest efficiency. 3. EXTVCC connected to an external supply. If an external supply is available in the 5V to 7V range, it may be used to power EXTVCC providing it is compatible with the MOSFET gate drive requirements. 4. EXTVCC connected to an output-derived boost network. For 3.3V and other low voltage regulators, efficiency gains can still be realized by connecting EXTVCC to an outputderived voltage which has been boosted to greater than 4.7V but less than 7V. This can be done with either the inductive boost winding as shown in Figure 5a or the capacitive charge pump shown in Figure 5b. The charge pump has the advantage of simple magnetics. Topside MOSFET Driver Supply (CB,DB) (Refer to Functional Diagram) External bootstrap capacitors CB1 and CB2 connected to the BOOST1 and BOOST2 pins supply the gate drive voltages for the topside MOSFETs. Capacitor CB in the Functional Diagram is charged though diode DB from + + VIN CIN VIN CIN VIN VIN 1N4148 TG1 LTC1709 + T1 BAT85 RSENSE VOUT SW1 COUT BG1 VOUT L1 + + BG1 BAT85 VN2222LL EXTVCC RSENSE SW1 N-CH LTC1709 1µF EXTVCC 0.22µF TG1 VSEC N-CH BAT85 COUT N-CH N-CH PGND PGND 1709 F05b 1709 F05a Figure 5a. Secondary Output Loop with EXTVCC Connection 16 Figure 5b. Capacitive Charge Pump for EXTVCC LTC1709-8/LTC1709-9 U W U U APPLICATIO S I FOR ATIO INTVCC when the SW pin is low. When the topside MOSFET turns on, the driver places the CB voltage across the gatesource of the desired MOSFET. This enhances the MOSFET and turns on the topside switch. The switch node voltage, SW, rises to VIN and the BOOST pin rises to VIN + VINTVCC. The value of the boost capacitor CB needs to be 30 to 100 times that of the total input capacitance of the topside MOSFET(s). The reverse breakdown of DB must be greater than VIN(MAX). The final arbiter when defining the best gate drive amplitude level will be the input supply current. If a change is made that decreases input current, the efficiency has improved. If the input current does not change then the efficiency has not changed either. Output Voltage The LTC1709 has a true remote voltage sense capablity. The sensing connections should be returned from the load back to the differential amplifier’s inputs through a common, tightly coupled pair of PC traces. The differential amplifier corrects for DC drops in both the power and ground paths. The differential amplifier output signal is divided down and compared with the internal precision 0.8V voltage reference by the error amplifier. Output Voltage Programming Table 1. VID Output Voltage Programming VID4 VID3 VID2 VID1 VID0 LTC1709-8 VRM8.4 LTC1709-9 VRM9.0 0 0 0 0 0 2.05V 1.850V 0 0 0 0 1 2.00V 1.825V 0 0 0 1 0 1.95V 1.800V 0 0 0 1 1 1.90V 1.775V 0 0 1 0 0 1.85V 1.750V 0 0 1 0 1 1.80V 1.725V 0 0 1 1 0 1.75V 1.700V 0 0 1 1 1 1.70V 1.675V 0 1 0 0 0 1.65V 1.650V 0 1 0 0 1 1.60V 1.625V 0 1 0 1 0 1.55V 1.600V 0 1 0 1 1 1.50V 1.575V 0 1 1 0 0 1.45V 1.550V 0 1 1 0 1 1.40V 1.525V 0 1 1 1 0 1.35V 1.500V 0 1 1 1 1 1.30V 1.475V 1 0 0 0 0 3.50V 1.450V 1 0 0 0 1 3.40V 1.425V 1 0 0 1 0 3.30V 1.400V 1 0 0 1 1 3.20V 1.375V 1 0 1 0 0 3.10V 1.350V 1 0 1 0 1 3.00V 1.325V 1 0 1 1 0 2.90V 1.300V The output voltage is digitally programmed as defined in Table 1 using the VID0 to VID4 logic input pins. The VID logic inputs program a precision, 0.25% internal feedback resistive divider. The LTC1709-8 has an output voltage range of 1.30V to 3.5V in 50mV and 100mV steps. The LTC1709-9 has an output voltage range of 1.10V to 1.85V in 25mV steps. 1 0 1 1 1 2.80V 1.275V 1 1 0 0 0 2.70V 1.250V 1 1 0 0 1 2.60V 1.225V 1 1 0 1 0 2.50V 1.200V 1 1 0 1 1 2.40V 1.175V 1 1 1 0 0 2.30V 1.150V 1 1 1 0 1 2.20V 1.125V Between the ATTENOUT pin and ground is a variable resistor, R1, whose value is controlled by the five VID input pins (VID0 to VID4). Another resistor, R2, between the ATTENIN and the ATTENOUT pins completes the resistive divider. The output voltage is thus set by the ratio of (R1␣ +␣ R2) to R1. 1 1 1 1 0 2.10V 1.100V 1 1 1 1 1 No_CPU/ Shutdown* No_CPU/ Shutdown* *Represents codes without a defined output voltage as specified in Intel specifications. The LTC1709 interprets these codes as a valid input and produces an output voltage as follows: LTC1709-8 (11111) = 2V LTC1709-9 (11111) = 1.075V 17 LTC1709-8/LTC1709-9 U W U U APPLICATIO S I FOR ATIO Each VID digital input is pulled up by a 40k resistor in series with a diode from VBIAS. Therefore, it must be grounded to get a digital low input, and can be either floated or connected to VBIAS to get a digital high input. The series diode is used to prevent the digital inputs from being damaged or clamped if they are driven higher than VBIAS. The digital inputs accept CMOS voltage levels. VBIAS is the supply voltage for the VID section. It is normally connected to INTVCC but can be driven from other sources. If it is driven from another source, that source must be in the range of 2.7V to 5.5V and must be alive prior to enabling the LTC1709. ( ) 3V − 1.5V CSS = 1.25s /µF CSS 1.2µA By pulling the RUN/SS pin below 0.8V the LTC1709 is put into low current shutdown (IQ < 40µA). The RUN/SS pins can be driven directly from logic as shown in Figure 6. Diode D1 in Figure 6 reduces the start delay but allows CSS to ramp up slowly providing the soft-start function. The RUN/SS pin has an internal 6V zener clamp (see Functional Diagram). 3.3V OR 5V The RUN/SS pin provides three functions: 1) Run/Shutdown, 2) soft-start and 3) a defeatable short-circuit latchoff timer. Soft-start reduces the input power sources’ surge currents by gradually increasing the controller’s current limit ITH(MAX). The latchoff timer prevents very short, extreme load transients from tripping the overcurrent latch. A small pull-up current (>5µA) supplied to the RUN/ SS pin will prevent the overcurrent latch from operating. The following explanation describes how the functions operate. An internal 1.2µA current source charges up the soft-start capacitor, CSS. When the voltage on RUN/SS reaches 1.5V, the controller is permitted to start operating. As the voltage on RUN/SS increases from 1.5V to 3.0V, the internal current limit is increased from 25mV/RSENSE to 75mV/RSENSE. The output current limit ramps up slowly, taking an additional 1.4s/µF to reach full current. The output current thus ramps up slowly, reducing the starting surge current required from the input power supply. If RUN/SS has been pulled all the way to ground there is a delay before starting of approximately: 18 tIRAMP = INTVCC VIN Soft-Start/Run Function tDELAY = The time for the output current to ramp up is then: ( ) 1.5V CSS = 1.25s /µF CSS 1.2µA D1 RUN/SS RSS* RSS* D1* RUN/SS CSS CSS *OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF 170989 F06 Figure 6. RUN/SS Pin Interfacing Fault Conditions: Overcurrent Latchoff The RUN/SS pin also provides the ability to latch off the controllers when an overcurrent condition is detected. The RUN/SS capacitor, CSS, is used initially to limit the inrush current of both controllers. After the controllers have been started and been given adequate time to charge up the output capacitors and provide full load current, the RUN/ SS capacitor is used for a short-circuit timer. If the output voltage falls to less than 70% of its nominal value after CSS reaches 4.1V, CSS begins discharging on the assumption that the output is in an overcurrent condition. If the condition lasts for a long enough period as determined by the size of the CSS, the controller will be shut down until the RUN/SS pin voltage is recycled. If the overload occurs during start-up, the time can be approximated by: tLO1 ≈ (CSS • 0.6V)/(1.2µA) = 5 • 105 (CSS) LTC1709-8/LTC1709-9 U W U U APPLICATIO S I FOR ATIO If the overload occurs after start-up, the voltage on CSS will continue charging and will provide additional time before latching off: tLO2 ≈ (CSS • 3V)/(1.2µA) = 2.5 • 106 (CSS) This built-in overcurrent latchoff can be overridden by providing a pull-up resistor, RSS, to the RUN/SS pin as shown in Figure 6. This resistance shortens the soft-start period and prevents the discharge of the RUN/SS capacitor during a severe overcurrent and/or short-circuit condition. When deriving the 5µA current from VIN as in the figure, current latchoff is always defeated. The diode connecting this pull-up resistor to INTVCC, as in Figure␣ 6, eliminates any extra supply current during shutdown while eliminating the INTVCC loading from preventing controller start-up. Why should you defeat current latchoff? During the prototyping stage of a design, there may be a problem with noise pickup or poor layout causing the protection circuit to latch off the controller. Defeating this feature allows troubleshooting of the circuit and PC layout. The internal short-circuit and foldback current limiting still remains active, thereby protecting the power supply system from failure. A decision can be made after the design is complete whether to rely solely on foldback current limiting or to enable the latchoff feature by removing the pull-up resistor. The value of the soft-start capacitor CSS may need to be scaled with output voltage, output capacitance and load current characteristics. The minimum soft-start capacitance is given by: of 1.2V corresponds to a frequency of approximately 220kHz. The nominal operating frequency range of the LTC1709 is 140kHz to 310kHz. The phase detector used is an edge sensitive digital type which provides zero degrees phase shift between the external and internal oscillators. This type of phase detector will not lock up on input frequencies close to the harmonics of the VCO center frequency. The PLL hold-in range, ∆fH, is equal to the capture range, ∆fC: ∆fH = ∆fC = ±0.5 fO (150kHz-300kHz) The output of the phase detector is a complementary pair of current sources charging or discharging the external filter network on the PLLFLTR pin. A simplified block diagram is shown in Figure 7. If the external frequency (fPLLIN) is greater than the oscillator frequency f0SC, current is sourced continuously, pulling up the PLLFLTR pin. When the external frequency is less than f0SC, current is sunk continuously, pulling down the PLLFLTR pin. If the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. Thus the voltage on the PLLFLTR pin is adjusted until the phase and frequency of the external and internal oscillators are identical. At this stable operating point the phase comparator output is open and the filter capacitor CLP holds the voltage. The LTC1709 PLLIN pin must be driven from a low impedance source such as a logic gate located close to the pin. 2.4V CSS > (COUT )(VOUT)(10-4)(RSENSE) The minimum recommended soft-start capacitor of CSS = 0.1µF will be sufficient for most applications. PHASE DETECTOR CLP EXTERNAL OSC PLLFLTR PLLIN Phase-Locked Loop and Frequency Synchronization The LTC1709 has a phase-locked loop comprised of an internal voltage controlled oscillator and phase detector. This allows the top MOSFET turn-on to be locked to the rising edge of an external source. The frequency range of the voltage controlled oscillator is ±50% around the center frequency fO. A voltage applied to the PLLFLTR pin RLP 10k 50k DIGITAL PHASE/ FREQUENCY DETECTOR OSC 1709 F07 Figure 7. Phase-Locked Loop Block Diagram 19 LTC1709-8/LTC1709-9 U W U U APPLICATIO S I FOR ATIO The loop filter components (CLP, RLP) smooth out the current pulses from the phase detector and provide a stable input to the voltage controlled oscillator. The filter components CLP and RLP determine how fast the loop acquires lock. Typically RLP =10k and CLP is 0.01µF to 0.1µF. Minimum On-Time Considerations Minimum on-time, tON(MIN), is the smallest time duration that the LTC1709 is capable of turning on the top MOSFET. It is determined by internal timing delays and the gate charge required to turn on the top MOSFET. Low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: tON(MIN) < VOUT () VIN f If the duty cycle falls below what can be accommodated by the minimum on-time, the LTC1709 will begin to skip cycles resulting in variable frequency operation. The output voltage will continue to be regulated, but the ripple current and ripple voltage will increase. The minimum on-time for the LTC1709 is generally less than 200ns. However, as the peak sense voltage decreases, the minimum on-time gradually increases. This is of particular concern in forced continuous applications with low ripple current at light loads. If the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger ripple current and voltage ripple. If an application can operate close to the minimum on-time limit, an inductor must be chosen that has a low enough inductance to provide sufficient ripple amplitude to meet the minimum on-time requirement. As a general rule, keep the inductor ripple current of each phase equal to or greater than 15% of IOUT(MAX) at VIN(MAX). Voltage Positioning Voltage positioning can be used to minimize peak-to-peak output voltage excursion under worst-case transient loading conditions. The open-loop DC gain of the control loop 20 is reduced depending upon the maximum load step specifications. Voltage positioning can easily be added to the LTC1709 by loading the ITH pin with a resistive divider having a Thevenin equivalent voltage source equal to the midpoint operating voltage of the error amplifier, or 1.2V (see Figure 8). The resistive load reduces the DC loop gain while maintaining the linear control range of the error amplifier. The worst-case peak-to-peak output voltage deviation due to transient loading can theoretically be reduced to half or alternatively the amount of output capacitance can be reduced for a particular application. A complete explanation is included in Design Solutions 10 or the LTC1736 data sheet. (See www.linear-tech.com) INTVCC RT2 ITH RT1 RC LTC1709 CC 1709 F08 Figure 8. Active Voltage Positioning Applied to the LTC1709 Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: %Efficiency = 100% – (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC1709 circuits: 1) I2R losses, 2) Topside MOSFET transition losses, 3) INTVCC regulator current and 4) LTC1709 VIN current (including loading on the differential amplifier output). LTC1709-8/LTC1709-9 U W U U APPLICATIO S I FOR ATIO 1) I2R losses are predicted from the DC resistances of the fuse (if used), MOSFET, inductor, current sense resistor, and input and output capacitor ESR. In continuous mode the average output current flows through L and RSENSE, but is “chopped” between the topside MOSFET and the synchronous MOSFET. If the two MOSFETs have approximately the same RDS(ON), then the resistance of one MOSFET can simply be summed with the resistances of L, RSENSE and ESR to obtain I2R losses. For example, if each RDS(ON) = 10mΩ, RL = 10mΩ, and RSENSE = 5mΩ, then the total resistance is 25mΩ. This results in losses ranging from 2% to 8% as the output current increases from 3A to 15A per output stage for a 5V output, or a 3% to 12% loss per output stage for a 3.3V output. Efficiency varies as the inverse square of VOUT for the same external components and output power level. The combined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system! 2) Transition losses apply only to the topside MOSFET(s), and are significant only when operating at high input voltages (typically 12V or greater). Transition losses can be estimated from: Transition Loss = (1.7) VIN2 IO(MAX) CRSS f 3) INTVCC current is the sum of the MOSFET driver and control currents. The MOSFET driver current results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from INTVCC to ground. The resulting dQ/dt is a current out of INTVCC that is typically much larger than the control circuit current. In continuous mode, IGATECHG = (QT + QB), where QT and QB are the gate charges of the topside and bottom side MOSFETs. Supplying INTVCC power through the EXTVCC switch input from an output-derived source will scale the VIN current required for the driver and control circuits by the ratio (Duty Factor)/(Efficiency). For example, in a 20V to 5V application, 10mA of INTVCC current results in approximately 3mA of VIN current. This reduces the mid-current loss from 10% or more (if the driver was powered directly from VIN) to only a few percent. 4) The VIN current has two components: the first is the DC supply current given in the Electrical Characteristics table, which excludes MOSFET driver and control currents; the second is the current drawn from the differential amplifier output. VIN current typically results in a small (<0.1%) loss. Other “hidden” losses such as copper trace and internal battery resistances can account for an additional 5% to 10% efficiency degradation in portable systems. It is very important to include these “system” level losses in the design of a system. The internal battery and input fuse resistance losses can be minimized by making sure that CIN has adequate charge storage and a very low ESR at the switching frequency. A 50W supply will typically require a minimum of 200µF to 300µF of capacitance having a maximum of 10mΩ to 20mΩ of ESR. The LTC1709 2-phase architecture typically halves this input capacitance requirement over competing solutions. Other losses including Schottky conduction losses during deadtime and inductor core losses generally account for less than 2% total additional loss. Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in DC (resistive) load current. When a load step occurs, VOUT shifts by an amount equal to ∆ILOAD(ESR), where ESR is the effective series resistance of COUT (∆ILOAD) also begins to charge or discharge COUT generating the feedback error signal that forces the regulator to adapt to the current change and return VOUT to its steady-state value. During this recovery time VOUT can be monitored for excessive overshoot or ringing, which would indicate a stability problem. The availability of the ITH pin not only allows optimization of control loop behavior but also provides a DC coupled and AC filtered closed loop response test point. The DC step, rise time, and settling at this test point truly reflects the closed loop response. Assuming a predominantly second order system, phase margin and/or damping factor can be 21 LTC1709-8/LTC1709-9 U W U U APPLICATIO S I FOR ATIO estimated using the percentage of overshoot seen at this pin. The bandwidth can also be estimated by examining the rise time at the pin. The ITH external components shown in the Figure 1 circuit will provide an adequate starting point for most applications. The ITH series RC-CC filter sets the dominant pole-zero loop compensation. The values can be modified slightly (from 0.2 to 5 times their suggested values) to optimize transient response once the final PC layout is done and the particular output capacitor type and value have been determined. The output capacitors need to be decided upon because the various types and values determine the loop gain and phase. An output current pulse of 20% to 80% of full-load current having a rise time of <2µs will produce output voltage and ITH pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. The initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. This is why it is better to look at the Ith pin signal which is in the feedback loop and is the filtered and compensated control loop response. The gain of the loop will be increased by increasing RC and the bandwidth of the loop will be increased by decreasing CC. If RC is increased by the same factor that CC is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. Automotive Considerations: Plugging into the Cigarette Lighter As battery-powered devices go mobile, there is a natural interest in plugging into the cigarette lighter in order to conserve or even recharge battery packs during operation. But before you connect, be advised: you are plugging into the supply from hell. The main battery line in an automobile is the source of a number of nasty potential transients, including load-dump, reverse-battery, and double-battery. Load-dump is the result of a loose battery cable. When the cable breaks connection, the field collapse in the alternator can cause a positive spike as high as 60V which takes several hundred milliseconds to decay. Reverse-battery is just what it says, while double-battery is a consequence of tow truck operators finding that a 24V jump start cranks cold engines faster than 12V. The network shown in Figure 9 is the most straightforward approach to protect a DC/DC converter from the ravages of an automotive power line. The series diode prevents current from flowing during reverse-battery, while the transient suppressor clamps the input voltage during load-dump. Note that the transient suppressor should not conduct during double-battery operation, but must still clamp the input voltage below breakdown of the converter. Although the LT1709 has a maximum input voltage of 36V, most applications will be limited to 30V by the MOSFET BVDSS. 50A IPK RATING 12V TRANSIENT VOLTAGE SUPPRESSOR GENERAL INSTRUMENT 1.5KA24A VIN LTC1709 170989 F09 Figure 9. Automotive Application Protection 22 LTC1709-8/LTC1709-9 U W U U APPLICATIO S I FOR ATIO Design Example As a design example, assume VIN = 5V (nominal), VIN␣ =␣ 5.5V (max), VOUT = 1.8V, IMAX = 20A, TA = 70°C and f␣ =␣ 300kHz. The inductance value is chosen first based on a 30% ripple current assumption. The highest value of ripple current occurs at the maximum input voltage. Tie the FREQSET pin to the INTVCC pin for 300kHz operation. The minimum inductance for 30% ripple current is: L≥ ≥ VOUT VOUT 1− VIN f ∆I ( ) ( 1.8 V 1− 300kHz 30% 10 A 5.5V 1.8 V ≥ 1.35µH )( )( ) A 1.5µH inductor will produce 27% ripple current. The peak inductor current will be the maximum DC value plus one half the ripple current, or 11.4A. The minimum ontime occurs at maximum VIN: tON(MIN) = VOUT 1.8 V = = 1.1µs VINf (5.5V )(300kHz) The RSENSE resistors value can be calculated by using the maximum current sense voltage specification with some accomodation for tolerances: 50mV RSENSE = ≈ 0.004Ω 11.4A The power dissipation on the topside MOSFET can be easily estimated. Using a Siliconix Si4420DY for example; RDS(ON) = 0.013Ω, CRSS = 300pF. At maximum input voltage with TJ (estimated) = 110°C at an elevated ambient temperature: PMAIN = ( ) [1+ (0.005)(110°C − 25°C)] 2 0.013Ω + 1.7(5.5V ) (10 A )(300pF ) (300kHz) = 0.65W 1.8 V 10 5.5V 2 The worst-case power disipated by the synchronous MOSFET under normal operating conditions at elevated ambient temperature and estimated 50°C junction temperature rise is: ( ) (1.48)(0.013Ω) 5.5V − 1.8 V 10 A 5.5V = 1.29W PSYNC = 2 A short-circuit to ground will result in a folded back current of about: ISC = ( ) = 6.6A 25mV 1 200ns 5.5V + 0.004Ω 2 1.5µH The worst-case power disipated by the synchronous MOSFET under short-circuit conditions at elevated ambient temperature and estimated 50°C junction temperature rise is: ( ) (1.48)(0.013Ω) 5.5V − 1.8 V 6.6 A 5.5V = 564mW PSYNC = 2 which is less than half of the normal, full-load dissipation. Incidentally, since the load no longer dissipates power in the shorted condition, total system power dissipation is decreased by over 99%. The duty factor for this application is: DF = VO 1.8 V = = 0.36 VIN 5V Using Figure 4, the RMS ripple current will be: IINRMS = (20A)(0.23) = 4.6ARMS An input capacitor(s) with a 4.6ARMS ripple current rating is required. The output capacitor ripple current is calculated by using the inductor ripple already calculated for each inductor and multiplying by the factor obtained from Figure␣ 3 along with the calculated duty factor. The output ripple in 23 LTC1709-8/LTC1709-9 U U W U APPLICATIO S I FOR ATIO continuous mode will be highest at the maximum input voltage since the duty factor is < 50%. The maximum output current ripple is: ( ) VOUT 0.3 at 33% D F fL 1.8 V 0.3 ∆ICOUTMAX = 300kHz 1.5µH ∆ICOUT = ( = 1.2ARMS )( ( ) ) VOUTRIPPLE = 20mΩ 1.2ARMS = 24mVRMS PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC1709. These items are also illustrated graphically in the layout diagram of Figure␣ 10. Check the following in your layout: 1) Are the signal and power grounds segregated? The LTC1709 signal ground pin should return to the (–) plate of COUT separately. The power ground returns to the sources of the bottom N-channel MOSFETs, anodes of the Schottky diodes, and (–) plates of CIN, which should have as short lead lengths as possible. 2) Does the LTC1709 VOS+ pin connect to the point of load? Does the LTC1709 VOS– pin connect to the load return? 3) Are the SENSE – and SENSE + leads routed together with minimum PC trace spacing? The filter capacitors between SENSE + and SENSE – pin pairs should be as close as possible to the LTC1709. Ensure accurate current sensing with Kelvin connections at the current sense resistor. 4) Does the (+) plate of CIN connect to the drains of the topside MOSFETs as closely as possible? This capacitor provides the AC current to the MOSFETs. Keep the input 24 current path formed by the input capacitor, top and bottom MOSFETs, and the Schottky diode on the same side of the PC board in a tight loop to minimize conducted and radiated EMI. 5) Is the INTVCC 1µF ceramic decoupling capacitor connected closely between INTVCC and the power ground pin? This capacitor carries the MOSFET driver peak currents. A small value is recommended to allow placement immediately adjacent to the IC. 6) Keep the switching nodes, SW1 (SW2), away from sensitive small-signal nodes. Ideally the switch nodes should be placed at the furthest point from the LTC1709. 7) Use a low impedance source such as a logic gate to drive the PLLIN pin and keep the lead as short as possible. The diagram in Figure 10 illustrates all branch currents in a 2-phase switching regulator. It becomes very clear after studying the current waveforms why it is critical to keep the high-switching-current paths to a small physical size. High electric and magnetic fields will radiate from these “loops” just as radio stations transmit signals. The output capacitor ground should return to the negative terminal of the input capacitor and not share a common ground path with any switched current paths. The left half of the circuit gives rise to the “noise” generated by a switching regulator. The ground terminations of the sychronous MOSFETs and Schottky diodes should return to the negative plate(s) of the input capacitor(s) with a short isolated PC trace since very high switched currents are present. A separate isolated path from the negative plate(s) of the input capacitor(s) should be used to tie in the IC power ground pin (PGND) and the signal ground pin (SGND). This technique keeps inherent signals generated by high current pulses from taking alternate current paths that have finite impedances during the total period of the switching regulator. External OPTI-LOOP compensation allows overcompensation for PC layouts which are not optimized but this is not the recommended design procedure. LTC1709-8/LTC1709-9 U W U U APPLICATIO S I FOR ATIO SW1 L1 RSENSE1 D1 VIN VOUT RIN CIN + + SW2 BOLD LINES INDICATE HIGH, SWITCHING CURRENT LINES. KEEP LINES TO A MINIMUM LENGTH. L2 COUT RL RSENSE2 D2 170989 F10 Figure 10. Instantaneous Current Path Flow in a Multiple Phase Switching Regulator Simplified Visual Explanation of How a 2-Phase Controller Reduces Both Input and Output RMS Ripple Current A multiphase power supply significantly reduces the amount of ripple current in both the input and output capacitors. The RMS input ripple current is divided by, and the effective ripple frequency is multiplied up by the number of phases used (assuming that the input voltage is greater than the number of phases used times the output voltage). The output ripple amplitude is also reduced by, and the effective ripple frequency is increased by the number of phases used. Figure 11 graphically illustrates the principle. SINGLE PHASE SW V ICIN DUAL PHASE SW1 V SW2 V IL1 ICOUT IL2 ICIN ICOUT RIPPLE 1709 F11 Figure 11. Single and 2-Phase Current Waveforms 25 LTC1709-8/LTC1709-9 U W U U APPLICATIO S I FOR ATIO The worst-case RMS ripple current for a single stage design peaks at an input voltage of twice the output voltage. The worst-case RMS ripple current for a two stage design results in peak outputs of 1/4 and 3/4 of input voltage. When the RMS current is calculated, higher effective duty factor results and the peak current levels are divided as long as the currents in each stage are balanced. Refer to Application Note 19 for a detailed description of how to calculate RMS current for the single stage switching regulator. Figures 3 and 4 help to illustrate how the input and output currents are reduced by using an additional phase. The input current peaks drop in half and the frequency is doubled for this 2-phase converter. The input capacity requirement is thus reduced theoretically by a factor of four! Ceramic input capacitors with their unbeatably low ESR characteristics can be used. Figure 4 illustrates the RMS input current drawn from the input capacitance vs the duty cycle as determined by the ratio of input and output voltage. The peak input RMS current level of the single phase system is reduced by 50% in a 2-phase solution due to the current splitting between the two stages. 26 An interesting result of the 2-phase solution is that the VIN which produces worst-case ripple current for the input capacitor, VOUT = VIN/2, in the single phase design produces zero input current ripple in the 2-phase design. The output ripple current is reduced significantly when compared to the single phase solution using the same inductance value because the VOUT/L discharge current term from the stage that has its bottom MOSFET on subtracts current from the (VIN - VOUT)/L charging current resulting from the stage which has its top MOSFET on. The output ripple current is: ∆IRIPPLE = ( ) 2VOUT 1 − 2D 1 − D fL 1 − 2D + 1 where D is duty factor. The input and output ripple frequency is increased by the number of stages used, reducing the output capacity requirements. When VIN is approximately equal to 2(VOUT) as illustrated in Figures 3 and 4, very low input and output ripple currents result. LTC1709-8/LTC1709-9 U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. G Package 36-Lead Plastic SSOP (0.209) (LTC DWG # 05-08-1640) 12.67 – 12.93* (0.499 – 0.509) 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 7.65 – 7.90 (0.301 – 0.311) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 5.20 – 5.38** (0.205 – 0.212) 1.73 – 1.99 (0.068 – 0.078) 0° – 8° 0.13 – 0.22 (0.005 – 0.009) 0.55 – 0.95 (0.022 – 0.037) NOTE: DIMENSIONS ARE IN MILLIMETERS *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.152mm (0.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE 0.65 (0.0256) BSC 0.25 – 0.38 (0.010 – 0.015) 0.05 – 0.21 (0.002 – 0.008) G36 SSOP 1098 27 LTC1709-8/LTC1709-9 U TYPICAL APPLICATIO LTC1709-8 0.1µF 1000pF 2.7k RUNN/SS NC 2 SENSE1 + TG1 3 SENSE1 – SW1 4 10k INTVCC 6 51k 15k 5 7 47k 8 3.3nF 100pF 9 10 11 PLLIN VIN BG1 NC EXTVCC ITH INTVCC SGND VDIFFOUT PGND BG2 BOOST2 VOS + SW2 13 SENSE2 – TG2 14 SENSE2 + PGOOD 15 470pF BOOST1 PLLFLTR VOS – 12 1000pF EAIN 16 17 18 ATTENOUT VBIAS ATTENIN VID4 VID0 VID3 VID1 VID2 36 L1 35 0.004Ω 34 0.22µF 33 M1 M2 32 D1 MBRS140T3 31 30 10Ω 5V (OPT) CIN 47µF 35V + 29 28 + 1 0.1µF 10µF COUT VIN 5V TO 28V 27 26 25 M3 0.22µF M4 VOUT 1.3V TO 3.5V 20A 0.004Ω 24 100k 23 L2 PGOOD 22 21 D2 MBRS140T3 0.1µF 10Ω 20 SWITCHING FREQUENCY = 200kHz CIN: 5A RIPPLE CURRENT RATING REQUIRED COUT: 4 × 180µF/4V PANASONIC SP L1 TO L2: 1.5µH SUMIDA CEP125-1R5MC M1 TO M4: FAIRCHILD FDS7760A 19 VID INPUTS 170989 F12 Figure 12. 1.3V to 2.5V/20A CPU Power Supply with Active Voltage Positioning RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1438/LTC1439 Dual High Efficiency Low Noise Synchronous Step-Down Switching Regulators POR, Auxiliary Regulator LTC1438-ADJ Dual Synchronous Controller with Auxiliary Regulator POR, External Feedback Divider LTC1538-AUX Dual High Efficiency Low Noise Synchronous Step-Down Switching Regulator Auxiliary Regulator, 5V Standby LTC1539 Dual High Efficiency Low Noise Synchronous Step-Down Switching Regulator 5V Standby, POR, Low-Battery, Aux Regulator LTC1436A-PLL High Efficiency Low Noise Synchronous Step-Down Switching Regulator Adaptive PowerTM Mode, 24-Pin SSOP LTC1628/LTC1628-PG Dual High Efficiency, 2-Phase Synchronous Step-Down Switching Regulators Constant Frequency, Standby, 5V and 3.3V LDOs LTC1629/LTC1629-PG PolyPhase High Efficiency Controllers Expandable Up to 12 Phases, G-28, Up to 120A LTC1929 2-Phase High Efficiency Controller Adjustable Output Up to 40A, G-28 LTC1702/LTC1703 Dual High Efficiency, 2-Phase Synchronous Step-Down Switching Regulators 500kHz, 25MHz GBW LTC1708-PG Dual High Efficiency, 2-Phase Synchronous Step-Down Switching Regulator with 5-Bit VID and Power Good Indication 1.3V ≤ VOUT ≤ 3.5V, Current Mode Ensures Accurate Current Sharing, 3.5V ≤ VIN ≤ 36V LTC1709 High Efficiency, 2-Phase Synchronous Step-Down Switching Regulator with 5-Bit VID and Fault Coupling Control 1.3V ≤ VOUT ≤ 3.5V, Current Mode Ensures Accurate Current Sharing, 3.5V ≤ VIN ≤ 36V LTC1735 High Efficiency Synchronous Step-Down Controller Burst ModeTM Operation, 16-Pin Narrow SSOP, Fault Protection, 3.5V ≤ VIN ≤ 36V LTC1736 High Efficiency Synchronous Step-Down Controller with 5-Bit VID Output Fault Protection, Power Good, GN-24, 3.5V ≤ VIN ≤ 36V, 0.925V ≤ VOUT ≤ 2V Adaptive Power and Burst Mode are trademarks of Linear Technology Corporation. 28 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com 170989i LT/TP 0500 4K • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2000