INTERSIL CA1523

CA1523
Voltage Regulator Control Circuit
for Variable Switching Regulator
April 1994
Features
Description
• Operates up to 200kHz
The CA1523 monolithic silicon integrated circuit is a variable
interval pulse regulator designed to provide the control circuitry for use in switching regulator circuits. It operates from
11V to 15V.
• Pins ESD Protected
• Remote ON/OFF
• Slow Start with Reset
• Overcurrent Sensing
• Lower Peak Currents than PWM Regulator
- Less Prone to Magnetic Saturation
Ordering Information
PART
NUMBER
CA1523E
TEMPERATURE
RANGE
0oC to +70oC
PACKAGE
14 Lead Plastic DIP
The regulator provides a single output drive capable of
300mA source/200mA sink. The maximum operating frequency is better than 200kHz. An attractive feature of the
CA1523 is that the timing capacitor charge and discharge
current is set up externally via a single resistor. The ratio of
charge to discharge current is internally set at a maximum of
2 to 1 allowing simultaneous change in output pulse width
with increased frequency at higher load. The pulse width
variation at higher frequencies effectively compensates for
the losses in magnetics and thereby increases the power
supply efficiency at higher load end by as much as 20
percent.
Pinout
CA1523 (PDIP)
TOP VIEW
ERROR
1
14 TIMING
CURRENT SENSE
2
13 ZENER
GND
3
12 ON/OFF
RISE TIME
4
11 OVER CURRENT
OUTPUT GND
5
10 SLOW START
OUTPUT
6
9
LOGIC OUTPUT
VCC
7
8
NC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
407-727-9207 | Copyright © Intersil Corporation 1999
7-11
File Number
1785.2
Specifications CA1523
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V
Supply Current
|6(MAX). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
|6(MAX), 1µs,1800pF Load . . . . . . . . . . . . . . . . . . . . +300, -200mA
Device Dissipation
Up to TA = 70oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530mW
Above TA = 70oC. . . . . . . . . . . . . . . Derate Linearly at 6.7mW/oC
Thermal Resistance
θJA
Plastic DIP Package . . . . . . . . . . . . . . . . . . . . . . . .
120oC/W
Device Dissipation
Up to TA = 70oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665mW
Ambient Temperature Range
Operating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to +70oC
Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +150oC
Lead Temperature (During Soldering)
At distance 1/16 ± in. (1.59mm ±0.79mm)
from case for 10s Max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
PARAMETERS
TA = +25oC, Refer to condition shown in test circuit; V7 = 13V, V1 = 5.9V Unless Otherwise Specified
PIN
TEST CONDITIONS
MIN
TYP
MAX
UNITS
9.5
13
-
V
20
27
34
mA
7.8
8.4
8.9
V
POWER SUPPLY, VCC (PIN 7)
Supply Voltage
7
Supply Current
7
Zener Voltage
13
VCC = +13V
OUTPUT PULSE (PIN 6)
Maximum Pulse Width
6
Measured at 6V Threshold Level
5.5
6.5
7.5
µs
Minimum Pulse Width
6
Measured at 6V Threshold Level
2
3
4
µs
Output High Voltage
6
|6 = 0mA, V4 = 0V
11.1
12
12.6
V
Output Low Voltage
6
|6 = 50mA, V12 = 0V
0.6
1
1.3
V
Rise Time
6
Measured at 1.8V and 10V Threshold Levels
250
600
1250
ns
Fall Time
6
Measured at 1.8V and 10V Threshold Levels
50
200
350
ns
1
Adjust RT; Observe Pin 6 Min/Max
Frequency Range
5.9
6.8
7.5
V
Charge Current
14
Adjust RT, V1 = 7.5V; Set V14 = 0V, Then V14 = 2.5V
190
220
250
µA
Discharge Current
14
Adjust RT = 5.9V; Set V14 = 5.5V, Then 5V
95
110
125
µA
Slow Start Discharge Current
14
Maintain V14 = 5V, V10 = 5.5V
Set V10 = 5.5V, Measure I14 (Hi)
Set V10 = 4V, Measure I14 (Lo)
Limits = I14 (Hi) - I14 (Lo)
1.5
20
30
40
µA/V
Discharge Voltage
10
Pin 12 = 1kΩ to GND
1.7
2.4
3.2
V
Output Inhibit Voltage
7
Increase V7 Until V9 ≥ 2V
7.9
8.4
9.1
V
Overcurrent Trip Voltage
11
V12 = 5V; V10 = 0V; Increase V11 Until V9 ≤ 0.5V
1.1
1.25
1.4
V
ERROR VOLTAGE RANGE (PIN 1)
Error Voltage Reference
CHARGE CURRENT (PIN 14)
LOGIC TESTS
7-12
CA1523
Other Desirable Features
• Slow Start with Reset: Externally programmed against
internal 3V reference. Reset is initiated upon Inhibit ensuring soft start at power up and restart.
Other desirable features along with various circuit block
function explanations are listed below.
• The Oscillator is a sawtooth generator whose charge
(rise) cycle determines the output pulse width and discharge which is continuously variable from very low to
maximum of ICHARGE.
• Over Current Sense: Internal stable thresholds of 1.2V.
• Supply Voltage Monitors: Locks out the drive until
VSUPPLY has reached 8V-9V.
• Charge ICHARGE = IO -IDISCHARGE giving 2 to 1 pulse-width
control
• ON/OFF: Activates regulator independent of raw DC.
• Discharge IDISCHARGE = approximately 0 to 1/2 IO to
frequency control.
• Error Amplifier: Compares output against a stable 6.8V
internal reference and controls the discharge current sink
on the timing capacitor.
• Pulse Shaping: Applied to the oscillator output via RS
Flip-Flop with parallel inhibit controlled by slow-start overcurrent sense, supply voltage monitor and ON/OFF functions.
• Band-Gap: Reference voltage (internal) provides temperature compensated 1.2V and 6.8V references.
• Separate GND: The power GND is separated from circuit
ground for improved noise.
• Pulse Rise Time: Modified to meet RFI requirements by
external slow-down capacitor.
• ESD Protection: Pins are protected against ESD.
Block Diagram
CURRENT
SENSE
VCC
ZENER
2
7
13
CURRENT
SETUP
REF. VOLTAGE
SOURCES
IC
IC/2
VCC
5V
REF.
S1
1
ERROR
VOLTAGE
VL
2.5V
+
S
-
6.8V
REF.
ID
14
Q
4
RISE
TIME
F/F
+
ID ~ IC/2
FOR
VI << 6.8V
S2 OPEN
WHEN VIO > 6.8V
TIMING
CAP
Q HIGH CLOSES S1
+6.8V
REF.
VH
5V
R
6
-
PULSE
OUTPUT
-
3V
REF.
5
S
+
Q
OUTPUT
GND
F/F
VCC > 8.4V
11
R
3
(CONTROL
CIRCUIT
GND)
1.2V
REF.
3K
GND
OVER
CURRENT
+
Q LOW
S3
CLOSES S3
10
12
9
SLOW
START
ON/OFF
LOGIC
OUT
7-13
CA1523
VCC
+
0.0033µF
56K
2 CHARGE
CURRENT
13 ZENER
7
CURRENT
SET UP
REF. VOLT.
SOURCES
IC VCC
IC/2
VCC
S1
15K
ERROR
VOLTAGE
+6.8V
REF
1
RT
20K
TRIM
RES.
5V
REF
RISE/FALL
VL 2.5V
+
S
4
Q
47pF
F/F
TIMING
S2
ID IC/2
˜
FOR VI <<6.8V
S2 OPEN
WHEN V10 > 6.8V
14
240pF
Q HIGH
CLOSES S1
-
6.8V
REF
3V
REF.
NC
8
+
-
PULSE OUTPUT
6
R
5V
VH
1800pF
-
5
Q
S
+
(CONTROL
3K
CIRCUIT
GND)
1.2V
REF.
OUTPUT
GND
F/F
VCC
>6.4V
-
R
Q
+
3
Q LOW
S3
CLOSES
S3
11
VCC
12K
12 ON/OFF
ON
SLOW 10
START
9
220
VCC
220
LOGIC
OUT
+5V
OFF
30K
1K
VIO
FIGURE 1. TEST CIRCUIT FOR THE CA1523
7-14
OVER
CURRENT
V11
1K
CA1523
TYP. INPUT
5.6k
10W
NC
NC
NC
8
9
13
PRIMARY
SENSE
+
4.7µF
16k
68µF
TYPICAL
RECT.
OUTPUT
TRANSFORMER
0.85A
20k (TRIM RESISTOR)
13V
11V
11k
+
------------
FEEDBACK
30k
+150
SEC. “A”
+150V
RECTIFIED AC LINE
INPUT
V01 +130V
V04 -24V
SEC. “D”
V02 +16V
SEC. “C”
SEC. “D”
10
220
ON/OFF
BIAS
VOLTAGE
1
7
V03 +24V
47Ω
CA1523
1.5k
6
12
4
68
pF
14
3
2
11 5
RFP 7N40
10k
240
pF
68k
0.0033
µF
0.15
3W
22pF
OPTO-COUPLER
FIGURE 2. TYPICAL APPLICATION CIRCUIT FOR THE CA1523
VCC
7
+VCC
4K
15K
8K
8.3K
+7.5V
10K
+
+
2K
10K
2
5.0V
-
2K
ERROR
1
+7.5V
6.8V
BAND
GAP
REF
VOLTAGE
1.21V
2.5V +
1.8K
2K
30K
SLOW
START
10
1.5K
14
1.5K
+VCC
3K
12K
6K
9
LOGIC OUT
FIGURE 3. TIMING CIRCUIT FOR THE CA1523
7-15
VH
+
R
Q
S
Q
VL
CA1523
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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