TI BQ4011YMA-85N 128kx8 nonvolatile sram Datasheet

bq4013/Y
128Kx8 Nonvolatile SRAM
Features
General Description
➤ Data retention for at least 10
years without power
The CMOS bq4013/Y is a nonvolatile
1,048,576-bit static RAM organized as
131,072 words by 8 bits. The integral
control circuitry and lithium energy
source provide reliable nonvolatility
coupled with the unlimited write cycles of standard SRAM.
➤ Automatic write-protection during
power-up/power-down cycles
➤ Conventional SRAM operation,
including unlimited write cycles
➤ Internal isolation of battery before power application
➤ Industry standard 32-pin DIP
pinout
The control circuitry constantly
monitors the single 5V supply for an
out-of-tolerance condition. When
VCC falls out of tolerance, the SRAM
is unconditionally write-protected to
prevent inadvertent write operation.
The bq4013/Y uses an extremely
low standby current CMOS SRAM,
coupled with a small lithium coin
cell to provide nonvolatility without
long write-cycle times and the
write-cycle limitations associated
with EEPROM.
The bq4013/Y requires no external
circuitry and is socket-compatible
with industry-standard SRAMs and
most EPROMs and EEPROMs.
At this time the integral energy
source is switched on to sustain the
memory until after VCC returns valid.
Pin Connections
Pin Names
A0–A16
Address inputs
WE
Write enable input
DQ0–DQ7
Data input/output
NC
No connect
CE
Chip enable input
VCC
Supply voltage input
OE
Output enable input
VSS
Ground
Selection Guide
Part
Number
Maximum
Access
Time (ns)
Negative
Supply
Tolerance
Part
Number
bq4013YMA -70
Maximum
Access
Time (ns)
Negative
Supply
Tolerance
70
-10%
bq4013MA -85
85
-5%
bq4013YMA -85
85
-10%
bq4013MA-120
120
-5%
bq4013YMA-120
120
-10%
9/96 D
1
bq4013/Y
As VCC falls past VPFD and approaches 3V, the control
circuitry switches to the internal lithium backup supply,
which provides data retention until valid VCC is applied.
Functional Description
When power is valid, the bq4013/Y operates as a standard CMOS SRAM. During power-down and power-up
cycles, the bq4013/Y acts as a nonvolatile memory, automatically protecting and preserving the memory contents.
When VCC returns to a level above the internal backup
cell voltage, the supply is switched back to VCC. After
VCC ramps above the VPFD threshold, write-protection
continues for a time tCER (120ms maximum) to allow for
processor stabilization. Normal memory operation may
resume after this time.
Power-down/power-up control circuitry constantly monitors the VCC supply for a power-fail-detect threshold
VPFD. The bq4013 monitors for VPFD = 4.62V typical for
use in systems with 5% supply tolerance. The bq4013Y
monitors for VPFD = 4.37V typical for use in systems
with 10% supply tolerance.
The internal coin cell used by the bq4013/Y has an extremely long shelf life and provides data retention for
more than 10 years in the absence of system power.
As shipped from Unitrode, the integral lithium cell of
the MA-type module is electrically isolated from the
memory. (Self-discharge in this condition is approximately 0.5% per year.) Following the first application of
VCC, this isolation is broken, and the lithium backup cell
provides data retention on subsequent power-downs.
When VCC falls below the VPFD threshold, the SRAM automatically write-protects the data. All outputs become
high impedance, and all inputs are treated as “don’t
care.” If a valid access is in process at the time of
power-fail detection, the memory cycle continues to completion. If the memory cycle fails to terminate within
time tWPT, write-protection takes place.
Block Diagram
OE
WE
A0–A16
128K x 8
SRAM
Block
DQ0–DQ7
CECON
Power
CE Power-Fail VCC
Control
Lithium
Cell
BD-42
2
bq4013/Y
Truth Table
CE
WE
OE
I/O Operation
Power
Not selected
Mode
H
X
X
High Z
Standby
Output disable
L
H
H
High Z
Active
Read
L
H
L
DOUT
Active
Write
L
L
X
DIN
Active
Absolute Maximum Ratings
Value
Unit
VCC
Symbol
DC voltage applied on VCC relative to VSS
-0.3 to 7.0
V
VT
DC voltage applied on any pin excluding VCC
relative to VSS
-0.3 to 7.0
V
VT ≤ VCC + 0.3
TOPR
Operating temperature
0 to +70
°C
Commercial
-40 to +85
°C
Industrial “N”
-40 to +70
°C
Commercial
-40 to +85
°C
Industrial “N”
-10 to +70
°C
Commercial
-40 to +85
°C
Industrial “N”
+260
°C
For 10 seconds
TSTG
Parameter
Storage temperature
TBIAS
Temperature under bias
TSOLDER
Soldering temperature
Note:
Conditions
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation
should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability.
3
bq4013/Y
Recommended DC Operating Conditions (TA = TOPR)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
4.5
5.0
5.5
V
bq4013Y
4.75
5.0
5.5
V
bq4013
0
0
0
V
VCC
Supply voltage
VSS
Supply voltage
VIL
Input low voltage
-0.3
-
0.8
V
VIH
Input high voltage
2.2
-
VCC + 0.3
V
Note:
Typical values indicate operation at TA = 25°C.
DC Electrical Characteristics (TA = TOPR, VCCmin
Symbol
Notes
Parameter
≤ VCC ≤ VCCmax)
Minimum
Typical
Maximum
Unit
Conditions/Notes
ILI
Input leakage current
-
-
±1
µA
VIN = VSS to VCC
ILO
Output leakage current
-
-
±1
µA
CE = VIH or OE = VIH or
WE = VIL
VOH
Output high voltage
2.4
-
-
V
IOH = -1.0 mA
VOL
Output low voltage
-
-
0.4
V
ISB1
Standby supply current
-
4
7
mA
CE = VIH
ISB2
Standby supply current
-
2.5
4
mA
CE ≥ VCC - 0.2V,
0V ≤ VIN ≤ 0.2V,
or VIN ≥ VCC - 0.2V
ICC
Operating supply current
-
75
105
mA
Min. cycle, duty = 100%,
CE = VIL, II/O = 0mA
VPFD
4.55
4.62
4.75
V
bq4013
Power-fail-detect voltage
4.30
4.37
4.50
V
bq4013Y
-
3
-
V
VSO
Note:
Supply switch-over voltage
IOL = 2.1 mA
Typical values indicate operation at TA = 25°C, VCC = 5V.
Capacitance (TA = 25°C, F = 1MHz, VCC = 5.0V)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
CI/O
Input/output capacitance
-
-
10
pF
Output voltage = 0V
CIN
Input capacitance
-
-
10
pF
Input voltage = 0V
Note:
These parameters are sampled and not 100% tested.
4
Conditions
bq4013/Y
AC Test Conditions
Parameter
Test Conditions
Input pulse levels
0V to 3.0V
Input rise and fall times
5 ns
Input and output timing reference levels
1.5 V (unless otherwise specified)
Output load (including scope and jig)
See Figures 1 and 2
Figure 1. Output Load A
Read Cycle
Figure 2. Output Load B
(TA = TOPR, VCCmin ≤ VCC ≤ VCCmax)
-70/-70N
Symbol
Parameter
-85/-85N
-120
Min.
Min.
Min.
Max.
Min.
Max.
Unit
70
-
85
-
120
-
ns
Conditions
tRC
Read cycle time
tAA
Address access time
-
70
-
85
-
120
ns
Output load A
tACE
Chip enable access time
-
70
-
85
-
120
ns
Output load A
tOE
Output enable to output valid
-
35
-
45
-
60
ns
Output load A
tCLZ
Chip enable to output in low Z
5
-
5
-
5
-
ns
Output load B
tOLZ
Output enable to output in low Z
0
-
0
-
0
-
ns
Output load B
tCHZ
Chip disable to output in high Z
0
25
0
35
0
45
ns
Output load B
tOHZ
Output disable to output in high Z
0
25
0
25
0
35
ns
Output load B
tOH
Output hold from address change
10
-
10
-
10
-
ns
Output load A
5
bq4013/Y
Read Cycle No. 1 (Address Access) 1,2
Read Cycle No. 2 (CE Access) 1,3,4
Read Cycle No. 3 (OE Access) 1,5
Notes:
1. WE is held high for a read cycle.
2. Device is continuously selected: CE = OE = VIL.
3. Address is valid prior to or coincident with CE transition low.
4. OE = VIL.
5. Device is continuously selected: CE = VIL.
6
bq4013/Y
Write Cycle
(TA =TOPR , VCCmin ≤ VCC ≤ VCCmax)
-70/-70N
Symbol
Parameter
-85/-85N
-120
Min. Max. Min. Max. Min. Max.
Units
Conditions/Notes
tWC
Write cycle time
70
-
85
-
120
-
ns
tCW
Chip enable to end of
write
65
-
75
-
100
-
ns
(1)
tAW
Address valid to end of
write
65
-
75
-
100
-
ns
(1)
tAS
Address setup time
0
-
0
-
0
-
ns
Measured from address valid
to beginning of write. (2)
tWP
Write pulse width
55
-
65
-
85
-
ns
Measured from beginning of
write to end of write. (1)
tWR1
Write recovery time
(write cycle 1)
5
-
5
-
5
-
ns
Measured from WE going high
to end of write cycle. (3)
tWR2
Write recovery time
(write cycle 2)
15
-
15
-
15
-
ns
Measured from CE going high
to end of write cycle. (3)
tDW
Data valid to end of
write
30
-
35
-
45
-
ns
Measured to first low-to-high
transition of either CE or WE.
tDH1
Data hold time
(write cycle 1)
0
-
0
-
0
-
ns
Measured from WE going high
to end of write cycle. (4)
tDH2
Data hold time
(write cycle 2)
10
-
10
-
10
-
ns
Measured from CE going high
to end of write cycle. (4)
tWZ
Write enabled to output
in high Z
0
25
0
30
0
40
ns
I/O pins are in output state. (5)
tOW
Output active from end
of write
0
-
0
-
0
-
ns
I/O pins are in output state. (5)
Notes:
1. A write ends at the earlier transition of CE going high and WE going high.
2. A write occurs during the overlap of a low CE and a low WE. A write begins at the later transition
of CE going low and WE going low.
3. Either tWR1 or tWR2 must be met.
4. Either tDH1 or tDH2 must be met.
5. If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in
high-impedance state.
7
bq4013/Y
Write Cycle No. 1 (WE-Controlled) 1,2,3
Write Cycle No. 2 (CE-Controlled) 1,2,3,4,5
Notes:
1. CE or WE must be high during address transition.
2. Because I/O may be active (OE low) during this period, data input signals of opposite polarity to the
outputs must not be applied.
3. If OE is high, the I/O pins remain in a state of high impedance.
4. Either tWR1 or tWR2 must be met.
5. Either tDH1 or tDH2 must be met.
8
bq4013/Y
Power-Down/Power-Up Cycle (TA = TOPR)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
tPF
VCC slew, 4.75 to 4.25 V
300
-
-
µs
tFS
VCC slew, 4.25 to VSO
10
-
-
µs
tPU
VCC slew, VSO to VPFD (max.)
0
-
-
µs
Conditions
Time during which
SRAM is
write-protected after
VCC passes VPFD on
power-up.
tCER
Chip enable recovery time
40
80
120
ms
tDR
Data-retention time in
absence of VCC
10
-
-
years
TA = 25°C. (2)
tDR-N
Data-retention time in
absence of VCC
6
-
-
years
TA = 25°C (2); industrial
temperature range only
150
µs
tWPT
Notes:
Write-protect time
40
100
Delay after VCC slews
down past VPFD before
SRAM is
write-protected.
1. Typical values indicate operation at TA = 25°C, VCC = 5V.
2. Battery is disconnected from circuit until after VCC is applied for the first time. tDR is the
accumulated time in absence of power beginning when power is first applied to the device.
Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode
may affect data integrity.
Power-Down/Power-Up Timing
9
bq4013/Y
MA: 32-Pin A-Type Module
Dimension
Minimum
A
0.365
A1
0.015
B
0.017
C
0.008
D
1.670
E
0.710
e
0.590
G
0.090
L
0.120
S
0.075
All dimensions are in inches.
Maximum
0.375
0.023
0.013
1.700
0.740
0.630
0.110
0.150
0.110
MS: 34-Pin Leaded Chip carrier for LIFETIME LITHIUM Module
34-Pin LCR LIFETIME LITHIUM Module
Dimension
Minimum
A
0.920
B
0.980
C
D
0.052
E
0.045
F
0.015
G
0.020
H
J
0.053
All dimensions are in inches.
10
Maximum
0.930
0.995
0.080
0.060
0.055
0.025
0.030
0.090
0.073
1
Centerline of lead within ±0.005 of true position.
2
Leads coplanar within ±0.004 at seating plane.
3
Components and location may vary.
bq4013/Y
MS: LIFETIME LITHIUM Module Housing
LIFETIME LITHIUM Module Housing
Dimension
Minimum
A
0.845
B
0.955
C
0.210
D
0.065
E
0.065
All dimensions are in inches.
1
Maximum
0.855
0.965
0.220
0.075
0.075
Edges coplanar within ±0.025.
MS: LIFETIME LITHIUM Module with LCR attached
LIFETIME LITHIUM Module
Dimension
Minimum
A
0.955
B
0.980
C
0.240
D
0.052
E
0.045
F
0.015
All dimensions are in inches.
11
Maximum
0.965
0.995
0.250
0.060
0.055
0.025
1
Leads coplanar within ±0.004 at seating plane.
2
Components and location may vary.
bq4013/Y
Data Sheet Revision History
Change No.
Page No.
Description
1
2, 3, 4, 6, 8, 9
2
1, 4, 6, 9
Added 70ns speed grade for bq4013Y-70.
3
Notes:
Added industrial temperature range.
Removed industrial temperature range for bq4013YMA-120N
Change 1 = Sept. 1992 B changes from Sept. 1990 A.
Change 2 = Aug. 1993 C changes from Sept. 1991 B.
Change 3 = Sept. 1996 D changes from Aug. 1993 C.
Ordering Information
bq4013
xx Temperature:
blank = Commercial (0 to +70°C)
N = Industrial (-40 to +85°C)1
Speed Options:
70 = 70 ns
85 = 85 ns
120 = 120 ns
Package Option:
MA = A-type Module
Supply Tolerance:
no mark = 5% negative supply tolerance
Y = 10% negative supply tolerance
Device:
bq4013 128K x 8 NVSRAM
Notes:
1. Only 10% supply MA module (“Y-MA”) version is available in industrial
temperature range; contact factory for speed grade availability.
12
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
BQ4013MA-120
ACTIVE
DIP MOD
ULE
MA
0
1
TBD
Call TI
Call TI
BQ4013MA-85
ACTIVE
DIP MOD
ULE
MA
0
1
TBD
Call TI
Call TI
BQ4013YMA-120
ACTIVE
DIP MOD
ULE
MA
0
1
TBD
Call TI
Call TI
BQ4013YMA-70
ACTIVE
DIP MOD
ULE
MA
0
1
TBD
Call TI
Call TI
BQ4013YMA-70N
ACTIVE
DIP MOD
ULE
MA
0
1
TBD
Call TI
Call TI
BQ4013YMA-85
ACTIVE
DIP MOD
ULE
MA
0
1
TBD
Call TI
Call TI
BQ4013YMA-85N
ACTIVE
DIP MOD
ULE
MA
0
1
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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