TECHNICAL NOTE
HIGH GRADE Specification HIGH RELIABILITY series
I2C BUS Serial EEPROMs
Supply voltage 1.8V~5.5V
Operating temperature –40°C~+85°C type
BR24L01A-W, BR24L02-W, BR24L04-W, BR24L08-W, BR24L16-W, BR24L32-W, BR24L64-W
Description
BR24L-W series is a serial EEPROM of I2C BUS interface method.
Features
y
y
y
y
y
y
y
y
y
y
y
y
y
Completely conforming to the world standard I2C BUS. All controls available by 2 ports of serial clock (SCL) and serial data (SDA)
Other devices than EEPROM can be connected to the same port, saving microcontroller port
1.8 ~ 5.5V*1 single power source action most suitable for battery use
Page write mode useful for initial value write at factory shipment
Highly reliable connection by Au pad and Au wire
Auto erase and auto end function at data rewrite
Low current consumption
At write action (5V)
: 1.2mA (Typ.)*2
At read action (5V)
: 0.2mA (Typ.)
At standby action (5V) : 0.1µA (Typ.)
Write mistake prevention function
Write (write protect) function added
Write mistake prevention function at low voltage
SOP8/SOP-J8/SSOP-B8/TSSOP-B8/MSOP8/TSSOP-B8J compact package *3 *4
Data rewrite up to 1,000,000 times
Data kept for 40 years
Page write
Noise filter built in SCL / SDA terminal
Number of
Shipment data all address FFh
*1
BR24L16-W, BR24L32-W : 1.7~5.5V
*2
BR24L32-W, BR24L64-W: 1.5mA
*3
BR24L32-W: SOP8/SOP-J8/
SSOP-B8/TSSOP-B8
*4
BR24L64-W: SOP8/SOP-J8
pages
Product
number
16 Byte
8 Byte
BR24L01A-W
BR24L02-W
BR24L04-W
BR24L08-W
BR24L16-W
32 Byte
BR24L32-W
BR24L64-W
BR24L series
Capacity
Bit format
Type
Power source
voltage
1Kbit
128 × 8
BR24L01A-W
1.8 ~ 5.5V
2Kbit
256 × 8
BR24L02-W
1.8 ~ 5.5V
4Kbit
512 × 8
BR24L04-W
1.8 ~ 5.5V
8Kbit
1K × 8
BR24L08-W
1.8 ~ 5.5V
16Kbit
2K × 8
BR24L16-W
1.7 ~ 5.5V
32Kbit
4K × 8
BR24L32-W
1.7 ~ 5.5V
64Kbit
8K × 8
BR24L64-W
1.8 ~ 5.5V
SOP8
SOP-J8
SSOP-B8
TSSOP-B8
MSOP8
TSSOP-B8J
Ver.B Oct.2005
Recommended action conditions
Absolute maximum ratings (Ta=25˚C)
Parameter
Symbol
Impressed voltage
VCC
Permissible
dissipation
Unit
Limits
-0.3 ~ +6.5
Pd
Parameter Symbol
Power source
voltage
V
450 (SOP8)
*1
450 (SOP-J8)
*2
300 (SSOP-B8)
*3
330 (TSSOP-B8)
*4
310 (MSOP8)
*5
Input voltage
VCC
Limits
Unit
*1
1.8 ~ 5.5
VIN
Memory cell characteristics (Ta = 25˚C, Vcc = 1.8 ~ 5.5V)*1
0 ~ VCC
Limits
Parameter
V
*1 BR24L16/L32-W : 1.7~5.5V
Unit
Min.
Typ.
Max.
Number of data rewrite times
*2
1,000,000
-
-
Times
Data hold years
*2
40
-
-
Years
V
Shipment data all address FFh
mW
*1 BR24L16/L32-W : 1.7~5.5V
*2 Not 100% TESTED
310 (TSSOP-B8J) *6
Storage
temperature range
Action
temperature range
Tstg
-65 ~ +125
˚C
Topr
-40 ~ +85
˚C
Terminal voltage
-
V
-0.3 ~ VCC+1.0
Action timing characteristics
* When using at Ta = 25°C or higher, 4.5mW (*1, *2), 3.0mW (*3), 3.3mW (*4)
3.1mW (*5,*6) to be reduced per 1°C
*1
(Unless otherwise specified, Ta = -40 ~ +85°C, Vcc = 1.8 ~ 5.5V)
Parameter
Symbol
Min.
Limits
Typ.
Max.
*1
(Unless otherwise specified, Ta=-40 ~ +85˚C, Vcc=1.8 ~ 5.5V)
Electrical characteristics
Unit
Conditions
Symbol
Parameter
FAST-MODE
2.5V≤Vcc≤5.5V
STANDARD-MODE
1.8V≤Vcc≤5.5V
Min.
Typ.
Max.
Unit
Min.
Typ.
Max.
SCL frequency
fSCL
-
-
400
-
-
100
kHz
Data clock "HIGH" time
tHIGH
0.6
-
-
4.0
-
-
µs
tLOW
1.2
-
-
4.7
-
-
µs
"HIGH" input voltage 1
VIH1
0.7VCC
-
VCC+1.0 *2
V
2.5V≤VCC≤5.5V
Data clock "LOW" time
"LOW" input voltage 1
VIL1
-0.3 *2
-
0.3VCC
V
2.5V≤VCC≤5.5V
SDA,SCL rise time
*2
tR
-
-
0.3
-
-
1.0
µs
"HIGH" input voltage 2
VIH2
0.8VCC
-
VCC+1.0 *2
V
1.8V≤VCC<2.5V
SDA,SCL fall time
*2
tF
-
-
0.3
-
-
0.3
µs
"LOW" input voltage 2
VIL2
-0.3 *2
-
0.2VCC
V
1.8V≤VCC<2.5V
Start condition hold time
tHD:STA
0.6
-
-
4.0
-
-
µs
"HIGH" input voltage 3 *3
VIH3
0.8VCC
-
VCC+1.0
V
1.7V≤VCC<1.8V
Start condition setup time
tSU:STA
0.6
-
-
4.7
-
-
µs
"HIGH" input voltage 3 *4
VIH3
0.9VCC
-
VCC+1.0
V
1.7V≤VCC<1.8V
Input data hold time
tHD:DAT
0
-
-
0
-
-
ns
"LOW" input voltage 3 *2
VIL3
-0.3
-
0.1VCC
V
1.7V≤VCC<1.8V
Input data setup time
tSU:DAT
100
-
-
250
-
-
ns
"LOW" output voltage 1
VOL1
-
-
0.4
V
IOL=3.0mA, 2.5V≤VCC≤5.5V, (SDA)
Output data delay time
tPD
0.1
-
0.9
0.2
-
3.5
µs
"LOW" output voltage 2
VOL2
-
-
0.2
V
IOL=0.7mA, 1.7V≤VCC<2.5V, (SDA)
Output data hold time
µs
Input leak current
ILI
-1
-
1
µA
VIN=0V ~ VCC
Stop condition setup time
Output leak current
ILO
-1
-
1
µA
VOUT=0V ~ VCC (SDA)
ICC1
-
-
mA
Current consumption at
action
ICC2
Standby current
-
-
ISB
-
Radiation resistance design is not made.
*1
*2
*3
2.0 *5
3.0 *6
0.5
2.0
mA
µA
tDH
0.1
-
-
0.2
-
-
tSU:STO
0.6
-
-
4.7
-
-
µs
Bus release time before transfer start
tBUF
1.2
-
-
4.7
-
-
µs
VCC=5.5V, fSCL=400kHz, tWR=5ms,
Byte write, page write
Internal write cycle time
tWR
-
-
5
-
-
5
ms
tl
-
-
0.1
-
-
0.1
µs
VCC=5.5V, fSCL=400kHz
Random read, current read, sequential
read
WP hold time
tHD:WP
0
-
-
0
-
-
ns
WP setup time
tSU:WP
0.1
-
-
0.1
-
-
µs
VCC=5.5V, SDA·SCL=VCC,
A0, A1, A2=GND, WP=GND
WP valid time
tHIGH:WP
1.0
-
-
1.0
-
-
µs
BR24L16/L32-W : 1.7~5.5V
BR24L16/L32-W
BR24L16-W
*4
*5
*6
Noise removal valid period (SDA,SCL terminal)
*1 BR24L16/L32-W : 1.7~5.5V
*2 Not 100% tested.
BR24L32-W
BR24L01A/L02/L04/L08/L16-W
BR24L32/L64-W
FAST-MODE and STANDARD-MODE
FAST-MODE and STANDARD-MODE are of same actions, and mode is not changed. They are distinguished by action speeds. 100kHz
action is called STANDARD-MODE, and 400kHz action is called FAST-MODE. This action frequency is the maximum action frequency,
so 100kHz clock may be used in FAST-MODE. When power source voltage goes down, action at high speed is not carried out,
therefore, at Vcc = 2.5V ~ 5.5V, 400kHz, namely, action is made in FASTMODE. (Action is made also in STANDARD-MODE) Vcc =
1.8V ~ 2.5V is only action in 100kHz STANDARD-MODE.
Sync data input / output timing
tR
tF
tHIGH
SCL
SCL
tHD : STA
tSU : DAT
tLOW
DATA (1)
tHD : DAT
SDA
(Input)
SDA
D1
DATA (n)
D0
ACK
ACK
tWR
tBUF
tPD
tDH
Stop condition
SDA
(Output)
WP
Input read at the rise edge of SCL
Data output in sync with the fall of SCL
tSU : WP
tHD : WP
Fig.1-(d) WP timing at write execution
Fig.1-(a) Sync data input / output timing
SCL
SCL
tSU : STA
tHD : STA
tSU : STO
DATA (n)
DATA (1)
SDA
SDA
START BIT
STOP BIT
D1
D0
ACK
ACK
tHIGH : WP
tWR
Fig.1-(b) Start - stop bit timing
WP
At write execution, in the area from the DO taken clock rise of the first DATA (1), to tWR, set WP =
"LOW".
By setting WP "HIGH" in the area, write can be cancelled.
When it is set WP = "HIGH" during tWR, write is forcibly ended, and data of address under access is not
guaranteed, therefore write it once again.
SCL
SDA
D0
Write data
(n-th address)
ACK
Fig.1-(e) WP timing at write cancel
tWR
Stop condition
Fig.1-(c) Write cycle timing
Start condition
2/16
Block diagram
*2
1
A0
1Kbit ~ 64Kbit EEPROM array
*1
2
A1
Address
decoder
7bit 11bit
8bit 12bit
9bit 13bit
10bit
*2
Data
register
Slave - word
address register
*1
START
3
A2
VCC
7
WP
6
SCL
5
SDA
8bit
7bit 11bit
8bit 12bit
9bit 13bit
10bit
*2
8
STOP
Control circuit
ACK
GND
High voltage
generating circuit
4
*1
Pin assignment and description
1
A0
8
BR24L01A-W
BR24L02-W
BR24L04-W
BR24L08-W
BR24L16-W
BR24L32-W
BR24L64-W
2
A1
3
A2
GND
7
VCC
WP
6 SCL
4
5 SDA
Power source
voltage detection
: BR24L04-W
*2 A0=N.C.
: BR24L08-W
A0, A1=N.C.
A0, A1=N.C. A2=Don't Use : BR24L16-W
7bit : BR24L01A-W
8bit : BR24L02-W
9bit : BR24L04-W
10bit : BR24L08-W
11bit : BR24L16-W
12bit : BR24L32-W
13bit : BR24L64-W
Fig.2 Block diagram
Function
Terminal
name
Input /
output
VCC
-
Connect the power source.
GND
-
Reference voltage of all input / output, 0V
A0
Input
A1
Input
BR24L01A-W
BR24L02-W
Slave address
setting
Slave address
setting
Slave address
setting
BR24L04-W
Slave address
setting
Slave address
setting
Slave address
setting
BR24L08-W
BR24L16-W
Not connected
Not connected
Not connected
Slave address
setting
Slave address
setting
Not connected
Not connected
Slave address
setting
Not used
A2
Input
SCL
Input
Serial clock input
SDA
Input/
output
Slave and word address,
Serial data input serial data output
WP
Input
Write protect terminal
BR24L32-W
BR24L64-W
Slave address
setting
Slave address
setting
Slave address
setting
Slave address
setting
Slave address
setting
Slave address
setting
6
5
5
SPEC
3
2
Ta=85˚C
Ta=-40˚C
Ta=25˚C
1
4
Ta=85˚C
Ta=-40˚C
Ta=25˚C
3
2
1
SPEC
*1
0
0
1
2
3
4
5
6
SUPPLY VOLTAGE : VCC (V)
Fig.3 H input voltage VIH
(A0,A1,A2,SCL,SDA,WP)
*1
INPUT LEAK CURRENT : ILI (µA)
L OUTPUT VOLTAGE : VOL (V)
1
0.8
0.6
SPEC
0.4
Ta=25˚C
Ta=85˚C
0.2
0
0
BR24L16-W
No A0, A1, A2
BR24L08-W
No A0, A1
BR24L04-W
No A0
0
0
1
2
3
4
5
2
3
4
5
6
L OUTPUT CURRENT : IOL (mA)
Fig.6 L output voltage VOL-IOL(VCC=2.5V)
0.6
Ta=25˚C
0.4
Ta=85˚C
SPEC
0.2
Ta=-40˚C
6
SUPPLY VOLTAGE : VCC (V)
Fig.4 L input voltage VIL
(A0,A1,A2,SCL,SDA,WP)
*1
2
3
4
5
6
Fig.5 L output voltage VOL-IOL(VCC=1.8V)
1.2
1.2
SPEC
1
0.8
0.6
0.4
Ta=85˚C
Ta=25˚C
Ta=-40˚C
0.2
0
0
1
L OUTPUT CURRENT : IOL (mA)
Ta=-40˚C
1
0.8
0
0
OUTPUT LEAK CURRENT : ILO (µA)
4
1
L OUTPUT VOLTAGE : VOL (V)
6
L INPUT VOLTAGE : VIL (V)
H INPUT VOLTAGE : VIH (V)
Characteristic data (The following values are Typ. ones.)
1
2
3
4
5
SUPPLY VOLTAGE : VCC (V)
Fig.7 Input leak current ILI
(A0,A1,A2,SCL,WP)
*1
3/16
6
SPEC
1
0.8
0.6
0.4
Ta=85˚C
Ta=25˚C
Ta=-40˚C
0.2
0
0
1
2
3
4
5
6
SUPPLY VOLTAGE : VCC (V)
Fig.8 Output leak current ILO (SDA)
Characteristic data
3.5
SPEC
2
fSCL=400kHz
DATA=AAh
1.5
Ta=25˚C
1
Ta=85˚C
Ta=-40˚C
0.5
0
0
1
2
3
4
5
0.6
[BR24L32/64 series]
SPEC
3
CURRENT CONSUMPTION
AT READING : ICC2 (mA)
[BR24L01A/02/04/08/16 series]
CURRENT CONSUMPTION
AT WRITING : ICC1 (mA)
CURRENT CONSUMPTION
AT WRITING : ICC1 (mA)
2.5
fSCL=400kHz
DATA=AAh
2.5
2
Ta=25˚C
1.5
Ta=85˚C
1
Ta=-40˚C
0.5
0
0
6
2
1
3
4
5
fSCL=400kHz
DATA=AAh
0.4
0.3
Ta=25˚C
Ta=85˚C
0.2
0.1
Ta=-40˚C
0
0
6
2
1
3
4
5
6
SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V)
Fig.9 Consumption current at write action ICC1
(fSCL=400kHz)
Fig.10 Consumption current at write action ICC1
(fSCL=400kHz)
Fig.11 Consumption current at read action ICC2
(fSCL=400kHz)
3.5
SPEC
2
fSCL=100kHz
DATA=AAh
1.5
Ta=25˚C
1
Ta=85˚C
Ta=-40˚C
0.5
0
0
1
2
3
4
5
0.6
[BR24L32/64 series]
SPEC
3
CURRENT CONSUMPTION
AT READING : ICC2 (mA)
[BR24L01A/02/04/08/16 series]
CURRENT CONSUMPTION
AT WRITING : ICC1 (mA)
CURRENT CONSUMPTION
AT WRITING : ICC1 (mA)
2.5
fSCL=100kHz
DATA=AAh
2.5
2
Ta=25˚C
1.5
Ta=85˚C
1
Ta=-40˚C
0.5
0
0
6
1
2
3
4
5
SUPPLY VOLTAGE : VCC (V)
Fig.12 Consumption current at write action ICC1
(fSCL=100kHz)
Fig.13 Consumption current at write action ICC1
(fSCL=100kHz)
1
0.5
Ta=25˚C
Ta=-40˚C
Ta=85˚C
0
0
1
2
3
4
5
0.1
Ta=-40˚C
2
1
3
4
5
6
5
1000
SPEC1
100
SPEC2
10
SPEC1:FAST-MODE
SPEC2:STANDARD-MODE
1
0
6
Ta=25˚C
Ta=85˚C
0.2
Fig.14 Consumption current at read action ICC2
(fSCL=100kHz)
DATA CLK H TIME : tHIGH (µs)
SCL FREQUENCY : fSCL (kHz)
1.5
0.3
SUPPLY VOLTAGE : VCC (V)
Ta=85˚C
Ta=25˚C
Ta=-40˚C
SPEC
2
fSCL=100kHz
DATA=AAh
0.4
0
0
10000
2.5
SPEC
0.5
6
SUPPLY VOLTAGE : VCC (V)
STANDBY CURRENT : ISB (µA)
SPEC
0.5
1
2
3
4
5
3
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
2
1
6
0
0
SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V)
SPEC2
4
Ta=-40˚C
Ta=25˚C
Ta=85˚C
1
SPEC1
2
3
4
5
6
SUPPLY VOLTAGE : VCC (V)
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
2
SPEC1
Ta=85˚C
Ta=25˚C
Ta=-40˚C
1
0
0
1
2
3
4
5
6
4
3
1
0
0
INPUT DATA HOLD TIME : tHD:DAT (ns)
INPUT DATA HOLD TIME : tHD:DAT (ns)
Ta=-40˚C
Ta=25˚C
Ta=85˚C
1
SPEC1
2
3
4
5
6
SPEC1,2
0
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
-50
-100
Ta=85˚C
Ta=25˚C
Ta=-40˚C
-150
1
2
3
4
5
6
SUPPLY VOLTAGE : VCC (V)
Fig.21 Input data hold time tHD:DAT(HIGH)
6
SPEC2
5
4
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
3
2
1
0
0
Ta=-40˚C
Ta=25˚C
Ta=85˚C
1
SPEC1
2
3
4
5
6
SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V)
Fig.19 Start condition hold time tHD:STA
Fig.20 Start condition setup time tSU:STA
50
50
-200
0
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
2
SUPPLY VOLTAGE : VCC (V)
Fig.18 Data clock "L" time tLOW
SPEC2
START CONDITION SET UP TIME : tSU:STA (µs)
4
5
INPUT DATA SET UP TIME : tSU:DAT (ns)
DATA CLK L TIME : tLOW (µs)
SPEC2
START CONDITION HOLD TIME : tHD:STA (µs)
5
3
Fig.17 Data clock "H" time tHIGH
Fig.16 SCL frequency fSCL
Fig.15 Standby current ISB
SPEC1,2
0
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
-50
Ta=85˚C
-100
-150
Ta=25˚C
-200
0
1
Ta=-40˚C
2
3
4
5
6
SUPPLY VOLTAGE : VCC (V)
Fig.22 Input data hold time tHD:DAT(LOW)
4/16
300
200
SPEC2
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
SPEC1
100
0
Ta=85˚C
Ta=25˚C
Ta=-40˚C
-100
-200
0
1
2
3
4
5
6
SUPPLY VOLTAGE : VCC (V)
Fig.23 Input data setup time tSU:DAT(HIGH)
300
SPEC1
100
Ta=85˚C
0
-200
0
1
Ta=-40˚C
2
3
4
5
SPEC2
3
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
2
Ta=85˚C
Ta=25˚C
Ta=-40˚C
1
SPEC2
SPEC1
0
0
6
1
SPEC2
4
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
2
SPEC1
Ta=-40˚C
Ta=25˚C
Ta=85˚C
1
2
3
4
5
6
SUPPLY VOLTAGE : VCC (V)
NOISE REDUCTION
EFFECTIVE TIME : tI (SDA H) (µs)
NOISE REDUCTION
EFFECTIVE TIME : tI (SCL L) (µs)
0.5
0.4
0.3
Ta=-40˚C
Ta=25˚C
Ta=85˚C
0.1
SPEC1,2
1
2
3
4
5
4
3
6
2
1
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
2
1
3
4
5
-0.2
Ta=85˚C
-0.4
Ta=-40˚C
Ta=25˚C
1
2
3
4
5
SUPPLY VOLTAGE : VCC (V)
Fig.33 WP setup time tSU:WP
6
1
4
5
6
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
Ta=-40˚C
0.4
Ta=25˚C
0.3
Ta=85˚C
0.2
0.1
SPEC1,2
1
2
3
4
5
6
0.6
0.5
0.4
Ta=-40˚C
Ta=25˚C
Ta=85˚C
0.2
0.1
SPEC1,2
2
1
1
3
4
5
6
SPEC1,2
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
0.6
0.4
Ta=-40˚C
Ta=25˚C
Ta=85˚C
0.2
1
2
3
4
5
SUPPLY VOLTAGE : VCC (V)
Fig.34 WP valid time tHIGH:WP
5/16
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
0.5
0.4
0.3
Ta=-40˚C
Ta=25˚C
Ta=85˚C
0.2
0.1
SPEC1,2
0
0
1
2
3
4
5
6
SUPPLY VOLTAGE : VCC (V)
0.8
0
0
3
Fig.29 Noise removal valid time tI (SCL H)
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
0.3
2
SUPPLY VOLTAGE : VCC (V)
Fig.31 Noise removal valid time tI (SDA H)
WP EFFECTIVE TIME : tHIGH:WP (µs)
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
SPEC1
0.5
0
0
SUPPLY VOLTAGE : VCC (V)
1.2
SPEC1,2
SPEC2
0
0
Fig.26 "L" output data delay time tPD1
6
SUPPLY VOLTAGE : VCC (V)
0.2
WP SET UP TIME : tSU:WP (µs)
Ta=25˚C
Ta=85˚C
0
0
Fig.30 Noise removal valid time tI (SCL L)
-0.6
0
Ta=-40˚C
0
0
SPEC1
0.6
5
SUPPLY VOLTAGE : VCC (V)
0
1
Ta=85˚C
Ta=25˚C
Ta=-40˚C
SUPPLY VOLTAGE : VCC (V)
0.6
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
2
6
Fig.28 Internal write cycle time tWR
0.6
0
0
5
SPEC1,2
Fig.27 Bus release time before transfer start tBUF
0.2
4
6
INTERNAL WRITING CYCLE TIME : tWR (ms)
BUS OPEN TIME
BEFORE TRANSMISSION : tBUF (µs)
5
0
0
3
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
Fig.25 "L" output data delay time tPD0
Fig.24 Input data setup time tSU:DAT(LOW)
1
2
SPEC2
3
SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V)
3
SPEC1
NOISE REDUCTION
EFFECTIVE TIME : tI (SCL H) (µs)
-100
Ta=25˚C
OUTPUT DATA DELAY TIME : tPD (µs)
SPEC2
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
NOISE REDUCTION
EFFECTIVE TIME : tI (SDA L) (µs)
200
4
4
OUTPUT DATA DELAY TIME : tPD (µs)
INPUT DATA SET UP TIME : tSU:DAT (ns)
Characteristic data
6
Fig.32 Noise removal valid time tI (SDA L)
I2C BUS communication
I2C BUS data communication
I2C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long, and
acknowledge is always required after each byte.
I2C BUS carries out data transmission with plural devices connected by 2 communication lines of serial data (SDA) and serial
clock (SCL).
Among devices, there are "master" that generates clock and control communication start and end, and "slave" that is controlled
by addresses peculiar to devices.
EEPROM becomes "slave". And the device that outputs data to bus during data communication is called "transmitter", and the
device that receives data is called "receiver".
SDA
SCL
1-7
8
9
R/W
ACK
1-7
8
9
1-7
8
9
S
P
START ADDRESS
condition
DATA
ACK
DATA
ACK
STOP
condition
Fig.35 Data transfer timing
Start condition (start bit recognition)
y Before executing each command, start condition (start bit) where SDA goes from "HIGH" down to "LOW" when SCL is "HIGH" is
necessary.
y This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this condition is satisfied, any
command is executed.
Stop condition (stop bit recognition)
y Each command can be ended by SDA rising from "LOW" to "HIGH" when stop condition (stop bit), namely, SCL is "HIGH"
Acknowledge (ACK) signal
y This acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In master and
slave, the device (µ-COM at slave address input of write command, read command, and this IC at data output of read command)
at the transmitter (sending) side releases the bus after output of 8bit data.
y The device (this IC at slave address input of write command, read command, and µ-COM at data output of read command) at the
receiver (receiving) side sets SDA "LOW" during 9 clock cycles, and outputs acknowledge signal (ACK signal) showing that it has
received the 8bit data.
y This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) "LOW".
y Each write action outputs acknowledge signal (ACK signal) "LOW", at receiving 8bit data (word address and write data).
y Each read action outputs 8bit data (read data), and detects acknowledge signal (ACK signal) "LOW".
y When acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (µ-COM) side, this IC continues
data output. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, and recognizes stop condition
(stop bit), and ends read action.
And this IC gets in standby status.
Device addressing
y Output slave address after start condition from master.
y The significant 4 bits of slave address are used for recognizing a device type.
The device code of this IC is fixed to "1010".
y Next slave addresses (A2 A1 A0 --- device address) are for selecting devices, and plural ones can be used on a same bus according
to the number of device addresses.
y The most insignificant bit (R/W --- READ/WRITE) of slave address is used for designating write or read action, and is as shown
below.
Setting R/W to 0 --- write (setting 0 to word address setting of random read)
Setting R/W to 1 --- read
Type
BR24L01A-W
BR24L02-W
BR24L04-W
BR24L08-W
BR24L16-W
BR24L32-W
BR24L64-W
Maximum number
of connected buses
Slave address
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
A2
A2
A2
A2
P2
A2
A2
A1
A1
A1
P1
P1
A1
A1
A0
A0
PS
P0
P0
A0
A0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PS, P0 ~ P2 are page select bits.
Note) Up to 4 units of BR24L04-W, up to 2 units of BR24L08-W, and one unit of
BR24L16-W can be connected.
Device address is set by "H" and "L" of each pin of A0, A1, and A2.
6/16
8
8
4
2
1
8
8
A0
1
A1
2
A2
3
GND
4
BR24L01A-W
BR24L02-W
BR24L04-W
BR24L08-W
BR24L16-W
BR24L32-W
BR24L64-W
8
VCC
7
WP
6 SCL
5 SDA
Command
Write cycle
y Arbitrary data is written to EEPROM. When to write only 1 byte, byte write is normally used, and when to write continuous
data of 2 bytes or more, simultaneous write is possible by page write cycle. The maximum number of write bytes is specified
per device of each capacity.
Up to 32 arbitrary bytes can be written. (In the case of BR24L32 / L64-W)
S
T
A
R
T
SDA
LINE
W
R
I
T
E
SLAVE
ADDRESS
WORD
ADDRESS
WA
7
1 0 1 0 A2 A1 A0
R A
/ C
W K
Note)
S
T
O
P
DATA
WA
0
D7
D0
*1
*1 As for WA7, BR24L01A-W becomes Don't Care.
A
C
K
A
C
K
Fig.36 Byte write cycle (BR24L01A/02/04/08/16-W)
S
T
A
R
T
SDA
LINE
SLAVE
ADDRESS
W
R
I
T
E
1st WORD
ADDRESS
* * *
1 0 1 0 A2 A1 A0
Note)
2nd WORD
ADDRESS
WA WA
12 11
R A
/ C
W K
WA
0
A
C
K
*1
S
T
O
P
DATA
D7
*1 As for WA12, BR24L32-W becomes Don't care.
D0
A
C
K
A
C
K
Fig.37 Byte write cycle (BR24L32/64-W)
S
T
A
R
T
SDA
LINE
SLAVE
ADDRESS
W
R
I
T
E
WORD
ADDRESS (n)
Note)
WA
0
WA
7
1 0 1 0 A2 A1 A0
DATA (n)
R A
/ C *1
W K
D7
DATA (n+15)
D0
A
C
K
S
T
O
P
*2
D0
A
C
K
A
C
K
*1
As for WA7, BR24L01A-W becomes Don't care.
*2
As for BR24L01A/L02-W becomes (n+7).
*1
As for WA12, BR24L32-W becomes Don't care.
Fig.38 Page write cycle (BR24L01A/02/04/08/16-W)
S
T
A
R
T
SDA
LINE
SLAVE
ADDRESS
W
R
I
T
E
* * *
1 0 1 0 A2 A1 A0
Note)
1st WORD
ADDRESS (n)
R A
/ C
W K
*1
2nd WORD
ADDRESS (n)
WA WA
12 11
DATA (n)
WA
0
A
C
K
D7
A
C
K
S
T
O
P
DATA (n+31)
D0
D0
A
C
K
A
C
K
Fig.39 Page write cycle (BR24L32/64-W)
Data is written to the address designated by word address (n-th address).
By issuing stop bit after 8bit data input, write to memory cell inside starts.
When internal write is started, command is not accepted for tWR (5ms at maximum).
By page write cycle, the following can be written in bulk: Up to 8 bytes (BR24L01A-W, BR24L02-W)
Up to 16 bytes (BR24L04-W, BR24L08-W, BR24L16-W)
Up to 32 bytes (BR 24L32-W, BR24L64-W)
And when data of the maximum bytes or higher is sent, data from the first byte is overwritten.
(Refer to "Internal address increment" of "Notes on page write cycle" in P8/16.)
y As for page write cycle of BR24L01A-W and BR24L02-W, after the significant 5 bits (4 significant bits in BR24L01-W) of word
address are designated arbitrarily, and as for page write command of BR24L04-W, BR24L08-W, and BR24L16-W, after page
select bit (PS) of slave address is designated arbitrarily, by continuing data input of 2 bytes or more, the address of
insignificant 4 bits (insignificant 3 bits in BR24L01A-W, and BR24L02-W) is incremented internally, and data up to 16 bytes (up
to 8 bytes in BR24L01A-W and BR24L02-W) can be written.
y As for page write cycle of BR24L32-W and BR24L64-W, after the significant 7 bits (in the case of BR24L32-W) of word
address, or the significant 8 bits (in the case of BR24L64-W) of word address are designated arbitrarily, by continuing data
input of 2 bytes or more, the address of insignificant 5 bits is incremented internally, and data up to 32 bytes can be written.
y
y
y
y
Note)
*1*2*3
1 0 1 0 A2A1A0
Fig.40 Difference of slave address of each type
7/16
*1 In BR24L16-W, A2 becomes P2.
*2 In BR24L08-W, BR24L16-W, A1 becomes P1.
*3 In BR24L04-W, A0 becomes PS, and in BR24L08-W
and BR24L16-W, A0 becomes P0.
Notes on write cycle continuous input
S
T
A
R
T
SDA
LINE
SLAVE
ADDRESS
At STOP (stop bit),
write starts.
W
R
I
T
E
WORD
ADDRESS (n)
*1
Note)
WA
0
WA
7
1 0 1 0 A2 A1 A0
R A
/ C
W K
D7
A
C
K
S
T
O
P
DATA (n+7) *2
*3
DATA (n)
D0
D0
A
C
K
1 0 1 0
Next command
A
C
K
tWR (maximum : 5ms)
Command is not accepted for this period.
*1 BR24L01A-W becomes Don't Care.
*2 BR24L04W-W, BR24L08-W, and BR24L16-W become (n + 15).
*3 BR24L32-W and BR24L64-W become (n + 31).
Fig.41 Page write cycle
Note)
Note)
*1 In BR24L16-W, A2 becomes P2.
*2 In BR24L08-W, BR24L16-W, A1 becomes P1.
*3 In BR24L04-W, A0 becomes PS, and in BR24L08-W
and BR24L16-W, A0 becomes P0.
3
1 * 1 * 2 * ＊3
1
0
11 0 01 0A2A2A1A0
A1 A0
Fig.42 Difference of each type of slave address
Fig.42 スレイブアドレスの各機種の違い
Notes on page write cycle
List of numbers of page write
Number of
pages
Product
number
8 Byte
BR24L01A-W
BR24L02-W
16 Byte
BR24L04-W
BR24L08-W
BR24L16-W
32 Byte
Internal address increment
Page write mode (in the case of BR24L02-W)
BR24L32-W
WA7
WA4
WA3
WA2
BR24L64-W
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
1
0
0
0
0
1
1
1
0
0
0
0
0
0
The above numbers are maximum bytes for respective types. Any bytes
below these can be written.
In the case of BR24L02-W, 1 page = 8 bytes, but the page write cycle write time is 5ms at
maximum for 8byte bulk write.
It does not stand 5ms at maximum x 8 bytes = 40ms (Max.).
06h
WA1 WA0
Increment
Significant bit is fixed.
No digit up
For example, when it is started from address 06h,
therefore, increment is made as below,
06h → 07h → 00h → 01h ---, which please note.
* 06h --- 06 in hexadecimal, therefore, 00000110 becomes a binary
number.
Write protect terminal (WP)
y Write protect function (WP)
When WP terminal is set Vcc (H level), data rewrite of all addresses is prohibited. When it is set GND (L level), data rewrite of all
addresses is enabled. Be sure to connect this terminal to Vcc or GND, or control it to H level or L level. Do not use it open.
At extremely low voltage at power ON/OFF, by setting the WP terminal "H", mistake write can be prevented.
During tWR, set the WP terminal always to "L". If it is set "H", write is forcibly terminated.
8/16
Command
Read cycle
Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle.
Random read cycle is a command to read data by designating address, and is used generally.
Current read cycle is a command to read data of internal address register without designating address, and is used when to
verify just after write cycle. In both the read cycles, sequential read cycle is available, and the next address data can be read in
succession.
S
T
A
R
T
SDA
LINE
W
R
I
T
E
SLAVE
ADDRESS
WORD
ADDRESS(n)
WA
7
1 0 1 0 A2A1A0
S
T
A
R
T
WA
0
R A *1
/ C
W K
Note)
R
E
A
D
SLAVE
ADDRESS
DATA(n)
1 0 1 0 A2A1A0
A
C
K
S
T
O
P
D7
It is necessary to input "H"
to the last ACK.
D0
R A
/ C
W K
*1
As for WA7, BR24L01A-W become Don't care.
*1
As for WA12, BR24L32-W become Don't care.
A
C
K
Fig.43 Random read cycle (BR24L01A/02/04/08/16-W)
S
T
A
R
T
SDA
LINE
W
R
I
T
E
SLAVE
ADDRESS
1st WORD
ADDRESS(n)
* * *
1 0 1 0 A2A1A0
R A
/ C
W K
Note)
S
T
A
R
T
2nd WORD
ADDRESS(n)
WA WA
12 11
WA
0
S
T
O
P
DATA(n)
1 0 1 0 A2A1A0
A
C
K
A
C
K
*1
R
E
A
D
SLAVE
ADDRESS
D7
D0
R A
/ C
W K
A
C
K
Fig.44 Random read cycle (BR24L32/64-W)
S
T
A
R
T
SDA
LINE
R
E
A
D
SLAVE
ADDRESS
1
0
1
0 A2 A1 A0
Note)
D7
It is necessary to input "H"
to the last ACK.
S
T
O
P
DATA
D0
R A
/ C
W K
A
C
K
Fig.45 Current read cycle
S
T
A
R
T
SDA
LINE
SLAVE
ADDRESS
R
E
A
D
1 0 1 0 A2 A1 A0
Note)
DATA(n)
D7
R A
/ C
W K
S
T
O
P
DATA(n+x)
D0
D7
A
C
K
A
C
K
It is necessary to input "H"
to the last ACK.
D0
A
C
K
Fig.46 Sequential read cycle (in the case of current read cycle)
y In random read cycle, data of designated word address can be read.
y When the command just before current read cycle is random read cycle, current read cycle (each including sequential read cycle),
data of incremented last read address (n-th) address, i.e., data of the (n+1)-th address is output.
y When ACK signal "LOW" after D0 is detected, and stop condition is not sent from the master (µ-COM) side, the next address data can
be read in succession.
y Read cycle is ended by stop condition where "H" is input to ACK signal after D0 and SDA signal is started at SCL signal "H".
y When "H" is not input to ACK signal after D0, sequential read gets in, and the next data is output.
Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to input "H" to ACK
signal after D0, and to start SDA at SCL signal "H".
y Sequential read is ended by stop condition where "H" is input to ACK signal after arbitrary D0 and SDA is started at SCL signal "H".
Note)
*1*2*3
1 0 1 0 A2A1A0
Fig.47 Difference of slave address of each type
9/16
*1 In BR24L16-W, A2 becomes P2.
*2 In BR24L08-W, BR24L16-W, A1 becomes P1.
*3 In BR24L04-W, A0 becomes PS, and in BR24L08-W
and BR24L16-W, A0 becomes P0.
Software reset
Software reset is executed when to avoid malfunction after power on, and to reset during command input. Software reset has several
kinds, and 3 kinds of them are shown in the figure below. (Refer to Fig. 48 (a), Fig. 48 (b) and Fig. 48 (c).) In dummy clock input area,
release the SDA bus ("H" by pull up). In dummy clock area, ACK output and read data "0" (both "L" level) may be output from EEPROM,
therefore, if "H" is input forcibly, output may conflict and over current may flow, leading to instantaneous power failure of system power
source or influence upon devices.
Dummy clock × 14
SCL
1
2
Start × 2
13
14
Normal command
Normal command
SDA
Fig.48-(a) The case of dummy clock + START + START + command input
Dummy clock × 9
Start
SCL
1
2
Start
8
9
Normal command
Normal command
SDA
Fig.48-(b) The case of START + 9 dummy clocks + START + command input
Start × 9
SCL
1
2
3
7
8
9
Normal command
Normal command
SDA
Fig.48-(c) START × 9 + command input
* Start normal command from START input.
Acknowledge polling
During internal write execution, all input commands are ignored, therefore ACK is not sent back. During internal automatic write execution
after write cycle input, next command (slave address) is sent, and if the first ACK signal sends back "L", then it means end of write action,
while if it sends back "H", it means now in writing. By use of acknowledge polling, next command can be executed without waiting for
tWR = 5ms.
When to write continuously, R/W = 0, when to carry out current read cycle after write, slave address R/W = 1 is sent, and if ACK signal
sends back "L", then execute word address input and data output and so forth.
During internal write,
ACK = HIGH is sent back.
First write command
S
T
A
R
T
S
T
A
R
T
S
T
O
P
Write command
S
T
A
R
T
A
C
K
H
Slave address
Slave address
A
C
K
H
tWR
Second write command
S
T
A
R
T
Slave address
A
C
K
H
S
T
A
R
T
Slave address
tWR
A
C
K
L
Word address
A
C
K
L
Data
After completion of internal
write, ACK = LOW is sent
back, so input next word
address and data in
succession.
Fig.49 Case to continuously write by acknowledge polling
10/16
A
C
K
L
S
T
O
P
WP valid timing (write cancel)
WP is usually fixed to "H" or "L", but when WP is used to cancel write cycle and so forth, pay attention to the following WP valid timing.
During write cycle execution, in cancel valid area, by setting WP = "H", write cycle can be cancelled. In both byte write cycle and page
write cycle, the area from the first start condition of command to the rise of clock to taken in D0 of data (in page write cycle, the first byte
data) is cancel invalid area.
WP input in this area becomes Don't care. Set the setup time to rise of D0 taken SCL 100ns or more. The area from the rise of SCL to
take in D0 to the end of internal automatic write (tWR) is cancel valid area. And, when it is set WP = "H" during tWR, write is ended
forcibly, data of address under access is not guaranteed, therefore, write it once again. (Refer to Fig. 50.) After execution of forced end by
WP, standby status gets in, so there is no need to wait for tWR (5ms at maximum).
y Rise of D0 taken clock
SCL
SCL
SDA
D1
D0
ACK
SDA
y Rise of SDA
D0
Enlarged view
SDA
S
T
A
R
T
Slave
address
A
C
K
L
Word
address
A
C
K
L
D7
ACK
Enlarged view
D6
D5
D4
D3
D2
D1
D0
WP cancel invalid area
A
C
K
L
Data
A
C
K
L
S
T
O
P
tWR
WP cancel valid area
Write forced end
Data is not written.
Data not guaranteed
WP
Fig.50 WP valid timing
Command cancel by start condition and stop condition
During command input, by continuously inputting start condition and stop condition, command can be cancelled. (Refer to Fig. 51.)
However, in ACK output area and during data read, SDA bus may output "L", and in this case, start condition and stop condition cannot
be input, so reset is not available. Therefore, execute software reset. And when command is cancelled by start, stop condition, during
random read cycle, sequential read cycle, or current read cycle, internal setting address is not determined, therefore, it is not possible to
carry out current read cycle in succession. When to carry out read cycle in succession, carry out random read cycle.
SCL
SDA
1
0
1
0
Start condition
Stop condition
Fig.51 Case of cancel by start, stop condition during slave address input
11/16
I/O peripheral circuit
Pull up resistance of SDA terminal
SDA is NMOS open drain, so requires pull up resistance. As for this resistance value (RPU), select an appropriate value to this resistance
value from microcontroller VIL, IL, and VOL - IOL characteristics of this IC. If RPU is large, action frequency is limited. The smaller the RPU,
the larger the consumption current at action.
Maximum value of RPU
The maximum value of RPU is determined by the following factors.
(1) SDA rise time to be determined by the capacity (CBUS) of bus line of RPU and SDA should be tR or below.
And AC timing should be satisfied even when SDA rise time is late.
(2) The bus electric potential A to be determined by input leak total (IL) of device connected to bus at output of "H" to SDA bus and
RPU should sufficiently secure the input "H" level (VIH) of microcontroller and EEPROM including recommended noise margin 0.2VCC.
VCC-ILRPU - 0.2VCC≥VIH
RPU = 0.8VCC-VIH
IL
BR24LXX
Microcontroller
RPU
Ex.) When VCC = 3V, IL = 10µA, VIH = 0.7VCC,
from ( 2 )
A
SDA terminal
IL
IL
Bus line
capacity CBUS
RPU ≤ 0.8 × 3–0.7–6× 3
10 × 10
≤300[k ]
Fig.52 I/O circuit diagram
Minimum value of Rpu
The minimum value of Rpu is determined by the following factors.
(1) When IC outputs LOW, it should be satisfied that VOLMAX = 0.4V and IOLMAX = 3mA.
VCC - VOL ≤ IOL
RPU
RPU ≥
VCC - VOL
IOL
(2) VOLMAX = 0.4V should secure the input "L" level (VIL) of microcontroller and EEPROM including recommended noise margin 0.1VCC.
VOLMAX ≤ VIL - 0.1VCC
Ex.) When VCC = 3V, VOL = 0.4V, IOL = 3mA, microcontroller, EEPROM VIL = 0.3VCC
From (1),
RPU≥
3 – 0.4
3 ×10–3
≥867[ ]
And
VOL =0.4[V]
VIL =0.3 × 3
=0.9[V]
Therefore, the condition (2) is satisfied.
Pull up resistance of SCL terminal
When SCL control is made at CMOS output port, there is no need, but in the case there is timing where SCL becomes "Hi-Z", add a pull up
resistance. As for the pull up resistance, one of several k ~ several ten k is recommended in consideration of drive performance of
output port of microcontroller.
A0, A1, A2, WP process
Process of device address terminals (A0, A1, A2)
Check whether the set device address coincides with device address input sent from the master side or not, and select one among
plural devices connected to a same bus. Connect this terminal to pull up or pull down, or Vcc or GND. And, pins (N, C, PIN) not
used as device address may be set to any of "H", "L", and "Hi-Z".
Types with N.C. PIN
BR24L16/F/FJ/FV/FVT/FVM/FVJ-W
BR24L08/F/FJ/FV/FVT/FVM/FVJ-W
BR24L04/F/FJ/FV/FVT/FVM/FVJ-W
A0、A1、A2
A0、A1
A0
Process of WP terminal
WP terminal is the terminal that prohibits and permits write in hardware manner. In "H" status, only READ is available and WRITE of all
addresses is prohibited. In the case of "L", both are available. In the case to use it as an ROM, it is recommended to connect it to pull
up or Vcc. In the case to use both READ and WRITE, control WP terminal or connect it to pull down or GND.
12/16
Cautions on microcontroller connection
Rs
In I2C BUS, it is recommended that SDA port is of open drain input /output. However, when to use CMOS input / output of tri state to
SDA port, insert a series resistance Rs between the pull up resistance Rpu and the SDA terminal of EEPROM. This controls over
current that occurs when PMOS of the microcontroller and NMOS of EEPROM are turned ON simultaneously. Rs also plays the role of
protection of SDA terminal against surge. Therefore, even when SDA port is open drain input / output, Rs can be used.
ACK
RPU
SCL
RS
SDA
"H" output of microcontroller
"L" output of EEPROM
Microcontroller
EEPROM
Over current flows to SDA line by "H" output of
microcontroller and "L" output of EEPROM.
Fig.53 I/O circuit diagram
Fig.54 Input / output collision timing
Maximum value of Rs
The maximum value of Rs is determined by the following relations.
(1) SDA rise time to be determined by the capacity (CBUS) of bus line of Rpu and SDA should be tR or below.
And AC timing should be satisfied even when SDA rise time is late.
(2) The bus electric potential A to be determined by Rpu and Rs at the moment when EEPROM outputs "L" to SDA bus should
sufficiently secure the input "L" level (VIL) of microcontroller including recommended noise margin 0.1Vcc.
VCC
(VCC-VOL) × RS
+ VOL+0.1VCC ≤ VIL
RPU+RS
A
RPU
RS
VOL
RS ≤
IOL
× RPU
Example) When Vcc = 3V, VIL = 0.3Vcc, VOL = 0.4V, RPU = 20k ,
Bus line
capacity CBUS
from (2),
RS ≤
VIL
EEPROM
Microcontroller
VIL-VOL-0.1VCC
1.1VCC-VIL
0.3×3-0.4-0.1×3
1.1×3-0.3×3
× 20×103
≤ 1.67 [k ]
Fig.55 I/O circuit diagram
Minimum value of Rs
The minimum value of Rs is determined by over current at bus collision. When over current flows, noises in power source line, and
instantaneous power failure of power source may occur. When allowable over current is defined as I, the following relation must be
satisfied. Determine the allowable current in consideration of impedance of power source line in set and so forth. Set the over current
to EEPROM 10mA or below.
VCC
≤I
RS
RPU
RS
"L" output
RS ≥
VCC
I
Example) When Vcc = 3V, I = 10mA,
Over current I
"H" output
RS ≥
Microcontroller
EEPROM
3
10×10-3
≥ 300 [ ]
Fig.56 I/O circuit diagram
13/16
I2C BUS input / output circuit
Input (A0, A2, SCL)
Fig.57 Input pin circuit diagram
Input / output (SDA)
Fig.58 Input / output pin circuit diagram
Input (A1, WP)
Fig.59 Input pin circuit diagram
14/16
Notes on power ON
At power on, in IC internal circuit and set, Vcc rises through unstable low voltage area, and IC inside is not completely reset, and
malfunction may occur. To prevent this, functions of POR circuit and LVCC circuit are equipped. To assure the action, observe the
following conditions at power on.
1. Set SDA = "H" and SCL = "L" or "H".
2. Start power source so as to satisfy the recommended conditions of tR, tOFF, and Vbot for operating POR circuit.
tR
Recommended conditions of tR, tOFF, Vbot
VCC
tR
tOFF
Vbot
10ms or below 10ms or higher 0.3V or below
tOFF
Vbot
100ms or below 10ms or higher 0.2V or below
0
Fig.60 Rise waveform diagram
3. Set SDA and SCL so as not to become "Hi-Z".
When the above conditions 1 and 2 cannot be observed, take the following countermeasures.
a) In the case when the above condition 1 cannot be observed. When SDA becomes "L" at power on.
→Control SCL and SDA as shown below, to make SCL and SDA, "H" and "H".
Vcc
tLOW
SCL
SDA
After Vcc becomes stable
After Vcc becomes stable
tDH
tSU:DAT
tSU:DAT
Fig.61 When SCL = "H" and SDA = "L"
Fig.62 When SCL = "H" and SDA = "L"
b) In the case when the above condition 2 cannot be observed.
→After power source becomes stable, execute software reset (P10).
c) In the case when the above conditions 1 and 2 cannot be observed.
→Carry out a), and then carry out b).
Low voltage malfunction prevention function
LVCC circuit prevents data rewrite action at low power, and prevents wrong write. At LVCC voltage (Typ. = 1.2V) or below, it prevent data
rewrite.
Vcc noise countermeasures
Bypass capacitor
When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is recommended to attach a
by pass capacitor (0.1µF) between IC Vcc and GND. At that moment, attach it as close to IC as possible.
And, it is also recommended to attach a bypass capacitor between board Vcc and GND.
Cautions on use
(1) Described numeric values and data are design representative values, and the values are not guaranteed.
(2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further sufficiently. In
the case of use by changing the fixed number of external parts, make your decision with sufficient margin in consideration of static
characteristics and transition characteristics and fluctuations of external parts and our LSI.
(3) Absolute maximum ratings
If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded, LSI may be
destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of fear exceeding the absolute
maximum ratings, take physical safety countermeasures such as fuses, and see to it that conditions exceeding the absolute maximum
ratings should not be impressed to LSI.
(4) GND electric potential
Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is lower than that of GND terminal.
(5) Thermal design
In consideration of permissible loss in actual use condition, carry out heat design with sufficient margin.
(6) Terminal to terminal shortcircuit and wrong packaging
When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may destruct LSI. And in
the case of shortcircuit between LSI terminals and terminals and power source, terminal and GND owing to foreign matter, LSI may be
destructed.
(7) Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently.
15/16
Selection of order type
B R
2 4
ROHM type BUS type
name
24 : I2C
L
0 1
Operating
temperature
F
- W
Capacity Package
01 = 1K
L : −40℃〜＋85℃ 02 = 2K
H : −40℃〜＋125℃ 04 = 4K
08 = 8K
16 =16K
32 =32K
64 =64K
E 2
Double cell
Package specifications
E2 : reel shape emboss taping
TR : reel shape emboss taping
(MSOP8 package only)
F : SOP8
FJ : SOP-J8
FV : SSOP-B8
FVT : TSSOP-B8
FVM : MSOP8
FVJ : TSSOP-B8J
Package specifications
SOP8/SOP-J8/SSOP-B8/TSSOP-B8/TSSOP-B8J
<External appearance>
<Package specifications>
+0.05
0.65
0.45±0.15
0.95±0.2
4.9±0.2
3.0±0.1
0.1±0.05
0.08 S
0.245 -0.04
0.85±0.05
4.4±0.1
6.4±0.2
1.0±0.1
0.1±0.05
6.4±0.3
4.4±0.2
0.1
6.0±0.3
0.3Min.
0.45Min.
1.15±0.1
0.1
0.22±0.1
0.65
4
+0.05
0.145 -0.03
1234
(0.52)
1
+0.05
0.145 -0.03
1234
0.42±0.1
4
1234
0.1
1.27
1
0.15±0.1
1234
0.11
4
Emboss taping
2500pcs
E2
(When the reel is gripped by the left hand, and the tape is pulled out
by the right hand, No.1 pin of the product is at the left top.)
1234
1.5±0.1
1
0.2±0.1
Package type
Package quantity
Package direction
1234
0.1
5
3.0±0.1
8 5
1234
1.27
0.42±0.1
1 2 3 4
+0.1
-0.05
8
3.0±0.1
8 5
• TSSOP-B8J
1234
0.17
3.9±0.2
4
8 7 6 5
1.375±0.1
0.175
1
6.2±0.3
4.4±0.2
5
• TSSOP-B8
3.0±0.2
4.9±0.2
5.0±0.2
8
• SSOP-B8
0.5±0.15
1.0±0.2
• SOP-J8
0.3Min.
• SOP8
0.08 S
0.32
+0.05
-0.04
Pin No.1
0.65
Pulling side
Reel
(Unit : mm)
* For ordering, specify a number of multiples of the package quantity.
MSOP8
<External appearance>
<Package specifications>
5
0.9Max.
0.75 ± 0.05
0.08 ± 0.05
0.475
1
4
Emboss taping
3000pcs
TR
(When the reel is gripped by the left hand, and the tape is pulled out
by the right hand, No.1 pin of the product is at the right top.)
0.145+0.05
-0.03
0.22+0.05
-0.04
0.65
Package type
Package quantity
Package direction
0.29 ± 0.15
0.6 ± 0.2
8
2.8 ± 0.1
4.0 ± 0.2
2.9 ± 0.1
0.08 M
0.08 S
Pin No.1
Pulling side
Reel
(Unit : mm)
* For ordering, specify a number of multiples of the package quantity.
The contents described herein are correct as of October, 2005
The contents described herein are subject to change without notice. For updates of the latest information, please contact and confirm with ROHM CO.,LTD.
Any part of this application note must not be duplicated or copied without our permission.
Application circuit diagrams and circuit constants contained herein are shown as examples of standard use and operation. Please pay careful attention to the peripheral conditions when designing circuits and deciding
upon circuit constants in the set.
Any data, including, but not limited to application circuit diagrams and information, described herein are intended only as illustrations of such devices and not as the specifications for such devices. ROHM CO.,LTD. disclaims any
warranty that any use of such devices shall be free from infringement of any third party's intellectual property rights or other proprietary rights, and further, assumes no liability of whatsoever nature in the event of any such
infringement, or arising from or connected with or related to the use of such devices.
Upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or otherwise dispose of the same, implied right or license to practice or commercially exploit any intellectual property rights or other
proprietary rights owned or controlled by ROHM CO., LTD. is granted to any such buyer.
The products described herein utilize silicon as the main material.
The products described herein are not designed to be X ray proof.
Published by
Application Engineering Group
Catalog No. 05T822Ae '05.10
© 2000
ROHMTSU
Appendix
Notes
No technical content pages of this document may be reproduced in any form or transmitted by any
means without prior permission of ROHM CO.,LTD.
The contents described herein are subject to change without notice. The specifications for the
product described in this document are for reference only. Upon actual use, therefore, please request
that specifications to be separately delivered.
Application circuit diagrams and circuit constants contained herein are shown as examples of standard
use and operation. Please pay careful attention to the peripheral conditions when designing circuits
and deciding upon circuit constants in the set.
Any data, including, but not limited to application circuit diagrams information, described herein
are intended only as illustrations of such devices and not as the specifications for such devices. ROHM
CO.,LTD. disclaims any warranty that any use of such devices shall be free from infringement of any
third party's intellectual property rights or other proprietary rights, and further, assumes no liability of
whatsoever nature in the event of any such infringement, or arising from or connected with or related
to the use of such devices.
Upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or
otherwise dispose of the same, no express or implied right or license to practice or commercially
exploit any intellectual property rights or other proprietary rights owned or controlled by
ROHM CO., LTD. is granted to any such buyer.
Products listed in this document are no antiradiation design.
The products listed in this document are designed to be used with ordinary electronic equipment or devices
(such as audio visual equipment, office-automation equipment, communications devices, electrical
appliances and electronic toys).
Should you intend to use these products with equipment or devices which require an extremely high level
of reliability and the malfunction of which would directly endanger human life (such as medical
instruments, transportation equipment, aerospace machinery, nuclear-reactor controllers, fuel controllers
and other safety devices), please be sure to consult with our sales representative in advance.
It is our top priority to supply products with the utmost quality and reliability. However, there is always a chance
of failure due to unexpected factors. Therefore, please take into account the derating characteristics and allow
for sufficient safety features, such as extra margin, anti-flammability, and fail-safe measures when designing in
order to prevent possible accidents that may result in bodily harm or fire caused by component failure. ROHM
cannot be held responsible for any damages arising from the use of the products under conditions out of the
range of the specifications or due to non-compliance with the NOTES specified in this catalog.
Thank you for your accessing to ROHM product informations.
More detail product informations and catalogs are available, please contact your nearest sales office.
ROHM Customer Support System
www.rohm.com
Copyright © 2007 ROHM CO.,LTD.
THE AMERICAS / EUPOPE / ASIA / JAPAN
Contact us : webmaster@ rohm.co. jp
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Appendix1-Rev2.0