BSI Very Low Power/Voltage CMOS SRAM 512K X 16 bit (Single CE Pin) FEATURES BS616LV8019 DESCRIPTION • Vcc operation voltage : 4.5~5.5V • Very low power consumption : Vcc = 5.0V C-grade: 75mA (@55ns) operating current I -grade: 76mA (@55ns) operating current C-grade: 60mA (@70ns) operating current I -grade: 61mA (@70ns) operating current 8.0uA (Typ.) CMOS standby current • High speed access time : -55 55ns -70 70ns • Automatic power down when chip is deselected • Three state outputs and TTL compatible • Fully static operation • Data retention supply voltage as low as 1.5V • Easy expansion with CE and OE options • I/O Configuration x8/x16 selectable by LB and UB pin The BS616LV8019 is a high performance, very low power CMOS Static Random Access Memory organized as 524,288 words by 16 bits and operates from a range of 4.5V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 8.0uA at 5V/25oC and maximum access time of 55ns at 5.0V/85oC. Easy memory expansion is provided by an active LOW chip enable (CE) ,active LOW output enable(OE) and three-state output drivers. The BS616LV8019 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS616LV8019 is available in 48B BGA and 44L TSOP2 packages. PRODUCT FAMILY PRODUCT FAMILY OPERATING TEMPERATURE BS616LV8019EC BS616LV8019FC BS616LV8019EI BS616LV8019FI O O A4 A3 A2 A1 A0 CE DQ0 DQ1 DQ2 DQ3 Vcc Vss DQ4 DQ5 DQ6 DQ7 WE A18 A17 A16 A15 A14 A POWER DISSIPATION STANDBY Operating SPEED ( ns ) 55ns : 4.5~5.5V 70ns : 4.5~5.5V ( I CCSB1, Max ) PKG TYPE ( ICC , Max ) Vcc=5V Vcc=5V Vcc=5V 55ns 70ns +0 C to +70 C 4.5V ~ 5.5V 55 / 70 55uA 75mA 60mA -40 O C to +85O C 4.5V ~ 5.5V 55 / 70 110uA 76mA 61mA PIN CONFIGURATIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Vcc RANGE BS616LV8019EC BS616LV8019EI TSOP2-44 BGA-48-0912 TSOP2-44 BGA-48-0912 BLOCK DIAGRAM 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB DQ15 DQ14 DQ13 DQ12 Vss Vcc DQ11 DQ10 DQ9 DQ8 A8 A9 A10 A11 A12 A13 1 2 3 4 5 6 LB OE A0 A1 A2 NC A4 A3 A2 A1 Address A0 A17 A16 A15 A14 A13 A12 Input Buffer 22 2048 Row Memory Array Decoder 2048 x 4096 4096 16 D0 . . . . . . . . D8 UB A3 A4 CE D0 C D9 D10 A5 A6 D1 D2 D V SS D11 A17 A7 D3 V CC WE E V CC D12 VSS A16 D4 V SS OE UB F D14 D13 A 14 A 15 D5 D6 LB G D15 NC . A12 A 13 WE D7 H A 18 A8 A9 A 10 A 11 NC Vcc Vss 16 Column I/O Write Driver Sense Amp 16 Data Output Buffer D15 B Data Input Buffer 256 16 Column Decoder 16 CE Control Address Input Buffer A11 A10 A9 A8 A7 A6 A5 A18 48-Ball CSP top View Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice. R0201-BS616LV8019 1 Revision 2.1 Jan. 2004 BSI BS616LV8019 PIN DESCRIPTIONS Name Function A0-A18 Address Input These 19 address inputs select one of the 524,288 x 16-bit words in the RAM. CE Chip Enable Input CE is active LOW. Chip enables must be active when data read from or write to the device. if chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected. WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive. LB and UB Data Byte Control Input Lower byte and upper byte data input/output control pins. D0 - D15 Data Input/Output Ports These 16 bi-directional ports are used to read data from or write data into the RAM. Vcc Power Supply Vss Ground TRUTH TABLE MODE Not selected (Power Down) Output Disabled Read Write CE H WE OE LB UB D0~D7 D8~D15 X X X X High Z High Z ICCSB , I CCSB1 X X X H H High Z L L X H X H H X H X High Z High Z High Z High Z ICCSB , I CCSB1 ICC L L Dout H L L H L L L L ABSOLUTE MAXIMUM SYMBOL H L L X with High Z ICC Dout ICC High Z Dout ICC Dout High Z ICC Din Din ICC H L X Din ICC L H Din X ICC RATINGS(1) PARAMETER Vcc CURRENT RATING UNITS -0.5 to Vcc+0.5 V VTERM Terminal Voltage Respect to GND TBIAS Temperature Under Bias -40 to +85 O TSTG Storage Temperature -60 to +150 O PT Power Dissipation 1.0 W IOUT DC Output Current 20 mA OPERATING RANGE AMBIENT RANGE TEMPERATURE Commercial C Industrial C 0 O C to +70O C O O -40 C to +85 C Vcc 4.5V ~ 5.5V 4.5V ~ 5.5V CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz) SYMBOL PARAMETER CONDITIONS MAX. UNIT Input CIN VIN=0V 10 pF 1. Stresses greater than those listed under ABSOLUTE MAXIMUM Capacitance RATINGS may cause permanent damage to the device. This is a Input/Output CDQ VI/O=0V 12 pF stress rating only and functional operation of the device at these Capacitance or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute 1. This parameter is guaranteed and not 100% tested. maximum rating conditions for extended periods may affect reliability. R0201-BS616LV8019 2 Revision 2.1 Jan. 2004 BSI BS616LV8019 DC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC ) PARAMETER NAME PARAMETER TEST CONDITIONS Guaranteed Input Low Voltage (3) Guaranteed Input High Voltage(3) VIL VIH (1) MIN. TYP. MAX. UNITS Vcc=5.0V -0.5 -- 0.8 V Vcc=5.0V 2.2 -- Vcc+0.3 V IIL Input Leakage Current Vcc = Max, VIN = 0V to Vcc -- -- 1 uA ILO Output Leakage Current Vcc = Max, CE = VIH , or OE = VIH , VI/O = 0V to Vcc -- -- 1 uA VOL Output Low Voltage Vcc = Max, IOL = 2mA Vcc=5.0V -- -- 0.4 V VOH Output High Voltage Vcc = Min, IOH = -1mA Vcc=5.0V 2.4 -- -- V -- -- 76 -- -- 61 ICC (4) Operating Power Supply Current ICCSB (5) ICCSB1 CE = VIL ,IDQ = 0mA ,F = Fmax(2) 55ns Vcc=5.0V 70ns mA Standby Current - TTL CE = VIH ,I DQ = 0mA Vcc=5.0V -- -- 2 mA Standby Current - CMOS CE ≧ Vcc -0.2V, VIN ≧ Vcc - 0.2V or VIN≦ 0.2V Vcc=5.0V -- 8.0 110 uA 1. Typical characteristics are at TA = 25oC. 2. Fmax = 1/tRC . 3. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 4. Icc_Max. is 75mA(@55ns) / 60mA(@70ns) during 0~70oC operation. 5.IccsB1 is 55uA at Vcc=5.0V and TA=70oC. DATA RETENTION CHARACTERISTICS ( TA = -40 to + 85oC ) SYMBOL VDR ICCDR tCDR tR (3) PARAMETER TEST CONDITIONS MIN. TYP. (1) MAX. UNITS Vcc for Data Retention CE ≧ Vcc - 0.2V VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V 1.5 -- -- V Data Retention Current CE ≧ Vcc - 0.2V VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V -- 0.8 2.5 uA -- -- ns -- -- ns Chip Deselect to Data Retention Time See Retention Waveform Operation Recovery Time 0 TRC (2) 2. tRC = Read Cycle Time 1. Vcc = 1.5V, TA = + 25OC 3. IccDR(Max.) is 1.3uA at TA=70OC. LOW VCC DATA RETENTION WAVEFORM ( CE Controlled ) Data Retention Mode Vcc VDR ≥ 1.5V Vcc CE R0201-BS616LV8019 VIH Vcc tR t CDR CE ≥ Vcc - 0.2V 3 VIH Revision 2.1 Jan. 2004 BSI BS616LV8019 KEY TO SWITCHING WAVEFORMS AC TEST CONDITIONS (Test Load and Input/Output Reference) Input Pulse Levels Vcc / 0V Input Rise and Fall Times WAVEFORM INPUTS OUTPUTS 1V/ns MUST BE STEADY MUST BE STEADY Input and Output Timing Reference Level 0.5Vcc MAY CHANGE FROM H TO L WILL BE CHANGE FROM H TO L Output Load CL = 30pF+1TTL CL = 100pF+1TTL MAY CHANGE FROM L TO H WILL BE CHANGE FROM L TO H , DON T CARE: ANY CHANGE PERMITTED CHANGE : STATE UNKNOWN DOES NOT APPLY CENTER LINE IS HIGH IMPEDANCE ”OFF ”STATE AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC ) READ CYCLE JEDEC PARAMETER PARAMETER NAME NAME Vcc = 4.5~5.5V Vcc = 4.5~5.5V UNIT MIN. TYP. MAX. MIN. TYP. MAX. Read Cycle Time 70 -- -- 55 -- -- ns Address Access Time -- -- 70 -- -- 55 ns (CE) -- -- 70 -- -- 55 ns (LB,UB) -- -- 35 -- -- 30 ns -- -- 35 -- -- 30 ns tAVAX tAVQV tELQV tRC tAA t ACS tBA tBA tGLQV tELQX tBE tGLQX tOE tCLZ tBE tOLZ Output Enable to Output Valid tEHQZ tBDO tCHZ tBDO Chip Deselect to Output in High Z tGHQZ tOHZ tAXOX tOH Chip Select Access Time (1) CYCLE TIME : 70ns CYCLE TIME : 55ns DESCRIPTION Data Byte Control Access Time (CE) 10 -- -- 10 -- -- ns (LB,UB) 5 -- -- 5 -- -- ns 5 -- -- 5 -- -- ns (CE) -- -- 35 -- -- 30 ns Data Byte Control to Output High Z (LB,UB) -- -- 35 -- -- 30 ns Output Disable to Output in High Z -- -- 30 -- -- 25 ns Data Hold from Address Change 10 -- -- 10 -- -- ns Chip Select to Output Low Z Data Byte Control to Output Low Z Output Enable to Output in Low Z NOTE : 1. tBA is 35ns/30ns (@speed=70ns/55ns) with address toggle . tBA is 70ns/55ns (@speed=70ns/55ns) without address toggle . R0201-BS616LV8019 4 Revision 2.1 Jan. 2004 BSI BS616LV8019 SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE1 (1,2,4) t RC ADDRESS t t t OH AA OH D OUT READ CYCLE2 (1,3,4) CE t ACS t BA LB,UB t BE D OUT t t t BDO (5) (5) CHZ CLZ READ CYCLE3 (1,4) t RC ADDRESS t AA OE t t CE t t t OE OH OLZ t ACS (5) CLZ OHZ (5) (1,5) t CHZ t BDO LB,UB t BE t BA D OUT NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE = VIL . 3. Address valid prior to or coincident with CE transition low. 4. OE = VIL . 5. The parameter is guaranteed but not 100% tested. R0201-BS616LV8019 5 Revision 2.1 Jan. 2004 BSI BS616LV8019 AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + WRITE CYCLE JEDEC PARAMETER PARAMETER NAME NAME t AVAX t E1LWH t AVWL t AVWH t WLWH t WHAX t BW t WLQZ t DVWH t WHDX t GHQZ t WC t CW t AS t AW t WP t WR t BW (1) t WHZ t DW t DH t OHZ t WHOX t OW 85oC ) CYCLE TIME : 70ns CYCLE TIME : 55ns DESCRIPTION Vcc = 4.5~5.5V Vcc = 4.5~5.5V MIN. TYP. MAX. MIN. TYP. MAX. UNIT Write Cycle Time 70 -- -- 55 -- -- ns Chip Select to End of Write 55 -- -- ns 70 -- -- Address Setup Time 0 -- -- 0 -- -- ns Address Valid to End of Write 70 -- -- 55 -- -- ns Write Pulse Width 35 -- -- 30 -- -- ns 0 -- -- 0 -- -- ns Date Byte Control to End of Write (LB,UB) (CE,WE) 30 -- -- 25 -- -- ns Write to Output in High Z -- -- 30 -- -- 25 ns Data to Write Time Overlap 30 -- -- 25 -- -- ns Data Hold from Write Time 0 -- -- 0 -- -- ns Output Disable to Output in High Z -- -- 30 -- -- 25 ns End of Write to Output Active 5 -- -- 5 -- -- ns Write recovery Time NOTE : 1. tBW is 30ns/25ns (@speed=70ns/55ns) with address toggle. ; tBW is 70ns/55ns (@speed=70ns/55ns) without address toggle. SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE1 (1) t WC ADDRESS (3) t WR OE (11) t CW (5) CE t BW (5) LB,UB t AW WE (3) t WP t AS (2) (4,10) t OHZ D OUT t DH t DW D IN R0201-BS616LV8019 6 Revision 2.1 Jan. 2004 BSI BS616LV8019 WRITE CYCLE2 (1,6) t WC ADDRESS (11) t (5) CE t BW (5) LB,UB t WE CW AW t WR t WP (3) (2) t AS (4,10) t WHZ D OUT t OW t DH (7) (8) t DW (8,9) D IN NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE or WE going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL ). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE going low to the end of write. R0201-BS616LV8019 7 Revision 2.1 Jan. 2004 BSI BS616LV8019 ORDERING INFORMATION BS616LV8019 X X Z YY SPEED 55: 55ns 70: 70ns PKG MATERIAL -: Normal G: Green P: Pb free GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC PACKAGE F :BGA-48-0912 E :TSOP2-44 Note: BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support systems and critical medical instruments. 1.4 Max. 0.25± 0.05 PACKAGE DIMENSIONS NOTES: 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS. SIDE VIEW D 0.1 3.375 D1 N D E D1 E1 e 48 12.0 9.0 5.25 3.75 0.75 E1 2.625 E ± 0.1 e SOLDER BALL 0.35±0.05 VIEW A 48 mini-BGA (9mm x 12mm) R0201-BS616LV8019 8 Revision 2.1 Jan. 2004 BSI BS616LV8019 PACKAGE DIMENSIONS (continued) TSOP2-44 R0201-BS616LV8019 9 Revision 2.1 Jan. 2004