BSI Very Low Power/Voltage CMOS SRAM 32K X 8 bit BS62LV2565 DESCRIPTION FEATURES • Wide Vcc operation voltage : 4.5V ~ 5.5V • Very low power consumption : Vcc = 5.0V C-grade : 35mA (Max.) operating current I- grade : 40mA (Max.) operating current 0.4uA (Typ.) CMOS standby current • High speed access time : -55 55ns (Max.) = 5.0V -70 70ns (Max.) = 5.0V • Automatic power down when chip is deselected • Three state outputs and TTL compatible • Fully static operation • Data retention supply voltage as low as 1.5V • Easy expansion with CE and OE options The BS62LV2565 is a high performance, very low power CMOS Static Random Access Memory organized as 32,768 words by 8 bits and operates from a wide range of 4.5V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.4uA and maximum access time of 55ns in 5V operation. Easy memory expansion is provided by an active LOW chip enable (CE), and active LOW output enable (OE) and three-state output drivers. The BS62LV2565 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS62LV2565 is available in the JEDEC standard 28 pin 330mil Plastic SOP, 300mil Plastic SOJ, 600mil Plastic DIP and 8mmx13.4mm TSOP (normal type). PRODUCT FAMILY PRODUCT FAMILY OPERATING TEMPERATURE Vcc RANGE POWER DISSIPATION STANDBY Operating SPEED (ns) Vcc=5.0V BS62LV2565SC BS62LV2565TC BS62LV2565PC BS62LV2565JC BS62LV2565DC BS62LV2565SI BS62LV2565TI BS62LV2565PI BS62LV2565JI BS62LV2565DI O O 0 C to +70 C O O -40 C to +85 C Vcc=5.0V 55 / 70 1.0uA 35mA 4.5V ~ 5.5V 55 / 70 2.0uA 40mA A14 1 • 28 VCC A12 2 27 WE A7 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 23 A6 A7 A12 A11 A14 A3 7 22 OE A13 A2 8 21 A10 A1 9 20 CE A0 10 19 DQ7 DQ0 11 18 DQ6 DQ1 12 17 DQ5 DQ2 13 16 DQ4 GND 14 15 DQ3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Vcc=5.0V PKG TYPE SOP-28 TSOP-28 PDIP-28 SOJ-28 DICE SOP-28 TSOP-28 PDIP-28 SOJ-28 DICE BLOCK DIAGRAM • OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 (I CC , Max) 4.5V ~ 5.5V PIN CONFIGURATIONS BS62LV2565SC BS62LV2565SI BS62LV2565PC BS62LV2565PI BS62LV2565JC BS62LV2565JI (I CCSB1 , Max) BS62LV2565TC BS62LV2565TI 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A5 A8 Address Input Buffer 18 512 Row Memory Array 512 x 512 Decoder A9 A11 512 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 A0 A1 A2 8 8 Data Input Buffer Data Output Buffer Column I/O 8 8 Write Driver Sense Amp 64 Column Decoder 12 CE WE Control Address Input Buffer OE Vdd Gnd A4 A3 A2 A1 A0 A10 Brilliance Semiconductor Inc. reserves the right to modify document contents without notice. R0201-BS62LV2565 1 Revision 2.2 April 2001 BSI BS62LV2565 PIN DESCRIPTIONS Name Function A0-A14 Address Input These 15 address input select one of the 32768 x 8-bit wordsin the RAM CE Chip Enable Input CE is active LOW. Chip enables must be active to read from or write to the device. If chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected. WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive. DQ0-DQ7 Data Input/Output Ports These 8 bi-directional ports are used to read data from or write data into the RAM. Vcc Power Supply Gnd Ground TRUTH TABLE MODE WE CE OE I/O OPERATION Vcc CURRENT Not selected X H X High Z ICCSB, ICCSB1 Output Disabled H L H High Z ICC Read H L L DOUT ICC Write L L X DIN ICC ABSOLUTE MAXIMUM RATINGS(1) SYMBOL OPERATING RANGE PARAMETER RATING UNITS V TERM Terminal Voltage with Respect to GND -0.5 to +6.0 V T BIAS Temperature Under Bias -40 to +125 O C T STG Storage Temperature -60 to +150 O C PT Power Dissipation 1.0 W I OUT DC Output Current 20 mA RANGE Commercial Industrial O O 0 C to +70 C O O -40 C to +85 C Vcc 4.5V ~ 5.5V 4.5V ~ 5.5V CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz) SYMBOL 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. R0201-BS62LV2565 AMBIENT TEMPERATURE 2 CIN CDQ PARAMETER Input Capacitance Input/Output Capacitance CONDITIONS MAX. UNIT VIN=0V 6 pF VI/O=0V 8 pF 1. This parameter is guaranteed and not tested. Revision 2.2 April 2001 BSI BS62LV2565 DC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC ) PARAMETER NAME VIL VIH PARAMETER TEST CONDITIONS Guaranteed Input Low (2) Voltage Guaranteed Input High Voltage(2) MIN. TYP. (1) MAX. UNITS Vcc=5.0V -0.5 -- 0.8 V Vcc=5.0V 2.2 -- Vcc+0.2 V IIL Input Leakage Current Vcc = Max, VIN = 0V to Vcc -- -- 1 uA IOL Output Leakage Current Vcc = Max, CE = VIH, or OE = VIH, VI/O = 0V to Vcc -- -- 1 uA VOL Output Low Voltage Vcc = Max, IOL = 2mA Vcc=5.0V -- -- 0.4 V VOH Output High Voltage Vcc = Min, I OH = -1mA Vcc=5.0V 2.4 -- -- V ICC Operating Supply Current (3) CE = VIL, IDQ = 0mA, F = Fmax Vcc=5.0V -- -- 35 Vcc=5.0V -- -- 2 Vcc=5.0V -- 0.4 1.0 Power ICCSB Standby Current-TTL CE = VIH, IDQ = 0mA ICCSB1 Standby Current-CMOS CE Њ Vcc-0.2V, VIN Њ Vcc - 0.2V or VIN Љ 0.2V mA mA uA 1. Typical characteristics are at TA = 25oC. 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 3. Fmax = 1/tRC . DATA RETENTION CHARACTERISTICS ( TA = 0oC to + 70oC ) SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. (1) MAX. UNITS VDR Vcc for Data Retention CE Њ Vcc - 0.2V VIN Њ Vcc - 0.2V or VIN Љ 0.2V 1.5 -- -- V ICCDR Data Retention Current CE Њ Vcc -0.2V VINЊ Vcc - 0.2V or VIN Љ 0.2V -- 0.01 0.40 uA tCDR Chip Deselect to Data Retention Time -- -- ns -- -- ns tR See Retention Waveform Operation Recovery Time 0 TRC (2) 1. Vcc = 1.5V, TA = + 25OC 2. tRC = Read Cycle Time LOW VCC DATA RETENTION WAVEFORM (1) ( CE Controlled ) Data Retention Mode Vcc VDR ≥ 1.5V Vcc CE R0201-BS62LV2565 VIH Vcc tR t CDR CE ≥ Vcc - 0.2V 3 VIH Revision 2.2 April 2001 BSI BS62LV2565 KEY TO SWITCHING WAVEFORMS AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Vcc/0V 5ns WAVEFORM 0.5Vcc AC TEST LOADS AND WAVEFORMS 1928 Ω 5.0V 1928 Ω 5.0V OUTPUT INPUTS OUTPUTS MUST BE STEADY MUST BE STEADY MAY CHANGE FROM H TO L WILL BE CHANGE FROM H TO L MAY CHANGE FROM L TO H WILL BE CHANGE FROM L TO H OUTPUT , 100PF INCLUDING JIG AND SCOPE 5PF INCLUDING JIG AND SCOPE 1020 Ω 1020 Ω FIGURE 1A FIGURE 1B THEVENIN EQUIVALENT 667 Ω OUTPUT DON T CARE: ANY CHANGE PERMITTED CHANGE : STATE UNKNOWN DOES NOT APPLY CENTER LINE IS HIGH IMPEDANCE ”OFF ”STATE 1.73V ALL INPUT PULSES Vcc GND → 10% 90% 90% 10% ← → ← 5ns FIGURE 2 AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC, Vcc=5V ) READ CYCLE JEDEC PARAMETER PARAMETER NAME NAME tAVAX tAVQV tELQV tGLQV tELQX tGLQX tEHQZ tGHQZ tRC tAA tACS tOE tCLZ tOLZ tCHZ tOHZ tAXOX tOH R0201-BS62LV2565 BS62LV2565-55 MIN. TYP. MAX. BS62LV2565-70 MIN. TYP. MAX. Read Cycle Time 55 -- -- 70 -- -- ns Address Access Time -- -- 55 -- -- 70 ns Chip Select Access Time -- -- 55 -- -- 70 ns Output Enable to Output Valid -- -- 25 -- -- 35 ns Chip Select to Output Low Z 10 -- -- 10 -- -- ns Output Enable to Output in Low Z 10 -- -- 10 -- -- ns Chip Deselect to Output in High Z 0 -- 30 0 -- 35 ns Output Disable to Output in High Z 0 -- 25 0 -- 30 ns Output Disable to Output Address Change 10 -- -- 10 -- -- ns DESCRIPTION 4 UNIT Revision 2.2 April 2001 BSI BS62LV2565 SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE1 (1,2,4) t RC ADDRESS t t t OH AA OH D OUT READ CYCLE2 (1,3,4) CE t t (5) ACS t CHZ (5) CLZ D OUT READ CYCLE3 (1,4) t RC ADDRESS t AA OE t OE t OH t OLZ CE t ACS (5) t CLZ t OHZ (5) (1,5) t CHZ D OUT NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE = VIL. 3. Address valid prior to or coincident with CE transition low. 4. OE = VIL . 5. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. R0201-BS62LV2565 5 Revision 2.2 April 2001 BSI BS62LV2565 AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC, Vcc=5V ) WRITE CYCLE JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION BS62LV2565-55 MIN. TYP. MAX. BS62LV2565-70 MIN. TYP. MAX. UNIT tAVAX tWC Write Cycle Time 55 -- -- 70 -- -- ns tE1LWH tCW Chip Select to End of Write 55 -- -- 70 -- -- ns tAVWL tAS Address Set up Time 0 -- -- 0 -- -- ns tAVWH tAW Address Valid to End of Write 55 -- -- 70 -- -- ns tWLWH tWP Write Pulse Width 35 -- -- 45 -- -- ns tWHAX tWR Write Recovery Time 0 -- -- 0 -- -- ns tWLOZ tWHZ Write to Output in High Z -- -- 25 -- -- 30 ns tDVWH tDW Data to Write Time Overlap 35 -- -- 40 -- -- ns tWHDX tDH Data Hold from Write Time 0 -- -- 0 -- -- ns tGHOZ tOHZ Output Disable to Output in High Z 0 -- 25 ns -- 30 ns tWHQX tOW End ot Write to Output Active 5 -- -- 5 -- -- ns (CE , WE) SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE1 (1) t WC ADDRESS t (3) WR OE (11) t CW (5) CE t AW WE t WP t AS (2) (4,10) t OHZ D OUT t t DH DW D IN R0201-BS62LV2565 6 Revision 2.2 April 2001 BSI BS62LV2565 WRITE CYCLE2 (1,6) t WC ADDRESS (11) t CW (5) CE t AW t WP (2) WE t t AS DH (4,10) t WHZ (7) D OUT (8) t DW t DH (8,9) D IN NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE or WE going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL ). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE going low to the end of write. R0201-BS62LV2565 7 Revision 2.2 April 2001 BSI BS62LV2565 ORDERING INFORMATION BS62LV2565 X X ˀˀ Y Y SPEED 55 : 55ns 70: 70ns GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC PACKAGE J: SOJ S: SOP P: PDIP T: TSOP (8mm x 13.4mm) D: DICE PACKAGE DIMENSIONS 0.020 ̈́ 0.005X45̓ θ WITH PLATING b c c1 BASE METAL b1 SOP - 28 R0201-BS62LV2565 8 Revision 2.2 April 2001 BSI BS62LV2565 PACKAGE DIMENSIONS (continued) UNIT SYMBOL 12̓(2x) e 12̓(2x) HD 1 E cL b 28 y Seating Plane 14 15 12̓ (2X) "A" D A A2 GAUGE PLANE A1 0 14 15 MM 0.0433̈́0.004 1.10̈́0.10 A1 A2 b b1 c 0.0045̈́0.0026 0.039̈́0.002 0.009̈́0.002 0.008̈́0.001 0.004 ~ 0.008 0.115̈́0.065 1.00̈́0.05 0.22̈́0.05 0.20̈́0.03 0.10 ~ 0.21 c1 D E e HD 0.004 ~ 0.006 0.465̈́0.004 0.315̈́0.004 0.022̈́0.004 0.528̈́0.008 0.10 ~ 0.16 11.80̈́0.10 8.00̈́0.10 0.55̈́0.10 13.40̈́0.20 L L1 y 0 0.0197 +0.008 - 0.004 0.0315̈́0.004 0.004 Max. 0̓~ 8̓ 0.50 +0.20 - 0.10 0.80̈́0.10 0.1 Max. 0̓~ 8̓ 0.254 A INCH A A SEATING PLANE 12 (2X) L "A" DATAIL VIEW b WITH PLATING 1 28 L1 c c1 BASE METAL b1 SECTION A-A TSOP - 28 PDIP - 28 R0201-BS62LV2565 9 Revision 2.2 April 2001 BSI BS62LV2565 PACKAGE DIMENSIONS (continued) SOJ - 28 R0201-BS62LV2565 10 Revision 2.2 April 2001 BSI BS62LV2565 REVISION HISTORY Revision Description Date 2.2 2001 Data Sheet release Apr. 15, 2001 R0201-BS62LV2565 11 Note Revision 2.2 April 2001