TI BUF22821AIDCPR Programmable gamma-voltage generator and vcom calibrator with integrated two-bank memory Datasheet

 BU
®
F22
821
BUF22821
SBOS399 – JUNE 2007
Programmable Gamma-Voltage Generator and
VCOM Calibrator with Integrated Two-Bank Memory
FEATURES
•
•
•
•
•
•
•
•
•
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DESCRIPTION
24-CHANNEL GAMMA
– 22-CHANNEL PROGRAMMABLE
– 2-CHANNEL STATIC GAMMA
2-CHANNEL PROGRAMMABLE VCOM
10-BIT RESOLUTION
16x REWRITABLE NONVOLATILE MEMORY
TWO INDEPENDENT MEMORY BANKS
RAIL-TO-RAIL OUTPUT
LOW SUPPLY CURRENT: 0.5mA/channel
SUPPLY VOLTAGE: 9V to 20V
DIGITAL SUPPLY: 2V to 5.5V
I2C™ INTERFACE
APPLICATIONS
•
TFT-LCD REFERENCE DRIVERS
Digital
(2.0V to 5.5V)
BKSEL
Analog
(9V to 20V)
1
STATOUTH
STATINH
AVDD
OUT1
The BUF22821 offers 22 programmable gamma
channels, two programmable VCOM channels, and
two static gamma channels. It is ideal for the new
10-bit source drivers that require 22 gamma
channels.
The final gamma and VCOM values can be stored in
the on-chip, nonvolatile memory. To allow for
programming errors or liquid crystal display (LCD)
panel rework, the BUF22821 supports up to 16 write
operations to the on-chip memory. The BUF22821
has two separate banks of memory, allowing
simultaneous storage of two different gamma curves
to facilitate switching between gamma curves.
All gamma and VCOM channels offer a rail-to-rail
output that typically swings to within 100mV of either
supply rail with a 10mA load. All channels are
programmed using an I2C interface that supports
standard operations up to 400kHz and high-speed
data transfers up to 3.4MHz.
The BUF22821 is manufactured using Texas
Instruments’ proprietary, state-of-the-art, high-voltage
CMOS process. This process offers very dense logic
and high supply voltage operation of up to 20V. The
BUF22821 is offered in a HTSSOP-38 PowerPAD™
package. It is specified from –40°C to +85°C.
RELATED PRODUCTS
DAC Registers
¼
¼
¼
¼
¼
DAC Registers
16x Nonvolatile Memory BANK0
16x Nonvolatile Memory BANK1
OUT2
OUT21
OUT22
STATINL
AVDD
STATOUTL
FEATURES
PRODUCT
12-Channel Gamma Correction Buffer
BUF12800
20-Channel Programmable Buffer, 10-Bit, VCOM
BUF20800
16-/20-Channel Programmable Buffer with Memory
BUF20820
Programmable VCOM Driver
BUF01900
18V Supply, Traditional Gamma Buffers
BUF11704
22V Supply, Traditional Gamma Buffers
BUF11705
VCOM1
VCOM2
SDA
SCL
Control IF
BUF22821
A0
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
I2C is a trademark of NXP Semiconductors.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
BUF22821
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SBOS399 – JUNE 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION (1)
(1)
PRODUCT
PACKAGE
PACKAGE DESIGNATOR
PACKAGE MARKING
BUF22821
HTSSOP-38
DCP
BUF22821
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range (unless otherwise noted).
BUF22821
UNIT
Supply Voltage, VS
+22
V
Supply Voltage, VSD
+6
V
Digital Input Terminals, SCL, SDA, AO, BKSEL: Voltage
–0.5 to +6
V
Digital Input Terminals, SCL, SDA, AO, BKSEL: Current
±10
mA
Analog Input Terminals, STATINL, STATINH: Voltage
–0.5 to VS + 0.5
V
Analog Input Terminals, STATINL, STATINH: Current
±10
mA
Output Short-Circuit (2)
–40 to +95
°C
Storage Temperature
–65 to +150
°C
Junction Temperature
ESD Ratings
(1)
(2)
2
Continuous
Operating Temperature
+125
°C
Human Body Model
4000
V
Charged-Device Model
1000
V
Machine Model
200
V
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
Short-circuit to ground, one channel at a time.
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ELECTRICAL CHARACTERISTICS
Boldface limits apply over the specified temperature range, TA = –40°C to +85°C.
At TA = +25°C, VS = +18V, VSD = +2V, RL = 1.5kΩ connected to ground, and CL = 200pF, unless otherwise noted.
BUF22821
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG GAMMA BUFFER CHANNELS
Reset Value
Code 512
OUT 1–22 Output Swing: High
Code = 1023, Sourcing 10mA
OUT 1–22 Output Swing: Low
Code = 0, Sinking 10mA
STATINH Output Swing: High
VIN = 18V, Sourcing 10mA
STATINL Output Swing: Low
VIN = 0V, Sinking 10mA
VCOM1, 2 Output Swing: High
Code = 1023, Sourcing 100mA
VCOM1, 2 Output Swing: Low
Code = 0, Sinking 100mA
Continuous Output Current
Note
9
17.7
13
Code 512
V
mA
±50
mV
±25
µV/°C
Bits
INL
0.3
Differential Nonlinearity
DNL
0.3
Load Regulation, 10mA
REG
Code 512 or VCC/2, IOUT = +5mA to –5mA Step
V
V
2
30
±20
vs Temperature
V
V
0.2
16.2
0.6
(1)
V
0.2
17.85
0.17
Output Accuracy
Integral Nonlinearity
17.85
0.07
17.7
V
0.5
Bits
1.5
mV/mA
16
Cycles
OTP MEMORY
Number of OTP Write Cycles
Memory Retention
100
Years
ANALOG POWER SUPPLY
Operating Range
Total Analog Supply Current
9
IS
Outputs at Reset Values, No Load
12
Over Temperature
20
V
17
mA
18
mA
DIGITAL
Logic 1 Input Voltage
VIH
Logic 0 Input Voltage
VIL
Logic 0 Output Voltage
VOL
0.7 × VSD
ISINK = 3mA
Input Leakage
Clock Frequency
fCLK
V
0.3 × VSD
V
0.15
0.4
V
±0.01
±10
µA
Standard/Fast Mode
400
kHz
High-Speed Mode
3.4
MHz
DIGITAL POWER SUPPLY
Operating Range
Digital Supply Current
VSD
ISD
2.0
Outputs at Reset Values, No Load, Two-Wire Bus Inactive
115
Over Temperature
5.5
V
150
µA
µA
115
TEMPERATURE RANGE
Specified Range
Operating Range
Junction Temperature < +125°C
Storage Range
Thermal Resistance (1)
HTSSOP-38
(1)
–40
+85
°C
–40
+95
°C
–65
+150
°C
θJA
Note
(1)
40
°C/W
Thermal pad attached to printed circuit board (PCB), 0lfm airflow, and 76mm × 76mm copper area.
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PIN CONFIGURATIONS
BUF22821
HTSSOP-38
Top View
VCOM2
1
38
VCOM1
STATINH
2
37
STATINL
OUT21
3
36
OUT20
OUT22
4
35
OUT19
OUT1
5
34
STATOUTL
OUT2
6
33
OUT18
OUT3
7
32
OUT17
OUT4
8
31
OUT16
OUT5
9
30
OUT15
OUT6
10
29
OUT14
(1)
11
28
GNDA
VS
12
27
VS
OUT7
13
26
OUT13
OUT8
14
25
OUT12
OUT9
15
24
OUT11
STATOUTH
16
23
OUT10
VSD
17
22
GNDD
SCL
18
21
BKSEL
SDA
19
20
A0
GNDA
PowerPAD
Lead-Frame
Die Pad
Exposed on
Underside
(must connect to
GNDA and GNDD)
(1)
(1)
NOTE: (1) GNDA and GNDD must be connected together.
4
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PIN CONFIGURATIONS (continued)
PIN DESCRIPTIONS
PIN #
NAME
DESCRIPTION
1
VCOM2
VCOM channel 2
2
STATINH
3
OUT21
DAC output 21
4
OUT22
DAC output 22
5
OUT1
DAC output 1
6
OUT2
DAC output 2
7
OUT3
DAC output 3
8
OUT4
DAC output 4
9
OUT5
DAC output 5
10
OUT6
DAC output 6
11, 28
GNDA
Analog ground; must be connected to digital ground (GNDD).
12, 27
VS
13
OUT7
DAC output 7
14
OUT8
DAC output 8
15
OUT9
DAC output 9
16
STATOUTH
Static gamma input high; voltage can be set by external voltage divider.
VS connected to analog supply
Static gamma output high; connect to gamma input on source driver that is closest to VS.
17
VSD
Digital supply; connect to logic supply
18
SCL
Serial clock input; open-drain, connect to pull-up resistor.
19
SDA
Serial data I/O; open-drain, connect to pull-up resistor.
20
A0
21
BKSEL
Selects memory bank 0 or 1; either connect to logic 1 to select bank 1 or logic 0 to select bank 0.
22
GNDD
Digital ground; must be connected to analog ground at the BUF22821.
23
OUT10
DAC output 10
24
OUT11
DAC output 11
25
OUT12
DAC output 12
26
OUT13
DAC output 13
29
OUT14
DAC output 14
30
OUT15
DAC output 15
31
OUT16
DAC output 16
32
OUT17
DAC output 17
33
OUT18
DAC output 18
34
STATOUTL
35
OUT19
DAC output 19
36
OUT20
DAC output 20
37
STATINL
38
VCOM1
A0 address pin for I2C address; either connect to logic 1 or logic 0.
Static gamma output low; connect to gamma input on source driver that is closest to GND
Static gamma input low; voltage can be set by external voltage divider
VCOM channel 1
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TYPICAL CHARACTERISTICS
At TA = +25°C, VS = +18V, VSD = +2V, RL = 1.5kΩ connected to ground, and CL = 200pF, unless otherwise noted.
18.0
17.5
17.0
16.5
16.0
15.5
15.0
3.0
2.5
2.0
1.5
1.0
0.5
0
0
25
50
75
100
125
150
0
75
100
125
Figure 2.
OUTPUT VOLTAGE vs OUTPUT CURRENT
(STATOUTL)
OUTPUT VOLTAGE vs OUTPUT CURRENT
(STATOUTH)
25
50
75
100
125
0
150
25
50
75
100
Output Current (mA)
Figure 3.
Figure 4.
14.0
118
13.5
114
112
110
108
106
104
125
150
ANALOG SUPPLY CURRENT vs TEMPERATURE
120
116
150
18.0
17.5
17.0
16.5
16.0
15.5
15.0
3.0
2.5
2.0
1.5
1.0
0.5
0
Output Current (mA)
Analog Supply Current (mA)
Digital Supply Current (mA)
50
Figure 1.
DIGITAL SUPPLY CURRENT vs TEMPERATURE
13.0
12.5
12.0
11.5
11.0
10.5
10.0
102
9.5
100
-50
6
25
Output Current (mA)
18.0
17.5
17.0
16.5
16.0
15.5
15.0
3.0
2.5
2.0
1.5
1.0
0.5
0
0
18.0
17.5
17.0
16.5
16.0
15.5
15.0
3.0
2.5
2.0
1.5
1.0
0.5
0
Output Current (mA)
Output Voltage (V)
Output Voltage (V)
OUTPUT VOLTAGE vs OUTPUT CURRENT
(Channels 1–22)
Output Voltage (V)
Output Voltage (V)
OUTPUT VOLTAGE vs OUTPUT CURRENT
(VCOM1 and VCOM2)
-25
0
25
50
75
100
125
-50
-25
0
25
50
Temperature (°C)
Temperature (°C)
Figure 5.
Figure 6.
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75
100
125
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SBOS399 – JUNE 2007
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = +18V, VSD = +2V, RL = 1.5kΩ connected to ground, and CL = 200pF, unless otherwise noted.
OUTPUT VOLTAGE vs TEMPERATURE
INTEGRAL LINEARITY ERROR
9.020
0.15
10 Typical Units Shown
9.015
0.10
9.005
Error (LSB)
Initial Voltage (V)
9.010
9.000
8.995
0.05
0
-0.05
8.990
-0.10
8.985
8.980
-0.15
-50
-25
0
25
50
100
75
125
0
200
Temperature (°C)
400
600
800
1000
Input Code
Figure 7.
Figure 8.
DIFFERENTIAL LINEARITY ERROR
BKSEL SWITCHING TIME DELAY
0.15
0.10
780ms
0
9V
-0.05
DAC Channel
(2V/div)
-0.10
5V
-0.15
0
200
400
600
800
1ms/div
1000
Input Code
Figure 9.
Figure 10.
LARGE-SIGNAL STEP RESPONSE
Output Voltage (2V/div)
Error (LSB)
BKSEL (2V/div)
0.05
Time (1ms/div)
Figure 11.
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APPLICATION INFORMATION
GENERAL
The BUF22821 programmable voltage reference
allows fast and easy adjustment of 22 programmable
gamma reference outputs and two VCOM outputs,
each with 10-bit resolution. The BUF22821 is
programmed through a high-speed, I2C interface.
The final gamma and VCOM values can be stored in
the on-chip, nonvolatile memory. To allow for
programming errors or liquid crystal display (LCD)
panel rework, the BUF22821 supports up to 16 write
operations to the on-chip memory. The BUF22821
has two separate banks of memory, allowing
simultaneous storage of two different gamma curves
to facilitate dynamic switching between gamma
curves.
The BUF22821 can be powered using an analog
supply voltage from 9V to 20V, and a digital supply
from 2V to 5.5V. The digital supply must be applied
prior to the analog supply to avoid excessive current
and power consumption, or possibly even damage to
the device if left connected only to the analog supply
for extended periods of time. A typical configuration
of the BUF22821 is illustrated in Figure 12.
TWO-WIRE BUS OVERVIEW
The
BUF22821
communicates
through
an
industry-standard, two-wire interface to receive data
in slave mode. This standard uses a two-wire,
open-drain interface that supports multiple devices
on a single bus. Bus lines are driven to a logic low
level only. The device that initiates the
communication is called a master, and the devices
controlled by the master are slaves. The master
generates the serial clock on the clock signal line
(SCL), controls the bus access, and generates the
START and STOP conditions.
To address a specific device, the master initiates a
START condition by pulling the data signal line
(SDA) from a HIGH to a LOW logic level while SCL
is HIGH. All slaves on the bus shift in the slave
address byte on the rising edge of SCL, with the last
bit indicating whether a read or write operation is
intended. During the ninth clock pulse, the slave
being addressed responds to the master by
generating an Acknowledge and pulling SDA LOW.
Data transfer is then initiated and eight bits of data
are sent, followed by an Acknowledge bit. During
data transfer, SDA must remain stable while SCL is
HIGH. Any change in SDA while SCL is HIGH is
interpreted as a START or STOP condition.
Once all data have been transferred, the master
generates a STOP condition, indicated by pulling
SDA from LOW to HIGH while SCL is HIGH. The
BUF22821 can act only as a slave device; therefore,
it never drives SCL. SCL is an input only for the
BUF22821.
ADDRESSING THE BUF22821
The address of the BUF22821 is 111010x, where x
is the state of the A0 pin. When the A0 pin is LOW,
the device acknowledges on address 74h (1110100).
If the A0 pin is HIGH, the device acknowledges on
address 75h (1110101). The A0 pin settings and
BUF22821 address options are shown in Table 1.
Other valid addresses are possible through a simple
mask change. Contact your TI representative for
information.
Table 1. Quick-Reference Table of BUF22821
Addresses
DEVICE/COMPONENT
BUF22821 Address:
ADDRESS
A0 pin is LOW
(device acknowledges on address 74h)
1110100
A0 pin is HIGH
(device acknowledges on address 75h)
1110101
Table 2. Quick-Reference Table of Command Codes
COMMAND
8
CODE
General Call Reset
Address byte of 00h followed by a data byte of 06h.
High-Speed Mode
00001xxx, with SCL ≤ 400kHz; where xxx are bits unique to the Hs-capable master. This
byte is called the Hs master code.
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BUF22821
(1)
VCOM2
VS
(1)
(1)
38
VCOM1
STATINL
37
VS
OUT21
OUT20
36
4
OUT22
OUT19
35
5
OUT1
STATOUTL
34
6
OUT2
OUT18
33
VCOM2
2
STATINH
3
(1)
(1)
Source
Driver
(1)
100nF
10mF
32
8
OUT4
OUT16
31
9
OUT5
OUT15
30
10
OUT6
OUT14
29
11
GNDA
(2)
28
12
VS
VS
27
13
OUT7
OUT13
26
14
OUT8
OUT12
25
(1)
(1)
Source
Driver
(1)
3.3V
1 mF
(1)
(1)
(1)
(2)
GNDA
10mF
VS
(1)
Source
Driver
(1)
OUT9
OUT11
24
16
STATOUTH
OUT10
23
17
VSD
(2)
22
18
SCL
BKSEL
21
19
SDA
AO
20
100nF
100nF
(1)
15
(1)
Source
Driver
(1)
OUT17
(1)
(1)
(1)
OUT3
(1)
(1)
(1)
7
(1)
VS
(1)
VCOM1
1
(1)
GNDD
Timing
Controller
(1) RC combination optional.
(2) GNDA and GNDD must be connected together.
Figure 12. Typical Application Configuration
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DATA RATES
OUTPUT VOLTAGE
The two-wire bus operates in one of three speed
modes:
• Standard: allows a clock frequency of up to
100kHz;
• Fast: allows a clock frequency of up to 400kHz;
and
• High-speed mode (also called Hs mode): allows a
clock frequency of up to 3.4MHz.
Buffer output values are determined by the analog
supply voltage (VS) and the decimal value of the
binary input code used to program that buffer. The
value is calculated using Equation 1:
CODE10
VOUT = VS ´
1024
(1)
The BUF22821 is fully compatible with all three
modes. No special action is required to use the
device in Standard or Fast modes, but High-speed
mode must be activated. To activate High-speed
mode, send a special address byte of 00001xxx, with
SCL = 400kHz, following the START condition;
where xxx are bits unique to the Hs-capable master,
which can be any value. This byte is called the Hs
master code. (Note that this is different from normal
address bytes—the low bit does not indicate
read/write status.) The BUF22821 responds to the
High-speed command regardless of the value of
these last three bits. The BUF22821 does not
acknowledge this byte; the communication protocol
prohibits acknowledgement of the Hs master code.
On receiving a master code, the BUF22821 switches
on its Hs mode filters, and communicates at up to
3.4MHz. Additional high-speed transfers may be
initiated without resending the Hs mode byte by
generating a repeat START without a STOP. The
BUF22821 switches out of Hs mode with the next
STOP condition.
GENERAL-CALL RESET AND POWER-UP
The BUF22821 responds to a General-Call Reset,
which is an address byte of 00h (0000 0000)
followed by a data byte of 06h (0000 0110). The
BUF22821 acknowledges both bytes. Upon receiving
a General-Call Reset, the BUF22821 performs a full
internal reset, as though it had been powered off and
then on. It always acknowledges the General-Call
address byte of 00h (0000 0000), but does not
acknowledge any General-Call data bytes other than
06h (0000 0110).
When the BUF22821 powers up, it automatically
performs a reset. As part of the reset, the BUF22821
is configured for all outputs to change to the last
programmed nonvolatile memory values, or
1000000000 if the nonvolatile memory values have
not been programmed.
10
The BUF22821 outputs are capable of a full-scale
voltage output change in typically 5µs—no
intermediate steps are required.
UPDATING THE DAC OUTPUTS
Because the BUF22821 features a double-buffered
register structure, updating the digital-to-analog
converter (DAC) and/or the VCOM register is not the
same as updating the DAC and/or VCOM output
voltage. There are two methods for updating the
DAC/VCOM output voltages.
Method 1: Method 1 is used when it is desirable to
have the DAC/VCOM output voltage change
immediately after writing to a DAC register. For each
write transaction, the master sets data bit 15 to a '1'.
The DAC/VCOM output voltage update occurs after
receiving the 16th data bit for the currently-written
register.
Method 2: Method 2 is used when it is desirable to
have all DAC/VCOM output voltages change at the
same time. First, the master writes to the desired
DAC/VCOM channels with data bit 15 a '0'. Then,
when writing the last desired DAC/VCOM channel, the
master sets data bit 15 to a '1'. All DAC/VCOM
channels are updated at the same time after
receiving the 16th data bit.
NONVOLATILE MEMORY
BKSEL Pin
The BUF22821 has 16x rewrite capability of the
nonvolatile memory. Additionally, the BUF22821 has
the ability to store two distinct gamma curves in two
different nonvolatile memory banks, each of which
has 16x rewrite capability. One of the two available
banks is selected using the external input pin,
BKSEL. When this pin is low, BANK0 is selected;
when this pin is high, BANK1 is selected.
When the BKSEL pin changes state, the BUF22821
acquires the last programmed DAC/VCOM values
from the nonvolatile memory associated with this
newly chosen bank. At power-up, the state of the
BKSEL pin determines which memory bank is
selected.
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The I2C master also has the ability to update
(acquire) the DAC registers with the last
programmed nonvolatile memory values using
software control. The bank to be acquired depends
on the state of BKSEL.
Approximately 36µs (±4µs) after issuing this
command, the specified DAC/VCOM register and
DAC/VCOM output voltage change to the appropriate
OTP memory value.
MaxBank
General Acquire Command
A general acquire command is used to update all
registers and DAC/VCOM outputs to the last
programmed values stored in nonvolatile memory. A
single-channel acquire command updates only the
register and DAC/VCOM output of the DAC/VCOM
corresponding to the DAC/VCOM address used in the
single-channel acquire command.
The sequence to initiate a general channel acquire is
as follows:
1. Be sure BKSEL is in its desired state and has
been stable for at least 1ms.
2. Send a START condition on the bus.
3. Send the appropriate device address (based
on A0) and the read/write bit = LOW. The
BUF22821 acknowledges this byte.
4. Send a DAC/VCOM pointer address byte. Set
bit D7 = 1 and D6 = 0. Bits D5–D0 are any
valid DAC/VCOM address. Only addresses
000000 to 010111 are valid and are
acknowledged. See Table 5 for valid
DAC/VCOM addresses.
5. Send a STOP condition on the bus.
Approximately 750µs (±80µs) after issuing this
command, all DAC/VCOM registers and DAC/VCOM
output voltages change to the respective, appropriate
nonvolatile memory values.
The BUF22821 can provide the user with the number
of times the nonvolatile memory of a particular
DAC/VCOM channel nonvolatile memory has been
written to for the current memory bank. This
information is provided by reading the register at
pointer address 111111.
There are two ways to update the MaxBank register:
1. After initiating a single-acquire comand, the
BUF22821 updates the MaxBank register with
a code corresponding to how many times that
particular channel memory has been written
to.
2. Following a general-acquire command, the
BUF22821 updates the MaxBank register with
a code corresponding to the maximum
number of times the most used channel
(OUT1–22 and VCOMs) has been written to.
MaxBank is a read-only register and is only updated
by performing a general- or single-channel acquire.
Table 3 shows the relationship between the number
of times the nonvolatile memory has been
programmed and the corresponding state of the
MaxBank Register.
Table 3. MaxBank Details
TIMES WRITTEN TO
RETURNS CODE
0
0000
1
0000
2
0001
3
0010
4
0011
5
0100
6
0101
7
0110
8
0111
9
1000
10
1001
11
1010
12
1011
13
1100
14
1101
15
1110
16
1111
Single-Channel Acquire Command
The sequence to initiate a single-channel acquire is
as follows:
1. Be sure BKSEL is in its desired state and has
been stable for at least 1ms.
2. Send a START condition on the bus.
3. Send the device address (based on A0) and
read/write bit = LOW. The BUF22821
acknowledges this byte.
4. Send a DAC/VCOM pointer address byte using
the DAC/VCOM address corresponding to the
output and register to update with the OTP
memory value. Set bit D7 = 0 and D6 = 1. Bits
D5–D0 are the DAC/VCOM address. Only
addresses 000000 to 010111 are valid and
are acknowledged. See Table 5 for valid
DAC/VCOM addresses.
5. Send a STOP condition on the bus.
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SBOS399 – JUNE 2007
Parity Error Correction
The BUF22821 provides single-bit parity error
correction for data stored in the nonvolatile memory
to provide increased reliability of the nonvolatile
memory. Should a single bit of nonvolatile memory
for a channel fail, the BUF22821 corrects for it and
updates the appropriate DAC with the intended value
when its memory is acquired.
Should more than one bit of nonvolatile memory for a
channel fail, the BUF22821 does not correct for it,
and updates the appropriate DAC/VCOM with the
default value of 1000000000.
DIE_ID AND DIE_REV REGISTERS
The user can verify the presence of the BUF22821 in
the system by reading from address 111101. The
BUF22821 returns 0101100100100101 when read at
this address.
The user can also determine the die revision of the
BUF22821 by reading from register 111100. The
BUF22821 returns 0000000000000000 when a RevA
die is present. RevB would be designated by
0000000000000001 and so on.
READ/WRITE OPERATIONS
Read and write operations can be done for a single
DAC/VCOM or for multiple DACs/VCOMs. Writing to a
DAC/VCOM register differs from writing to the
nonvolatile memory. Bits D15–D14 of the most
significant byte of data determines if data are written
to the DAC/VCOM register or the nonvolatile memory.
Read/Write: DAC/VCOM Register (volatile memory)
The BUF22821 is able to read from a single
DAC/VCOM, or multiple DACs/VCOMs, or write to the
register of a single DAC/VCOM, or multiple
DACs/VCOMs in a single communication transaction.
DAC pointer addresses begin with 000000 (which
corresponds to OUT1) through 010111 (which
corresponds to OUT22).
Write commands are performed by setting the
read/write bit LOW. Setting the read/write bit HIGH
performs a read transaction.
Writing: DAC/VCOM Register (volatile memory)
To write to a single DAC/VCOM register:
1. Send a START condition on the bus.
2. Send the device address and read/write bit =
LOW. The BUF22821 acknowledges this byte.
3. Send a DAC/VCOM pointer address byte. Set
bit D7 = 0 and D6 = 0. Bits D5–D0 are the
DAC/VCOM address. Only addresses 000000
to 010111 are valid and are acknowledged;
see Table 5 for valid addresses.
12
4. Send two bytes of data for the specified
register. Begin by sending the most significant
byte first (bits D15–D8, of which only bits D9
and D8 are used, and bits D15–D14 must not
be 01), followed by the least significant byte
(bits D7–D0). The register is updated after
receiving the second byte.
5. Send a STOP or START condition on the bus.
The BUF22821 acknowledges each data byte. If the
master terminates communication early by sending a
STOP or START condition on the bus, the specified
register is not updated. Updating the DAC/VCOM
register is not the same as updating the DAC/VCOM
output voltage; see the Output Latch section.
The process of updating multiple DAC/VCOM registers
begins the same as when updating a single register.
However, instead of sending a STOP condition after
writing the addressed register, the master continues
to send data for the next register. The BUF22821
automatically and sequentially steps through
subsequent registers as additional data are sent. The
process continues until all desired registers have
been updated or a STOP or START condition is
sent.
To write to multiple DAC/VCOM registers:
1. Send a START condition on the bus.
2. Send the device address and read/write bit =
LOW. The BUF22821 acknowledges this byte.
3. Send either the OUT1 pointer address byte to
start at the first DAC, or send the pointer
address byte for whichever DAC/VCOM is the
first in the sequence of DACs/VCOMs to be
updated. The BUF22821 begins with this
DAC/VCOM and steps through subsequent
DACs/VCOMs in sequential order.
4. Send the bytes of data; begin by sending the
most significant byte (bits D15–D8, of which
only bits D9 and D8 have meaning, and bits
D15–D14 must not be 01), followed by the
least significant byte (bits D7–D0). The first
two bytes are for the DAC/VCOM addressed in
the previous step. The DAC/VCOM register is
automatically updated after receiving the
second byte. The next two bytes are for the
following DAC/VCOM. That DAC/VCOM register
is updated after receiving the fourth byte. This
process continues until the registers of all
following DACs/VCOMs have been updated.
5. Send a STOP or START condition on the bus.
The BUF22821 acknowledges each byte. To
terminate communication, send a STOP or START
condition on the bus. Only DAC registers that have
received both bytes of data are updated.
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SBOS399 – JUNE 2007
Reading:
memory)
DAC/VCOM/OTHER
Register
(volatile
8. When all desired DACs have been read, send
a STOP or START condition on the bus.
Reading a register returns the data stored in that
DAC/VCOM/OTHER register.
Communication may be terminated by sending a
premature STOP or START condition on the bus, or
by not sending the acknowledge bit. The reading of
registers DieID, DieRev, and MaxBank is not
supported in this mode of operation (they must be
read using the single register read method).
To read a single DAC/VCOM/OTHER register:
1. Send a START condition on the bus.
2. Send the device address and read/write bit =
LOW. The BUF22821 acknowledges this byte.
3. Send the DAC/VCOM/OTHER pointer address
byte. Set bit D7 = 0 and D6 = 0; bits D5–D0
are the DAC/VCOM/OTHER address. Only
addresses 000000–010111, 111100, 111101,
and 111111 are valid and are acknowledged.
4. Send a START or STOP/START condition.
5. Send the correct device address and
read/write bit = HIGH. The BUF22821
acknowledges this byte.
6. Receive two bytes of data. They are for the
specified register. The most significant byte
(bits D15–D8) is received first; next is the
least significant byte (bits D7–D0). In the case
of DAC/VCOM channels, bits D15–D10 have no
meaning.
7. Acknowledge after receiving the first byte.
8. Send a STOP or START condition on the bus
or do not acknowledge the second byte to end
the read transaction.
Communication may be terminated by sending a
premature STOP or START condition on the bus, or
by not acknowledging.
To read multiple registers:
1. Send a START condition on the bus.
2. Send the device address and read/write bit =
LOW. The BUF22821 acknowledges this byte.
3. Send either the OUT1 pointer address byte to
start at the first DAC, or send the pointer
address byte for whichever register is the first
in the sequence of DACs/VCOMs to be read.
The BUF22821 begins with this DAC/VCOM
and steps through subsequent DACs/VCOMs in
sequential order.
4. Send a START or STOP/START condition on
the bus.
5. Send the correct device address and
read/write bit = HIGH. The BUF22821
acknowledges this byte.
6. Receive two bytes of data. They are for the
specified DAC/VCOM. The first received byte is
the most significant byte (bits D15–D8, only
bits D9 and D8 have meaning), next is the
least significant byte (bits D7–D0).
7. Acknowledge after receiving each byte of
data.
Write: Nonvolatile Memory for the DAC Register
The BUF22821 is able to write to the nonvolatile
memory of a single DAC/VCOM in a single
communication transaction. In contrast to the
BUF20820, writing to multiple nonvolatile memory
words in a single transaction is not supported. Valid
DAC/VCOM pointer addresses begin with 000000
(which corresponds to OUT1) through 010111 (which
corresponds to OUT22).
When programming the nonvolatile memory, the
analog supply voltage must be between 9V and 20V.
Write commands are performed by setting the
read/write bit LOW.
To write to a single nonvolatile register:
1. Send a START condition on the bus.
2. Send the device address and read/write bit =
LOW. The BUF22821 acknowledges this byte.
Only addresses 000000 to 010111 are valid
and are acknowledged. See Table 5 for
DAC/VCOM addresses.
3. Send a DAC/VCOM pointer address byte. Set
bit D7 = 0 and D6 = 0. Bits D5–D0 are the
DAC/VCOM address.
4. Send two bytes of data for the nonvolatile
register of the specified DAC/VCOM. Begin by
sending the most significant byte first (bits
D15–D8, of which only bits D9 and D8 are
data bits, and bits D15–D14 must be 01),
followed by the least significant byte (bits
D7–D0). The register is updated after
receiving the second byte.
5. Send a STOP condition on the bus.
The BUF22821 acknowledges each data byte. If the
master terminates communication early by sending a
STOP or START condition on the bus, the specified
nonvolatile register is not updated. Writing a
nonvolatile register also updates the DAC/VCOM
register and output voltage.
The DAC/VCOM register and DAC/VCOM output
voltage are updated immediately, while the
programming of the nonvolatile memory takes up to
250µs. Once a nonvolatile register write command
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SBOS399 – JUNE 2007
has been issued, no communication with the
BUF22821 should take place for at least 250µs.
Writing or reading over the serial interface while the
nonvolatile memory is being written jeopardizes the
integrity of the data being stored.
Table 4. Other Register Pointer Addresses
REGISTER
POINTER ADDRESS
Die_Rev
111100
Die_ID
111101
MaxBank
111111
Read: Nonvolatile Memory for the DAC Register
To read the data present in nonvolatile register for a
particular DAC/VCOM channel, the master must first
issue
a
general-acquire
command,
or
a
single-acquire command with the appropriate
DAC/VCOM channel chosen. This action updates both
the DAC/VCOM register(s) and DAC/VCOM output
voltage(s). The master may then read from the
appropriate DAC/VCOM register as described earlier.
Table 5. DAC Register Pointer Addresses
14
REGISTER
POINTER ADDRESS
OUT1
000000
OUT2
000001
OUT3
000010
OUT4
000011
OUT5
000100
OUT6
000101
OUT7
000110
OUT8
000111
OUT9
001000
OUT10
001001
OUT11
001010
OUT12
001011
OUT13
001100
OUT14
001101
OUT15
001110
OUT16
001111
OUT17
010000
OUT18
010001
VCOM1
010010
VCOM2
010011
OUT19
010100
OUT20
010101
OUT21
010110
OUT22
010111
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Figure 13. Write DAC Register Timing
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A4
A4
A6
A6
SDA_In
Device_Out
Start
A3
A3
A5
A5
A4
A4
A5
A5
A4
A4
A3
A3
Device Address
A2
A2
A5
A5
A4
A4
A3
A3
Device Address
A2
A2
A1
A1
A1
A1
A3
A3
Device Address
Read multiple DAC registers. P4-P0 specify DAC address.
A6
SCL
A6
SDA_In
Start
Device_Out
SCL
A5
A5
Read single DAC register. P4-P0 specify DAC address.
A6
A6
SDA_In
Start
Device_Out
SCL
A6
Device Address
A2
A2
A1
A1
A0
A0
A0
A0
A2
A2
W
W
Write
W
W
Write
A1
A1
Write multiple DAC register. P4-P0 specify DAC address.
A6
SDA_In
Device_Out
SCL
Start
Write single DAC register. P4-P0 specify DAC address.
Ackn
Ackn
Ackn
W
D7
W
D7
D7
D7
Read operation.
Ackn
Ackn
Ackn
W
W
Write
Read operation.
A0
A0
A0
A0
Write
D7
D7
D7
D7
D5
D5
D6
D6
D5
D5
D5
D5
P4
P4
P3
P3
P2
P2
P4
D6
D6
D5
D5
P4
P4
P3
P3
P2
P2
P1
P1
P1
P1
P4
Start DAC address pointer. D7-D5 must be 000.
D6
D6
P4
P4
P3
P3
P2
P2
P0
P0
P0
P0
P3
P3
Ackn
Ackn
Ackn
Ackn
Ackn
Ackn
P2
P2
P1
P1
P1
P1
Start
Start
DAC address pointer. D7-D5 must be 000.
D6
D6
DAC address pointer. D7-D5 must be 000.
DAC address pointer. D7-D5 must be 000.
Ackn
Ackn
Ackn
Write Operation
Ackn
Ackn
Ackn
Write Operation
D14
D14
D15
D14
D14
A3
A3
A4
A3
A3
Device Address
A4
D14
D14
D15
D13
D13
D11
D11
D10
D10
D13
D13
D12
D12
D11
D11
D10
D10
DAC (pointer) MSbyte. D14 must be 0.
Device Address
A4
D12
D12
D9
D9
D8
D8
Ackn
Ackn
D7
D7
D9
D9
D8
D8
Ackn
Ackn
Ackn
D7
D7
A2
A2
A2
A2
A1
A1
A1
A1
A0
A0
A0
A0
D12
D12
D11
D11
D10
D10
D9
D9
D8
D8
R
R
Read
R
R
Ackn
Ackn
Ackn
Ackn
Ackn
Ackn
Ackn
D7
D7
D15
D15
D15
D11
D11
D10
D10
D9
D9
D6
D6
D6
D6
D8
D8
D13
D12
D12
D11
D11
D10
D10
D6
D6
D14
D14
D5
D5
D13
D13
D11
D11
D4
D4
D3
D3
DAC 20 LSbyte.
D12
D12
D2
D2
D10
D10
D4
D4
D3
D3
DAC LSbyte
D9
D9
Ackn
Ackn
Ackn
D5
D5
D1
D1
D9
D9
D0
D0
D8
D8
D8
D8
D4
D4
Ackn
D1
D1
D0
D0
Ackn
Ackn
Ackn
D2
D1
D1
D0
D0
Ackn
Ackn
D7
D7
D6
D6
D5
D5
D5
D5
D4
D4
D2
D2
D4
D4
D3
D3
DAC LSbyte.
D3
D3
DAC 20 LSbyte
is updated in this moment.
Stop
D2
D2
D1
D1
D15
D15
D1
D1
D14
D14
D0
D0
D0
D0
Stop
Stop
No Ackn
No Ackn
Ackn
Ackn
Ackn
D13
D13
DAC (pointer + 1) MSbyte. D14 must be 0.
The whole DAC register D9-D0
D2
Ackn
is updated in this moment.
The whole DAC register D9-D0
D2
D2
Stop
D6
D6
Ackn
Ackn
Ackn
Ackn
Ackn
Ackn
Ackn
Ackn
D7
D7
D3
D3
DAC (pointer) LSbyte
D5
D5
DAC (pointer) MSbyte. D15-D10 have no meaning.
D14
D13
DAC MSbyte. D15-D10 have no meaning.
D14
D12
D13
D15
D12
D13
Ackn
Ackn
D14
D15
Read
D14
D15
DAC 20 (VCOM OUT2) MSbyte. D14 must be 0.
If D15 = 1, all DACs are updated when the current DAC register is updated.
D15
A4
D13
D13
Ackn
If D15 = 1, all DACs are updated when the current DAC register is updated.
D15
D15
DAC MSbyte. D14 must be 0.
DAC 20 (VCOM OUT2) MSbyte. D15-D10 have no meaning.
A5
A5
A5
A5
Ackn
Ackn
Ackn
Ackn
Ackn
D15
A6
A6
A6
A6
P0
P0
P0
P0
Ackn
BUF22821
www.ti.com
SBOS399 – JUNE 2007
Figure 14. Read Register Timing
15
16
A6
A6
SDA_In
Device_Out
SCL
Start
A5
A5
A4
A4
A3
A3
Device Address
Figure 15. Write Nonvolatile Register Timing
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A1
A0
W
W
Ackn
Ackn
D6
D6
D5
D5
P4
P4
P3
P3
P2
P2
A5
A5
A4
A4
A3
A3
Device address.
A2
A2
A1
A1
P1
A0
A0
P1
A6
A6
SDA_In
Device_Out
Start
A5
A5
A4
A4
A3
A3
Device address.
A2
A2
A1
A1
A0
A0
P0
W
W
W
Write
W
Ackn
Ackn
Ackn
D15
D15
D7
D7
Ackn
Ackn
Ackn
D7
D7
Write Operation
Ackn
Ackn
Ackn
Write Operation
P0
Write
Single channel acquire command. P4-P0 must specify and valid DAC address.
A6
Start
A6
SCL
D7
D7
DAC address pointer. D7-D0 must be 000.
General acquire command. P4-P0 must specify and valid DAC address.
A0
Ackn
Write operation.
Device_Out
SCL
A1
Write
SDA_In
A2
A2
Write single OTP register. P4-P0 specify DAC address.
D14
D13
D13
D12
D12
D11
D11
D10
D10
D9
D9
D5
P4
P4
P3
P3
P2
P2
D6
D6
D5
D5
P4
P4
P3
P3
P2
P2
DAC address pointer. D7-D5 must be 010.
D6
D5
DAC address pointer. D7-D5 must be 100.
D6
D14
DAC MSbyte. D15-D14 must be 01.
D8
P1
P1
P1
P1
D8
P0
P0
P0
P0
Ackn
Ackn
Ackn
D7
D6
D6
Ackn
Ackn
Ackn
Ackn
Ackn
Ackn
D7
D5
Stop
Stop
D5
D4
D4
D2
D2
D1
D1
D0
D0
Ackn
Ackn
Ackn
t2
Stop
t2: minimum 100ms, maximum 2ms.
The OTP register (D9-D0) is updated in this moment.
t1: > 20ms before falling edge of clock.
D3
D3
DAC LSbyte.
Write supply active.
Write signal active.
t1
BUF22821
SBOS399 – JUNE 2007
www.ti.com
Figure 16. Acquire Operation Timing
Figure 17. General-Call Reset Timing
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SDA
SCL
SDA
SCL
Start
High-Speed Command
Start
General-Call Reset Command
Address Byte = 00h
Address Byte = 00001xxx (HS Master Code)
Ackn
Ackn
Device enters high-speed mode at ACK clock pulse.
Device exits high-speed mode with stop condition.
No Ackn
Device begins reset at arrow and is in reset until ACK clock pulse.
Then the device acquires memory, etc as at power-up.
Address Byte = 06h
BUF22821
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SBOS399 – JUNE 2007
Figure 18. High-Speed Mode Timing
17
BUF22821
www.ti.com
SBOS399 – JUNE 2007
STATIC GAMMA CHANNELS
DYNAMIC GAMMA CONTROL
The BUF22821 offers two static gamma buffers.
These two analog signal paths can be used to
provide
additional
gamma
channels.
The
STATOUTH pin is a buffered version of the
STATINH pin. The STATOUTL pin is a buffered
version of the STATINL pin. For typical output swing,
see the Typical Characteristics.
Dynamic gamma control is a technique used to
improve the picture quality in LCD television
applications. This technique typically requires
switching gamma curves between frames. Using the
BKSEL pin to switch between two gamma curves will
not likely lead to good results because of the 750µs
it takes to transfer the data from the nonvolatile
memory to the DAC register. However, dynamic
gamma control can still be accomplished by storing
two gamma curves in an external EEPROM and
writing directly to the DAC register (nonvolatile).
END-USER SELECTED GAMMA CONTROL
Because the BUF22821 has two banks of nonvolatile
memory, it is well-suited for providing two levels of
gamma control by using the BKSEL pin, as shown in
Figure 19. When the state of the BKSEL pin
changes,
the
BUF22821
updates
all
24
programmable buffer outputs simultaneously after
750µs (±80µs).
To update all 24 programmable output voltages
simultaneously via hardware:
Toggle the BKSEL pin to switch between Gamma
Curve 0 (stored in Bank0) and Gamma Curve 1
(stored in Bank1).
All DAC/VCOM registers and output voltages are
updated simultaneously after approximately 750µs.
The double register input structure saves
programming time by allowing updated DAC values
to be pre-stored into the first register bank. Storage
of this data can occur while a picture is still being
displayed. Because the data are only stored into the
first register bank, the DAC/VCOM output values
remain unchanged—the display is unaffected. At the
beginning or the end of a picture frame, the
DAC/VCOM outputs (and therefore, the gamma
voltages) can be quickly updated by writing a '1' in bit
15 of any DAC/VCOM register. For details on the
operation of the double register input structure, see
the Updating the DAC Outputs section.
To update all 24 programmable output voltages
simultaneously via software:
5V
BUF22821
STEP 1: Write to registers 1–24 with bit 15 always
'0'.
BKSEL
STEP 2: Write any DAC/VCOM register a second time
with identical data. Make sure that bit 15 is set to '1'.
All DAC/VCOM channels are updated simultaneously
after receiving the last bit of data.
OUT1
Change in
Output Voltages
BANK0
BANK1
Switch
OUT22
2
IC
Figure 19. Gamma Control
18
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Oct-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
BUF22821AIDCPR
ACTIVE
HTSSOP
DCP
Pins Package Eco Plan (2)
Qty
38
2000
Pb-Free
(RoHS)
Lead/Ball Finish
CU NIPDAU
MSL Peak Temp (3)
Level-3-260C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Oct-2007
TAPE AND REEL BOX INFORMATION
Device
BUF22821AIDCPR
Package Pins
DCP
38
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
SITE 60
330
16
6.9
10.2
1.8
12
Pack Materials-Page 1
W
Pin1
(mm) Quadrant
16
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Oct-2007
Device
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
BUF22821AIDCPR
DCP
38
SITE 60
346.0
346.0
33.0
Pack Materials-Page 2
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