CAT1163 Supervisory Circuits with I2C Serial Serial CMOS EEPROM, Precision Reset Controller and Watchdog Timer (16K) EEPROM memory (16K) with hardware memory write protection, a system power supervisor with brown out protection and a watchdog timer are integrated together in low power CMOS technology. Memory interface is via an I2C bus. FEATURES Watchdog timer input (WDI) 400kHz I2C bus compatible 2.7V to 6.0V operation The 1.6-second watchdog circuit returns a system to a known good state if a software or hardware glitch halts or “hangs” the system. The CAT1163 watchdog monitors the WDI input pin. Low power CMOS technology 16-Byte page write buffer Built-in inadvertent write protection — VCC lock out — Write protect pin, WP The power supply monitor and reset circuit protects memory and system controllers during power up/down and against brownout conditions. Five reset threshold voltages support 5V, 3.3V and 3V systems. If power supply voltages are out of tolerance reset signals become active, preventing the system microcontroller, ASIC or peripherals from operating. Reset signals become inactive typically 200ms after the supply voltage exceeds the reset threshold level. With both active high and low reset signals, interface to microcontrollers and other ICs is simple. In addition, a reset pin can be used as debounced input for pushbutton manual reset capability. Active high or low reset — Precision power supply voltage monitor — 5V, 3.3V and 3V systems — Five threshold voltage options 1,000,000 Program/Erase cycles Manual reset 100 Year data retention 8-pin DIP or 8-pin SOIC Commercial and industrial temperature ranges DESCRIPTION The CAT1163 memory features a 16-byte page. In addition, hardware data protection is provided by a write protect pin WP and by a VCC sense circuit that prevents writes to memory whenever VCC falls below the reset threshold or until VCC reaches the reset threshold during power up. The CAT1163 is a complete memory and supervisory solution for microcontroller-based systems. A serial Available packages include an 8-pin DIP and a surface mount, 8-pin SO package. PIN CONFIGURATION PIN FUNCTIONS For Ordering Information details, see page 13. PDIP 8 Lead SOIC 8 Lead WDI 1 ¯¯¯¯¯¯ RESET 2 WP GND Pin Name Function WDI Warchdog Timer Input ¯¯¯¯¯¯ RESET Active Low Reset I/O 8 VCC 7 RESET 3 6 SCL GND Ground 4 5 SDA SDA Serial Data/Address SCL Clock Input CAT1163 WP RESET VCC © 2007 Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Write Protect Active High Reset I/O Power Supply Doc. No. 3003 Rev. E CAT1163 RESET THRESHOLD OPTION BLOCK DIAGRAM EXTERNAL LOAD SENSEAMPS SHIFT REGISTERS DOUT ACK Part Dash Number Minimum Threshold Maximum Threshold -45 4.50 4.75 -42 4.25 4.50 -30 3.00 3.15 -28 2.85 3.00 -25 2.55 2.70 VCC WORDADDRESS BUFFERS GND COLUMN DECODERS START/STOP LOGIC SDA EEPROM XDEC CONTROL LOGIC WP DATA IN STORAGE HIGHVOLTAGE/ TIMING CONTROL RESET Controller WATCHDOG STATE COUNTERS Precision SCL SLAVE ADDRESS COMPARATORS Vcc Monitor WDI RESET RESET ABSOLUTE MAXIMUM RATINGS(1) Parameters Ratings Units –55 to +125 ºC –65 to +150 ºC –2.0 to VCC + 2.0 V –2.0 to 7.0 V Package Power Dissipation Capability (TA = 25°C) 1.0 W Lead Soldering Temperature (10 secs) 300 ºC 100 mA Temperature Under Bias Storage Temperature Voltage on any Pin with Respect to Ground (2) VCC with Respect to Ground Output Short Circuit Current (3) REABILITY CHARACTERISTICS Symbol NEND TDR (4) (4) VZAP(4) ILTH(4)(5) Parameter Reference Test Method Min Endurance MIL-STD-883, Test Method 1033 1,000,000 Cycles/Byte Data Retention MIL-STD-883, Test Method 1008 100 Years ESD Susceptibility MIL-STD-883, Test Method 3015 2000 Volts JEDEC Standard 17 100 mA Latch-up Max Units Notes: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (3) Output shorted for no more than one second. No more than one output shorted at a time. (4) This parameter is tested initially and after a design or process change that affects the parameter. (5) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC +1V. Doc. No. 3003 Rev. E 2 © 2007 Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT1163 D.C. OPERATING CHARACTERISTICS VCC = 2.7V to 6.0V, unless otherwise specified. Symbol ICC ISB ILI ILO VIL VIH VOL1 Parameter Power Supply Current Standby Current Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage (SDA) Test Conditions fSCL = 100kHz VCC = 3.3V VCC = 5V VIN = GND or VCC VIN = GND or VCC Min Typ -1 VCC x 0.7 IOL = 3 mA, VCC = 3.0V Max 3 40 50 2 10 VCC x 0.3 VCC + 0.5 0.4 Units mA µA µA µA µA V V V CAPACITANCE TA = 25ºC, f = 1.0MHz, VCC = 5V Symbol Test Conditions Max Units CI/O(1) CIN(1) Input/Output Capacitance (SDA) VI/O = 0V 8 pF Input Capacitance (SCL) VIN = 0V 6 pF A.C. CHARACTERISTICS VCC = 2.7V to 6.0V unless otherwise specified. Output Load is 1 TTL Gate and 100pF. Vcc = 2.7V - 6V Vcc = 4.5V – 5.5V Symbol Parameter Min Max Min Max Units FSCL Clock Frequency 100 400 kHz TI(1) Noise Suppresion Time Constant at SCL, SDA Inputs 200 200 ns tAA SLC Low to SDA Data Out and ACK Out 3.5 1 µs tBUF(1) Time the Bus Must be Free Before a New Transmission Can Start tHD:STA Start Condition Hold Time 4.7 1.2 µs 4 0.6 µs tLOW Clock Low Period 4.7 1.2 µs tHIGH Clock High Period 4 0.6 µs 4.7 0.6 µs tSU:STA Start Condition Setup Time (for a Repeated Start Condition) tHD:DAT Data in Hold Time 0 0 ns tSU:DAT Data in Setup Time 50 50 ns (1) SDA and SCL Rise Time 1 0.3 µs (1) SDA and SCL Fall Time 300 300 ns tR tF tSU:STO tDH Stop Condition Setup Time Data Out Hold Time 4 0.6 µs 100 100 ns POWER-UP TIMING (1)(2) Symbol Parameter Max Units tPUR Power-up to Read Operation 1 ms tPUW Power-up to Write Operation 1 ms Notes: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specific operation can be initiated. © 2007 Catalyst Semiconductor, Inc. Characteristics subject to change without notice 3 Doc. No. 3003 Rev. E CAT1163 WRITE CYCLE LIMITS Symbol Parameter tWR Write Cycle Time Min Typ Max Units 10 ms The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address. RESET CIRCUIT CHARACTERISTICS Symbol Parameter tGLITCH Glitch Reject Pulse Width VRT Reset Threshold Hystersis Min Typ Max Units 100 ns 15 mV VOLRS Reset Output Low Voltage (IOLRS=1mA) VOHRS Reset Output High Voltage VCC - 0.75 Reset Threshold (VCC=5V) (CAT1163-45) 4.50 4.75 Reset Threshold (VCC=5V) (CAT1163-42) 4.25 4.50 Reset Threshold (VCC=3.3V) (CAT1163-30) 3.00 3.15 Reset Threshold (VCC=3.3V) (CAT1163-28) 2.85 3.00 Reset Threshold (VCC=3V) (CAT1163-25) 2.55 2.70 Power-Up Reset Timeout 130 270 VTH tPURST tWP Watchdog Period tRPD VTH to RESET Output Delay VRVALID Doc. No. 3003 Rev. E 0.4 V 1.6 1 4 V ms sec 5 RESET Output Valid V µs V © 2007 Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT1163 up/down conditions. It is configured with open drain RESET outputs. During power-up, the RESET outputs remain active until VCC reaches the VTH threshold and will continue driving the outputs for approximately 200ms (tPURST) after reaching VTH. After the tPURST timeout interval, the device will cease to drive the reset outputs. At this point the reset outputs will be pulled up or down by their respective pull up/down resistors. During power-down, the RESET outputs will ¯¯¯¯¯¯ be active when VCC falls below VTH. The RESET outputs will be valid so long as VCC is >1.0V (VRVALID). PIN DESCRIPTION WDI: WATCHDOG INPUT If there is no transition on the WDI for more than 1.6 seconds, the watchdog timer times out. WP: WRITE PROTECT If the pin is tied to VCC the entire memory array becomes Write Protected (READ only). When the pin is tied to GND or left floating normal read/write operations are allowed to the device. The RESET pins are I/Os; therefore, the CAT1163 can act as a signal conditioning circuit for an externally applied manual reset. The inputs are edge triggered; that is, the RESET input in the CAT1163 will initiate a reset timeout after detecting a low to high ¯¯¯¯¯¯ input will initiate a reset transition and the RESET timeout after detecting a high to low transition. ¯¯¯¯¯¯: RESET I/O RESET/RESET These are open drain pins and can be used as reset trigger inputs. By forcing a reset condition on the pins the device will initiate and maintain a reset condition. The RESET pin must be connected through a pull¯¯¯¯¯¯ pin must be connected down resistor, and the RESET through a pull-up resistor. SCL: SERIAL CLOCK Serial clock input. Watchdog Timer The Watchdog Timer provides an independent protection for microcontrollers. During a system failure, the CAT1163 will respond with a reset signal after a time-out interval of 1.6 seconds for a lack of activity. The CAT1163 is designed with the Watchdog Timer feature on the SDA input. If the microcontroller does not toggle the SDA input pin within 1.6 seconds, the Watchdog Timer times out. This will generate a reset condition on reset outputs. The Watchdog Timer is cleared by any transition on WDI. DEVICE OPERATION As long as the reset signal is asserted, the Watchdog Timer will not count and will stay cleared. SDA: SERIAL DATA ADDRESS The bidirectional serial data/address pin is used to transfer all data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs. If there is no transition on the SDA for more than 1.6 seconds, the watchdog timer times out. Reset Controller Description The CAT1163 precision RESET controller ensures correct system operation during brownout and power Figure 1. RESET Output Timing t GLITCH VTH VRVALID VCC t PURST t RPD t PURST RESE T t RPD RESE T © 2007 Catalyst Semiconductor, Inc. Characteristics subject to change without notice 5 Doc. No. 3003 Rev. E CAT1163 Hardware Data Protection The CAT1163 is designed with the following hardware data protection features to provide a high degree of data integrity. whenever VCC falls below (power down) VTH or until VCC reaches the reset threshold (power up) VTH. Any attempt to access the internal EEPROM is not recognized and an ACK will not be sent on ¯¯¯¯¯¯ is active. the SDA line when RESET or RESET (1) The CAT1163 features a WP pin. When the WP pin is tied high the entire memory array becomes write protected (read only). (2) The VCC sense provides write protection when VCC falls below the reset threshold value (VTH). The VCC lock out inhibits writes to the serial EEPROM Reset Threshold Voltage The CAT1163 is offered with five reset threshold voltage ranges. They are 4.50 ÷ 4.75V, 4.25 ÷ 4.50V, 3.00 ÷ 3.15V, 2.85 ÷ 3.00V and 2.55 ÷ 2.70V. Figure 2. Bus Timing tF tHIGH tLOW tR tLOW SCL tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO SDA IN tAA tBUF tDH SDA OUT Figure 3. Write Cycle Timing SCL SDA 8TH BIT ACK BYTE n tWR STOP CONDITION START CONDITION ADDRESS Figure 4. Start/Stop Timing SDA SCL START BIT © 2007 Catalyst Semiconductor, Inc. Characteristics subject to change without notice STOP BIT 6 Doc. No. 3003 Rev. E CAT1163 STOP Condition A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition. FUNCTIONAL DESCRIPTION The CAT1163 supports the I2C Bus data transmis– sion protocol. This Inter-Integrated Circuit Bus proto– col defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. The transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. Both the Master device and Slave device can operate as either transmitter or receiver, but the Master device controls which mode is activated. Device Addressing The Master begins a transmission by sending a START condition. The Master sends the address of the particular slave device it is requesting. The four most significant bits of the 8-bit slave address are fixed as 1010. The next three bits (Figure 6) define memory addressing. For the CAT1163 the three bits define higher order bits. I2C BUS PROTOCOL The features of the I2C bus protocol are defined as follows: The last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected. (1) Data transfer may be initiated only when the bus is not busy. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition. After the Master sends a START condition and the slave address byte, the CAT1163 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT1163 then performs a Read or Write ¯¯ bit. operation depending on the R/W START Condition The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT1163 monitors the SDA and SCL lines and will not respond until this condition is met. Figure 5. Acknowledge Timing SCL FROM MASTER 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE Figure 6. Slave Address Bits CAT1163 1 0 1 0 a10 a9 a8 ¯¯ R/W *a8, a9 and a10 correspond to the address of the memory array address word. © 2007 Catalyst Semiconductor, Inc. Characteristics subject to change without notice 7 Doc. No. 3003 Rev. E CAT1163 Acknowledge After a successful data transfer, each receiving device is required to generate an acknowledge. The acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. receiving another acknowledge from the Slave, the Master device transmits the data to be written into the addressed memory location. The CAT1163 acknow– ledges once more and the Master generates the STOP condition. At this time, the device begins an internal programming cycle to non-volatile memory. While the cycle is in progress, the device will not respond to any request from the Master device. The CAT1163 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8-bit byte. Page Write The CAT1163 writes up to 16 bytes of data in a single write cycle, using the Page Write operation. The page write operation is initiated in the same manner as the byte write operation, however instead of terminating after the initial byte is transmitted, the Master is allowed to send up to 15 additional bytes. After each byte has been transmitted, the CAT1163 will respond with an acknowledge and internally increment the lower order address bits by one. The high order bits remain unchanged. When the CAT1163 begins a READ mode it transmits 8 bits of data, releases the SDA line and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT1163 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. WRITE OPERATIONS If the Master transmits more than 16 bytes before sending the STOP condition, the address counter ‘wraps around,’ and previously transmitted data will be overwritten. Byte Write In the Byte Write mode, the Master device sends the START condition and the slave address information ¯¯ bit set to zero) to the Slave device. (with the R/W After the Slave generates an acknowledge, the Master sends a 8-bit address that is to be written into the address pointers of the CAT1163. After When all 16 bytes are received, and the STOP condition has been sent by the Master, the internal programming cycle begins. At this point, all received data is written to the CAT1163 in a single write cycle. Figure 7. Byte Write Timing BUS ACTIVITY: MASTER SDA LINE S T A R T SLAVE ADDRESS BYTE ADDRESS S T O P DATA S P A C K A C K A C K Figure 8. Page Write Timing BUS ACTIVITY: MASTER SDA LINE S T A R T SLAVE ADDRESS BYTE ADDRESS (n) DATA n+1 S P A C K Doc. No. 3003 Rev. E DATA n S T DATA n+15 O P A C K A C K 8 A C K A C K © 2007 Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT1163 Acknowledge Polling Disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host’s write opration, the CAT1163 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the CAT1163 is still busy with the write operation, no ACK will be returned. If a write operation has completed, an ACK will be returned and the host can then proceed with the next read or write operation. READ OPERATIONS The READ operation for the CAT1163 is initiated in the same manner as the write operation with one exception, ¯¯ bit is set to one. Three different READ ope– that R/W rations are possible: Immediate/Current Address READ, Selective/Random READ and Sequential READ. Immediate/Current Address Read The CAT1163’s address counter contains the address of the last byte accessed, incremented by one. In other words, if the last READ or WRITE access was to address N, the READ immediately following would access data from address N+1. For all devices, N=E=2047. The counter will wrap around to Zero and continue to clock out valid data for the 16K devices. After the CAT1163 receives its slave address ¯¯ bit set to one), it issues an information (with the R/W acknowledge, then transmits the 8-bit byte requested. The master device does not send an acknowledge, but will generate a STOP condition. WRITE PROTECTION The Write Protection feature allows the user to protect against inadvertent memory array programming. If the WP pin is tied to VCC, the entire memory array is protected and becomes read only. The CAT1163 will accept both slave and byte addresses, but the memory location accessed is protected from programming by the device’s failure to send an acknowledge after the first byte of data is received. Figure 9. Immediate Address Read Timing BUS ACTIVIT Y: MASTER SDA LINE S T A R T S T O P SLAVE ADDRESS P S A C K DATA N O A C K SCL SDA 8 9 8TH BI T DATA OUT © 2007 Catalyst Semiconductor, Inc. Characteristics subject to change without notice NO ACK 9 STOP Doc. No. 3003 Rev. E CAT1163 Selective/Random Read Selective/Random READ operations allow the Master device to select at random any memory location for a READ operation. The Master device first performs a ‘dummy’ write operation by sending the START condition, slave address and byte addresses of the location it wishes to read. After the CAT1163 acknowledges, the Master device sends the START condition and the slave address again, ¯¯ bit set to one. The CAT1163 this time with the R/W then responds with its acknowledge and sends the 8-bit byte requested. The master device does not send an acknowledge but will generate a STOP condition. Sequential Read The Sequential READ operation can be initiated by either the Immediate Address READ or Selective READ operations. After the CAT1163 sends the inital 8-bit byte requested, the Master will responds with an acknowledge which tells the device it requires more data. The CAT1163 will continue to output an 8-bit byte for each acknowledge, thus sending the STOP condition. The data being transmitted from the CAT1163 is outputted sequentially with data from address N followed by data from address N+1. The READ operation address counter increments all of the CAT1163 address bits so that the entire memory array can be read during one operation. If more than E (where E=2047 for the CAT1163) bytes are read out, the counter will ‘wrap around’ and continue to clock out data bytes. Manual Reset Operation ¯¯¯¯¯¯ pin can also be used The CAT116x RESET or RESET as a manual reset input. Only the “active” edge internally sensed. The RESET is used as a negative edge is sensed reset input. of the manual reset input is positive edge is sensed if manual reset input and the ¯¯¯¯¯¯ is used as a manual if RESET An internal counter starts a 200ms count. During this time, the complementary reset output will be kept in the active state. If the manual reset input is forced active for more than 200ms, the complementary reset output will switch back to the non active state after the 200ms expired, regardless for how long the manual reset input is forced active. The embedded EEPROM is disabled as long as a reset condition is maintained on any RESET pin. If the ¯¯¯¯¯¯ is longer than internal external forced RESET/RESET controlled time-out period, tPURST, the memory will not respond with an acknowledge for any access as long as the manual reset input is active. Figure 10. Selective Read Timing BUS ACTIVITY: MASTER SDA LINE S T A R T SLAVE ADDRESS S T A R T BYTE ADDRESS (n) S T O P SLAVE ADDRESS P S S A C K A C K A C K DATA n N O A C K Figure 11. Sequential Read Timing BUS ACTIVITY: MASTER SLAVE ADDRESS DATA n DATA n+1 DATA n+2 S T O P DATA n+x SDA LINE P A C K A C K A C K A C K N O A C K Doc. No. 3003 Rev. E 10 © 2007 Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT1163 PACKAGE OUTLINES 8-LEAD 300 MIL WIDE PLASTIC DIP (L) E1 E D A2 A c A1 L e eB b2 b SYMBOL A A1 A2 b b2 c D E E1 e eB L MIN NOM MAX 4.57 0.38 3.05 0.36 1.14 0.21 9.02 7.62 6.09 0.46 0.26 7.87 6.35 2.54 BSC 3.81 0.56 1.77 0.35 10.16 8.25 7.11 9.65 3.81 7.87 2.92 For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: (1) (2) All dimensions are in millimeters. Complies with JEDEC Publication 95 MS001 dimensions; however, some of the dimensions may be more stringent. © 2007 Catalyst Semiconductor, Inc. Characteristics subject to change without notice 11 Doc. No. 3003 Rev. E CAT1163 8-LEAD 150 MIL SOIC (W) E1 E h x 45 D C A q1 e A1 L b SYMBOL MIN A1 A b C D E E1 e h L q1 0.10 1.35 0.33 0.19 4.80 5.80 3.80 NOM MAX 0.25 1.75 0.51 0.25 5.00 6.20 4.00 1.27 BSC 0.25 0.40 0° 0.50 1.27 8° For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: (1) (2) All dimensions are in millimeters. Complies with JEDEC specification MS-012 dimensions. Doc. No. 3003 Rev. E 12 © 2007 Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT1163 EXAMPLE OF ORDERING INFORMATION Prefix Device # Suffix CAT 1163 W Optional Company ID I -30 Temperature Range I = Industrial (-40ºC to 85ºC) Product Number 1163: 16K Package L: PDIP W: SOIC Reset Threshold Voltage -45: 4.50V to 4.75V -42: 4.25V to 4.50V -30: 3.00V to 3.15V -28: 2.85V to 3.00V -25: 2.55V to 2.70V – G T3 Tape & Reel T: Tape & Reel 3: 3000/Reel Lead Finish Blank: Matte-Tin G: NiPdAu Notes: (1) (2) (3) (4) All packages are RoHS-compliant (Lead-free, Halogen-free). The standard lead finish is Matte-Tin. This device used in the above example is a CAT1163WI-30-GT3 (SOIC, Industrial Temperature, 3V to 3.15V, NiPdAu, Tape & Reel) NiPdAu is a lead finish option on the Green packages only. Unless indicated with a “G”, the Pb-free packages are shipped with a Sn matte lead finish. ORDERING PART NUMBER CAT1163LI-45 CAT1163LI-42 CAT1163LI-30 CAT1163LI-28 CAT1163LI-25 CAT1163WI-45 CAT1163WI-42 CAT1163WI-30 CAT1163WI-28 CAT1163WI-25 © 2007 Catalyst Semiconductor, Inc. Characteristics subject to change without notice 13 Doc. No. 3003 Rev. E REVISION HISTORY Date Rev. 02/17/05 D 02/02/07 E Reason Add Green Logo Add Package Outline Update Ordering Information Update Example of Ordering Information Update Package Outline Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include ech of the following: Beyond Memory™, DPP™, EZDim™, MiniPot™, and Quad-Mode™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 2975 Stender Way Santa Clara, CA 95054 Phone: 408.542.1000 Fax: 408.542.1200 www.catsemi.com Document No: 3003 Revision: E Issue date: 02/02/07