CAT140xx Voltage Supervisor with I2C Serial CMOS EEPROM FEATURES DESCRIPTION Precision Power Supply Voltage Monitor The CAT140xx (see table below) are memory and supervisory solutions for microcontroller based systems. A CMOS serial EEPROM memory and a system power supervisor with brown-out protection are integrated together. Memory interface is via both the standard (100kHz) as well as fast (400kHz) I2C protocol. 5V, 3.3V, 3V & 2.5V systems 7 threshold voltage options Active High or Low Reset Valid reset guaranteed at VCC = 1 V Supports Standard and Fast I2C Protocol The CAT140xx provides a precision VCC sense circuit with two reset output options: CMOS active low output or CMOS active high. The RESET output is active whenever VCC is below the reset threshold or falls below the reset threshold voltage. 16-Byte Page Write Buffer Low power CMOS technology 1,000,000 Program/Erase cycles 100 year data retention Industrial temperature range The power supply monitor and reset circuit protect system controllers during power up/down and against brownout conditions. Seven reset threshold voltages support 5V, 3.3V, 3V and 2.5V systems. If power supply voltages are out of tolerance reset signals become active, preventing the system microcontroller, ASIC or peripherals from operating. Reset signals become inactive typically 240ms after the supply voltage exceeds the reset threshold level. RoHS-compliant 8-pin SOIC package For Ordering Information details, see page 14. PIN CONFIGURATION SOIC (W) MEMORY SIZE SELECTOR CAT14016 / 08 / 04 / 02 NC / NC / NC / A0 1 8 VCC NC / NC / A1 / A1 NC / A2 / A2 / A2 2 7 3 VSS 4 Product Memory density RST/RST 14002 2-Kbit 6 SCL 14004 4-Kbit 5 SDA 14008 8-Kbit 14016 16-Kbit PIN FUNCTION Pin Name Function A0, A1, A2 Device Address Inputs SDA Serial Data Input/Output SCL Serial Clock Input ¯¯¯¯ RST/RST Reset Output VCC Power Supply VSS Ground NC No Connect © 2006 Catalyst Semiconductor, Inc. Characteristics subject to change without notice THRESHOLD SUFFIX SELECTOR 1 Nominal Threshold Voltage Threshold Suffix Designation 4.63V L 4.38V M 4.00V J 3.08V T 2.93V S 2.63V R 2.32V Z Doc. No. 1117 Rev. A CAT140xx BLOCK DIAGRAM VCC SDA SCL A0 VOLTAGE DETECTOR EEPROM RST or RST A1 A2 VSS ABSOLUTE MAXIMUM RATINGS(1) Parameters Storage Temperature Voltage on Any Pin with Respect to Ground (2) Ratings Units -65 to +150 °C -0.5 to +6.5 V RELIABILITY CHARACTERISTICS(3) Symbol Parameter Min Units (4) Endurance 1,000,000 Program/ Erase Cycles 100 Years NEND TDR Data Retention D.C. OPERATING CHARACTERISTICS VCC = +2.5V to +5.5V unless otherwise specified. Symbol Parameter ICC Supply Current ISB Standby Current IL I/O Pin Leakage VIL Input Low Voltage VIH VOL Input High Voltage Output Low Voltage SDA Min. Limits Typ. Max. Test Condition Units 1 Read or Write at 400kHz 10 22 VCC < 5.5V; All I/O Pins at VSS or VCC 8 17 VCC < 3.6V; All I/O Pins at VSS or VCC 2 Pin at GND or VCC mA μA μA -0.5 VCC x 0.3 V VCC x 0.7 VCC + 0.5 V 0.4 VCC ≥ 2.5 V, IOL = 3.0 mA V Notes: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) The DC input voltage on any pin should not be lower than -0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may undershoot to no less than -1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns. (3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. (4) Page Mode, VCC = 5 V, 25°C Doc. No. 1117 Rev. A 2 © 2006 Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT140xx A.C. CHARACTERISTICS (MEMORY)(1) VCC = 2.5V to 5.5V, TA = -40°C to 85°C, unless otherwise specified. Symbol FSCL tHD:STA Parameter Standard Min Max Fast Min Max 100 400 Clock Frequency START Condition Hold Time Units kHz 4 0.6 µs tLOW Low Period of SCL Clock 4.7 1.3 µs tHIGH High Period of SCL Clock 4 0.6 µs 4.7 0.6 µs tSU:STA START Condition Setup Time tHD:DAT Data In Hold Time 0 0 µs tSU:DAT Data In Setup Time 250 100 ns (2) SDA and SCL Rise Time 1000 300 ns (2) SDA and SCL Fall Time 300 300 ns tR tF tSU:STO STOP Condition Setup Time tBUF Bus Free Time Between STOP and START tAA SCL Low to Data Out Valid tDH Data Out Hold Time (2) µs 4.7 1.3 µs 100 Noise Pulse Filtered at SCL and SDA Inputs tWR tPU 0.6 3.5 Ti (2, 3) 4 0.9 100 µs ns 100 100 ns Write Cycle Time 5 5 ms Power-up to Ready Mode 1 1 ms Notes: (1) Test conditions according to “A.C. Test Conditions” table. (2) Tested initially and after a design or process change that affects this parameter. (3) tPU is the delay between the time VCC is stable and the device is ready to accept commands. A.C. TEST CONDITIONS Input Levels 0.2 x VCC to 0.8 x VCC Input Rise and Fall Times ≤ 50 ns Input Reference Levels 0.3 x VCC, 0.7 x VCC Output Reference Levels 0.5 x VCC Output Load Current Source: IOL = 3 mA; CL = 100 pF © 2006 Catalyst Semiconductor, Inc. Characteristics subject to change without notice 3 Doc. No. 1117 Rev. A CAT140xx ELECTRICAL CHARACTERISTICS (SUPERVISORY FUNCTION) VCC = Full range, TA = -40ºC to +85ºC unless otherwise noted. Typical values at TA = +25ºC and VCC = 5V for L/M/J versions, VCC = 3.3V for T/S versions, VCC = 3V for R version and VCC = 2.5V for Z version. Symbol VTH Parameter Reset Threshold Voltage Threshold L M J T S R Z Symbol Parameter Conditions Min Typ Max TA = +25ºC TA = -40ºC to +85ºC 4.56 4.50 4.63 4.70 4.75 TA = +25ºC 4.31 4.38 4.45 TA = -40ºC to +85ºC 4.25 TA = +25ºC 3.93 TA = -40ºC to +85ºC 3.89 TA = +25ºC 3.04 TA = -40ºC to +85ºC 3.00 TA = +25ºC 2.89 TA = -40ºC to +85ºC 2.85 TA = +25ºC 2.59 TA = -40ºC to +85ºC 2.55 TA = +25ºC 2.28 TA = -40ºC to +85ºC 2.25 Conditions Min Reset Threshold Tempco tRPD tPURST VOL VOH VCC to Reset Delay (2) 4.06 4.10 3.08 3.11 3.15 2.93 3.00 2.63 2.66 2.70 2.32 2.35 2.38 Typ(1) Max ppm/ºC 20 µs 0.3 VCC = VTH min, ISINK = 3.2 mA J/L/M 0.4 VCC > 1.0V, ISINK = 50µA 0.3 (Push-pull, active HIGH, CAT140xx1) (Push-pull, active HIGH, CAT140xx1) 0.8VCC VCC = VTH max, ISOURCE = -800µA J/L/M VCC - 1.5 240 460 ms V V VCC > VTH max, ISINK = 1.2mA R/S/T/Z 0.3 VCC > VTH max, ISINK = 3.2mA J/L/M 0.4 1.8V < VCC ≤ VTH min, ISOURCE = -150µA Units 30 VCC = VTH min, ISINK = 1.2 mA R/S/T/Z VCC = VTH max, ISOURCE = -500µA R/S/T/Z V 2.96 ¯¯¯¯¯¯ Output Voltage Low RESET (Push-pull, active LOW, CAT140xx9) RESET Output Voltage High VOH 4.00 TA = -40ºC to +85ºC ¯¯¯¯¯¯ Output Voltage High RESET (Push-pull, active LOW, CAT140xx9) 140 4.50 Reset Active Timeout Period RESET Output Voltage Low VOL VCC = VTH to (VTH -100mV) Units V 0.8VCC V Notes: (1) (2) Production testing done at TA = +25ºC; limits over temperature guaranteed by design only. RESET output for the CAT140xx9; RESET output for the CAT140xx1. Doc. No. 1117 Rev. A 4 © 2006 Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT140xx and remains asserted for at least 140ms (tPURST) after the power supply voltage has risen above the threshold. Reset output timing is shown in Figure 1. PIN DESCRIPTION ¯¯¯¯¯¯ : RESET OUTPUT RESET/RESET This output is available in two versions: CMOS Active Low (CAT140xx9) and CMOS Active High (CAT140xx1). Both versions are push-pull outputs for high efficiency. The CAT140xx devices protect μPs against brownout failure. Short duration VCC transients of 4μsec or less and 100mV amplitude typically do not generate a Reset pulse. SDA: SERIAL DATA ADDRESS The Serial Data I/O pin receives input data and transmits data stored in EEPROM. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of SCL. Figure 2 shows the maximum pulse duration of negativegoing VCC transients that do not cause a reset condition. As the amplitude of the transient goes further below the threshold (increasing VTH - VCC), the maximum pulse duration decreases. In this test, the VCC starts from an initial voltage of 0.5V above the threshold and drops below it by the amplitude of the overdrive voltage (VTH - VCC). TRANSIENT DURATION [µs] SCL: SERIAL CLOCK The Serial Clock input pin accepts the Serial Clock generated by the Master. A0, A1, A2: Device Address Inputs The Address inputs set the device address when cascading multiple devices. When not driven, these pins are pulled LOW internally. DEVICE OPERATION The CAT140xx products combine the accurate voltage monitoring capabilities of a standalone voltage supervisor with the high quality and reliability of standard EEPROMs from Catalyst Semiconductor. RESET CONTROLLER DESCRIPTION The reset signal is asserted LOW for the CAT140xx9 and HIGH for the CAT140xx1 when the power supply voltage falls below the threshold trip voltage VCC TAMB = 25ºC CAT140xxZ CAT140xxM RESET OVERDRIVE V TH - VCC [mV] Figure 2. Maximum Transient Duration Without Causing a Reset Pulse vs. Overdrive Voltage VTH VRVALID t PURST t RPD t PURST t RPD RESE T CAT140xx9 RESE T CAT140xx1 Figure 1. RESET Output Timing © 2006 Catalyst Semiconductor, Inc. Characteristics subject to change without notice 5 Doc. No. 1117 Rev. A CAT140xx EMBEDDED EEPROM OPERATION STOP The STOP condition completes all commands. It consists of a LOW to HIGH transition on SDA while SCL is HIGH. The STOP starts the internal Write cycle (when following a Write command) or sends the Slave into standby mode (when following a Read command). The CAT140xx supports the Inter-Integrated Circuit (I2C) Bus data transmission protocol, which defines a device that sends data to the bus as a transmitter and a device receiving data as a receiver. Data flow is controlled by a Master device, which generates the serial clock and all START and STOP conditions. The CAT140xx acts as a Slave device. Master and Slave alternate as either transmitter or receiver. Device Addressing The Master initiates data transfer by creating a START condition on the bus. The Master then broadcasts an 8-bit serial Slave address. For normal Read/Write operations, the first 4 bits of the Slave address are fixed at 1010 (Ah). The next 3 bits are used as programmable address bits when cascading multiple devices and/or as internal address bits. The last bit of the slave address, R/W, specifies whether a Read (1) or Write (0) operation is to be performed. The 3 address space extension bits are assigned as illustrated in Figure 4. A2, A1 and A0 must match the state of the external address pins, and a10, a9 and a8 are internal address bits. I2C BUS PROTOCOL The I2C bus consists of two ‘wires’, SCL and SDA. The two wires are connected to the VCC supply via pull-up resistors. Master and Slave devices connect to the 2-wire bus via their respective SCL and SDA pins. The transmitting device pulls down the SDA line to ‘transmit’ a ‘0’ and releases it to ‘transmit’ a ‘1’. Data transfer may be initiated only when the bus is not busy (see A.C. Characteristics). During data transfer, the SDA line must remain stable while the SCL line is HIGH. An SDA transition while SCL is HIGH will be interpreted as a START or STOP condition (Figure 3). The START condition precedes all commands. It consists of a HIGH to LOW transition on SDA while SCL is HIGH. The START acts as a ‘wake-up’ call to all receivers. Absent a START, a Slave will not respond to commands. The STOP condition completes all commands. It consists of a LOW to HIGH transition on SDA while SCL is HIGH. Acknowledge After processing the Slave address, the Slave responds with an acknowledge (ACK) by pulling down the SDA line during the 9th clock cycle (Figure 5). The Slave will also acknowledge the address byte and every data byte presented in Write mode. In Read mode the Slave shifts out a data byte, and then releases the SDA line during the 9th clock cycle. As long as the Master acknowledges the data, the Slave will continue transmitting. The Master terminates the session by not acknowledging the last data byte (NoACK) and by issuing a STOP condition. Bus timing is illustrated in Figure 6. START The START condition precedes all commands. It consists of a HIGH to LOW transition on SDA while SCL is HIGH. The START acts as a ‘wake-up’ call to all receivers. Absent a START, a Slave will not respond to commands. Doc. No. 1117 Rev. A 6 © 2006 Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT140xx Figure 3. START/STOP Conditions SCL SDA START CONDITION STOP CONDITION Figure 4. Slave Address Bits 1 0 1 0 A2 A1 A0 R/W CAT14002 1 0 1 0 A2 A1 a8 R/W CAT14004 1 0 1 0 A2 a9 a8 R/W CAT14008 1 0 1 0 a10 a9 a8 R/W CAT14016 Figure 5. Acknowledge Timing BUS RELEASE DELAY (TRANSMITTER) SCL FROM MASTER 1 BUS RELEASE DELAY (RECEIVER) 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACK SETUP (≥ tSU:DAT) ACK DELAY (≤ tAA) Figure 6. Bus Timing tHIGH tF tLOW tR tLOW SCL tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO SDA IN tAA tDH tBUF SDA OUT © 2006 Catalyst Semiconductor, Inc. Characteristics subject to change without notice 7 Doc. No. 1117 Rev. A CAT140xx WRITE OPERATIONS Byte Write In Byte Write mode, the Master sends the START condition and the Slave address with the R/W bit set to zero to the Slave. After the Slave generates an acknowledge, the Master sends the byte address that is to be written into the address pointer of the CAT140xx. After receiving another acknowledge from the Slave, the Master transmits the data byte to be written into the addressed memory location. The CAT140xx device will acknowledge the data byte and the Master generates the STOP condition, at which time the device begins its internal Write cycle to nonvolatile memory (Figure 7). While this internal cycle is in progress (tWR), the SDA output will be tristated and the CAT140xx will not respond to any request from the Master device (Figure 8). Page Write The CAT140xx writes up to 16 bytes of data in a single write cycle, using the Page Write operation (Figure 9). The Page Write operation is initiated in the same manner as the Byte Write operation, however instead of terminating after the data byte is transmitted, the Master is allowed to send up to fifteen additional bytes. After each byte has been transmitted the CAT140xx will respond with an acknowledge and internally increments the four low order address bits. The high order bits that define the page address remain unchanged. If the Master transmits more than sixteen bytes prior to sending the STOP condition, the address counter ‘wraps around’ to the beginning of page and previously transmitted data will be overwritten. Once all sixteen bytes are received and the STOP condition has been sent by the Master, the internal Write cycle begins. At this point all received data is written to the CAT140xx in a single write cycle. Acknowledge Polling The acknowledge (ACK) polling routine can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host’s write operation, the CAT140xx initiates the internal write cycle. The ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the CAT140xx is still busy with the write operation, NoACK will be returned. If the CAT140xx has completed the internal write operation, an ACK will be returned and the host can then proceed with the next read or write operation. Doc. No. 1117 Rev. A 8 © 2006 Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT140xx Figure 7. Byte Write Sequence BUS ACTIVITY: MASTER S T A R T SLAVE ADDRESS ADDRESS BYTE DATA BYTE a7⎟ a0 d7÷d0 S T O P P S A C K SLAVE A C K A C K Figure 8. Write Cycle Timing SCL 8th Bit Byte n SDA ACK tWR STOP CONDITION START CONDITION ADDRESS Figure 9. Page Write Timing BUS ACTIVITY: MASTER S T A R T DATA BYTE n ADDRESS BYTE SLAVE ADDRESS DATA BYTE n+1 DATA BYTE n+P S T O P S SLAVE P A C K A C K A C K A C K A C K n=1 P ≤ 15 © 2006 Catalyst Semiconductor, Inc. Characteristics subject to change without notice 9 Doc. No. 1117 Rev. A CAT140xx READ OPERATIONS Immediate Read Upon receiving a Slave address with the R/W bit set to ‘1’, the CAT140xx will interpret this as a request for data residing at the current byte address in memory. The CAT140xx will acknowledge the Slave address, will immediately shift out the data residing at the current address, and will then wait for the Master to respond. If the Master does not acknowledge the data (NoACK) and then follows up with a STOP condition (Figure 10), the CAT140xx returns to Standby mode. Selective Read Selective Read operations allow the Master device to select at random any memory location for a read operation. The Master device first performs a ‘dummy’ write operation by sending the START condition, slave address and byte address of the location it wishes to read. After the CAT140xx acknowledges the byte address, the Master device resends the START condition and the slave address, this time with the R/W bit set to one. The CAT140xx then responds with its acknowledge and sends the requested data byte. The Master device does not acknowledge the data (NoACK) but will generate a STOP condition (Figure 11). Sequential Read If during a Read session, the Master acknowledges st the 1 data byte, then the CAT140xx will continue transmitting data residing at subsequent locations until the Master responds with a NoACK, followed by a STOP (Figure 12). In contrast to Page Write, during Sequential Read the address count will automatically increment to and then wrap-around at end of memory (rather than end of page). POWER-ON RESET (POR) Each CAT140xx incorporates Power-On Reset (POR) circuitry which protects the internal logic against powering up in the wrong state. A CAT140xx device will power up into Standby mode after VCC exceeds the POR trigger level and will power down into Reset mode when VCC drops below the POR trigger level. This bi-directional POR feature protects the device against ‘brown-out’ failure follo– wing a temporary loss of power. Delivery State The CAT140xx is shipped erased, i.e., all bytes are FFh. © 2006 Catalyst Semiconductor, Inc. Characteristics subject to change without notice 10 Doc. No. 1117 Rev. A CAT140xx Figure 10. Immediate Read Sequence and Timing BUS ACTIVITY: MASTER N O S T A R T S AT CO KP SLAVE ADDRESS P S A C K SLAVE SCL 8 DATA BYTE 9 8th Bit SDA DATA OUT NO ACK STOP Figure 11. Selective Read Sequence BUS ACTIVITY: MASTER S T A R T S T A R T ADDRESS BYTE SLAVE ADDRESS N O S AT CO KP SLAVE ADDRESS P S S A C K SLAVE A C K A C K DATA BYTE Figure 12. Sequential Read Sequence N O BUS ACTIVITY: MASTER A C K SLAVE ADDRESS A C K S AT CO KP A C K P SLAVE A C K © 2006 Catalyst Semiconductor, Inc. Characteristics subject to change without notice DATA BYTE n DATA BYTE n+1 11 DATA BYTE n+2 DATA BYTE n+x Doc. No. 1117 Rev. A CAT140xx PACKAGE OUTLINES 8-LEAD 150 MIL SOIC (W) E1 E h x 45 D C A q1 e A1 L b SYMBOL MIN A1 A b C D E E1 e h L q1 0.10 1.35 0.33 0.19 4.80 5.80 3.80 NOM MAX 0.25 1.75 0.51 0.25 5.00 6.20 4.00 1.27 BSC 0.25 0.40 0° 0.50 1.27 8° For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC specification MS-012 dimensions. Doc. No. 1117 Rev. A 12 © 2006 Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT140xx ORDERING INFORMATION Prefix CAT Device # Suffix 14002 9 S W I - G T3 Lead Finish G: NiPdAu (PPF) Company ID Temperature Range I = Industrial (-40ºC to 85ºC) Product Type with Memory Density 02 – 2K-bits 04 – 4K-bits 08 – 8K-bits 16 – 16K-bits Tape & Reel T: Tape & Reel 3: 3000 units / Reel Package W: SOIC Reset Threshold Voltage L: 4.50V – 4.75V M: 4.25V – 4.50V J: 3.89V – 4.10V T: 3.00V – 3.15V S: 2.85V – 3.00V R: 2.55V – 2.70V Z: 2.25V – 2.38V Supervisor Output Type 9: CMOS Active Low 1: CMOS Active High Notes: (1) All packages are RoHS-compliant (Lead-free, Halogen-free). (2) The standard lead finish is NiPdAu pre-plated (PPF) lead frames. (3) The device used in the above example is a CAT140029SWI-GT3 (2Kb EEPROM, with Active Low CMOS output, with a reset threshold between 2.85V - 3.00V, in an SOIC, Industrial Temperature, NiPdAu, Tape and Reel. (4) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office. © 2006 Catalyst Semiconductor, Inc. Characteristics subject to change without notice 13 Doc. No. 1117 Rev. A REVISION HISTORY Date 11/09/06 Rev. A Reason Initial Issue Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: Beyond Memory™, DPP™, EZDim™, MiniPot™, and Quad-Mode™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 2975 Stender Way Santa Clara, CA 95054 Phone: 408.542.1000 Fax: 408.542.1200 www.catsemi.com Document No: 1117 Revision: A Issue date: 11/09/06