Catalyst CAT24WC03PATE13 2k/4k-bit serial eeprom with partial array write protection Datasheet

CAT24WC03/05
2K/4K-Bit Serial EEPROM with Partial Array Write Protection
FEATURES
■ Self-timed write cycle with auto-clear
s
t
r
■ 400 kHz I2C bus compatible*
■ 1,000,000 Program/Erase cycles
■ 1.8 to 5.5 volt operation
■ 100 Year data retention
■ Low power CMOS technology
■ 8-pin DIP, 8-pin SOIC, 8-lead MSOP and 8-pin
TSSOP Package
■ Write protect feature
–Top 1/2 array protected when WP at VIH
a
P
■ Commercial, industrial and automotive
temperature ranges
■ 16-Byte page write buffer
■ "Green" package options available
DESCRIPTION
d
e
The CAT24WC03/05 is a 2K/4K-bit Serial CMOS
EEPROM internally organized as 256/512 words of 8
bits each. Catalyst’s advanced CMOS technology substantially reduces device power requirements. The
CAT24WC03/05 features a 16-byte page write buffer.
The device operates via the I2C bus serial interface, has
a special write protection feature, and is available in 8pin DIP or 8-pin SOIC packages.
PIN CONFIGURATION
BLOCK DIAGRAM
DIP Package (P, L, GL)
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
1
2
8
7
A2
VSS
3
4
6
5
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VCC
WP
SCL
SDA
MSOP Package (R, Z, GZ)
A0
A1
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
EXTERNAL LOAD
VCC
WP
SCL
SDA
SENSE AMPS
SHIFT REGISTERS
DOUT
ACK
VCC
VSS
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
TSSOP Package (U, Y, GY)
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SOIC Package (J, W, GW)
VCC
A0
WP
A1
SCL
A2
SDA VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
SDA
START/STOP
LOGIC
XDEC
WP
E2PROM
CONTROL
LOGIC
PIN FUNCTIONS
Pin Name
Function
A0, A1, A2
Device Address Inputs
SDA
Serial Data/Address
SCL
Serial Clock
WP
Write Protect
VCC
+1.8V to +5.5V Power Supply
VSS
Ground
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
SCL
A0
A1
A2
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1005, Rev. F
CAT24WC03/05
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +125°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Storage Temperature ....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground(1) ........... –2.0V to +VCC + 2.0V
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) .................................. 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
NEND(3)
TDR
Endurance
(3)
VZAP
Min.
(3)
ILTH(3)(4)
1,000,000
Data Retention
100
ESD Susceptibility
2000
Latch-up
100
D.C. OPERATING CHARACTERISTICS
VCC = +1.8V to +5.5V, unless otherwise specified.
Symbol
Max.
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Parameter
ICC
Power Supply Current
IS(5)
Standby Current (VCC = 5.0V)
Units
Cycles/Byte
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u
n
Limits
Min
a
P
Typ
Years
Volts
mA
Max
Units
Test Conditions
3
mA
fSCL = 100 kHz
0
µA
VIN = GND or VCC
10
µA
VIN = GND to VCC
10
µA
VOUT = GND to VCC
ILI
Input Leakage Current
ILO
Output Leakage Current
VIL
Input Low Voltage
–1
VCC x 0.3
V
VIH
Input High Voltage
VCC x 0.7
VCC + 0.5
V
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VOL1
Output Low Voltage (VCC = 3.0V)
0.4
V
IOL = 3 mA
VOL2
Output Low Voltage (VCC = 1.8V)
0.5
V
IOL = 1.5 mA
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CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V
Symbol
Test
Max
Units
Conditions
CI/O(3)
Input/Output Capacitance (SDA)
8
pF
VI/O = 0V
CIN(3)
Input Capacitance (A0, A1, A2, SCL, WP)
6
pF
VIN = 0V
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
(5) Standby Current (ISB) = 0µA (<900nA).
Doc. No. 1005, Rev. F
2
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24WC03/05
A.C. CHARACTERISTICS
VCC = +1.8V to +5.5V, unless otherwise specified.
Read & Write Cycle Limits
CAT24WCXX-1.8
1.8V-5.5V
Symbol
Min.
Parameter
FSCL
Clock Frequency
tBUF
Noise Suppression Time Constant at
SCL, SDA Inputs
SCL Low to SDA Data Out and ACK
Out
Time the Bus Must be Free Before
a New Transmission Can Start
tHD:STA
Start Condition Hold Time
tLOW
(1)
TI
tAA
(1)
CAT24WCXX
2.5V-5.5V
Max.
Min.
100
200
200
3.5
3.5
4.7
4
4
Clock Low Period
4.7
4.7
tHIGH
Clock High Period
4
tSU:STA
Start Condition Setup Time
(for a Repeated Start Condition)
tHD:DAT
Data In Hold Time
tSU:DAT
Data In Setup Time
SDA and SCL Rise Time
tF
SDA and SCL Fall Time
tSU:STO
Stop Condition Setup Time
tDH
Data Out Hold Time
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Power-Up Timing(1)(2)
Symbol
tPUW
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Write Cycle Limits
Symbol
tWR
0
u
n
1
4
100
400
kHz
200
ns
1
µs
s
t
r
µs
µs
µs
0.6
µs
0.6
µs
0
ns
50
ns
50
30 0
Units
1
0.3
µs
300
300
ns
4
0.6
µs
100
100
ns
Parameter
Max
Units
Power-up to Read Operation
1
ms
Power-up to Write Operation
1
ms
c
s
tPUR
1.2
4.7
50
Max.
a
P
0.6
d
e
4.7
Min.
1.2
4
0
(1)
tR
Max.
10 0
4.7
(1)
4.5V-5.5V
Parameter
Min
Write Cycle Time
Typ
Max
Units
10
ms
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. 1005, Rev. F
CAT24WC03/05
FUNCTIONAL DESCRIPTION
clock all data transfers into or out of the device. This is
an input pin.
The CAT24WC03/05 supports the I2C Bus data transmission protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be
a transmitter and any device receiving data to be a
receiver. Data transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. The CAT24WC03/05
operates as a Slave device. Both the Master and Slave
devices can operate as either transmitter or receiver, but
the Master device controls which mode is activated. A
maximum of 8 devices (24WC03) and 4 devices
(24WC05) may be connected to the bus as determined
by the device address inputs A0, A1, and A2.
SDA: Serial Data/Address
The CAT24WC03/05 bidirectional serial data/address
pin is used to transfer data into and out of the device. The
SDA pin is an open drain output and can be wire-ORed
with other open drain or open collector outputs.
SCL: Serial Clock
The CAT24WC03/05 serial clock input pin is used to
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Figure 1. Bus Timing
Figure 2. Write Cycle Timing
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A maximum of eight devices can be cascaded when
using the CAT24WC03. All three address pins are used
for CAT24WC03. If only one CAT24WC03 is addressed
on the bus, all three address pins (A0, A1, and A2) can
be left floating or connected to VSS.
PIN DESCRIPTIONS
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A0, A1, A2: Device Address Inputs
These inputs set device address when cascading multiple devices. When these pins are left floating the
default values are zeros.
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Figure 3. Start/Stop Timing
Doc. No. 1005, Rev. F
4
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24WC03/05
A total of four devices can be addressed on a single bus
when using the CAT24WC05 device. Only A1 and A2
address pins are used with this device. The A0 address
pin is a no connect pin and can be tied to VSS or left
floating. If only one CAT24WC05 is being addressed on
the bus, the address pins (A1 and A2) can be left floating
or connected to VSS.
STOP Condition
WP: Write Protect
If the WP pin is tied to VCC the upper half of memory array
becomes Write Protected (READ only)(locations 80H to
FFH for the CAT24WC03 and locations 100H to 1FFH
for the CAT24WC05). When the WP pin is tied to VSS or
left floating normal read/write operations are allowed to
the device.
The bus Master begins a transmission by sending a
START condition. The Master then sends the address
of the particular slave device it is requesting. The four
most significant bits of the 8-bit slave address are fixed
as 1010 for the CAT24WC03/05 (see Fig. 5). The next
three significant bits (A2, A1, A0) are the device address
bits and define which device or which part of the device
the Master is accessing. Up to eight CAT24WC03 and
four CAT24WC05 can be individually addressed by the
system. The last bit of the slave address specifies
whether a Read or Write operation is to be performed.
When this bit is set to 1, a Read operation is selected,
and when set to 0, a Write operation is selected.
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
DEVICE ADDRESSING
I2C BUS PROTOCOL
The following defines the features of the I2C bus protocol:
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e
(1) Data transfer may be initiated only when the bus is
not busy.
After the Master sends a START condition and the slave
address byte, the CAT24WC03/05 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24WC03/05 then performs a Read or Write operation
depending on the state of the R/W bit.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
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START Condition
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Acknowledge
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24WC03/05 monitor
the SDA and SCL lines and will not respond until this
condition is met.
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After a successful data transfer, each receiving device is
required to generate an acknowledge. The
Acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data.
Figure 4. Acknowledge Timing
SCL FROM
MASTER
i
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1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACKNOWLEDGE
START
Figure 5. Slave Address Bits
24WC03
1
0
1
0
A2
A1
A0
R/W
24WC05
1
0
1
0
A2
A1
a8
R/W
* A0, A1 and A2 correspond to pin 1, pin 2 and pin 3 of the device.
** a8 corresponds to the address of the memory array address word.
***A0, A1 and A2 must compare to its corresponding hard wired input pins (pins 1, 2 and 3).
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. 1005, Rev. F
CAT24WC03/05
The CAT24WC03/05 responds with an acknowledge
after receiving a START condition and its slave address.
If the device has been selected along with a write
operation, it responds with an acknowledge after receiving
each 8-bit byte.
The CAT24WC03/05 writes up to 16 bytes of data in a
single write cycle, using the Page Write operation. The
Page Write operation is initiated in the same manner as
the Byte Write operation; however, instead of terminating
after the initial word is transmitted, the Master is allowed
to send up to 15 additional bytes. After each byte has
been transmitted, the CAT24WC03/05 will respond with
an acknowledge and internally increment the low order
address bits by one. The high order bits remain
unchanged.
When the CAT24WC03/05 is in a READ mode it transmits
8 bits of data, releases the SDA line, and monitors the
line for an acknowledge. Once it receives this
acknowledge, the CAT24WC03/05 will continue to
transmit data. If no acknowledge is sent by the Master,
the device terminates data transmission and waits for a
STOP condition.
WRITE OPERATIONS
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
the byte address that is to be written into the address
pointer of the CAT24WC03/05. After receiving another
acknowledge from the Slave, the Master device transmits
the data byte to be written into the addressed memory
location. The CAT24WC03/05 acknowledge once more
and the Master generates the STOP condition, at which
time the device begins its internal programming cycle to
nonvolatile memory. While this internal cycle is in
progress, the device will not respond to any request from
the Master device.
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Figure 6. Byte Write Timing
c
s
BUS ACTIVITY:
MASTER
i
D
SDA LINE
S
T
A
R
T
a
P
Once all 16 bytes are received and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point all received data is written to
the CAT24WC03/05 in a single write cycle.
Byte Write
Page Write
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If the Master transmits more than 16 bytes prior to
sending the STOP condition, the address counter ‘wraps
around’, and previously transmitted data will be
overwritten.
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Acknowledge Polling
The disabling of the inputs can be used to take advantage
of the typical write cycle time. Once the stop condition
is issued to indicate the end of the host’s write operation,
the CAT24WC03/05 initiates the internal write cycle.
ACK polling can be initiated immediately. This involves
issuing the start condition followed by the slave address
for a write operation. If the CAT24WC03/05 is still busy
with the write operation, no ACK will be returned. If the
CAT24WC03/05 has completed the write operation, an
ACK will be returned and the host can then proceed with
the next read or write operation.
u
n
SLAVE
ADDRESS
BYTE
ADDRESS
DATA
S
S
T
O
P
P
Figure 7. Page Write Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
SLAVE
ADDRESS
BYTE
ADDRESS (n)
DATA n
DATA n+1
S
T
O
P
DATA n+P
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0
Doc. No. 1005, Rev. F
6
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24WC03/05
In other words, if the last READ or WRITE access was
to address N, the READ immediately following would
access data from address N+1. If N=E (where E = 255
for the CAT24WC03 and 511 for the CAT24WC05), then
the counter will ‘wrap around’ to address 0 and continue
to clock out data. After the CAT24WC03/05 receives its
slave address information (with the R/W bit set to one),
it issues an acknowledge, then transmits the 8-bit byte
requested. The master device does not send an
acknowledge but will generate a STOP condition.
WRITE PROTECTION
The Write Protection feature allows the user to protect
against inadvertent programming of the memory array.
If the WP pin is tied to VCC, the upper half (locations 80H
to FFH for CAT24WC03 and locations 100H to 1FFH for
CAT24WC05) of the memory array is protected and
becomes read only. The CAT24WC03/05 will accept
both slave and byte addresses, but the memory location
accessed is protected from programming by the device’s
failure to send an acknowledge after the first byte of data
is received.
Selective Read
READ OPERATIONS
The READ operation for the CAT24WC03/05 is initiated
in the same manner as the write operation with the one
exception that the R/W bit is set to a one. Three different
READ operations are possible: Immediate Address
READ, Selective READ and Sequential READ.
Immediate Address Read
The CAT24WC03/05 address counter contains the
address of the last byte accessed incremented by one.
Figure 8. Immediate Address Read Timing
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BUS ACTIVITY:
MASTER
SDA LINE
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SCL
S
T
A
R
T
S
a
P
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e
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SLAVE
ADDRESS
A
C
K
S
T
O
P
P
DATA
N
O
A
C
K
8
SDA
s
t
r
Selective READ operations allow the Master device to
select at random any memory location for a READ
operation. The Master device first performs a ‘dummy’
write operation by sending the START condition, slave
address and byte address of the location it wishes to
read. After the CAT24WC03/05 acknowledge the word
address, the Master device resends the START condition
and the slave address, this time with the R/W bit set to
one. The CAT24WC03/05 then responds with its
acknowledge and sends the 8-bit byte requested. The
master device does not send an acknowledge but will
generate a STOP condition.
9
8TH BIT
DATA OUT
NO ACK
STOP
Figure 9. Selective Read Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
SLAVE
ADDRESS
S
T
A
R
T
BYTE
ADDRESS (n)
S
S
T
O
P
SLAVE
ADDRESS
S
A
C
K
A
C
K
P
A
C
K
DATA n
N
O
A
C
K
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
7
Doc. No. 1005, Rev. F
CAT24WC03/05
Sequential Read
The data being transmitted from the CAT24WC03/05 is
outputted sequentially with data from address N followed
by data from address N+1. The READ operation address
counter increments all of the CAT24WC03/05 address
bits so that the entire memory array can be read during
one operation. If more than the E (where E = 255 for the
CAT24WC03 and 511 for the CAT24WC05) bytes are
read out, the counter will “wrap around” and continue to
clock out data bytes.
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT24WC03/05 sends the initial 8bit byte requested, the Master will respond with an
acknowledge which tells the device it requires more
data. The CAT24WC03/05 will continue to output an 8bit byte for each acknowledge sent by the Master. The
operation is terminated when the Master fails to respond
with an acknowledge, thus sending the STOP condition.
Figure 10. Sequential Read Timing
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
SDA LINE
A
C
K
A
C
K
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A
C
K
A
C
K
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a
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DATA n+x
N
O
s
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S
T
O
P
P
A
C
K
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Doc. No. 1005, Rev. F
8
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24WC03/05
8-LEAD 300 MIL WIDE PLASTIC DIP (P, L, GL)
0.245 (6.17)
0.295 (7.49)
0.300 (7.62)
0.325 (8.26)
0.355 (9.02)
0.400 (10.16)
0.120 (3.05)
0.150 (3.81) 0.180 (4.57) MAX
0.015 (0.38)
0.110 (2.79)
0.150 (3.81)
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0.100 (2.54)
BSC
0.045 (1.14)
0.060 (1.52)
0.014 (0.36)
0.022 (0.56)
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0.310 (7.87)
0.380 (9.65)
Notes:
1. Complies with JEDEC Publication 95 MS001 dimensions; however, some of the dimensions may be more stringent.
2. All linear dimensions are in inches and parenthetically in millimeters.
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8-LEAD 150 MIL WIDE SOIC (J, W, GW)
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0.1497 (3.80)
0.1574 (4.00)
0.1890 (4.80)
0.1968 (5.00)
0.2284 (5.80)
0.2440 (6.20)
0.0099 (0.25)
X 45
0.0196 (0.50)
0.0075 (0.19)
0.0098 (0.25)
0.0532 (1.35)
0.0688 (1.75)
0 —8
0.050 (1.27) BSC
0.013 (0.33)
0.020 (0.51)
0.0040 (0.10)
0.0098 (0.25)
0.016 (0.40)
0.050 (1.27)
Notes:
1. Complies with JEDEC publication 95 MS-012 dimensions; however, some dimensions may be more stringent.
2. All linear dimensions are in inches and parenthetically in millimeters.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
9
Doc. No. 1005, Rev. F
CAT24WC03/05
8 LEAD MSOP (R, Z, GZ)
0.38
0.28
0.0150
0.0110
0.1970
0.1890
5.00
4.80
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0.0256 [0.65] BSC
0.1220
0.1142
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0.0433 [1.10] MAX.
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0.039 [0.10] MAX.
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0.0276
0.0157
0.70
0.40
0.1220
0.1142
3.10
2.90
3.10
2.90
S
0.0059
0.0020
S
0.15
0.05
0.0374
0.0295
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0.95
0.75
S
0.0150
0.0110
0.38
0.28
WITH PLATING
0.0091
0.0051
0.23
0.13
0.0050 [0.127]
0˚ - 6˚
WITH
PLATING
BASE METAL
0.0118 [0.30] REF.
SECTION A - A
Notes:
(1) All dimensions are in mm Angles in degrees.
2 Does not include Mold Flash, Protrusion or Gate Burrs. Mold Flash, Protrusions or Gate Burrs shall not exceed 0.15 mm. per side.
3 Does not include Interlead Flash orProtrusion. Interlead Flash or Protrusion shall not exceed 0.25 mm per side.
4 Does not include Dambar Protrusion, allowable Dambar Protrusion shall be 0.08 mm.
(5) This part is compliant with JEDEC Specification MO-187 Variations AA.
(6) Lead span/stand off height/coplanarity are considered as special characteristics. (S)
(7) Controlling dimensions in inches. [mm]
Doc. No. 1005, Rev. F
10
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24WC03/05
8-LEAD TSSOP (U, Y, GY)
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© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
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Doc. No. 1005, Rev. F
CAT24WC03/05
ORDERING INFORMATION
Prefix
Device #
Suffix
CAT
24WC03
Optional
Company ID
Product Number
24WC03: 2K
24WC05: 4K
J
-1.8
I
Temperature Range
Blank = Commercial (0°C to 70°C)
I = Industrial (-40°C to 85°C)
A = Automotive (-40°C to 105°C)
E = Extended (-40°C to 125°C)
Package
P: PDIP
J: SOIC, JEDEC
R: MSOP
U: TSSOP
L: PDIP (Lead-free, Halogen-free)
W: SOIC, JEDEC (Lead-free, Halogen-free)
Z: MSOP (Lead-free, Halogen-free)
Y: TSSOP (Lead-free, Halogen-free)
GL: PDIP (Lead-free, Halogen-free, NiPdAu lead plating)
GW: SOIC, JEDEC (Lead-free, Halogen-free, NiPdAu lead plating)
GZ: MSOP (Lead-free, Halogen-free, NiPdAu lead plating)
GY: TSSOP (Lead-free, Halogen-free, NiPdAu lead plating)
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REV-C
Tape & Reel
a
P
Operating Voltage
Blank: 2.5V - 5.5V
1.8: 1.8V - 5.5V
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TE13
s
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Die Revision
24WC03: C
24WC05: A
Notes:
(1) The device used in the above example is a CAT24WC03JI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 5.5 Volt Operating
Voltage, Tape & Reel)
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Doc. No. 1005, Rev. F
12
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24WC03/05
REVISION HISTORY
Date
Revision Comments
7/24/2001
A
Initial issue
2/3/2004
B
Added: CAT24WC03 not recommended for new designs. See
CAT24FC03 data sheet.
04/18/04
C
Add Lead Free Logo
Update Features
Update Ordering Information
Add Revision History
Update Rev Number
05/18/04
D
Delete: CAT24WC03 not recommended for new designs. See
CAT24FC03 data sheet.
Update Revision History
Update Rev Number
06/07/04
E
Added Die Revision to Ordering Information
08/12/05
F
Update Features
Update Pin Functions
d
e
Update Reliability Characteristics
Update D.C. Operating Characteristics
Update A.C. Characteristics
Add Page Dimensions
Update Ordering Information
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© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
13
Doc. No. 1005, Rev. F
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Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP ™
AE2 ™
MiniPot™
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Publication #:
Revison:
Issue date:
1005
F
08/12/05