CAT28C64B 64K-Bit CMOS PARALLEL E2PROM FEATURES ■ Fast Read Access Times: ■ Commercial, Industrial and Automotive – 120/150ns Temperature Ranges ■ Low Power CMOS Dissipation: ■ Automatic Page Write Operation: – Active: 25 mA Max. – Standby: 100 µA Max. – 1 to 32 Bytes in 5ms – Page Load Timer ■ Simple Write Operation: ■ End of Write Detection: – On-Chip Address and Data Latches – Self-Timed Write Cycle with Auto-Clear – Toggle Bit – DATA Polling ■ Fast Write Cycle Time: ■ 100,000 Program/Erase Cycles – 5ms Max. ■ 100 Year Data Retention ■ CMOS and TTL Compatible I/O ■ Hardware and Software Write Protection DESCRIPTION The CAT28C64B is manufactured using Catalyst’s advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data retention of 100 years. The device is available in JEDECapproved 28-pin DIP, 28-pin TSOP, 28-pin SOIC, or, 32pin PLCC package . The CAT28C64B is a fast, low power, 5V-only CMOS Parallel E2PROM organized as 8K x 8-bits. It requires a simple interface for in-system programming. On-chip address and data latches, self-timed write cycle with auto-clear and VCC power up/down write protection eliminate additional timing and protection hardware. DATA Polling and Toggle status bits signal the start and end of the self-timed write cycle. Additionally, the CAT28C64B features hardware and software write protection. BLOCK DIAGRAM A5–A12 ADDR. BUFFER & LATCHES ROW DECODER VCC INADVERTENT WRITE PROTECTION HIGH VOLTAGE GENERATOR CE OE WE CONTROL LOGIC 32 BYTE PAGE REGISTER I/O BUFFERS TIMER A0–A4 8,192 x 8 E2PROM ARRAY DATA POLLING AND TOGGLE BIT ADDR. BUFFER & LATCHES I/O0–I/O7 COLUMN DECODER 5094 FHD F02 © 1999 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. 25006-0A 2/98 P-1 CAT28C64B PIN CONFIGURATION DIP Package (P) NC 1 28 SOIC Package (J, K) VCC A12 2 27 WE A7 A6 3 4 26 25 NC A8 A5 5 24 A9 A4 A3 6 23 22 A11 OE 21 A10 A2 7 8 A1 9 20 CE A0 10 I/O0 I/O1 11 12 19 18 17 I/O7 I/O6 I/O5 I/O2 VSS 13 14 16 15 I/O4 I/O3 NC 1 28 VCC A12 A7 A6 A5 A4 2 3 4 5 6 27 26 25 24 23 WE NC A8 A9 A11 A3 A2 A1 A0 7 8 9 10 11 22 21 20 19 18 OE 12 13 14 17 A10 CE I/O7 I/O6 I/O5 16 15 I/O4 I/O3 I/O0 I/O1 I/O2 VSS TSOP Package (8mm x 13.4mm) (T13) A7 A12 NC NC VCC WE NC PLCC Package (N) 4 3 2 1 32 31 30 A6 A5 A4 A3 A2 A1 A0 NC 29 28 27 26 9 10 11 12 TOP VIEW 25 24 23 22 13 21 14 15 16 17 18 19 20 A8 A9 A11 NC OE A10 CE I/O7 I/O6 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 I/O1 I/O2 VSS NC I/O3 I/O4 I/O5 I/O0 5 6 7 8 OE A11 A9 A8 NC WE VCC NC A12 A7 A6 A5 A4 A3 28C64B F03 5094 FHD F01 PIN FUNCTIONS Pin Name Function Pin Name Function A0–A12 Address Inputs WE Write Enable I/O0–I/O7 Data Inputs/Outputs VCC 5 V Supply CE Chip Enable VSS Ground OE Output Enable NC No Connect Doc. No. 25006-0A 2/98 P-1 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 2 CAT28C64B ABSOLUTE MAXIMUM RATINGS* *COMMENT Temperature Under Bias ................. –55°C to +125°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Storage Temperature ....................... –65°C to +150°C Voltage on Any Pin with Respect to Ground(2) ........... –2.0V to +VCC + 2.0V VCC with Respect to Ground ............... –2.0V to +7.0V Package Power Dissipation Capability (Ta = 25°C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300°C Output Short Circuit Current(3) ........................ 100 mA RELIABILITY CHARACTERISTICS Symbol NEND(1) TDR (1) VZAP(1) ILTH (1)(4) Parameter Min. Max. Units Test Method Endurance 105 Cycles/Byte MIL-STD-883, Test Method 1033 Data Retention 100 Years MIL-STD-883, Test Method 1008 ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015 Latch-Up 100 mA JEDEC Standard 17 MODE SELECTION Mode CE WE OE Read L H Byte Write (WE Controlled) L Byte Write (CE Controlled) I/O Power L DOUT ACTIVE H DIN ACTIVE L H DIN ACTIVE Standby, and Write Inhibit H X X High-Z STANDBY Read and Write Inhibit X H H High-Z ACTIVE CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V Symbol Test Max. Units Conditions CI/O(1) Input/Output Capacitance 10 pF VI/O = 0V CIN(1) Input Capacitance 6 pF VIN = 0V Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (3) Output shorted for no more than one second. No more than one output shorted at a time. (4) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC +1V. 3 Doc. No. 25006-0A 2/98 P-1 CAT28C64B D.C. OPERATING CHARACTERISTICS VCC = 5V ±10%, unless otherwise specified. Limits Symbol Parameter Min. Typ. Max. Units Test Conditions ICC VCC Current (Operating, TTL) 30 mA CE = OE = VIL, f = 1/tRC min, All I/O’s Open ICCC(1) VCC Current (Operating, CMOS) 25 mA CE = OE = VILC, f = 1/tRC min, All I/O’s Open ISB VCC Current (Standby, TTL) 1 mA CE = VIH, All I/O’s Open ISBC(2) VCC Current (Standby, CMOS) 100 µA CE = VIHC, All I/O’s Open ILI Input Leakage Current –10 10 µA VIN = GND to VCC ILO Output Leakage Current –10 10 µA VOUT = GND to VCC, CE = VIH VIH(2) High Level Input Voltage 2 VCC +0.3 V VIL(1) Low Level Input Voltage –0.3 0.8 V VOH High Level Output Voltage 2.4 VOL Low Level Output Voltage VWI Write Inhibit Voltage 0.4 3.5 IOH = –400µA V IOL = 2.1mA V Note: (1) VILC = –0.3V to +0.3V. (2) VIHC = VCC –0.3V to VCC +0.3V. Doc. No. 25006-0A 2/98 P-1 V 4 CAT28C64B A.C. CHARACTERISTICS, Read Cycle VCC = 5V ±10%, unless otherwise specified. 28C64B-12 Symbol Parameter Min. Max. 120 28C64B-15 Min. Max. Units tRC Read Cycle Time 150 tCE CE Access Time 120 150 ns tAA Address Access Time 120 150 ns tOE OE Access Time 60 70 ns tLZ(1) CE Low to Active Output 0 0 ns tOLZ(1) OE Low to Active Output 0 0 ns tHZ(1)(2) CE High to High-Z Output 50 50 ns tOHZ(1)(2) OE High to High-Z Output 50 50 ns tOH(1) Output Hold from Address Change 0 ns 0 ns Figure 1. A.C. Testing Input/Output Waveform(3) 2.4 V 2.0 V INPUT PULSE LEVELS REFERENCE POINTS 0.8 V 0.45 V 5096 FHD F03 Figure 2. A.C. Testing Load Circuit (example) 1.3V 1N914 3.3K DEVICE UNDER TEST OUT CL = 100 pF CL INCLUDES JIG CAPACITANCE 5096 FHD F04 Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer. (3) Input rise and fall times (10% and 90%) < 10 ns. 5 Doc. No. 25006-0A 2/98 P-1 CAT28C64B A.C. CHARACTERISTICS, Write Cycle VCC = 5V ±10%, unless otherwise specified. 28C64B-12 Min. Max. 28C64B-15 Symbol Parameter Min. tWC Write Cycle Time tAS Address Setup Time 0 0 ns tAH Address Hold Time 100 100 ns tCS CE Setup Time 0 0 ns tCH CE Hold Time 0 0 ns tCW(2) CE Pulse Time 110 110 ns tOES OE Setup Time 0 0 ns tOEH OE Hold Time 0 0 ns tWP(2) WE Pulse Width 110 110 ns tDS Data Setup Time 60 60 ns tDH Data Hold Time 0 0 ns tINIT(1) Write Inhibit Period After Power-up 5 10 5 10 ms tBLC(1)(3) Byte Load Cycle Time .05 100 .05 100 µs 5 Max. Units 5 ms Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) A write pulse of less than 20ns duration will not initiate a write cycle. (3) A timer of duration tBLC max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin; however a transition from HIGH to LOW within tBLC max. stops the timer. Doc. No. 25006-0A 2/98 P-1 6 CAT28C64B Byte Write DEVICE OPERATION A write cycle is executed when both CE and WE are low, and OE is high. Write cycles can be initiated using either WE or CE, with the address input being latched on the falling edge of WE or CE, whichever occurs last. Data, conversely, is latched on the rising edge of WE or CE, whichever occurs first. Once initiated, a byte write cycle automatically erases the addressed byte and the new data is written within 5 ms. Read Data stored in the CAT28C64B is transferred to the data bus when WE is held high, and both OE and CE are held low. The data bus is set to a high impedance state when either CE or OE goes high. This 2-line control architecture can be used to eliminate bus contention in a system environment. Figure 3. Read Cycle tRC ADDRESS tCE CE tOE OE VIH tLZ WE tOHZ DATA OUT tHZ tOH tOLZ HIGH-Z DATA VALID DATA VALID tAA 28C64B F06 Figure 4. Byte Write Cycle [WE Controlled] tWC ADDRESS tAS tAH tCH tCS CE OE tOES tWP tOEH WE tBLC DATA OUT DATA IN HIGH-Z DATA VALID tDS tDH 5096 FHD F06 7 Doc. No. 25006-0A 2/98 P-1 CAT28C64B Page Write (which can be loaded in any order) during the first and subsequent write cycles. Each successive byte load cycle must begin within tBLC MAX of the rising edge of the preceding WE pulse. There is no page write window limitation as long as WE is pulsed low within tBLC MAX. The page write mode of the CAT28C64B (essentially an extended BYTE WRITE mode) allows from 1 to 32 bytes of data to be programmed within a single E2PROM write cycle. This effectively reduces the byte-write time by a factor of 32. Upon completion of the page write sequence, WE must stay high a minimum of tBLC MAX for the internal automatic program cycle to commence. This programming cycle consists of an erase cycle, which erases any data that existed in each addressed cell, and a write cycle, which writes new data back into the cell. A page write will only write data to the locations that were addressed and will not rewrite the entire page. Following an initial WRITE operation (WE pulsed low, for tWP, and then high) the page write mode can begin by issuing sequential WE pulses, which load the address and data bytes into a 32 byte temporary buffer. The page address where data is to be written, specified by bits A5 to A12, is latched on the last falling edge of WE. Each byte within the page is defined by address bits A0 to A4 Figure 5. Byte Write Cycle [CE Controlled] tWC ADDRESS tAS tAH tBLC tCW CE tOEH OE tCS tOES tCH WE HIGH-Z DATA OUT DATA IN DATA VALID tDS tDH 5094 FHD F07 Figure 6. Page Mode Write Cycle OE CE t WP t BLC WE ADDRESS t WC I/O LAST BYTE BYTE 0 BYTE 1 BYTE 2 BYTE n BYTE n+1 BYTE n+2 5096 FHD F10 Doc. No. 25006-0A 2/98 P-1 8 CAT28C64B DATA Polling Toggle Bit DATA polling is provided to indicate the completion of write cycle. Once a byte write or page write cycle is initiated, attempting to read the last byte written will output the complement of that data on I/O7 (I/O0–I/O6 are indeterminate) until the programming cycle is complete. Upon completion of the self-timed write cycle, all I/O’s will output true data during a read cycle. In addition to the DATA Polling feature, the device offers an additional method for determining the completion of a write cycle. While a write cycle is in progress, reading data from the device will result in I/O6 toggling between one and zero. However, once the write is complete, I/O6 stops toggling and valid data can be read from the device. Figure 7. DATA Polling ADDRESS CE WE tOEH tOES tOE OE tWC I/O7 DIN = X DOUT = X DOUT = X 28C64B F10 Figure 8. Toggle Bit WE CE tOEH tOES tOE OE I/O6 (1) (1) tWC 28C64B F11 Note: (1) Beginning and ending state of I/O6 is indeterminate. 9 Doc. No. 25006-0A 2/98 P-1 CAT28C64B HARDWARE DATA PROTECTION (4) Noise pulses of less than 20 ns on the WE or CE inputs will not result in a write cycle. The following is a list of hardware data protection features that are incorporated into the CAT28C64B. SOFTWARE DATA PROTECTION (1) VCC sense provides for write protection when VCC falls below 3.5V min. The CAT28C64B features a software controlled data protection scheme which, once enabled, requires a data algorithm to be issued to the device before a write can be performed. The device is shipped from Catalyst with the software protection NOT ENABLED (the CAT28C64B is in the standard operating mode). (2) A power on delay mechanism, tINIT (see AC characteristics), provides a 5 to 10 ms delay before a write sequence, after VCC has reached 3.5V min. (3) Write inhibit is activated by holding any one of OE low, CE high or WE high. Figure 9. Write Sequence for Activating Software Data Protection WRITE DATA: ADDRESS: WRITE DATA: ADDRESS: WRITE DATA: ADDRESS: Figure 10. Write Sequence for Deactivating Software Data Protection AA WRITE DATA: 1555 ADDRESS: 55 WRITE DATA: 0AAA ADDRESS: A0 WRITE DATA: 1555 ADDRESS: SOFTWARE DATA (1) PROTECTION ACTIVATED WRITE DATA: WRITE DATA: ADDRESS: XX WRITE DATA: TO ANY ADDRESS ADDRESS: WRITE LAST BYTE TO LAST ADDRESS WRITE DATA: ADDRESS: 28C64B F12 AA 1555 55 0AAA 80 1555 AA 1555 55 0AAA 20 1555 5094 FHD F09 Note: (1) Write protection is activated at this point whether or not any more writes are completed. Writing to addresses must occur within tBLC Max., after SDP activation. Doc. No. 25006-0A 2/98 P-1 10 CAT28C64B To activate the software data protection, the device must be sent three write commands to specific addresses with specific data (Figure 9). This sequence of commands (along with subsequent writes) must adhere to the page write timing specifications (Figure 11). Once this is done, all subsequent byte or page writes to the device must be preceded by this same set of write commands. The data protection mechanism is activated until a deactivate sequence is issued regardless of power on/off transitions. This gives the user added inadvertent write protection on power-up in addition to the hardware protection provided. To allow the user the ability to program the device with an E2PROM programmer (or for testing purposes) there is a software command sequence for deactivating the data protection. The six step algorithm (Figure 10) will reset the internal protection circuitry, and the device will return to standard operating mode (Figure 12 provides reset timing). After the sixth byte of this reset sequence has been issued, standard byte or page writing can commence. Figure 11. Software Data Protection Timing DATA ADDRESS AA 1555 55 0AAA tWC A0 1555 CE tWP tBLC BYTE OR PAGE WRITES ENABLED WE 5094 FHD F13 Figure 12. Resetting Software Data Protection Timing DATA ADDRESS AA 1555 55 0AAA 80 1555 AA 1555 55 0AAA 20 1555 tWC SDP RESET CE DEVICE UNPROTECTED WE 5094 FHD F14 ORDERING INFORMATION Prefix Device # Suffix CAT 28C64B N Product Number Optional Company ID I Temperature Range Blank = Commercial (0˚C to +70˚C) I = Industrial (-40˚C to +85˚C) A = Automotive (-40˚ to +105˚C)* Package P: PDIP J: SOIC (JEDEC) K: SOIC (EIAJ) N: PLCC T13: TSOP (8mmx13.4mm) * -40˚C to +125˚C is available upon request -15 T Tape & Reel T: 500/Reel Speed 12: 120ns 15: 150ns 28C64B F15 Notes: (1) The device used in the above example is a CAT28C64BNI-15T (PLCC, Industrial temperature, 150 ns Access Time, Tape & Reel). 11 Doc. No. 25006-0A 2/98 P-1 CAT28C64B Doc. No. 25006-0A 2/98 P-1 12