Preliminary CAT28LV65 64K-Bit CMOS PARALLEL E2PROM FEATURES ■ 3.0V to 3.6V Supply ■ CMOS and TTL Compatible I/O ■ Read Access Times: ■ Automatic Page Write Operation: – 1 to 32 Bytes in 5ms – Page Load Timer – 250/300/350ns ■ Low Power CMOS Dissipation: ■ End of Write Detection: – Active: 8 mA Max. – Standby: 100 µA Max. – Toggle Bit – DATA Polling BUSY – RDY/BUSY ■ Simple Write Operation: – On-Chip Address and Data Latches – Self-Timed Write Cycle with Auto-Clear ■ Hardware and Software Write Protection ■ 100,000 Program/Erase Cycles ■ Fast Write Cycle Time: – 5ms Max. ■ 100 Year Data Retention ■ Commercial, Industrial and Automotive Temperature Ranges DESCRIPTION The CAT28LV65 is manufactured using Catalyst’s advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data retention of 100 years. The device is available in JEDEC approved 28-pin DIP, 28-pin TSOP, 28-pin SOIC or 32pin PLCC packages. The CAT28LV65 is a low voltage, low power, CMOS parallel E2PROM organized as 8K x 8-bits. It requires a simple interface for in-system programming. On-chip address and data latches, self-timed write cycle with auto-clear and VCC power up/down write protection eliminate additional timing and protection hardware. DATA Polling, RDY/BUSY and Toggle status bit signal the start and end of the self-timed write cycle. Additionally, the CAT28LV65 features hardware and software write protection. BLOCK DIAGRAM A5–A12 ADDR. BUFFER & LATCHES ROW DECODER VCC INADVERTENT WRITE PROTECTION HIGH VOLTAGE GENERATOR CE OE WE CONTROL LOGIC 32 BYTE PAGE REGISTER I/O BUFFERS TIMER A0–A4 8,192 x 8 E2PROM ARRAY DATA POLLING, RDY/BUSY & TOGGLE BIT ADDR. BUFFER & LATCHES COLUMN DECODER RDY/BUSY © 1998 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice I/O0–I/O7 28LV65 F01 1 Doc. No. 25041-00 2/98 CAT28LV65 Preliminary PIN CONFIGURATION DIP Package (P) SOIC Package (J, K) RDY/BUSY 1 28 VCC RDY/BUSY 1 28 VCC A12 A7 2 3 27 26 WE NC A12 A7 2 3 27 26 WE NC A6 A5 4 25 4 25 A8 24 A8 A9 A6 5 A5 5 24 A4 A3 6 23 22 A11 6 23 A10 CE 7 8 22 21 A9 A11 OE 21 A4 A3 A2 A1 9 20 A10 CE 10 11 19 18 I/O7 I/O6 12 13 14 17 I/O5 I/O4 I/O3 7 8 A2 A1 9 20 A0 I/O0 I/O1 10 19 11 12 18 17 I/O2 VSS 13 14 16 15 OE A0 I/O0 I/O1 I/O2 VSS I/O7 I/O6 I/O5 I/O4 I/O3 16 15 PLCC Package (N) A7 A12 RDY/BUSY NC VCC WE NC TSOP Top View (8mm x 13.4mm) (T13) 4 3 2 1 32 31 30 A6 A5 A4 A3 5 6 7 8 29 28 27 26 A2 A1 A0 NC 9 10 11 12 TOP VIEW 25 24 23 22 13 21 14 15 16 17 18 19 20 I/O7 I/O6 28LV65 F04 I/O1 I/O2 VSS NC I/O3 I/O4 I/O5 I/O0 A8 A9 A11 NC OE A10 CE 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 OE A11 A9 A8 NC WE Vcc RDY/BUSY A12 A7 A6 A5 A4 A3 PIN FUNCTIONS Pin Name Function Pin Name Function A0–A12 Address Inputs WE Write Enable I/O0–I/O7 Data Inputs/Outputs VCC 3.0 to 3.6 V Supply CE Chip Enable VSS Ground OE Output Enable NC No Connect RDY/BSY Ready/Busy Status Doc. No. 25041-00 2/98 2 A10 CE I/07 I/06 I/05 I/04 I/03 GND I/O2 I/O1 I/O0 A0 A1 A2 Preliminary CAT28LV65 ABSOLUTE MAXIMUM RATINGS* *COMMENT Temperature Under Bias ................. –55°C to +125°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Storage Temperature ....................... –65°C to +150°C Voltage on Any Pin with Respect to Ground(2) ........... –2.0V to +VCC + 2.0V VCC with Respect to Ground ............... –2.0V to +7.0V Package Power Dissipation Capability (Ta = 25°C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300°C Output Short Circuit Current(3) ........................ 100 mA RELIABILITY CHARACTERISTICS Symbol Units Test Method Endurance 105 Cycles/Byte MIL-STD-883, Test Method 1033 TDR(1) Data Retention 100 Years MIL-STD-883, Test Method 1008 VZAP(1) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015 ILTH(1)(4) Latch-Up 100 mA NEND (1) Parameter Min. Max. JEDEC Standard 17 MODE SELECTION Mode CE WE OE Read L H Byte Write (WE Controlled) L Byte Write (CE Controlled) I/O Power L DOUT ACTIVE H DIN ACTIVE L H DIN ACTIVE Standby, and Write Inhibit H X X High-Z STANDBY Read and Write Inhibit X H H High-Z ACTIVE Test Max. Units Conditions Input/Output Capacitance 10 pF VI/O = 0V Input Capacitance 6 pF VIN = 0V CAPACITANCE TA = 25°C, f = 1.0 MHz Symbol CI/O (1) CIN(1) Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (3) Output shorted for no more than one second. No more than one output shorted at a time. (4) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC +1V. 3 Doc. No. 25041-00 2/98 CAT28LV65 Preliminary D.C. OPERATING CHARACTERISTICS Vcc = 3.0V to 3.6V, unless otherwise specified. Limits Symbol Parameter Min. Typ. Max. Units Test Conditions ICC VCC Current (Operating, TTL) 8 mA CE = OE = VIL, f = 1/tRC min, All I/O’s Open ISBC(3) VCC Current (Standby, CMOS) 100 µA CE = VIHC, All I/O’s Open ILI Input Leakage Current –1 1 µA VIN = GND to VCC ILO Output Leakage Current –5 5 µA VOUT = GND to VCC, CE = VIH VIH(3) High Level Input Voltage 2 VCC +0.3 V VIL Low Level Input Voltage –0.3 0.6 V VOH High Level Output Voltage VOL Low Level Output Voltage VWI Write Inhibit Voltage 2 0.3 2 V IOH = –100µA V IOL = 1.0mA V A.C. CHARACTERISTICS, Read Cycle Vcc = 3.0V to 3.6V, unless otherwise specified. 28LV65-25 Symbol Parameter Min. Max. 250 28LV65-30 Min. Max. 300 28LV65-35 Min. Max. 350 Units tRC Read Cycle Time ns tCE CE Access Time 250 300 350 ns tAA Address Access Time 250 300 350 ns tOE OE Access Time 100 150 150 ns CE Low to Active Output 0 0 0 ns tOLZ(1) OE Low to Active Output 0 0 0 ns tHZ(1)(2) CE High to High-Z Output 55 60 60 ns tOHZ(1)(2) OE High to High-Z Output 55 60 60 ns tLZ (1) tOH (1) Output Hold from Address Change 0 0 0 Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer. (3) VIHC = VCC –0.3V to VCC +0.3V. Doc. No. 25041-00 2/98 4 ns Preliminary CAT28LV65 Figure 1. A.C. Testing Input/Output Waveform(4) VCC - 0.3 V 2.0 V INPUT PULSE LEVELS REFERENCE POINTS 0.6 V 0.0 V 28LV65 F05 Figure 2. A.C. Testing Load Circuit (example) Vcc 1.8 K DEVICE UNDER TEST OUTPUT CL= 100 pF 1. 3K CL INCLUDES JIG CAPACITANCE 28LV65 F07 A.C. CHARACTERISTICS, Write Cycle Vcc = 3.0V to 3.6V, unless otherwise specified. 28LV65-25 Symbol Parameter Min. Max. 28LV65-30 Min. 5 Max. 28LV65-35 Min. Units 5 ms tWC Write Cycle Time tAS Address Setup Time 0 0 0 ns tAH Address Hold Time 100 100 100 ns tCS CE Setup Time 0 0 0 ns tCH CE Hold Time 0 0 0 ns tCW(2) CE Pulse Time 150 150 150 ns tOES OE Setup Time 10 10 10 ns tOEH OE Hold Time 10 10 10 ns tWP(2) WE Pulse Width 150 150 150 ns tDS Data Setup Time 100 100 100 ns tDH Data Hold Time 0 0 0 ns tINIT(1) Write Inhibit Period After Power-up 5 10 5 10 5 10 ms tBLC(1)(3) Byte Load Cycle Time 0.1 100 0.1 100 0.1 100 µs tRB WE Low to RDY/BSY Low 220 ns 220 5 Max. 220 Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) A write pulse of less than 20ns duration will not initiate a write cycle. (3) A timer of duration tBLC max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin; however a transition from HIGH to LOW within tBLC max. stops the timer. (4) Input rise and fall times (10% and 90%) < 10 ns. 5 Doc. No. 25041-00 2/98 CAT28LV65 Preliminary Byte Write DEVICE OPERATION A write cycle is executed when both CE and WE are low, and OE is high. Write cycles can be initiated using either WE or CE, with the address input being latched on the falling edge of WE or CE, whichever occurs last. Data, conversely, is latched on the rising edge of WE or CE, whichever occurs first. Once initiated, a byte write cycle automatically erases the addressed byte and the new data is written within 5 ms. Read Data stored in the CAT28LV65 is transferred to the data bus when WE is held high, and both OE and CE are held low. The data bus is set to a high impedance state when either CE or OE goes high. This 2-line control architecture can be used to eliminate bus contention in a system environment. Figure 3. Read Cycle tRC ADDRESS tCE CE tOE OE VIH tLZ WE tOHZ HIGH-Z DATA OUT tHZ tOH tOLZ DATA VALID DATA VALID tAA 28LV65 F06 Figure 4. Byte Write Cycle [WE Controlled] tWC ADDRESS tAS tAH tCH tCS CE OE tOES tWP tOEH WE tRB RDY/BUSY DATA OUT DATA IN tBLC HIGH-Z HIGH-Z HIGH-Z DATA VALID tDS Doc. No. 25041-00 2/98 tDH 6 28LV65 F08 Preliminary CAT28LV65 Page Write (which can be loaded in any order) during the first and subsequent write cycles. Each successive byte load cycle must begin within tBLC MAX of the rising edge of the preceding WE pulse. There is no page write window limitation as long as WE is pulsed low within tBLC MAX. The page write mode of the CAT28LV65 (essentially an extended BYTE WRITE mode) allows from 1 to 32 bytes of data to be programmed within a single E2PROM write cycle. This effectively reduces the byte-write time by a factor of 32. Upon completion of the page write sequence, WE must stay high a minimum of tBLC MAX for the internal automatic program cycle to commence. This programming cycle consists of an erase cycle, which erases any data that existed in each addressed cell, and a write cycle, which writes new data back into the cell. A page write will only write data to the locations that were addressed and will not rewrite the entire page. Following an initial WRITE operation (WE pulsed low, for tWP, and then high) the page write mode can begin by issuing sequential WE pulses, which load the address and data bytes into a 32 byte temporary buffer. The page address where data is to be written, specified by bits A5 to A12, is latched on the last falling edge of WE. Each byte within the page is defined by address bits A0 to A4 Figure 5. Byte Write Cycle [CE Controlled] tWC ADDRESS tAS tAH tBLC tCW CE tOEH OE tOES tCS tCH WE tRB RDY/BUSY HIGH-Z HIGH-Z HIGH-Z DATA OUT DATA IN DATA VALID tDS 28LV65 F09 tDH Figure 6. Page Mode Write Cycle OE CE t WP t BLC WE ADDRESS t WC I/O LAST BYTE BYTE 0 BYTE 1 BYTE 2 BYTE n BYTE n+1 BYTE n+2 5096 FHD F10 7 Doc. No. 25041-00 2/98 CAT28LV65 Preliminary DATA Polling data from the device will result in I/O6 toggling between one and zero. However, once the write is complete, I/O6 stops toggling and valid data can be read from the device. DATA polling is provided to indicate the completion of write cycle. Once a byte write or page write cycle is initiated, attempting to read the last byte written will output the complement of that data on I/O7 (I/O0–I/O6 are indeterminate) until the programming cycle is complete. Upon completion of the self-timed write cycle, all I/O’s will output true data during a read cycle. BUSY (RDY/BUSY BUSY Ready/BUSY BUSY) The RDY/BUSY pin is an open drain output which indicates device status during programming. It is pulled low during the write cycle and released at the end of programming. Several devices may be OR-tied to the same RDY/BUSY line. Toggle Bit In addition to the DATA Polling feature, the device offers an additional method for determining the completion of a write cycle. While a write cycle is in progress, reading Figure 7. DATA Polling ADDRESS CE WE tOEH tOES tOE OE tWC I/O7 DIN = X DOUT = X DOUT = X 28LV65 F11 Figure 8. Toggle Bit WE CE tOEH tOES tOE OE I/O6 (1) (1) tWC 28LV65 F12 Note: (1) Beginning and ending state of I/O6 is indeterminate. Doc. No. 25041-00 2/98 8 Preliminary CAT28LV65 (4) Noise pulses of less than 20 ns on the WE or CE inputs will not result in a write cycle. HARDWARE DATA PROTECTION The following is a list of hardware data protection features that are incorporated into the CAT28LV65. SOFTWARE DATA PROTECTION (1) VCC sense provides for write protection when VCC falls below 2.0V min. The CAT28LV65 features a software controlled data protection scheme which, once enabled, requires a data algorithm to be issued to the device before a write can be performed. The device is shipped from Catalyst with the software protection NOT ENABLED (the CAT28LV65 is in the standard operating mode). (2) A power on delay mechanism, tINIT (see AC characteristics), provides a 5 to 10 ms delay before a write sequence, after VCC has reached 2.40V min. (3) Write inhibit is activated by holding any one of OE low, CE high or WE high. Figure 9. Write Sequence for Activating Software Data Protection WRITE DATA: ADDRESS: WRITE DATA: ADDRESS: WRITE DATA: ADDRESS: Figure 10. Write Sequence for Deactivating Software Data Protection WRITE DATA: AA ADDRESS: 1555 WRITE DATA: 55 ADDRESS: 0AAA WRITE DATA: A0 ADDRESS: 1555 (1) SOFTWARE DATA (12) PROTECTION ACTIVATED WRITE DATA: WRITE DATA: XX WRITE DATA: TO ANY ADDRESS ADDRESS: WRITE LAST BYTE TO LAST ADDRESS WRITE DATA: ADDRESS: ADDRESS: 5094 FHD F08 AA 1555 55 0AAA 80 1555 AA 1555 55 0AAA 20 1555 5094 FHD F09 Note: (1) Write protection is activated at this point whether or not any more writes are completed. Writing to addresses must occur within tBLC Max., after SDP activation. 9 Doc. No. 25041-00 2/98 CAT28LV65 Preliminary To activate the software data protection, the device must be sent three write commands to specific addresses with specific data (Figure 9). This sequence of commands (along with subsequent writes) must adhere to the page write timing specifications (Figure 11). Once this is done, all subsequent byte or page writes to the device must be preceded by this same set of write commands. The data protection mechanism is activated until a deactivate sequence is issued regardless of power on/off transitions. This gives the user added inadvertent write protection on power-up in addition to the hardware protection provided. To allow the user the ability to program the device with an E2PROM programmer (or for testing purposes) there is a software command sequence for deactivating the data protection. The six step algorithm (Figure 10) will reset the internal protection circuitry, and the device will return to standard operating mode (Figure 12 provides reset timing). After the sixth byte of this reset sequence has been issued, standard byte or page writing can commence. Figure 11. Software Data Protection Timing DATA ADDRESS AA 1555 55 0AAA tWC A0 1555 CE tBLC tWP BYTE OR PAGE WRITES ENABLED WE 5094 FHD F13 Figure 12. Resetting Software Data Protection Timing DATA ADDRESS AA 1555 55 0AAA 80 1555 AA 1555 55 0AAA tWC 20 1555 SDP RESET CE DEVICE UNPROTECTED WE 5094 FHD F14 ORDERING INFORMATION Prefix Device # CAT 28LV65 Suffix N Optional Company ID -25 I Temperature Range Blank = Commercial (0˚C to +70˚C) I = Industrial (-40˚C to +85˚C) A = Automotive (-40˚ to +105˚C)* Product Number Package P: PDIP J: SOIC (JEDEC) K: SOIC (EIAJ) N: PLCC T13: TSOP (8mmx13.4mm) T Tape & Reel T: 500/Reel Speed 25: 250ns 30: 300ns 35: 350ns * -40˚C to +125˚C is available upon request 28LV65 F17 Notes: (1) The device used in the above example is a CAT28LV65NI-25T (PLCC, Industrial temperature, 250 ns Access Time, Tape & Reel). Doc. No. 25041-00 2/98 10