H EE GEN FR ALO CAT34RC02 2-kb I2C Serial EEPROM, Serial Presence Detect LE FEATURES A D F R E ETM ■ 400 kHz I2C bus compatible* ■ Schmitt trigger on SCL and SDA inputs ■ 1.7 to 5.5 volt operation ■ Low power CMOS technology ■ 16-byte page write buffer ■ 1,000,000 program/erase cycles ■ Hardware write protection for entire memory ■ 100 year data retention ■ Permanent and reversible software write ■ 8-pin DIP, SOIC, TSSOP and TDFN packages protection for lower 128 bytes ■ Industrial and extended temperature ranges DESCRIPTION The CAT34RC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each. Catalyst’s advanced CMOS technology substantially reduces device power requirements. The CAT34RC02 features a 16-byte page write buffer. The device operates via the I2C bus serial interface and is available in 8-pin DIP, SOIC, TSSOP and TDFN packages. PIN CONFIGURATION FUNCTIONAL SYMBOL DIP Package (P, L) A0 A1 A2 VSS 1 2 3 4 8 7 6 5 VCC WP SCL SDA SOIC Package (J, W) 1 2 3 4 A0 A1 A2 VSS 8 7 6 5 VCC VCC WP SCL SDA SCL A2, A1, A0 TDFN Package (SP2, VP2) A0 1 8 VCC A1 2 A2 3 7 WP 6 SCL VSS 4 5 SDA CAT34RC02 SDA WP VSS PIN FUNCTIONS TSSOP Package (U, Y) A0 A1 A2 VSS 1 2 3 4 8 7 6 5 Pin Name VCC WP SCL SDA Function A0, A1, A2 Device Address Inputs SDA Serial Data/Address SCL Serial Clock WP Write Protect VCC 1.7 V to 5.5 V Power Supply VSS Ground * Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol. © 2004 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc No. 1052, Rev. K CAT34RC02 ABSOLUTE MAXIMUM RATINGS* *COMMENT Temperature Under Bias .................. -55°C to +125°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Storage Temperature ........................ -65°C to +150°C Voltage on Any Pin with Respect to Ground(1) ............ -2.0 V to VCC + 2.0 V Voltage on A0 .................................................. -2.0 V to +12.0 V VCC with Respect to VSS .............................. -2.0 V to +7.0 V RELIABILITY CHARACTERISTICS Symbol Parameter Reference Test Method Min Units (2)(*) Endurance MIL-STD-883, Test Method 1033 1,000,000 Program/ Erase Cycles Data Retention MIL-STD-883, Test Method 1008 100 Years MIL-STD-883, Test Method 3015 4000 Volts JEDEC Standard 17 100 mA NEND TDR(2)(*) VZAP(2)(*) ESD Susceptibility ILTH(2)(3) Latch-up (*) Page Mode, VCC = 5 V, 25°C D.C. OPERATING CHARACTERISTICS VCC = 1.7 V to 5.5 V, unless otherwise specified. Symbol Parameter Test Conditions ICC Power Supply Current (Read) ICC Min Typ Max Units fSCL = 100 kHz 1 mA Power Supply Current (Write) fSCL = 100 kHz 3 mA ISB(4) Standby Current (VCC = 5.0 V) VIN = GND or VCC 1 µA ILI Input Leakage Current VIN = GND to VCC 1 µA ILO Output Leakage Current VOUT = GND to VCC 1 µA VIL Input Low Voltage –1 VCC x 0.3 V VIH Input High Voltage VCC x 0.7 VCC + 1.0 V VOL1 Output Low Voltage (VCC = 3.0 V) IOL = 3 mA 0.4 V VOL2 Output Low Voltage (VCC = 1.7 V) IOL = 1.5 mA 0.5 V VHV RSWP Set/Clear Overdrive A0 High Voltage VHV - VCC > 4.8 V 10 V Max Units 7 CAPACITANCE TA = 25°C, f = 400 kHz, VCC = 5 V Symbol Test Conditions CI/O(2) Input/Output Capacitance (SDA) VI/O = 0 V 8 pF Input Capacitance (other pins) VIN = 0 V 6 pF ZWPL WP Input Impedance VIN < 0.5 V 5 70 kΩ ZWPH WP Input Impedance VIN > VCC x 0.7 500 CIN (2) Min Typ kΩ Note: (1) The DC input voltage on any pin should not be lower than -0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may undershoot to no less than -2.0 V or overshoot to no more than VCC + 2.0 V, for periods of less than 20 ns. The maximum DC voltage on address pin A0 is +12.0 V. (2) This parameter is tested initially and after a design or process change that affects the parameter. (3) Latch-up protection is provided for stresses up to 100 mA on I/O pins from -1.0 V to VCC + 1.0 V. (4) Standby Current, ISB = 10 µA max at extended temperature range. Doc. No. 1052, Rev. K 2 CAT34RC02 A.C. CHARACTERISTICS VCC = 1.7 V to 5.5 V, unless otherwise specified. Read & Write Cycle Limits Symbol Parameter 1.7 V - 5.5 V Min Max 2.5 V - 5.5 V Min Max Units FSCL Clock Frequency 100 400 kHz TI(1) Noise Suppression Time Constant at SCL, SDA Inputs 100 100 ns tAA SCL Low to SDA Data Out and ACK Out 3.5 0.9 µs tBUF(1) Time the Bus Must be Free Before a New Transmission Can Start tHD:STA Start Condition Hold Time tLOW 4.7 1.3 µs 4 0.6 µs Clock Low Period 4.7 1.3 µs tHIGH Clock High Period 4 0.6 µs tSU:STA Start Condition Setup Time (for a Repeated Start Condition) 4.7 0.6 µs tHD:DAT Data In Hold Time 0 0 ns tSU:DAT Data In Setup Time 250 100 ns tR(1) SDA and SCL Rise Time 1 0.3 µs SDA and SCL Fall Time 300 300 ns tF (1) tSU:STO Stop Condition Setup Time tDH Data Out Hold Time 4 0.6 µs 100 100 ns Power-Up Timing(1)(2) Symbol Parameter tPUR tPUW Min Typ Max Units Power-up to Read Operation 1 ms Power-up to Write Operation 1 ms Max Units 5 ms Write Cycle Limits Symbol Parameter tWR Write Cycle Time Min The write cycle time is the time elapsed between the STOP command (following the write instruction) and the completion of the internal write cycle. During the internal Typ write cycle, SDA is released by the Slave and the device does not acknowledge external commands. Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. 3 Doc No. 1052, Rev. K CAT34RC02 FUNCTIONAL DESCRIPTION PIN DESCRIPTIONS The CAT34RC02 supports the I2C (2-wire) Bus data transmission protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. Data transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The CAT34RC02 operates as a Slave device. Both the Master and Slave devices can operate as either transmitter or receiver, but the Master alone assigns those roles. A maximum of 8 devices may be connected to the bus as determined by the device address inputs A0, A1, and A2. SCL: Serial Clock The serial clock input pin is used to clock all data transfers into or out of the device. SDA: Serial Data/Address The bidirectional serial data/address pin is used to transfer data into and out of the device. This pin is an open drain output in transmit mode. A0, A1, A2: Device Address Inputs These inputs set the device address. When left floating, the address pins are internally pulled to ground. WP: Write Protect This input, when grounded or left floating, allows write operations to the entire memory. When this pin is tied to VCC, the entire memory is write protected. Figure 1. Bus Timing tHIGH tF tLOW tR tLOW SCL tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO SDA IN tAA tBUF tDH SDA OUT Figure 2. Write Cycle Timing SCL 8th Bit Byte n SDA ACK tWR STOP CONDITION START CONDITION Figure 3. Start/Stop Timing SDA SCL START BIT Doc. No. 1052, Rev. K STOP BIT 4 ADDRESS CAT34RC02 I2C BUS PROTOCOL Device Addressing The I2C bus consists of two ‘wires’, SCL and SDA. The two ‘wires’ are connected to the supply (VCC) via pull-up resistors. Master and Slave devices connect to the bus via their respective SCL and SDA pins. The transmitting device pulls down the SDA line to ‘transmit’ a ‘0’ and releases it to ‘transmit’ a ‘1’. The Master initiates a data transfer by creating a START condition on the bus. The Master then broadcasts an 8bit serial Slave address. The four most significant bits of the Slave address (the ‘preamble’) are fixed to 1010 (Ah), for normal read/write operations and 0110 (6h) for Software Write Protect (SWP) operations (Fig. 5). The next three bits, A2, A1 and A0, select one of eight possible Slave devices. The last bit, R/W, specifies whether a Read (1) or Write (0) operation is to be performed. (1) Data transfer may be initiated only when the bus is not busy (see A.C. Characteristics). (2) During a data transfer, the data line must remain stable whenever the SCL line is high. An SDA transition while SCL is high will be interpreted as a START or STOP condition. Acknowledge After processing the Slave address, the Slave responds with an acknowledge (ACK) by pulling down the SDA line during the 9th clock cycle. The Slave will aslo acknowledge the 8-bit byte address and every data byte presented in WRITE mode. In READ mode the Slave shifts out eight bits of data, and then ‘releases’ the SDA line durng the 9th clock cycle. If the Master acknowledges in the 9th clock cycle (by pulling down the SDA line), then the Slave continues transmitting. When data transfer is complete, the Master responds with a NoACK (it does not acknowledge the last data byte) and the Slave stops transmitting and waits for a STOP condition. START Condition The START Condition precedes all commands. It consists of a HIGH to LOW transition on SDA while SCL is HIGH. The START condition acts as a ‘wake-up’ call for the Slave devices. A Slave will not respond to commands unless the MASTER generates a START condition. STOP Condition The STOP condition completes all commands. It consists of a LOW to HIGH transition on SDA while SCL is HIGH. The STOP condition starts the internal write cycle, when following a WRITE command and sends the Slave into standby mode, when following a READ command. Figure 4. Acknowledge Timing SCL FROM MASTER 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE Figure 5. Slave Address Bits 1 0 1 0 A2 A1 A0 R/W Normal Read and Write R/W Programming the Write Protect Register DEVICE ADDRESS 0 1 1 0 A2 A1 5 A0 Doc No. 1052, Rev. K CAT34RC02 acknowledge the Slave address, as long as internal write is in progress. WRITE OPERATIONS Byte Write WRITE PROTECTION In Byte Write mode the Master creates a START condition, and then broadcasts the Slave address, byte address and data to be written. The Slave acknowledges the three bytes by pulling down the SDA line during the 9th clock cycle following each byte. The Master creates a STOP condition after the last ACK from the Slave, which then starts the internal write operation (Fig. 6). During internal write, the Slave will ignore any read/write request from the Master. Hardware Write Protection With the WP pin held HIGH, the entire memory, as well as the SWP flags are protected against WRITE operations (Fig. 9). If the WP pin is left floating or is grounded. then it has no impact on the operation of the CAT34RC02. Software Write Protection Page Write The lower half of memory (first 128 bytes) can be protected against WRITE operations by setting one of two Software Write Protection (SWP) flags/switches. The PSWP (Permanent Software Write Protection) flag can be set but not cleared by the user. The RSWP (Reversible Software Write Protection) flag can be set and cleared by the user. Whereas the PSWP flag can be set ‘in-system’, the RSWP flag is meant to be used during testing. RSWP commands require the presence of a very high voltage (higher than VCC) on address pin A0 and fixed logic levels for the other two address pins. The CAT34RC02 contains 256 bytes of data, arranged in 16 pages of 16 bytes each. The page is selected by the four most significant bits of the address byte presented to the device after the Slave address, while the four least significant bits point to the byte within the page. By ‘loading’ more than one data byte into the device, up to an entire page can be written in one write cycle (Fig. 7). The internal byte address counter will increment after each data byte. If the Master transmits more than 16 data bytes, then earlier bytes will be overwritten by later bytes in a ‘wrap-around’ fashion within the selected page. The internal write cycle is started following the STOP condition created by the Master. The CAT34RC02 is shipped ‘unprotected’. The state of the SWP flags can be read by issuing an ‘Immediate Address Read’ command, with the Slave address ‘preamble’ set to 0110 (6h) instead of the ‘normal’ 1010 (Ah). A SWP READ will return the complemented versions of the two flags in the last two slots of the resulting data byte; the other six more significant bits in the data byte have no meaning to the user (Fig. 11). Acknowledge Polling Acknowledge polling can be used to determine if the CAT34RC02 is busy writing or is ready to accept commands. Polling is implemented by sending a ‘Selective Read’ command (described under READ OPERATIONS) to the device. The CAT34RC02 will not Figure 6. Byte Write Timing BUS ACTIVITY: MASTER SDA LINE S T A R T SLAVE ADDRESS BYTE ADDRESS S T O P DATA S P A C K A C K A C K Figure 7. Page Write Timing BUS ACTIVITY: MASTER SDA LINE S T A R T SLAVE ADDRESS BYTE ADDRESS (n) S DATA n DATA n+1 DATA n+P P * A C K A C K A C K NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0 Doc. No. 1052, Rev. K S T O P 6 A C K A C K CAT34RC02 The PSWP flag can be set (forever) by issuing a ‘Byte Write’ command, with the Slave address preamble set to ‘6h’, followed by a ‘don’t care’ address, followed by ‘don’t care’ data and a STOP condition. The CAT34RC02 will acknowledge the Slave address, dummy byte address and dummy data (Fig. 10). The PSWP flag will be permanently set (after the internal write cycle is completed). command attempts to ‘reaffirm’ one of the two switches, then the CAT34RC02 will not acknowledge the command itself. In addition, the CAT34RC02 will not acknowledge a ‘reaffirming’ SWP command, even if the WP pin is LOW. Power-On Reset (POR) The CAT34RC02 incorporates Power-On Reset (POR) circuitry which protects the device against malfunctioning while VCC is lower than the recommended operating voltage. The SWP commands are shown in Table 1. Table 1. SWP Commands The device will power up into a read-only state and will power-down into a reset state when VCC crosses the POR level of ~1.3V. Slave Address PIN Preamble Device Address R/W W Command A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 SWP READ A2 A1 A0 0 1 1 0 A2 A1 A0 1 RSWP SET 0 0 VHV 0 1 1 0 0 0 1 0 RSWP CLEAR 0 1 VHV 0 1 1 0 0 1 1 0 A2 A1 A0 0 1 1 0 A2 A1 A0 0 PSWP SET READ OPERATIONS Immediate Address Read In standby mode, the CAT34RC02 internal address counter points to the data byte immediately following the last byte accessed by a previous operation. If the ‘previous’ byte was the last byte in memory, then the address counter will point to the first memory byte, etc. If the CAT34RC02 decodes a Slave address with a ‘1’ in the R/W bit position (Fig. 8), it will issue an ACK in the 9th clock cycle, and will then transmit the data byte being pointed at by the address counter. The Master can then stop further transmission by issuing a NoACK, followed by a STOP condition. The CAT34RC02 will not acknowledge RSWP or PSWP commands, once the PSWP flag is set. If the PSWP flag is not set, but the WP pin is HIGH, then the CAT34RC02 will react to RSWP or PSWP commands as follows: if the command attempts to ‘flip’ one of the two SWP switches, then the CAT34RC02 will respond the same way the regular memory would, i.e. the command and address (in this case dummy) are acknowledged, but the data (in this case dummy) will not be acknowledged; if the Selective Read The READ operation can also be started at an address different from the one stored in the address counter. The Figure 8. Immediate Address Read Timing BUS ACTIVITY: MASTER SDA LINE S T A R T S T O P SLAVE ADDRESS S P A C K DATA N O A C K SCL SDA 8 9 8th Bit DATA OUT NO ACK 7 STOP Doc No. 1052, Rev. K CAT34RC02 address counter can be ‘initialized’ by performing a ‘dummy’ WRITE operation (Fig. 12). The START condition is followed by the Slave address (with the R/W bit set to ‘0’) and the desired byte address. Instead of following up with data, the Master then issues a 2nd START, followed by the ‘Immediate Address Read’ sequence, as described earlier. Sequential Read If the Master acknowledges the 1st data byte transmitted by the CAT34RC02, then the device will continue transmitting as long as each data byte is acknowledged by the Master (Fig. 13). If the end of memory is reached during sequential READ, the address counter will ‘wraparound’ to the beginning of memory, etc. Sequential READ works with either ‘Immediate Address Read’ or ‘Selective Read’, the only difference being the starting byte address. Figure 9. Memory Array FFH Hardware Write Protectable (by connecting WP pin to Vcc) 7FH Software Write Protectable (by setting the write protect flags) 00H Figure 10. Software Write Protect (Write) BUS ACTIVITY: MASTER SDA LINE S T A R T SLAVE ADDRESS S BYTE ADDRESS DATA XXXXXXXX XXXXXXXX A C K A C K S T O P P A C K X = Don't Care * For PSWP A0 is at normal CMOS levels and for RSWP, A0 is at VHV which must be held high beyond the end of the STOP condition (approximately 1µs of “overlap” is sufficient). Doc. No. 1052, Rev. K 8 CAT34RC02 Figure 11. Software Write Protect (Read) BUS ACTIVITY: MASTER SDA LINE S T A R T RSWP S T O P PSWP SLAVE ADDRESS S P 00 00 0 0 A C K DATA N O A C K Figure 12. Selective Read Timing BUS ACTIVITY: MASTER SDA LINE S T A R T SLAVE ADDRESS S T A R T BYTE ADDRESS (n) S S T O P SLAVE ADDRESS S A C K P A C K A C K DATA n N O A C K Figure 13. Sequential Read Timing BUS ACTIVITY: MASTER SLAVE ADDRESS DATA n DATA n+1 DATA n+2 S T O P DATA n+x SDA LINE P A C K A C K A C K A C K N O A C K 9 Doc No. 1052, Rev. K CAT34RC02 8–22-LEAD 300 MIL WIDE PLASTIC DIP (P, L) 0.245 (6.17) 0.295 (7.49) 0.300 (7.62) 0.325 (8.26) D 0.120 (3.05) 0.150 (3.81) 0.180 (4.57) MAX 0.015 (0.38) — 0.110 (2.79) 0.150 (3.81) 0.100 (2.54) BSC 0.310 (7.87) 0.380 (9.65) 0.045 (1.14) 0.060 (1.52) 0.014 (0.36) 0.022 (0.56) Dimension D Pkg Min Max 8L 0.355 (9.02) 0.400 (10.16) Notes: 1. Complies with JEDEC Publication 95 MS001 dimensions; however, some of the dimensions may be more stringent. 2. All linear dimensions are in inches and parenthetically in millimeters. Doc. No. 1052, Rev. K 10 CAT34RC02 8-LEAD 150 MIL WIDE SOIC (J, W) 0.149 (3.80) 0.1574 (4.00) 0.2284 (5.80) 0.2440 (6.20) D 0.0532 (1.35) 0.0688 (1.75) 0.050 (1.27) BSC 0.0040 (0.10) 0.0098 (0.25) 0.013 (0.33) 0.020 (0.51) 0.0099 (0.25) X 45˚ 0.0196 (0.50) 0.0075 (0.19) 0.0098 (0.25) 0˚-8˚ 0.016 (0.40) 0.050 (1.27) Dimension D Pkg Min Max 8L 0.1890(4.80) 0.1968(5.00) Notes: 1. Complies with JEDEC publication 95 MS-012 dimensions; however, some dimensions may be more stringent. 2. All linear dimensions are in inches and parenthetically in millimeters. 3. Lead coplanarity is 0.004" (0.102mm) maximum. 11 Doc No. 1052, Rev. K CAT34RC02 8-PAD TDFN 2X3 PACKAGE (VP2, SP2) A 0.75 + 0.05 MAX. 3.00 + 0.10 (S) B 2X 0.15C PIN 1 INDEX AREA 2.00 + 0.10 (S) 2X 0.15C 0.0 - 0.05 1.50 + 0.10 0.10C 0.20 REF. 8X 0.08C C 1.85 + 0.10 DAP SIZE 1.7 X 2.1 C0.35 1 4 0.25 + 0.05 (8X) 8X 0.10 M C AB 0.30 + 0.10 (8X) 0.50 TYP. (6X) 1.50 REF. (2X) NOTE: 1. ALL DIMENSIONS IN MM. ANGLES IN DEGREES. 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMNALS. COPLANARITY SHALL NOT EXCEED 0.08 MM. 3. WARPAGE SHALL NOT EXCEED 0.10 MM. 4. PACKAGE LENGTH / PACKAGE WIDTH ARE NOT CONSIDERED AS SPECIAL CHARACTERISTIC. Doc. No. 1052, Rev. K 12 CAT34RC02 8-LEAD TSSOP (U, Y) 3.0 + 0.1 -A8 5 7.72 TYP 4.16 TYP 6.4 4.4 + 0.1 -B(1.78 TYP) 3.2 0.42 TYP 0.65 TYP 0.2 C B A 1 4 LAND PATTERN RECOMMENDATION ALL LEAD TIPS PIN #1 IDENT. SEE DETAIL A 1.1 MAX TYP 0.1 C ALL LEAD TIPS 0.09 - 0.20 TYP (0.9) -C0.10 + 0.05 TYP 0.65 TYP GAGE PLANE 0.19 - 0.30 TYP 0.3 M A B S C S 0.25 o 0-8 o 0.6+0.1 SEATING PLANE DETAIL A Notes: 1. Lead coplanarity is 0.004" (0.102mm) maximum. 13 Doc No. 1052, Rev. K CAT34RC02 ORDERING INFORMATION Prefix CAT Optional Company ID Device # 34RC02 Product Number Suffix J I TE13 Temperature Range I = Industri E = Extended (-40°C to +125°C) Package P: PDIP J: SOIC (JEDEC) U: TSSOP SP2: TDFN L: PDIP (Lead free, Halogen free) W: SOIC (JEDEC), (Lead free, Halogen free) Y: TSSOP (Lead free, Halogen free) VP2: TDFN (Lead free, Halogen free) REV-E Die Revision Tape & Reel Notes: (1) The device used in the above example is a 34RC02JI-TE13 (SOIC, Industrial Temperature, 1.7 Volt to 5.5 Volt Operating Voltage, Tape & Reel) Doc. No. 1052, Rev. K 14 CAT34RC02 REVISION HISTORY Date Revision Comments 09/22/03 A Initial Issue 12/09/03 B Removed Automotive temperature range Changed Industrial Temp to “ I” from “ Blank” in ordering information 01/12/04 C Updated Features Replaced Block Diagram with Functional Symbol Updated Notes for Reliability Characteristics, D.C. Operating Characteristics and Capacitance Updated TDFN package Updated packaging information to reflect new TDFN package 02/20/04 D Re-labeled TDFN package to A0, A1, A2 instead of A1, A2, A3 03/22/04 E Updated Absolute Max. Ratings Updated DC Operating Characteristics Updated Table 1 (SWP Commands) Updated Fig 11 Added mechanical package drawings Corrected TDFN drawing 03/31/04 F Corrected table 1 SWP Commands 05/16/04 G Update D.C. Operating Characteristics Update Write Cycle Limits Update Revision History Update Rev Number 06/03/04 H Update Die Revision in Ordering Information Eliminate data sheet designation Updated DC Operating Characteristics 06/07/04 I Updated Write Cycle Limits 9/27/04 J Added Power-On Reset (POR) description Added VHV and deleted ∆VHV in DC Operating Characteristics 10/18/04 K Updated DC Operating Characteristics & notes (removed Note 5) 15 Doc No. 1052, Rev. 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Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catalyst-semiconductor.com Publication #: Revison: Issue date: 1052 K 10/18/04