H CAT5269 EE GEN FR ALO Dual Digitally Programmable Potentiometers (DPP™) with 256 Taps and 2-wire Interface LE A D F R E ETM FEATURES ■ Two linear taper digitally programmable poten- ■ Automatic recall of saved wiper settings at tiometers power up ■ 256 resistor taps per potentiometer ■ 2.5 to 6.0 volt operation Ω or 100kΩ Ω ■ End to end resistance 50kΩ ■ Standby current less than 1 µA ■ Potentiometer control and memory access via ■ 1,000,000 nonvolatile WRITE cycles 2-wire interface (I2C like) ■ 100 year nonvolatile memory data retention Ω ■ Low wiper resistance, typically 100Ω ■ 24-lead SOIC and TSSOP packages ■ Nonvolatile memory storage for up to four ■ Industrial temperature range wiper settings for each potentiometer DESCRIPTION The CAT5269 is two digitally programmable potentiometers (DPPs™) integrated with control logic and 18 bytes of NVRAM memory. Each DPP consists of a series of resistive elements connected between two externally accessible end points. The tap points between each resistive element are connected to the wiper outputs with CMOS switches. A separate 8-bit control register (WCR) independently controls the wiper tap switches for each DPP. Associated with each wiper control register are four 8-bit non-volatile memory data registers (DR) used for storing up to four wiper settings. Writing to the wiper control register or any of the non-volatile data registers is via a 2-wire serial bus. On power-up, the contents of the first data register (DR0) for each of the four potentiometers is automatically loaded into its respective wiper control registers. PIN CONFIGURATION FUNCTIONAL DIAGRAM The CAT5269 can be used as a potentiometer or as a two terminal, variable resistor. It is intended for circuit level or system level adjustments in a wide variety of applications. It is available in the -40˚C to 85˚C industrial operating temperature range and offered in a 24-lead SOIC and TSSOP packages. SOIC Package (J, W) TSSOP Package (U, Y) RH0 RH1 NC 1 24 A3 A0 2 23 SCL NC 3 22 NC NC 4 21 NC SCL NC 5 20 NC SDA NC NC 6 VCC R L0 7 CAT 19 5269 18 8 17 R W1 R H0 9 16 R H1 RW0 10 15 R L1 A2 11 14 A1 WP 12 13 SDA GND 2-WIRE BUS INTERFACE WIPER CONTROL REGISTERS R W0 R W1 WP A0 A1 A2 A3 CONTROL LOGIC NONVOLATILE DATA REGISTERS RL0 RL1 © 2004 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Document No. 2123, Rev. B CAT5269 PIN DESCRIPTION Pin (SOIC) Name Function 1 NC No Connect 2 A0 Device Address, LSB 3 NC No Connect 4 NC No Connect 5 NC No Connect 6 NC 7 VCC Supply Voltage 8 RL0 Low Reference Terminal for Potentiometer 0 9 RH0 High Reference Terminal for Potentiometer 0 10 RW0 11 A2 PIN DESCRIPTIONS SCL: Serial Clock The CAT5269 serial clock input pin is used to clock all data transfers into or out of the device. SDA: Serial Data The CAT5269 bidirectional serial data pin is used to transfer data into and out of the device. The SDA pin is an open drain output and can be wire-Ored with the other open drain or open collector I/Os. No Connect A0, A1, A2, A3: Device Address Inputs These inputs set the device address when addressing multiple devices. A total of sixteen devices can be addressed on a single bus. A match in the slave address must be made with the address input in order to initiate communication with the CAT5269. Wiper Terminal for Potentiometer 0 Device Address 12 WP Write Protection 13 SDA Serial Data Input/Output 14 A1 Device Address 15 RL1 Low Reference Terminal for Potentiometer 1 16 RH1 High Reference Terminal for Potentiometer 1 17 RW1 Wiper Terminal for Potentiometer 1 18 GND Ground 19 NC No Connect 20 NC No Connect 21 NC No Connect 22 NC No Connect 23 SCL Bus Serial Clock 24 A3 Device Address RH, RL: Resistor End Points The two sets of RH and RL pins are equivalent to the terminal connections on a mechanical potentiometer. RW: Wiper The RW pins are equivalent to the wiper terminal of a mechanical potentiometer. WP WP: Write Protect Input The WP pin when tied low prevents non-volatile writes to the data registers (change of wiper control register is allowed) and when tied high or left floating normal read/write operations are allowed. See Write Protection on page 7 for more details. DEVICE OPERATION The CAT5269 is two resistor arrays integrated with a 2-wire serial interface, two 8-bit wiper control registers and eight 8-bit, non-volatile memory data registers. Each resistor array contains 255 separate resistive elements connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL). The tap positions between and at the ends of the series resistors are connected to the output wiper terminals (RW)by a CMOS transistor switch. Only one tap point for each potentiometer is connected to its wiper terminal at a time and is determined by the value of the wiper control register. Data can be read or written to the wiper control registers or the non-volatile memory data registers via the 2-wire bus. Additional instructions allow data to be transferred between the wiper control registers and each respective potentiometer's non-volatile data registers. Also, the device can be instructed to operate in an "increment/decrement" mode. Document No. 2123, Rev. B 2 CAT5269 ABSOLUTE MAXIMUM RATINGS* *COMMENT Temperature Under Bias ................. –55°C to +125°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Storage Temperature ....................... –65°C to +150°C Voltage on any Pin with Respect toVSS(1)(2) ................ –2.0V to +VCC +2.0V VCC with Respect to Ground ............... –2.0V to +7.0V Recommended Operating Conditions: Package Power Dissipation Capability (Ta = 25°C) ................................... 1.0W VCC = +2.5V to +6.0V Temperature Industrial Lead Soldering Temperature (10 secs) ............ 300°C Wiper Current .................................................... +6mA Min -40°C Max 85°C Note: (1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (2) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V. POTENTIOMETER CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.) Limits Typ. Symbol Parameter Min. Max. Units RPOT Potentiometer Resistance (100KΩ) 100 kΩ RPOT Potentiometer Resistance (50KΩ) 50 kΩ Test Conditions Potentiometer Resistance Tolerance +20 % RPOT Matching 1 % Power Rating 50 mW IW Wiper Current +3 mA RW Wiper Resistance 200 300 Ω IW = +3mA @ VCC = 3V RW Wiper Resistance 100 150 Ω IW = +3mA @ VCC = 5V VTERM Voltage on any RH or RL Pin VCC V VSS = 0V VN Noise nV/√Hz (1) VSS Resolution 0.4 25°C, each pot % Absolute Linearity (2) +1 LSB (4) Rw(n)(actual)-R(n)(expected)(5) Relative Linearity (3) +0.2 LSB (4) Rw(n+1)-[Rw(n)+LSB](5) ppm/˚C (1) ppm/˚C (1) TCRPOT Temperature Coefficient of RPOT +300 TCRATIO Ratiometric Temp. Coefficient CH/CL/CW Potentiometer Capacitances 10/10/25 pF (1) fc Frequency Response 0.4 MHz RPOT = 50KΩ(1) 20 Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) Absolute linearity is utilitzed to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (3) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (4) LSB = RTOT / 255 or (RH - RL) / 255, single pot (5) n = 0, 1, 2, ..., 255 3 Document No. 2123, Rev. B CAT5269 D.C. OPERATING CHARACTERISTICS VCC = +2.5V to +6.0V, unless otherwise specified. Symbol Parameter ICC1 Min Max Units Test Conditions Power Supply Current 1 mA fSCL = 400 KHz, SDA Open VCC = 6 V, Input = GND ICC2 Power Supply Current Non-volatile WRITE 5 mA fSCK = 400 KHz, SDA Open VCC = 6 V, Input = GND ISB Standby Current (VCC = 5.0V) 5 µA VIN = GND or VCC, SDA Open ILI Input Leakage Current 10 µA VIN = GND to VCC ILO Output Leakage Current 10 µA VOUT = GND to VCC VIL Input Low Voltage VCC x 0.3 V VIH Input High Voltage VCC x 0.7 VCC + 1.0 V VOL1 Output Low Voltage (VCC = 3.0V) 0.4 V IOL = 3 mA VOL2 Output Low Voltage (VCC = 1.8V) 0.5 V IOL = 1.5 mA -1 CAPACITANCE TA = 25˚C, f = 1.0 MHz, VCC = 5V Symbol CI/O CIN (1) (1) Test Max. Units Conditions Input/Output Capacitance (SDA) 8 pF VI/O = 0V Input Capacitance (A0, A1, A2, A3, SCL, WP) 6 pF VIN = 0V A.C. CHARACTERISTICS 2.5V-6.0V Symbol Parameter fSCL Min. Max. Units Clock Frequency 400 kHz TI(1) Noise Suppression Time Constant at SCL, SDA Inputs 200 ns tAA SLC Low to SDA Data Out and ACK Out 1 µs tBUF(1) Time the bus must be free before a new transmission can start 1.2 µs tHD:STA Start Condition Hold Time 0.6 µs tLOW Clock Low Period 1.2 µs tHIGH Clock High Period 0.6 µs tSU:STA Start Condition SetupTime (for a Repeated Start Condition) 0.6 µs tHD:DAT Data in Hold Time 0 ns tSU:DAT Data in Setup Time 50 ns tR(1) SDA and SCL Rise Time 0.3 µs tF(1) SDA and SCL Fall Time 300 ns tSU:STO Stop Condition Setup Time 0.6 µs tDH Data Out Hold Time 100 ns Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. Document No. 2123, Rev. B 4 CAT5269 POWER UP TIMING (1)(2) Symbol Parameter Max. Units tPUR Power-up to Read Operation 1 ms tPUW Power-up to Write Operation 1 ms XDCP TIMING Symbol Parameter tWRPO tWRL Min Max Units Wiper Response Time After Power Supply Stable 5 10 µs Wiper Response Time After Instruction Issued 5 10 µs WRITE CYCLE LIMITS Symbol tWR Parameter Max. Units Write Cycle Time 5 ms The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address. RELIABILITY CHARACTERISTICS Symbol Units Reference Test Method 1,000,000 Cycles/Byte MIL-STD-883, Test Method 1033 Data Retention 100 Years MIL-STD-883, Test Method 1008 VZAP ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015 ILTH(1) Latch-Up 100 mA NEND (1) TDR(1) (1) Parameter Endurance Min. Max. JEDEC Standard 17 Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. Figure 1. Bus Timing tHIGH tF tR tLOW tLOW SCL tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO SDA IN tAA tDH tBUF SDA OUT 5 Document No. 2123, Rev. B CAT5269 SERIAL BUS PROTOCOL After the Master sends a START condition and the slave address byte, the CAT5269 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The following defines the features of the 2-wire bus protocol: (1) Data transfer may be initiated only when the bus is not busy. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock is high will be interpreted as a START or STOP condition. Acknowledge After a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The device controlling the transfer is a master, typically a processor or controller, and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the CAT5269 will be considered a slave device in all applications. The CAT5269 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8-bit byte. When the CAT5269 is in a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT5269 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. START Condition The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT5269 monitors the SDA and SCL lines and will not respond until this condition is met. WRITE OPERATIONS STOP Condition In the Write mode, the Master device sends the START condition and the slave address information to the Slave device. After the Slave generates an acknowledge, the Master sends the instruction byte that defines the requested operation of CAT5269. The instruction byte consist of a four-bit opcode followed by two register selection bits and two pot selection bits. After receiving another acknowledge from the Slave, the Master device transmits the data to be written into the selected register. The CAT5269 acknowledges once more and the Master generates the STOP condition, at which time if a nonvolatile data register is being selected, the device begins an internal programming cycle to non-volatile memory. While this internal cycle is in progress, the device will not respond to any request from the Master device. A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition. DEVICE ADDRESSING The bus Master begins a transmission by sending a START condition. The Master then sends the address of the particular slave device it is requesting. The four most significant bits of the 8-bit slave address are fixed as 0101 for the CAT5269 (see Figure 5). The next four significant bits (A3, A2, A1, A0) are the device address bits and define which device the Master is accessing. Up to sixteen devices may be individually addressed by the system. Typically, +5V and ground are hard-wired to these pins to establish the device's address. Figure 2. Write Cycle Timing SCL SDA 8TH BIT BYTE n ACK tWR STOP CONDITION Document No. 2123, Rev. B 6 START CONDITION ADDRESS CAT5269 WRITE PROTECTION Acknowledge Polling The disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host's write operation, the CAT5269 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address. If the CAT5269 is still busy with the write operation, no ACK will be returned. If the CAT5269 has completed the write operation, an ACK will be returned and the host can then proceed with the next instruction operation. The Write Protection feature allows the user to protect against inadvertent programming of the non-volatile data registers. If the WP pin is tied to LOW, the data registers are protected and become read only. Similarly, the WP pin going low after start will interrupt a nonvolatile write to data registers, while the WP pin going low after an internal write cycle has stated will have no effect on any write operation (see also CAT5409 or CAT5259). The CAT5269 will accept both slave addresses and instructions, but the data registers are protected from programming by the device’s failure to send an acknowledge after data is received. Figure 3. Start/Stop Condition SDA SCL START CONDITION STOP CONDITION Figure 4. Acknowledge Condition SCL FROM MASTER 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER ACKNOWLEDGE START Figure 5. Slave Address Bits CAT5269 * ** 0 1 0 1 A3 A2 A1 A0 A0, A1, A2 and A3 correspond to pin A0, A1, A2 and A3 of the device. A0, A1, A2 and A3 must compare to its corresponding hard wired input pins. 7 Document No. 2123, Rev. B CAT5269 INSTRUCTION AND REGISTER DESCRIPTION INSTRUCTION BYTE The next byte sent to the CAT5269 contains the instruction and register pointer information. The four most significant bits used provide the instruction opcode I3 - I0. The R1 and R0 bits point to one of the four data registers of each associated potentiometer. The least two significant bits point to one of two Wiper Control Registers. The format is shown in Table 2. SLAVE ADDRESS BYTE The first byte sent to the CAT5269 from the master/ processor is called the Slave/DPP Address Byte. The most significant four bits of the slave address are a device type identifier. These bits for the CAT5269 are fixed at 0101[B] (refer to Table 1). Data Register Selection Data Register Selected The next four bits, A3 - A0, are the internal slave address and must match the physical device address which is defined by the state of the A3 - A0 input pins for the CAT5269 to successfully continue the command sequence. Only the device which slave address matches the incoming device address sent by the master executes the instruction. The A3 - A0 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. R1 R0 DR0 0 0 DR1 0 1 Figure 6. Write Timing BUS ACTIVITY: MASTER S T A R T SDA LINE INSTRUCTION BYTE SLAVE/DPP ADDRESS Fixed Variable Register Pot1 WCR Address Address op code S T O P DR1 WCRDATA S P A C K A C K A C K 5020 FHD F08 Table 1. Identification Byte Format Device Type Identifier Slave Address ID3 ID2 ID1 ID0 0 1 0 1 A3 A2 A1 (MSB) A0 (LSB) Table 2. Instruction Byte Format Instruction Opcode I3 I2 Data Register Selection I1 I0 R1 (MSB) Document No. 2123, Rev. B R0 WCR/Pot Selection P1 P0 (LSB) 8 CAT5269 four Data Registers and the associated Wiper Control Register. Any data changes in one of the Data Registers is a non-volatile operation and will take a maximum of 10ms. WIPER CONTROL AND DATA REGISTERS Wiper Control Register (WCR) The CAT5269 contains two 8-bit Wiper Control Registers, one for each potentiometer. The Wiper Control Register output is decoded to select one of 256 switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written by the host via Write Wiper Control Register instruction; it may be written by transferring the contents of one of four associated Data Registers via the XFR Data Register instruction, it can be modified one step at a time by the Increment/decrement instruction (see Instruction section for more details). Finally, it is loaded with the content of its data register zero (DR0) upon power-up. If the application does not require storage of multiple settings for the potentiometer, the Data Registers can be used as standard memory locations for system parameters or user preference data. INSTRUCTIONS Four of the nine instructions are three bytes in length. These instructions are: — Read Wiper Control Register - read the current wiper position of the selected potentiometer in the WCR — Write Wiper Control Register - change current wiper position in the WCR of the selected potentiometer The Wiper Control Register is a volatile register that loses its contents when the CAT5269 is powered-down. Although the register is automatically loaded with the value in DR0 upon power-up, this may be different from the value present at power-down. — Read Data Register - read the contents of the selected Data Register Data Registers (DR) — Write Data Register - write a new value to the selected Data Register Each potentiometer has four 8-bit non-volatile Data Registers. These can be read or written directly by the host. Data can also be transferred between any of the The basic sequence of the three byte instructions is illustrated in Figure 8. These three-byte instructions Table 3. Instruction Set Instruction Set Instruction Read Wiper Control Register Write Wiper Control Register I3 I2 I1 I0 R1 R0 WCR1/ P1 WCR0/ P0 1 0 0 1 0 0 1/0 1/0 1 0 1 0 0 0 1/0 1/0 Read Data Register 1 0 1 1 1/0 1/0 1/0 1/0 Write Data Register 1 1 0 0 1/0 1/0 1/0 1/0 XFR Data Register to Wiper Control Register 1 1 0 1 1/0 1/0 1/0 1/0 XFR Wiper Control Register to Data Register 1 1 1 0 1/0 1/0 1/0 1/0 Gang XFR Data Registers to Wiper Control Registers 0 0 0 1 1/0 1/0 0 0 Gang XFR Wiper Control Registers to Data Register 1 0 0 0 1/0 1/0 0 0 Increment/Decrement Wiper Control Register 0 0 1 0 0 0 1/0 1/0 Note: Operation Read the contents of the Wiper Control Register pointed to by P1-P0 Write new value to the Wiper Control Register pointed to by P1-P0 Read the contents of the Data Register pointed to by P1-P0 and R1-R0 Write new value to the Data Register pointed to by P1-P0 and R1-R0 Transfer the contents of the Data Register pointed to by P1-P0 and R1-R0 to its associated Wiper Control Register Transfer the contents of the Wiper Control Register pointed to by P1-P0 to the Data Register pointed to by R1-R0 Transfer the contents of the Data Registers pointed to by R1-R0 of both pots to their respective Wiper Control Registers Transfer the contents of both Wiper Control Registers to their respective data Registers pointed to by R1-R0 of both pots Enable Increment/decrement of the Control Latch pointed to by P1-P0 1/0 = data is one or zero 9 Document No. 2123, Rev. B CAT5269 exchange data between the WCR and one of the Data Registers. The WCR controls the position of the wiper. The response of the wiper to this action will be delayed by tWR. A transfer from the WCR (current wiper position), to a Data Register is a write to non-volatile memory and takes a minimum of tWR to complete. The transfer can occur between one of the two potentiometers and one of its associated registers; or the transfer can occur between both potentiometers and one associated register. — Gang XFR Data Register to Wiper Control Register This transfers the contents of all specified Data Registers to the associated Wiper Control Registers. — Gang XFR Wiper Counter Register to Data Register This transfers the contents of all Wiper Control Registers to the specified associated Data Registers. Four instructions require a two-byte sequence to complete, as illustrated in Figure 7. These instructions transfer data between the host/processor and the CAT5269; either between the host and one of the data registers or directly between the host and the Wiper Control Register. These instructions are: INCREMENT/DECREMENT COMMAND The final command is Increment/Decrement (Figure 9 and 10). The Increment/Decrement command is different from the other commands. Once the command is issued and the CAT5269 has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby providing a fine tuning capability to the host. For each SCL clock pulse (tHIGH) while SDA is HIGH, the selected wiper will move one resistor segment towards the RH terminal. Similarly, for each SCL clock pulse while SDA is LOW, the selected wiper will move one resistor segment towards the RL terminal. — XFR Data Register to Wiper Control Register This transfers the contents of one specified Data Register to the associated Wiper Control Register. — XFR Wiper Control Register to Data Register This transfers the contents of the specified Wiper Control Register to the specified associated Data Register. See Instructions format for more detail. Figure 7. Two-Byte Instruction Sequence SDA 0 1 0 1 S ID3 ID2 ID1 ID0 A3 A2 A1 A0 T A Internal R Device ID Address T A I3 C K I2 I1 I0 Instruction Opcode R1 R0 P1 P0 Register Address A C K Pot/WCR Address S T O P Figure 8. Three-Byte Instruction Sequence SDA 0 1 0 1 S ID3 ID2 ID1 ID0 A3 T A Device ID R T A2 A0 A I3 C K Internal Address I2 A1 I1 I0 R1 R0 P1 P0 A C K Data Pot/WCR Register Address Address Instruction Opcode D7 D6 D5 D4 D3 D2 D1 D0 WCR[7:0] or Data Register D[7:0] A C K S T O P Figure 9. Increment/Decrement Instruction Sequence 0 SDA S T A R T 1 0 1 ID3 ID2 ID1 ID0 Device ID Document No. 2123, Rev. B A3 A2 A1 A0 Internal Address A C K I3 I2 I1 I0 Instruction Opcode 10 R1 R0 P1 P0 A C Pot/WCR K Data Address Register Address I N C 1 I N C 2 I N C n D E C 1 D E C n S T O P CAT5269 Figure 10. Increment/Decrement Timing Limits INC/DEC Command Issued tWRL SCL SDA Voltage Out RW INSTRUCTION FORMAT Read Wiper Control Register (WCR) S T A R T DEVICE ADDRESSES 0 1 0 1 A A A A 3 A C K INSTRUCTION 1 0 0 1 0 0 P P 2 1 0 A C K 4 3 2 1 0 A C K S T O P DATA A C 2 1 0 K S T O P A C 2 1 0 K S T O P A C 2 1 0 K S T O P DATA 7 6 5 1 0 Write Wiper Control Register (WCR) S T A R T DEVICE ADDRESS 0 1 0 1 A A A A 3 A C K A C 1 0 1 0 0 0 P P K 1 0 A C K A C 1 0 1 1 R R P P K 1 0 1 0 A C K A C 1 1 0 0 R R P P K 1 0 1 0 2 1 0 INSTRUCTION 7 6 5 4 3 Read Data Register (DR) S T A R T DEVICE ADDRESS 0 1 0 1 A A A A 3 2 1 0 INSTRUCTION DATA 7 6 5 4 3 Write Data Register (DR) S T A R T DEVICE ADDRESS 0 1 0 1 A A A A 3 2 1 0 INSTRUCTION 11 DATA 7 6 5 4 3 Document No. 2123, Rev. B CAT5269 INSTRUCTION FORMAT (continued) Gang Transfer Data Register (DR) to Wiper Control Register (WCR) S T A R T DEVICE ADDRESS 0 1 0 1 A A A A 3 A C K 2 1 0 INSTRUCTION 0 0 0 1 R R 0 0 A C K 1 0 S T O P Gang Transfer Wiper Control Register (WCR) to Data Register (DR) S T A R T DEVICE ADDRESS 0 1 0 1 A A A A 3 A C K 2 1 0 INSTRUCTION 1 0 0 0 R R 0 0 A C K 1 0 S T O P Transfer Wiper Control Register (WCR) to Data Register (DR) S T A R T DEVICE ADDRESS 0 1 0 1 A A A A 3 A C K 2 1 0 A C 1 1 1 0 R R P P K 1 0 1 0 INSTRUCTION S T O P Transfer Data Register (DR) to Wiper Control Register (WCR) S T A R T DEVICE ADDRESS 0 1 0 1 A A A A 3 A C K 2 1 0 A C 1 1 0 1 R R P P K 1 0 1 0 INSTRUCTION S T O P Increment (I)/Decrement (D) Wiper Control Register (WCR) S T A R T DEVICE ADDRESS 0 1 0 1 A A A A 3 2 1 0 A C K A C 0 0 1 0 0 0 P P K 1 0 INSTRUCTION DATA I I / / D D • • • I I / / A C K S T O P D D Notes: (1) Any write or transfer to the Non-volatile Data Registers is followed by a high voltage cycle after a STOP has been issued. Document No. 2123, Rev. B 12 CAT5269 ORDERING INFORMATION U: TSSOP Y: TSSOP (Lead free, Halogen free) Notes: (1) The device used in the above example is a CAT5269JI00-TE13 (SOIC, Industrial Temperature, 100K Ohm, Tape & Reel) PACKAGING INFORMATION 24-LEAD 300 MIL WIDE SOIC (J, W) 0.2914 (7.40) 0.2992 (7.60) 0.394 (10.00) 0.419 (10.65) 0.5985 (15.20) 0.6141 (15.60) 0.0926 (2.35) 0.1043 (2.65) 0.050 (1.27) BSC 0.0040 (0.10) 0.0118 (0.30) 0.013 (0.33) 0.020 (0.51) 0.010 (0.25) X 45 0.029 (0.75) 0.0091 (0.23) 0.0125 (0.32) 0 —8 0.016 (0.40) 0.050 (1.27) 13 Package Information shown in inches (mm). Document No. 2123, Rev. B CAT5269 PACKAGING INFORMATION CON'T 24 Lead TSSOP (U) 7.8 + 0.1 -A- 7.72 TYP 6.4 4.16 TYP 4.4 + 0.1 -B(1.78 TYP) 3.2 0.42 TYP 0.65 TYP 0.2 C B A ALL LEAD TIPS PIN #1 INDENT. 1.1 MAX TYP LAND PATTERN RECOMMENDATION 0.1 C ALL LEAD TIPS (0.9) -C0.10 + 0.05 TYP 0.65 TYP 0.19 - 0.30 TYP 0.3 M A B S C S SEE DETAIL A GAGE PLANE 0.25 0.09 - 0.20 TYP o o 0-8 0.6+0.1 SEATING PLANE DETAIL A Package Information shown in mm. Document No. 2123, Rev. B 14 REVISION HISTORY Date Rev. Reason 11/18/2003 A Initial issue 5/6/2004 B Added TSSOP package in all areas Updated Functional Diagram Updated Pin Descriptions Updated notes in Absolute Max Ratings Updated Potentiometer Characteristics table Updated DC Characteristics table Added XDCP Timing table Updated Write Cycle LImits table Changed Figure 3 drawing to Start/Stop Condition from Start/Stop Timing Changed Figure 4 title to Acknowlege Condition (from Acknowlege Timing) Updated Table 3 Gang XFR Operation information Corrected Instruction Format for Gang Transfer Data Register (DR) to Wiper Control Register (WCR) Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP ™ AE2 ™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catalyst-semiconductor.com Publication #: Revison: Issue date: 2123 B 5/6/04