NSC CD4025BC Buffered triple 3-input nand,nor gate Datasheet

CD4023BM/CD4023BC
Buffered Triple 3-Input NAND Gate
CD4025BM/CD4025BC
Buffered Triple 3-Input NOR Gate
General Description
Features
These triple gates are monolithic complementary MOS
(CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. They have equal source
and sink current capabilities and conform to standard B series output drive. The devices also have buffered outputs
which improve transfer characteristics by providing very
high gain. All inputs are protected against static discharge
with diodes to VDD and VSS.
Y
Y
Y
Y
Y
Y
Wide supply voltage range
3.0V to 15V
High noise immunity
0.45 VDD (typ.)
Low power TTL
fan out of 2 driving 74L
compatibility
or 1 driving 74LS
5V – 10V – 15V parametric ratings
Symmetrical output characteristics
Maximum input leakage 1 mA at 15V over full
temperature range
Connection Diagrams
CD4025BM/CD4025BC
Dual-In-Line Package
CD4023BM/CD4023BC
Dual-In-Line Package
TL/F/5956 – 1
Top View
TL/F/5956 – 2
Top View
Order Number CD4023B or CD4025B
C1995 National Semiconductor Corporation
TL/F/5956
RRD-B30M105/Printed in U. S. A.
CD4023BM/CD4023BC Buffered Triple 3-Input NAND Gate
CD4025BM/CD4025BC Buffered Triple 3-Input NOR Gate
February 1988
Absolute Maximum Ratings (Notes 1 & 2)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
DC Supply Voltage (VDD)
Input Voltage (VIN)
Storage Temp. Range (TS)
Power Dissipation (PD)
Dual-In-Line
Small Outline
Lead Temperature (TL)
(Soldering, 10 seconds)
DC Supply Voltage (VDD)
Input Voltage (VIN)
Operating Temperature Range (TA)
CD4023BM, CD4025BM
CD4023BC, CD4025BC
b 0.5 VDC to a 18 VDC
b 0.5 VDC to VDD a 0.5 VDC
b 65§ C to a 150§ C
5 VDC to 15 VDC
0 VDC to VDD VDC
b 55§ C to a 125§ C
b 40§ C to a 85§ C
700 mW
500 mW
260§ C
DC Electrical Characteristics CD4023BM, CD4025BM (Note 2)
Symbol
Parameter
b 55§ C
Conditions
Min
Typ
a 25§ C
Min
a 125§ C
Typ
Max
Min
Units
Max
IDD
Quiescent Device Current VDD e 5V
VDD e 10V
VDD e 15V
0.25
0.5
1.0
0.004
0.005
0.006
0.25
0.5
1.0
7.5
15
30
mA
mA
mA
VOL
Low Level Output Voltage VDD e 5V
VDD e 10V
VDD e 15V
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
V
V
V
VOH
High Level Output Voltage VDD e 5V
VDD e 10V
VDD e 15V
VIL
Low Level Input Voltage
VIH
High Level Input Voltage
IOL
Low Level Output Current VDD e 5V, VO e 0.4V
(Note 3)
VDD e 10V, VO e 0.5V
VDD e 15V, VO e 1.5V
IOH
High Level Output Current VDD e 5V, VO e 4.6V
(Note 3)
VDD e 10V, VO e 9.5V
VDD e 15V, VO e 13.5V
IIN
Input Current
4.95
9.95
14.95
VDD e 5V, VO e 4.5V
VDD e 10V, VO e 9.0V
VDD e 15V, VO e 13.5V
lIOl k1mA
VDD e 5V, VO e 0.5V
VDD e 10V, VO e 1.0V
VDD e 15V, VO e 1.5V
IOl k1mA
(
(l
4.95
9.95
14.95
1.5
3.0
4.0
5
10
15
2
4
6
4.95
9.95
14.95
V
V
V
1.5
3.0
4.0
1.5
3.0
4.0
3.5
7.0
11.0
3.5
7.0
11.0
3
6
9
3.5
7.0
11.0
V
V
V
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.2
8
0.36
0.90
2.4
mA
mA
mA
b 0.36
b 0.90
b 2.4
mA
mA
mA
b 0.64
b 1.6
b 4.2
VDD e 15V, VIN e 0V
VDD e 15V, VIN e 15V
b 0.51 b 0.88
b 1.3 b 2.2
b 3.4
b8
b 0.10
0.10
b 10 b 5 b 0.10
10b5
b 1.0
0.10
Schematic Diagram
CD4023BC/CD4023BM
(/3 Device Shown
*All Inputs Protected
by Standard CMOS Input
Protection Circuit.
TL/F/5956 – 3
2
V
V
V
1.0
mA
mA
DC Electrical Characteristics CD4023BC, CD4025BC (Note 2)
Symbol
Parameter
b 40§ C
Conditions
Min
Typ
a 25§ C
Min
a 85§ C
Typ
Max
Min
Units
Max
IDD
Quiescent Device Current VDD e 5V
VDD e 10V
VDD e 15V
1.0
2.0
4.0
0.004
0.005
0.006
1.0
2.0
4.0
7.5
15
30
mA
mA
mA
VOL
Low Level Output Voltage VDD e 5V
VDD e 10V
VDD e 15V
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
V
V
V
VOH
High Level Output Voltage VDD e 5V
VDD e 10V
VDD e 15V
VIL
Low Level Input Voltage
VIH
High Level Input Voltage
4.95
9.95
14.95
VDD e 5V, VO e 4.5V
VDD e 10V, VO e 9.0V
VDD e 15V, VO e 13.5V
lIOl k1mA
VDD e 5V, VO e 0.5V
VDD e 10V, VO e 1.0V
VDD e 15V, VO e 1.5V
IO k1mA
(
(ll
IOL
Low Level Output Current VDD e 5V, VO e 0.4V
(Note 3)
VDD e 10V, VO e 0.5V
VDD e 15V, VO e 1.5V
IOH
High Level Output Current VDD e 5V, VO e 4.6V
(Note 3)
VDD e 10V, VO e 9.5V
VDD e 15V, VO e 13.5V
IIN
Input Current
4.95
9.95
14.95
1.5
3.0
4.0
5
10
15
4.95
9.95
14.95
2
4
6
1.5
3.0
4.0
V
V
V
1.5
3.0
4.0
V
V
V
3.5
7.0
11.0
3.5
7.0
11.0
3
6
9
3.5
7.0
11.0
V
V
V
0.52
1.3
3.6
0.44
1.1
3.0
0.88
2.2
8
0.36
0.90
2.4
mA
mA
mA
b 0.36
b 0.90
b 2.4
mA
mA
mA
b 0.52
b 1.3
b 3.6
VDD e 15V, VIN e 0V
VDD e 15V, VIN e 15V
b 0.44 b 0.88
b 1.1
b 2.2
b 3.0
b8
b 0.3
0.3
b 10 b 5 b 0.3
10b5
0.3
b 1.0
1.0
mA
mA
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices
should be operated at these limits. The table of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
Note 2: VSS e 0V unless otherwise specified.
Note 3: IOH and IOL are tested one output at a time.
Schematic Diagram
CD4025BM/CD4025BC
(/3 Device Shown
*All Inputs Protected
by Standard CMOS Input
Protection Circuit.
TL/F/5956 – 4
3
AC Electrical Characteristics* TA e 25§ C, CL e 50 pF, RL e 200k, unless otherwise specified
Symbol
Parameter
CD4023BC
CD4023BM
Conditions
Min
CD4025BC
CD4025BM
Typ
Max
Min
Units
Typ
Max
tPHL
Propagation Delay, High-to-Low Level
VDD e 5V
VDD e 10V
VDD e 15V
130
60
40
250
100
70
130
60
40
250
100
70
ns
ns
ns
tPLH
Propagation Delay, Low-to-High Level
VDD e 5V
VDD e 10V
VDD e 15V
110
50
35
250
100
70
120
60
40
250
100
70
ns
ns
ns
tTHL,
tTLH
Transition Time
VDD e 5V
VDD e 10V
VDD e 15V
90
50
40
200
100
80
90
50
40
200
100
80
ns
ns
ns
CIN
Average Input Capacitance
Any Input
5
7.5
5
7.5
pF
CPD
Power Dissipation Capacity (Note 4)
Any Gate
17
17
pF
*AC Parameters are guaranteed by DC correlated testing.
Note 4: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see 54C/74C Family Characteristics Application
Note AN-90.
4
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number CD4023BMJ, CD4023BCJ, CD4025BMJ or CD4025BCJ
NS Package Number J14A
5
CD4023BM/CD4023BC Buffered Triple 3-Input NAND Gate
CD4025BM/CD4025BC Buffered Triple 3-Input NOR Gate
Physical Dimensions inches (millimeters) (Continued)
Molded Dual-In-Line Package (N)
Order Number CD4023BMN, CD4023BCN, CD4025BMN or CD4025BCN
NS Package Number N14A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
National Semiconductor
Corporation
1111 West Bardin Road
Arlington, TX 76017
Tel: 1(800) 272-9959
Fax: 1(800) 737-7018
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
National Semiconductor
Europe
Fax: (a49) 0-180-530 85 86
Email: cnjwge @ tevm2.nsc.com
Deutsch Tel: (a49) 0-180-530 85 85
English Tel: (a49) 0-180-532 78 32
Fran3ais Tel: (a49) 0-180-532 93 58
Italiano Tel: (a49) 0-180-534 16 80
National Semiconductor
Hong Kong Ltd.
13th Floor, Straight Block,
Ocean Centre, 5 Canton Rd.
Tsimshatsui, Kowloon
Hong Kong
Tel: (852) 2737-1600
Fax: (852) 2736-9960
National Semiconductor
Japan Ltd.
Tel: 81-043-299-2309
Fax: 81-043-299-2408
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
Similar pages