SCHS354 − AUGUST 2004
D Matched Switching Characteristics,
Features
D Qualification in Accordance With
D
D
D
D
D
D
AEC-Q100†
Qualified for Automotive Applications
Customer-Specific Configuration Control
Can Be Supported Along With
Major-Change Approval
Wide Range of Digital and Analog Signal
Levels
− Digital: 3 V to 20 V
− Analog: 3 20 VP-P
Low ON Resistance, 125 Ω (Typ) Over
15 VP-P Signal Input Range
for VDD − VEE = 18 V
High OFF Resistance, Channel Leakage of
+100 pA (Typ) at VDD − VEE = 18 V
Logic-Level Conversion for Digital
Addressing Signals of 3 V to 20 V
(VDD − VSS = 3 V to 20 V) to Switch Analog
Signals to 20 VP-P (VDD − VEE = 20 V)
† Contact factory for details. Q100 qualification data available on
request.
D
D
D
D
D
D
ron = 5 Ω (Typ) for VDD − VEE = 15 V
Very Low Quiescent Power Dissipation
Under All Digital-Control Input and Supply
Conditions, 0.2 µW (Typ)
at VDD − VSS = VDD − VEE = 10 V
Binary Address Decoding on Chip
5-V, 10-V, and 15-V Parametric Ratings
100% Tested for Quiescent Current at 20 V
Maximum Input Current of 1µA at 18 V Over
Full Package Temperature Range, 100 nA at
18 V and 25°C
Break-Before-Make Switching Eliminates
Channel Overlap
Applications
D Analog and Digital Multiplexing and
Demultiplexing
D Analog-to-Digital (A/D) and
D
Digital-to-Analog (D/A) Conversion
Signal Gating
description/ordering information
The CD4051B, CD4052B, and CD4053B analog multiplexers are digitally-controlled analog switches that have
low ON impedance and very low OFF leakage current. Control of analog signals up to 20 VP-P can be achieved
by digital signal amplitudes of 4.5 V to 20 V (If VDD − VSS = 3 V, a VDD − VEE of up to 13 V can be controlled;
for VDD − VEE level differences above 13 V, a VDD − VSS of at least 4.5 V is required). For example, if
VDD = 4.5 V, VSS = 0 V, and VEE = −13.5 V, analog signals from −13.5 V to 4.5 V can be controlled by digital
inputs of 0 V to 5 V. These multiplexer circuits dissipate extremely low quiescent power over the full VDD − VSS
and VDD − VEE supply-voltage ranges, independent of the logic state of the control signals. When a logic high
(H) is present at the inhibit (INH) input, all channels are off.
ORDERING INFORMATION
PACKAGE‡
TA
−40°C to 125°C
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SOIC − M
Reel of 2500
CD4051BQM96Q1
CD4051Q
TSSOP − PW
Reel of 2000
CD4051BQPWRQ1
CM051BQ
SOIC − M
Reel of 2500
CD4052BQM96Q1§
CD4052Q
TSSOP − PW
Reel of 2000
CD4052BQPWRQ1§
CD4052Q
SOIC − M
Reel of 2500
CD4053BQM96Q1
CD4053Q
TSSOP − PW
Reel of 2000
CD4053BQPWRQ1§
CD4053Q
‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
§ Product Preview
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2004, Texas Instruments Incorporated
!"#$ %&'()*+! '&+!,#+$ #+-&.),!#&+ '(..*+! ,$ &- /(01#',!#&+ %,!*2 .&%('!$ '&+-&.) !&
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.&%('!#&+ /.&'*$$#+6 %&*$ +&! +*'*$$,.#15 #+'1(%* !*$!#+6 &- ,11
/,.,)*!*.$2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SCHS354 − AUGUST 2004
description/ordering information (continued)
The CD4051B is a single eight-channel multiplexer that has three binary control inputs (A, B, and C) and an
inhibit input. The three binary signals select one of eight channels to be turned on and connect one of the eight
inputs to the output.
The CD4052B is a differential four-channel multiplexer that has two binary control inputs (A and B) and an inhibit
input. The two binary input signals select one of four pairs of channels to be turned on and connect the analog
inputs to the outputs.
The CD4053B is a triple two-channel multiplexer with three separate digital control inputs (A, B, and C) and an
inhibit input. Each control input selects one of a pair of channels, which are connected in a single-pole,
double-throw configuration.
When these devices are used as demultiplexers, the CHANNEL IN/OUT terminals are the outputs, and the
common (COM OUT/IN) terminals are the inputs.
CD4051
M OR PW PACKAGE
(TOP VIEW)
CHANNEL I/O 4
CHANNEL I/O 6
COM OUT/IN
CHANNEL I/O 7
CHANNEL I/O 5
INH
VEE
VSS
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
CD4052
M OR PW PACKAGE
(TOP VIEW)
VDD
CHANNEL I/O 2
CHANNEL I/O 1
CHANNEL I/O 0
CHANNEL I/O 3
A
B
C
Y CHANNEL I/O 0
Y CHANNEL I/O 2
COM Y OUT/IN
Y CHANNEL I/O 3
Y CHANNEL I/O 1
INH
VEE
VSS
CD4053
M OR PW PACKAGE
(TOP VIEW)
IN/OUT by
IN/OUT bx
IN/OUT cy
OUT/IN CX OR CY
IN/OUT CX
INH
VEE
VSS
2
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
POST OFFICE BOX 655303
VDD
OUT/IN bx or by
OUT/IN ax or ay
IN/OUT ay
IN/OUT ax
A
B
C
• DALLAS, TEXAS 75265
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VDD
X CHANNEL I/O 2
X CHANNEL I/O 1
COM X OUT/IN
X CHANNEL I/O 0
X CHANNEL I/O 3
A
B
SCHS354 − AUGUST 2004
Function Tables
CD4051
INPUTS
B
ON
CHANNEL
INH
C
L
L
L
L
0
L
L
L
H
1
L
L
H
L
2
L
L
H
H
3
L
H
L
L
4
L
H
L
H
5
L
H
H
L
6
L
H
H
H
7
H
X
X
X
None
A
X = don’t care
CD4052
INPUTS
INH
B
A
ON
CHANNEL
L
L
L
0x, 0y
L
L
H
1x, 2y
L
H
L
2x, 2y
L
H
H
3x, 3y
H
X
X
None
X = don’t care
CD4053
INPUTS
INH
A OR B OR C
ON
CHANNEL
L
L
ax or bx or cx
L
H
ay or by or cy
H
X
None
X = don’t care
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SCHS354 − AUGUST 2004
logic diagram (positive logic)
CD4051B
CHANNEL I/O
16 VDD
7
6
5
4
3
2
1
0
4
2
5
1
12
15
14
13
TG
TG
A† 11
TG
Binary
to
1-of-8
Decoder
With
Inhibit
B† 10
Logic-Level
Conversion
C† 9
TG
3
COM
OUT/IN
TG
TG
TG
INH† 6
TG
8
VSS
7
VEE
† All inputs are protected by CMOS protection network.
CD4052B
X CHANNEL I/O
3
2
1
0
11
15
14
12
TG
VDD
16
TG
TG
A† 10
B† 9
Binary
to
1-of-4
Decoder
With
Inhibit
Logic-Level
Conversion
INH† 6
TG
13 COM X
TG
3
TG
TG
TG
8
VSS
7
VEE
1
5
2
4
0
1
2
3
Y CHANNEL I/O
† All inputs are protected by CMOS protection network.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
OUT/IN
COM Y
OUT/IN
SCHS354 − AUGUST 2004
logic diagrams (positive logic) (continued)
CD4053B
IN/OUT
16 VDD
A† 11
cy
cx
by
bx
ay
ax
3
5
1
2
13
12
Binary to
1-of-2
Decoders
With
Inhibit
Logic-Level
Conversion
TG
COM OUT/IN
ac or ay
14
TG
TG
B† 10
COM OUT/IN
bc or by
15
TG
C†
TG
9
COM OUT/IN
xc or xy
4
TG
INH† 6
VDD
8 VSS
7
VEE
† All inputs are protected by standard CMOS protection network.
absolute maximum ratings over operating free-air temperature (unless otherwise noted)‡
Supply voltage range, V+ to V− (voltages referenced to VSS terminal) . . . . . . . . . . . . . . . . . . . . . −0.5 to 20 V
DC input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VDD + 0.5 V
DC input current, any one input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA
Package thermal impedance, θJA (see Note 1): M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Lead temperature (during soldering):
At distance 1/16 ± 1/32 inch (1,59 ± 0,79 mm) from case for 10 s max . . . . . . . . . . . . . . . . . . . . . . . 265°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
ĕ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SCHS354 − AUGUST 2004
recommended operating conditions
MIN
VDD
Supply voltage
TA
Operating free-air temperature
MAX
UNIT
5
20
V
−40
125
°C
electrical characteristics, VSUPPLY = ±5 V, AV = 1 V, RL = 100 Ω, unless otherwise noted
(see Note 2)
PARAMETER
IDD
VDD
(V)
TEST CONDITIONS
Quiescent device
current
LIMITS AT INDICATED
TEMPERATURES
UNIT
25°C
−40°C
125°C
5
5
150
0.04
5
10
10
300
0.04
10
15
20
600
0.04
20
20
100
3000
0.08
100
MIN
TYP
MAX
µA
A
Signal Input (Vis) and Output (Vos)
ron
∆ron
Drain-to-source
ON-state resistance
ON-state resistance
difference between
any two switches
VEE = 0 V, VSS = 0 V,
VIS = 0 to VDD
VEE = 0 V, VSS = 0 V
5
850
1300
470
1050
10
330
550
180
400
15
210
320
125
240
5
15
10
10
15
5
Cis
Input capacitance
Cos
Output capacitance
VEE = −5 V, VSS = −5 V
Cios
Feedthrough
capacitance
VEE = −5 V, VSS = −5 V
5
0.2
5
30
60
tpd
Propagation delay
(signal input to
output)
VIS(p-p) = VDD, RL = 200 kΩ,
kΩ
CL = 50 pF, tr, tf = 20 ns
10
15
30
15
10
20
18
5
CD4051
CD4052
±1
±10−5
±0.1
5
µA
pF
18
pF
9
NOTES: 2. Peak-to-peak voltage symmetrical about VDD − VEE
2
3. Determined by minimum feasible leakage measurement for automatic testing
POST OFFICE BOX 655303
±0.1
30
5
CD4053
6
Ω
Any channel OFF (MAX) or all channels
OFF (COM OUT/IN) (Max),
VEE = 0 V, VSS = 0 V, See Note 3
VEE = −5 V, VSS = −5 V
Input/output leakage
current (switch off)
Ω
• DALLAS, TEXAS 75265
pF
ns
SCHS354 − AUGUST 2004
electrical characteristics, VSUPPLY = ±5 V, AV = 1 V, RL = 100 Ω, unless otherwise noted
(see Note 2) (continued)
PARAMETER
TEST CONDITIONS
VEE
(V)
VDD
(V)
LIMITS AT INDICATED
TEMPERATURES
UNIT
25°C
−40°C
125°C
MIN
TYP
MAX
Control (Address or Inhibit), VC
VIL
VIH
IIN
tpd1
tpd2
tpd3
CIN
VSS
5
1.5
1.5
1.5
Input low voltage
VIL = VDD through 1k
1kΩ,,
VIH = VDD through 1kΩ,
1k ,
RL = 1kΩ to VSS,
Iis < 2 µA on all OFF channels
VSS
10
3
3
3
VSS
15
4
4
VSS
5
3.5
3.5
Input high voltage
VIL = VDD through 1k
1kΩ,,
VIH = VDD through 1kΩ,
1k ,
RL = 1kΩ to VSS,
Iis < 2 µA on all OFF channels
VSS
10
7
7
7
VSS
15
11
11
11
18
±0.1
±1
Input current
VIN = 0 V, 18 V
Address-to-signal
OUT (channels ON
or OFF) propagation
delay
tr, tf = 20 ns, CL = 50 pF,
RL = 10 kΩ, VSS = 0 V,
See Figure 10, Figure 11, and
Figure 14
Inhibit-to-signal
OUT (channel
turning ON)
propagation delay
tr, tf = 20 ns, CL = 50 pF,
RL = 1 kΩ, VSS = 0 V,
V
See Figure 11
Inhibit-to-signal
OUT (channel
turning OFF)
propagation delay
tr, tf = 20 ns, CL = 50 pF,
RL = 10 kΩ, VSS = 0 V,
V
See Figure 15
4
3.5
V
±10−5
±0.1
0
5
450
720
0
10
160
320
0
15
120
240
−5
5
225
450
0
5
400
720
0
10
160
320
0
15
120
240
−10
5
200
400
0
5
200
450
0
10
90
210
0
15
70
160
−10
5
130
300
5
7.5
Input capacitance,
any address or
inhibit input
V
µA
ns
ns
ns
pF
NOTES: 2: Peak-to-peak voltage symmetrical about VDD − VEE
2
3: Determined by minimum feasible leakage measurement for automatic testing
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SCHS354 − AUGUST 2004
electrical specifications
PARAMETER
VIS
(V)
TEST CONDITIONS
VDD
(V)
LIMITS AT
INDICATED
TEMPERATURES
MIN
−3-dB cutoff
frequency,
channel ON
(sine-wave input)
THD
Total harmonic
distortion
RL = 1 kΩ,
k ,
VOS at COM OUT/IN,
See Note 2,
VOS at COM OUT/IN
VEE = VSS, 20log VOS/VIS = −3 dB,
VOS at any channel
5
10
30
CD4052
5
10
25
CD4051
5
10
20
RL = 10 kΩ,
See Note 2
2
5
3
10
0.2
5
15
0.12
RL = 1 kΩ,
VOS at COM OUT/IN,
See Note 2
VEE = VSS, 20log VOS/VIS = −40 dB,
Between sections,
Measured on any channel
5
10
8
CD4052
5
10
10
CD4051
5
10
12
%
MHz
8
5
10
3
6
CD4052
10
MHz
VEE = VSS, 20log VOS/VIS = −40 dB,
Between any two sections,
In pin 2, Out pin 14
2.5
CD4053
RL = 10 kΩ, See Note 4
6
10
VEE = 0 V, VSS = 0 V, tr, tf = 20 ns,
VCC = VDD − VSS (square wave)
65
65
NOTES: 2. Peak-to-peak voltage symmetrical about VDD − VEE
2
4. Both ends of channel
POST OFFICE BOX 655303
0.3
CD4053
VEE = VSS, 20log VOS/VIS = −40 dB,
VOS at any channel
VEE = VSS, 20log VOS/VIS = −40 dB,
Between any two sections,
In pin 15, Out pin 14
8
MHz
0.12
VEE = VSS, 20log VOS/VIS = −40 dB,
Between sections, Measured on common
Address or inhibit
to signal crosstalk
MAX
60
RL = 1 kΩ, between any two channels, See Note 2
−40-dB signal
crosstalk frequency
TYP
CD4053
VEE = VSS, fis = 1-kHz sine wave
−40-dB
feedthrough
frequency
(all channels OFF)
UNIT
25°C
• DALLAS, TEXAS 75265
mVPEAK
SCHS354 − AUGUST 2004
TYPICAL CHARACTERISTICS
600
Supply Voltage (VDD − VEE) = 5 V
500
TA = 125°C
CHANNEL ON-STATE RESISTANCE
vs
INPUT SIGNAL VOLTAGE
400
300
25°C
200
−55°C
100
0
−4
−3
−2
−1
0
1
2
3
4
ron − Channel ON−State Resistance − W
ron − Channel ON−State Resistance − W
CHANNEL ON-STATE RESISTANCE
vs
INPUT SIGNAL VOLTAGE
300
Supply Voltage (VDD − VEE) = 10 V
250
TA = 125°C
200
25°C
150
−55°C
100
50
0
−10
−7.5
−5
Vis − Input Signal Voltage − V
−2.5
0
2.5
5
7.5
Vis − Input Signal Voltage − V
92CS-27326RI
92CS-27327RI
Figure 1
Figure 2
CHANNEL ON-STATE RESISTANCE
vs
INPUT SIGNAL VOLTAGE
TA = 25°C
300
Supply Voltage (VDD − VEE) = 5 V
200
150
100
10 V
15 V
50
0
−10
−7.5
−5
−2.5
0
2.5
5
7.5
Vis − Input Signal Voltage − V
10
92CS-27330RI
ron − Channel ON−State Resistance − W
ron − Channel ON−State Resistance − W
CHANNEL ON-STATE RESISTANCE
vs
INPUT SIGNAL VOLTAGE
250
10
Supply Voltage (VDD − VEE) = 15 V
300
250
200
TA = 125°C
150
25°C
100
−55°C
50
0
−10
−7.5
−5
−2.5
0
2.5
5
Vis − Input Signal Voltage − V
Figure 3
7.5
10
92CS-27329RI
Figure 4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
SCHS354 − AUGUST 2004
TYPICAL CHARACTERISTICS
DYNAMIC POWER DISSIPATION
vs
SWITCHING FREQUENCY (CD4051B)
PD − Power Dissipation Per Package − mW
ON CHARACTERISTICS FOR
1-OF-8 CHANNELS (CD4051B)
Vos − Output Signal Voltage − V
6
VDD = 5 V
RL = 100 kW, RL = 10 kW
VSS = 0 V
4
1 kW
500 W
VEE = −5 V
100 W
TA = 255C
2
0
−2
−4
−6
−6
−4
−2
0
2
4
6
10 5
TA = 255C
Alternating O
Test Circuit
VDD
and I Pattern
10 4
VDD = 10 V
10 2
VDD = 5 V
100 Ω
10
1
10 2
10
CD4029
B/D
A B
100 Ω
10 9
1
5
2
4 CD4052
10 3
VDD = 10 V
VDD = 5 V
6
7
3 CL
13
12
14
15
11
8
CL = 15 pF
Ι
10 3
10 4
10 5
PD − Power Dissipation Per Package − mW
VDD
VDD = 15 V
100 Ω
PD − Power Dissipation Per Package − mW
f
10 2
10 5
VDD = 15 V
TA = 255C
Alternating O
VDD = 10 V
and I Pattern
10 4
CL = 50 pF
VDD
f
VDD = 5 V
10 2
CL = 15 pF
9
3
5
10
1
10
10 2
10 3
f − Switching Frequency − kHz
Figure 7
Figure 8
POST OFFICE BOX 655303
Test Circuit
4 CL
12
13
100 W
CD4053 2
10
1
11
15
6
14
7
8
Ι
100 W
10 3
f − Switching Frequency − kHz
10
10 5
DYNAMIC POWER DISSIPATION
vs
SWITCHING FREQUENCY (CD4053B)
Test Circuit
CL = 50 pF
10
10 4
Figure 6
and ÒIÓ Pattern
1
10 3
f − Switching Frequency − kHz
TA = 255C
Alternating ÒOÓ
10
Ι
CL = 15 pF
DYNAMIC POWER DISSIPATION
vs
SWITCHING FREQUENCY (CD4052B)
10 2
13
14
15
12 CD4051
1
5
3
2
4 8 7 6
CL
10 3
Figure 5
10 4
VDD
100 Ω 11 10 9
VDD = 15 V
Vis − Input Signal Voltage − V
10 5
B/D
CD4029
A B C
f
CL = 50 pF
• DALLAS, TEXAS 75265
10 4
10 5
SCHS354 − AUGUST 2004
PARAMETER MEASUREMENT INFORMATION
VDD = 15 V
VDD = 7.5 V
VDD = 5 V
5V
7.5 V
16
7
8
VSS = 0 V
VEE = –7.5 V
5V
16
16
7
8
VEE = –10 V
7
8
VEE = –5 V
7
8
(D)
(C)
(B)
(A)
16
VSS = 0 V
VSS = 0 V
VSS = 0 V
VEE = 0 V
VDD = 5 V
NOTE: The A, B, C, and INH input logic levels are L = VSS and H = VDD. The analog signal (through the TG) may swing from VEE to VDD.
Figure 9. Typical Bias-Voltage Test Circuits
tr = 20 ns
90%
50%
90%
50%
10%
tr = 20 ns
tf = 20 ns
10%
90%
50%
10%
tf = 20 ns
90%
50%
10%
Turn-On Time
90%
50%
90%
10%
10%
10%
Turn-Off Time
Turn-Off Time
Turn-On Time
tPHZ
Figure 10. Channel Turned ON Waveforms
(RL = 1 kΩ)
POST OFFICE BOX 655303
Figure 11. Channel Turned OFF Waveforms
(RL = 1 kΩ)
• DALLAS, TEXAS 75265
11
SCHS354 − AUGUST 2004
PARAMETER MEASUREMENT INFORMATION
1
2
3
4
5
6
7
16
15
14
13
12
11
10
8
9
VDD
VDD
VDD
1
2
3
4
5
6
7
8
IDD
CD4051
16
15
14
13
12
11
10
CD40529
1
2
3
4
5
6
7
8
IDD
16
15
14
13
12
11
10
9
IDD
CD4053
CD4052
Figure 12. OFF Channel Leakage Current, Any Channel OFF
VDD
1
2
3
4
5
6
7
8
IDD
VDD
VDD
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
IDD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CD4052
CD4051
16
15
14
13
12
11
10
9
IDD
CD4053
Figure 13. OFF Channel Leakage Current, All Channels OFF
VDD
VDD
1
2
3
4
5
6
7
VDD
VEE
16
15
14
13
12
11
10
8
Output
RL
Output
Output
CL
CL
RL
VDD
VEE
VDD
VSS
9
VEE
VEE
Clock
In
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
VEE
VDD
VSS
VSS
VSS
VSS
CD4051
CD4052
Clock
In
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RL
CL
VEE
VDD
VSS
Clock
In
VSS
CD4053
VSS
VSS
Figure 14. Propagation Delay, Address Input to Signal Output
50 pF
RL
VDD
VSS
VEE
VDD
Clock
In
VEE
VSS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
Output
VDD
Output
50 pF
RL
VEE
VDD
VDD
VSS
Clock
In
VEE
VSS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Output
RL
50 pF
VEE
VDD
VDD
VSS Clock
In
VEE
VSS
tPHL and tPLH VSS
tPHL and tPLH VSS
CD4052
CD4051
Figure 15. Propagation Delay, Inhibit Input to Signal Output
12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
tPHL and tPLH VSS
CD4053
VDD
SCHS354 − AUGUST 2004
PARAMETER MEASUREMENT INFORMATION
VDD
VDD
VDD
µA
VIH
1K
1K
VIH
VIL
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CD4051B
VIH
VIL
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1K
1K
µA
VIH
1K
VIL
VIH
16
15
14
13
12
11
10
9
1K
mA
VIH
VIL
CD4053B
CD4052B
VIL
1
2
3
4
5
6
7
8
VIL
Measure <2 mA on All OFF Channels (e.g., Channel 2x)
Measure <2 mA on All OFF Channels (e.g., Channel 6)
Measure <2 mA on All OFF Channels (e.g., Channel by)
Figure 16. Input-Voltage Test Circuit (Noise Immunity)
VDD
VDD
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Ι
CD4051
CD4053
Ι
16
15
14
13
12
11
10
9
CD4052
Figure 17. Quiescent Device Current
Keithley
610 Digital
Multimeter
VDD
TG
On
10 kW
1-kW
Range
Y
X−Y
Plotter
VSS
H.P.
Moseley
7030A
X
Figure 18. Channel ON-Resistance Test Circuit
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
SCHS354 − AUGUST 2004
PARAMETER MEASUREMENT INFORMATION
VDD
1
2
3
4
5
6
7
8
VSS
VDD
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
VDD
Ι
VSS
CD4051
CD4053
VSS
NOTE: Measure inputs sequentially to both VDD and VSS.
Connect all unused inputs to either VDD or VSS.
16
15
14
13
12
11
10
9
VDD
Ι
VSS
CD4051
CD4053
NOTE: Measure inputs sequentially to both VDD and VSS.
Connect all unused inputs to either VDD or VSS.
Figure 19. Input Current
5 VP−P
Channel
ON
OFF
Channel
5 VP−P
Common
RF
VM
RL
1K
VDD
Channel
ON
RF
VM
Channel
OFF
6
7
8
Channel In Y
ON or OFF
Channel In X
ON or OFF
RF
VM
RL
Figure 22. Crosstalk Between Duals or Triplets (CD4052B, CD4053B)
CD4052
CD4052
Communications
Link
Differential
Amplifier/Line
Driver
.
Differential
Receiver
Differential
Multiplexing
Demultiplexing
Figure 23. Typical Time-Division Application of the CD4052B
14
RL
Figure 21. Crosstalk Between Any Two Channels
RL
Differential
Signals
RF
VM
RL
RL
Figure 20. Feedthrough
5 VP−P
Channel
OFF
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCHS354 − AUGUST 2004
APPLICATION INFORMATION
In applications where separate power sources drive VDD and the signal inputs, the VDD current capability should
exceed VDD/RL (RL = effective external load). This provision avoids permanent current flow or clamp action on the
VDD supply when power is applied or removed from the CD4051B, CD4052B, or CD4053B.
A
B
C
D
E
A
B
CD4051B
C
INH
Q0
A
B
E
1/2
CD4556
Q1
Q2
A
B
CD4051B
C
INH
Common
Output
A
B
CD4051B
C
INH
Figure 24. 24-to-1 Multiplexer Addressing
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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