CD54FCT245, CD74FCT245 Data sheet acquired from Harris Semiconductor SCHS271A BiCMOS FCT Interface Logic, Octal-Bus Tranceivers, Three-State January 1997 - Revised October 1999 Features Description • Buffered Inputs • Typical Propagation Delay: 5.0ns at VCC = 5V, TA = 25oC • Noninverting • SCR Latchup Resistant BiCMOS Process and Circuit Design • Speed of Bipolar FAST™/AS/S • 64mA Output Sink Current (74 Series) • 48mA Output Sink Current (54 Series) • Output Voltage Swing Limited to 3.7V at VCC = 5V • Controlled Output Edge Rates • Input/Output Isolation to VCC • BiCMOS Technology with Low Quiescent Power The CD54/74FCT245 octal bus transceiver uses a small geometry BiCMOS technology. The output stage is a combination of bipolar and CMOS transistors that limits the output HIGH level to two diode drops below VCC. This resultant lowering of output swing (0V to 3.7V) reduces power bus ringing (a source of EMI) and minimizes VCC bounce and ground bounce and their effects during simultaneous output switching. The output configuration also enhances switching speed and is capable of sinking 48mA to 64mA. The CD54/74FCT245 is a noninverting, three-state, bidirectional transceiver/buffer intended for two-way transmission from”A” bus to “B” bus or “B” bus to “A” bus. The logic level present on the Direction Input (DIR) determines the data direction. When the Output Enable input is HIGH, the outputs are in the high impedance state. Ordering Information PART NUMBER CD74FCT245E TEMP. RANGE (oC) PACKAGE PKG. NO. 0 to 70 20 Ld PDIP E20.3 CD74FCT245M 0 to 70 20 Ld SOIC M20.3 CD54FCT245E -55 to 125 20 Ld PDIP E20.3 NOTE: When ordering the suffix M and SM packages, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. Pinout CD54FCT245, CD74FCT245 (PDIP, SOIC) TOP VIEW DIR 1 20 VCC A0 2 19 OE A1 3 18 B0 A2 4 17 B1 A3 5 16 B2 A4 6 15 B3 A5 7 14 B4 A6 8 13 B5 A7 9 12 B6 GND 10 11 B7 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. FAST™ is a trademark of Fairchild Semiconductor. Copyright © 1999, Texas Instruments Incorporated 1 CD54FCT245, CD74FCT245 Functional Diagram A0 A1 A2 A3 A4 A5 A6 A7 2 18 3 17 4 16 5 15 6 14 7 13 8 12 9 11 B1 B2 B3 B4 B5 B6 B7 19 1 DIR OE B0 GND = PIN 10 VCC = PIN 20 TRUTH TABLE (NOTE 1) CONTROL INPUTS OE DIR OPERATION L L B Data to A Bus L H A Data to B Bus H X Isolation NOTES: 1. H = High Voltage Level L = Low Voltage Level X = Irrelevant 2. To prevent excess currents in the High-Z (isolation) modes, all I/O terminals should be terminated with 10kΩ to 1 MΩ resistors. IEC Logic Symbol CD74FCT245, CD54FCT245 19 1 G3 3EN1 3EN1 1 2 2 18 3 17 4 16 5 15 6 14 7 13 8 12 9 11 2 CD54FCT245, CD74FCT245 Absolute Maximum Ratings Thermal Information DC Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6.0V DC Input Diode Current, IIK (for VI < -0.5V) . . . . . . . . . . . . . . -20mA DC Output Diode Current, IOK (for VO < -0.5V) . . . . . . . . . . . -50mA DC Output Sink Current per Output Pin, IO . . . . . . . . . . . . . . . 70mA DC Output Source Current per Output Pin, IO . . . . . . . . . . . . -30mA DC VCC Current (ICC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140mA DC Ground Current (IGND). . . . . . . . . . . . . . . . . . . . . . . . . . . 528mA Thermal Resistance (Typical, Note 3) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC Lead Tips Only) Operating Conditions Operating Temperature Range (TA) . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC CD74 Series, TA = 0oC to 70oC . . . . . . . . . . . . . . .4.75V to 5.25V CD54 Series,TA = -55oC to 125oC . . . . . . . . . . . . . . .4.5V to 5.5V DC Input Voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VCC DC Output Voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to ≤ VCC Input Rise and Fall Slew Rate, dt/dv. . . . . . . . . . . . . . . . 0 to 10ns/V CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. θJA is calculated in accordance with JESD 51. Electrical Specifications 74FCT Commercial Temperature Range 0oC to 70oC, VCC Max = 5.25V, VCC Min = 4.75V 54FCT Extended Industrial Temperature Range -55oC to 125oC; VCC Max = 5.5V, VCC Min = 4.5V AMBIENT TEMPERATURE (TA) TEST CONDITIONS PARAMETER SYMBOL VI IO (mA) 25oC 0oC TO 70oC -55oC TO 125oC VCC (V) MIN MAX MIN MAX MIN MAX UNITS High Level Input Voltage VIH 4.5 to 5.5 2 - 2 - 2 - V Low Level Input Voltage VIL 4.5 to 5.5 - 0.8 - 0.8 - 0.8 V High Level Output Voltage VOH Low Level Output Voltage VOL VIH or -15 Min 2.4 - 2.4 - - - V VIL -12 Min 2.4 - - - 2.4 - V VIH or 64 Min - 0.55 - 0.55 - - V VIL 48 Min - 0.55 - - - 0.55 V High Level Input Current IIH VCC Max - 0.1 - 1 - 1 µA Low Level Input Current IIL GND Max - -0.1 - -1 - -1 µA IOZH VCC Max - 0.5 - 10 - 10 µA IOZL GND Max - -0.5 - -10 - -10 µA Short Circuit Output Current (Note 4) IOS VCC or GND VO = 0 Max -60 - -60 - -60 - mA Input Clamp Voltage VIK VCC or GND -18 Min - -1.2 - -1.2 - -1.2 V Quiescent Supply Current, MSI ICC VCC or GND 0 Max - 8 - 80 - 500 µA ∆ICC 3.4V (Note 5) Max - 1.6 - 1.6 - 2 mA Three-State Leakage Current Additional Quiescent Supply Current per Input Pin TTL Inputs High, 1 Unit Load NOTES: 4. Not more than one output should be shorted at one time. Test duration should not exceed 100ms. 5. Inputs that are not measured are at VCC or GND. 6. FCT Input Loading: All inputs are 1 unit load. Unit load is ∆ICC limit specified in Static Characteristics Chart, e.g., 1.6mA Max at 70oC. 3 CD54FCT245, CD74FCT245 Switching Specifications tr, tf = 2.5ns, CL = 50pF, RL - See Figure 3 AMBIENT TEMPERATURE (TA) 25oC 0oC TO 70oC -55oC TO 125oC SYMBOL VCC (V) TYP MIN TYP MAX MIN TYP MAX UNITS tPLH, tPHL 5 5 1.5 - 7 1.5 - 7.5 ns Output Enable to Output tPZL, tPZH 5 6 1.5 - 9.5 1.5 - 10 ns Output Disable to Output tPLZ, tPHZ 5 6 1.5 - 7.5 1.5 - 10 ns CPD - 49 - 49 - - 49 - pF Min (Valley) VOHV During Switching of Other Outputs (Output Under Test Not Switching) VOHV 5 0.5 - - - - - - V Max (Peak) VOLP During Switching of Other Outputs (Output Under Test Not Switching) VOLP 5 1 - - - - - - V Cl - - - - 10 - - 10 pF CI/O - - - - 15 - - 15 pF PARAMETER Propagation Delays Data to Outputs) Power Dissipation Capacitance Input Capacitance Input/Output Capacitance NOTES: 7. 5V: Min is at 5.5V, Max is at 4.5V. 5V: Min is at 5.25V for 0oC to 70oC, Max is at 4.75V for 0oC to 70oC, Typ is at 5V. 8. CPD, measured per function, is used to determine the dynamic power consumption. PD (per package) = VCC ICC + ∑ (VCC2 fl CPD + VO2 fO CL + VCC ∆lCC D) where: VCC = supply voltage ∆lCC = flow through current x unit load CL = output load capacitance D = duty cycle of input high fO = output frequency fI= input frequency 4 CD54FCT245, CD74FCT245 Test Circuits and Waveforms VCC tr, tf = 2.5ns (NOTE 9) VI 3V 0 PULSE ZO GEN SWITCH POSITION 7V 500Ω RL V0 DUT CL 50pF RT RT = ZO 500Ω RL 9. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; ZOUT ≤ 50Ω; tf, tr ≤ 2.5ns. FIGURE 1. TEST CIRCUIT tPLZ, tPZL, Open Drain Closed tPHZ, tPZH, tPLH, tPHL Open 3V 1.5V 0V DATA INPUT tH 3V 1.5V 0V TIMING INPUT tREM ASYNCHRONOUS CONTROL SWITCH DEFINITIONS: CL = Load capacitance, includes jig and probe capacitance. RT = Termination resistance, should be equal to ZOUT of the Pulse Generator. VIN = 0V to 3V. Input: tr = tf = 2.5ns (10% to 90%), unless otherwise specified NOTE: tSH TEST 3V 1.5V 0V LOW-HIGH-LOW PULSE 1.5V tW SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tSH 3V 1.5V 0V tH HIGH-LOW-HIGH PULSE FIGURE 2. SETUP, HOLD, AND RELEASE TIMING ENABLE 1.5V FIGURE 3. PULSE WIDTH DISABLE 3V 3V SAME PHASE INPUT TRANSITION 1.5V CONTROL INPUT 0V 3.5V OUTPUT NORMALLY LOW SWITCH CLOSED SWITCH OPEN tPHL 3.5V VOH 1.5V 1.5V VOL OUTPUT 0.3V tPZH OUTPUT NORMALLY HIGH tPLH tPLZ tPZL 1.5V tPHZ 0.3V VOL tPLH tPHL VOH 3V OPPOSITE PHASE INPUT TRANSITION 1.5V 0V 0V 0V 1.5V 0V FIGURE 4. ENABLE AND DISABLE TIMING FIGURE 5. PROPAGATION DELAY 5 Test Circuits and Waveforms (Continued) VOH OTHER OUTPUTS VOL VOH OUTPUT UNDER TEST VOHV VOLP VOL NOTES: 10. VOLP is measured with respect to a ground reference near the output under test. VOHV is measured with respect to VOH. 11. Input pulses have the following characteristics: PRR ≤ 1MHz, tr = 2.5ns, tf = 2.5ns, skew 1ns. 12. R.F. fixture with 700MHz design rules required. IC should be soldered into test board and bypassed with 0.1µF capacitor. Scope and probes require 700MHz bandwidth. FIGURE 6. SIMULTANEOUS SWITCHING TRANSIENT WAVEFORMS 6 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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