TI CD54HC4351 High-speed cmos logic analog multiplexers/demultiplexers with latch Datasheet

[ /Title
(CD74
HC435
1,
CD74
HCT43
51,
CD74
HC435
2)
/Subject
(High
Speed
CMOS
Logic
Analog
Multiplexers/De
multiplexers
with
Latch)
/Autho
r ()
/Keywords
(High
Speed
CMOS
Logic
CD54HC4351, CD74HC4351,
CD74HCT4351, CD74HC4352
Data sheet acquired from Harris Semiconductor
SCHS213C
September 1998 - Revised July 2003
High-Speed CMOS Logic
Analog Multiplexers/Demultiplexers with Latch
Features
CMOS technology to achieve operating speeds similar to
LSTTL with the low power consumption of standard CMOS
integrated circuits.
• Wide Analog Input Voltage Range . . . . . . . . . ±5V (Max)
• Low “On” Resistance
- VCC - VEE = 4.5V. . . . . . . . . . . . . . . . . . . . . . 70Ω (Typ)
- VCC - VEE = 9V . . . . . . . . . . . . . . . . . . . . . . . 40Ω (Typ)
These analog multiplexers/demultiplexers are, in essence,
the HC/HCT4015 and HC4052 preceded by address latches
that are controlled by an active low Latch Enable input (LE).
Two Enable inputs, one active low (E1), and the other active
high (E2) are provided allowing enabling with either input
voltage level.
• Low Crosstalk Between Switches
• Fast Switching and Propagation Speeds
• “Break-Before-Make” Switching
Ordering Information
• Wide Operating Temperature Range . . . -55oC to 125oC
• HC Types
- 2V to 6V Operation, Control; 0V to 10V Switch
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
TEMP. RANGE
(oC)
PACKAGE
CD54HC4351F3A
-55 to 125
20 Ld CERDIP
CD74HC4351E
-55 to 125
20 Ld PDIP
CD74HC4351M
-55 to 125
20 Ld SOIC
CD74HC4351M96
-55 to 125
20 Ld SOIC
CD74HCT4351E
-55 to 125
20 Ld PDIP
CD74HC4352E
-55 to 125
20 Ld PDIP
PART NUMBER
• HCT Types
- 4.5V to 5.5V Operation, Control; 0V to 10V Switch
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
Description
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel.
The ’HC4351, CD74HCT4351, and CD74HC4352 are
digitally controlled analog switches which utilize silicon-gate
Pinouts
CD54HC4351
(CERDIP)
CD74HC4351
(PDIP, SOIC)
CD74HCT4351
(PDIP)
TOP VIEW
A4
1
CD74HC4352
(PDIP)
TOP VIEW
20 VCC
B0
1
B2
2
19 A2
NC
3
18 A1
B COMMON
4
17 A COMMON
5
16 A0
A6
2
19 A2
B3
NC
3
18 A1
B1
6
15 A3
A COMMON
4
17 A0
E1
7
14 NC
A7
5
16 A3
E2
8
13 S0
VEE
9
12 S1
GND 10
11 LE
A5
6
15 S0
E1
7
14 NC
E2
8
13 S1
VEE
9
12 S2
GND 10
11 LE
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
20 VCC
© 2003, Texas Instruments Incorporated
1
CD54HC4351, CD74HC4351, CD74HCT4351, CD74HC4352
Functional Diagram
’HC4351, CD74HCT4351
CHANNEL IN/OUT
VCC
20
A7
A6
A5
A4
A3
A2
A1
A0
5
2
6
1
16
19
18
17
TG
S0
15
TG
S1
13
S2
12
TG
LATCHES
TG
BINARY
TO
1 OF 8
DECODER
WITH
ENABLE
LOGIC
LEVEL
CONVERSION
LE
11
4
A
COMMON
OUT/IN
TG
TG
E1
TG
7
TG
E2
8
10
GND
9
VEE
TRUTH TABLE
’HC4351, CD74HCT4351
INPUT STATES
E1
E2
S2
S1
S0
(NOTE 1)
“ON”
SWITCHES
LE = H
L
H
L
L
L
A0
H
L
L
H
A1
L
H
L
H
L
A2
L
H
L
H
H
A3
L
H
H
L
L
A4
L
H
H
L
H
A5
L
H
H
H
L
A6
L
H
H
H
H
A7
H
L
X
X
X
None
FROM
SELECT
LOGIC
P
P
VCC
VCC
N
N
N
N
VEE
FIGURE 1. DETAIL OF ONE HC/HCT4351 SWITCH
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care
NOTE:
1. When LE is low S0-S2 data are latched and switches cannot
change state.
2
A COMMON
IN/OUT
L
An
IN/OUT
CD54HC4351, CD74HC4351, CD74HCT4351, CD74HC4352
Functional Diagram
CD74HC4352
A CHANNELS IN/OUT
VCC
A3
A2
A1
A0
15
19
18
16
20
TG
S0
13
S0
S0
LATCHES
S1
12
LE
TG
S1
TG
S1
BINARY
TO
1 OF 4
DECODER
WITH
ENABLE
LOGIC
LEVEL
CONVERSION
11
TG
17
A COMMON
OUT/IN
TG
4
B COMMON
OUT/IN
TG
E1
7
E2
8
TG
TG
10
9
GND
5
2
6
1
B0
B1
B2
B3
B CHANNELS IN/OUT
VEE
TRUTH TABLE
CD74HC4352
An (Bn)
IN/OUT
INPUT STATES
E1
E2
S1
S0
FROM
SELECT
LOGIC
(NOTE 2)
“ON”
SWITCHES
LE = H
H
L
L
A0, B0
L
H
L
H
A1, B1
L
H
H
L
A2, B2
L
H
H
H
A3, B3
H
L
X
X
None
VCC
N
N
N
N
VEE
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care
NOTE:
FIGURE 2. DETAIL OF ONE CD74HC4352 SWITCH
2. When Latch Enable is “Low” channel-select data is latched and
switches cannot change state.
3
A COMMON (B COMMON)
IN/OUT
L
P
P
VCC
CD54HC4351, CD74HC4351, CD74HCT4351, CD74HC4352
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Supply Voltage, VCC - VEE . . . . . . . . . . . . . . . . . . -0.5V to 10.5V
DC Supply Voltage, VEE . . . . . . . . . . . . . . . . . . . . . . . . 0.5V to -7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC 0.5V. . . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Switch Diode Current, IOK
For VI < VEE -0.5V or VI < VCC + 0.5V . . . . . . . . . . . . . . . . .±25mA
DC Switch Current, IOK (Note 3)
For VI > VEE -0.5V or VI < VCC + 0.5V . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Thermal Resistance (Typical, Note 4)
θJA (oC/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .
69
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .
58
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
Supply Voltage Range, VCC - VEE
HC, HCT Types (Figure 3) . . . . . . . . . . . . . . . . . . . . . . .2V to 10V
Supply Voltage Range, VEE
HC, HCT Types (Figure 4) . . . . . . . . . . . . . . . . . . . . . . . 0V to -6V
DC Input or Output Voltage, VI . . . . . . . . . . . . . . . . . . . GND to VCC
Analog Switch I/O Voltage, VIS . . . . . . . . . . . . . . . . . . . . . VEE (Min)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC (Max)
Input Rise and Fall Time, tr, tf
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. In certain applications, the external load-resistor current may include both VCC and signal-line components. To avoid drawing VCC current
when switch current flows into the transmission gate inputs, the voltage drop across the bidirectional switch must not exceed 0.6V (calculated from RON values shown in the DC Electrical Specifications table). No VCC current will flow through RL if the switch current flows
into terminal 3 on the ’HC4351 and CD74HCT4351; terminals 3 and 13 on the CD74HC4352.
4. The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Area as a Function of Supply Voltage
8
6
VCC - GND
(V)
4
8
6
VCC - GND
(V)
4
HCT
HC
2
0
HCT
HC
2
0
2
0
4
6
8
10 12
VCC - VEE (V)
FIGURE 3.
0
-2
-4 -6 -8
VEE - GND (V)
FIGURE 4.
4
CD54HC4351, CD74HC4351, CD74HCT4351, CD74HC4352
DC Electrical Specifications
PARAMETER
-40oC TO
85oC
25oC
TEST CONDITIONS
-55oC TO
125oC
SYMBOL
VI (V)
VIS (V)
VEE
(V)
VCC
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
VIH
-
-
-
2
1.5
-
-
1.5
-
1.5
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
0
4.5
-
70
160
-
200
-
240
Ω
0
6
-
60
140
-
175
-
210
Ω
-4.5
4.5
-
40
120
-
150
-
180
Ω
0
4.5
-
90
180
-
225
-
270
Ω
0
6
-
80
160
-
200
-
240
Ω
-4.5
4.5
-
45
130
-
162
-
195
Ω
0
4.5
-
10
-
-
-
-
-
Ω
0
6
-
8.5
-
-
-
-
-
Ω
-4.5
4.5
-
5
-
-
-
-
-
Ω
0
6
-
-
±0.1
-
±1
-
±1
µA
-5
5
-
-
±0.2
-
±2
-
±2
µA
0
6
-
-
±0.2
-
±2
-
±2
µA
-5
5
-
-
±0.4
-
±4
-
±4
µA
HC TYPES
High Level Input
Voltage
Low Level Input
Voltage
“ON” Resistance
IO = 1mA
Figure 9
VIL
RON
-
VIH or
VIL
-
VCC or VEE
VCC to VEE
Maximum “ON”
Resistance Between
Any Two Channels
Switch On/Off
Leakage Current
4 Channels (4352)
∆RON
IIZ
-
VIH or
VIL
Switch On/Off
Leakage Current
8 Channels (4351)
-
For Switch
OFF:
When
VIS = VCC
VOS = VEE;
When
VIS = VEE,
VOS = VCC
For Switch
ON:
All
Applicable
Combinations of VIS
and VOS
Voltage
Levels
-
Control Input Leakage
Current
IIL
VCC or
GND
-
0
6
-
-
±0.1
-
±1
-
±1
µA
Quiescent Device
Current
IO = 0
ICC
VCC or
GND
When
VIS = VEE,
VOS = VCC,
When
VIS = VCC,
VOS = VEE
0
6
-
-
8
-
80
-
160
µA
-5
5
-
-
16
-
160
-
320
µA
5
CD54HC4351, CD74HC4351, CD74HCT4351, CD74HC4352
DC Electrical Specifications
(Continued)
SYMBOL
VI (V)
VIS (V)
VEE
(V)
VCC
(V)
High Level Input
Voltage
VIH
-
-
-
Low Level Input
Voltage
VIL
-
-
“ON” Resistance
IO = 1mA
Figure 9
RON
VIH or
VIL
VCC or VEE
PARAMETER
-40oC TO
85oC
25oC
TEST CONDITIONS
-55oC TO
125oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
4.5 to
5.5
2
-
-
2
-
2
-
V
-
4.5 to
5.5
-
-
0.8
-
0.8
-
0.8
V
0
4.5
-
70
160
-
200
-
240
Ω
-4.5
4.5
-
40
120
-
150
-
180
Ω
0
4.5
-
90
180
-
225
-
270
Ω
-4.5
4.5
-
45
130
-
162
-
195
Ω
0
4.5
-
10
-
-
-
-
-
Ω
-4.5
4.5
-
5
-
-
-
-
-
Ω
0
6
-
-
±0.1
-
±1
-
±1
µA
-5
5
-
-
±0.2
-
±2
-
±2
µA
0
6
-
-
±0.2
-
±2
-
±2
µA
-5
5
-
-
±0.4
-
±4
-
±4
µA
0
5.5
-
-
±0.1
-
±1
-
±1
µA
0
5.5
-
-
8
-
80
-
160
µA
-4.5
5.5
-
-
16
-
160
-
320
µA
-
4.5 to
5.5
-
100
360
-
450
-
490
µA
HCT TYPES
VCC to VEE
Maximum “ON”
Resistance Between
Any Two Channels
Switch On/Off
Leakage Current
4 Channels (4352)
∆RON
IIZ
-
VIH or
VIL
Switch On/Off
Leakage Current
8 Channels (4351)
Control Input Leakage
Current
Quiescent Device
Current
IO = 0
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
II
VCC or
GND
ICC
-
For Switch
OFF:
When
VIS = VCC
VOS = VEE;
When
VIS = VEE,
VOS = VCC
For Switch
ON:
All
Applicable
Combinations of VIS
and VOS
Voltage
Levels
-
Any
When
Voltage VIS = VEE,
BeVOS = VCC,
tween
When
VCC
VIS = VCC,
and
VOS = VEE
GND
∆ICC
(Note 5)
VCC
-2.1
-
NOTE:
5. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
HCT Input Loading Table
TYPE
INPUT
UNIT LOADS
All
E1, E2, Sn
0.5
(4351, 4352)
LE
1.5
NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g.,
360µA max at 25oC.
6
CD54HC4351, CD74HC4351, CD74HCT4351, CD74HC4352
Switching Specifications Input tr, tf = 6ns
-40oC TO
85oC
25oC
PARAMETER
-55oC TO
125oC
SYMBOL
TEST
CONDITIONS
VEE
(V)
VCC
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
tPLH, tPHL
CL = 50pF
0
2
-
-
35
-
45
-
55
ns
0
4.5
-
-
7
-
9
-
11
ns
0
6
-
-
6
-
8
-
9
ns
-4.5
4.5
-
-
5
-
7
-
8
ns
0
2
-
-
300
-
375
-
450
ns
0
4.5
-
-
60
-
75
-
90
ns
0
6
-
-
51
-
64
-
77
ns
-4.5
4.5
-
-
55
-
69
-
83
ns
CL = 15pF
-
5
-
27
-
-
-
-
-
ns
CL = 50pF
0
2
-
-
350
-
440
-
525
ns
0
4.5
-
-
70
-
88
-
105
ns
0
6
-
-
60
-
75
-
90
ns
-4.5
4.5
-
-
60
-
75
-
90
ns
CL = 15pF
-
5
-
35
-
-
-
-
-
ns
CL = 50pF
0
2
-
-
300
-
375
-
450
ns
0
4.5
-
-
60
-
75
-
90
ns
0
6
-
-
51
-
64
-
77
ns
-4.5
4.5
-
-
50
-
63
-
75
ns
CL = 15pF
-
5
-
27
-
-
-
-
-
ns
CL = 50pF
0
2
-
-
375
-
470
-
565
ns
0
4.5
-
-
75
-
94
-
113
ns
0
6
-
-
64
-
80
-
96
ns
-4.5
4.5
-
-
55
-
69
-
83
ns
CL = 15pF
-
5
-
35
-
-
-
-
-
ns
CL = 50pF
0
2
-
-
250
-
315
-
375
ns
0
4.5
-
-
50
-
63
-
75
ns
0
6
-
-
43
-
54
-
64
ns
-4.5
4.5
-
-
40
-
50
-
60
ns
-
5
-
21
-
-
-
-
-
ns
HC TYPES
Propagation Delay,
Switch In to Switch Out
Maximum Switch Turn “ON”
Delay 4351
E1, E2, LE to VOS
Maximum Switch Turn “ON”
Delay 4352
E1, E2, LE to VOS
Maximum Switch Turn “ON”
Delay 4351
Sn to VOS
Maximum Switch Turn “ON”
Delay 4352
Sn to VOS
Maximum Switch Turn “OFF”
Delay 4351
E1 to VOS
tPZH, tPZL
tPZH, tPZL
tPZH, tPZL
tPZH, tPZL
tPHZ, tPLZ
CL = 50pF
CL = 15pF
7
CD54HC4351, CD74HC4351, CD74HCT4351, CD74HC4352
Switching Specifications Input tr, tf = 6ns
(Continued)
-40oC TO
85oC
25oC
PARAMETER
Maximum Switch Turn “OFF”
Delay 4351
E2 to VOS
Maximum Switch Turn “OFF”
Delay 4351
LE to VOS
Maximum Switch Turn “OFF”
Delay 4351
Sn to VOS
Maximum Switch Turn “OFF”
Delay 4352
E1, E2, LE to VOS
Setup Time 4351
Sn to LE
Hold Time 4351 and 4352
Sn to LE
Pulse Width 4351 and 4352
LE
Input (Control) Capacitance
Power Dissipation Capacitance
(Notes 6, 7) 4351
-55oC TO
125oC
SYMBOL
TEST
CONDITIONS
VEE
(V)
VCC
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
tPHZ, tPLZ
CL = 50pF
0
2
-
-
250
-
315
-
375
ns
0
4.5
-
-
50
-
63
-
75
ns
0
6
-
-
43
-
54
-
64
ns
-4.5
4.5
-
-
40
-
50
-
60
ns
CL = 15pF
-
5
-
21
-
-
-
-
-
ns
CL = 50pF
0
2
-
-
275
-
345
-
415
ns
0
4.5
-
-
55
-
69
-
83
ns
0
6
-
-
47
-
59
-
71
ns
-4.5
4.5
-
-
45
-
56
-
68
ns
0
2
-
-
275
-
345
-
415
ns
0
4.5
-
-
55
-
69
-
83
ns
0
6
-
-
47
-
59
-
71
ns
-4.5
4.5
-
-
48
-
60
-
71
ns
CL = 15pF
-
5
-
21
-
-
-
-
-
ns
CL = 50pF
0
2
-
-
275
-
345
-
415
ns
0
4.5
-
-
55
-
69
-
83
ns
0
6
-
-
47
-
59
-
71
ns
-4.5
4.5
-
-
50
-
63
-
75
ns
CL = 15pF
-
5
-
21
-
-
-
-
-
ns
CL = 50pF
0
2
-
-
60
-
75
-
90
ns
0
4.5
-
-
12
-
15
-
18
ns
0
6
-
-
10
-
13
-
15
ns
-4.5
4.5
-
-
18
-
23
-
27
ns
0
2
5
-
-
5
-
5
-
ns
0
4.5
5
-
-
5
-
5
-
ns
0
6
5
-
-
5
-
5
-
ns
-4.5
4.5
5
-
-
5
-
5
-
ns
0
2
100
-
-
125
-
150
-
ns
0
4.5
20
-
-
25
-
30
-
ns
0
6
17
-
-
21
-
26
-
ns
-4.5
4.5
25
-
-
31
-
38
-
ns
tPHZ, tPLZ
tPHZ, tPLZ
tPHZ, tPLZ
tSU
tH
tW
CL = 50pF
CL = 50pF
CL = 50pF
CI
-
-
-
-
-
10
-
10
-
10
pF
CPD
-
-
5
-
50
-
-
-
-
-
pF
8
CD54HC4351, CD74HC4351, CD74HCT4351, CD74HC4352
Switching Specifications Input tr, tf = 6ns
(Continued)
-40oC TO
85oC
25oC
-55oC TO
125oC
PARAMETER
SYMBOL
TEST
CONDITIONS
VEE
(V)
VCC
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
Power Dissipation Capacitance
(Notes 6, 7) 4352
CPD
-
-
5
-
74
-
-
-
-
-
pF
tPLH, tPHL
CL = 50pF
0
4.5
-
-
7
-
9
-
11
ns
-4.5
4.5
-
-
5
-
7
-
8
ns
0
4.5
-
-
75
-
94
-
113
ns
-4.5
4.5
-
-
60
-
75
-
90
ns
CL = 15pF
-
5
-
35
-
-
-
-
-
ns
CL = 50pF
0
4.5
-
-
75
-
94
-
113
ns
-4.5
4.5
-
-
60
-
75
-
90
ns
CL = 15pF
-
5
-
35
-
-
-
-
-
ns
CL = 50pF
0
4.5
-
-
55
-
69
-
83
ns
-4.5
4.5
-
-
40
-
50
-
60
ns
CL = 15pF
-
5
-
23
-
-
-
-
-
ns
CL = 50pF
0
4.5
-
-
60
-
75
-
90
ns
-4.5
4.5
-
-
50
-
63
-
75
ns
CL = 15pF
-
5
-
23
-
-
-
-
-
ns
CL = 50pF
0
4.5
-
-
60
-
75
-
90
ns
-4.5
4.5
-
-
55
-
69
-
83
ns
0
4.5
-
-
65
-
81
-
98
ns
-4.5
4.5
-
-
55
-
69
-
83
ns
CL = 15pF
-
5
-
23
-
-
-
-
-
ns
CL = 50pF
0
4.5
-
-
12
-
15
-
18
ns
-4.5
4.5
-
-
14
-
18
-
21
ns
0
4.5
5
-
-
5
-
5
-
ns
-4.5
4.5
5
-
-
5
-
5
-
ns
0
4.5
25
-
-
31
-
28
-
ns
-4.5
4.5
25
-
-
31
-
38
-
ns
HCT TYPES
Propagation Delay,
Switch In to Switch Out
Maximum Switch Turn “ON”
Delay 4351
E1, E2, LE to VOS
Maximum Switch Turn “ON”
Delay 4351
Sn to VOS
Maximum Switch Turn “OFF”
Delay 4351
E1 to VOS
Maximum Switch Turn “OFF”
Delay 4351
E2 to VOS
tPZH, tPZL
tPZH, tPZL
tPHZ, tPLZ
tPHZ, tPLZ
Maximum Switch Turn “OFF”
Delay 4351
LE to VOS
tPHZ, tPLZ
Maximum Switch Turn “OFF”
Delay 4351
Sn to VOS
tPHZ, tPLZ
Setup Time 4351
Sn to LE
Hold Time 4351 and 4352
Sn to LE
Pulse Width 4351
LE
Input (Control) Capacitance
Power Dissipation Capacitance
(Notes 6, 7) 4351
CL = 50pF
CL = 50pF
CL = 50pF
tW
CL = 50pF
CI
-
-
-
-
-
10
-
10
-
10
pF
CPD
-
-
5
-
52
-
-
-
-
-
pF
NOTES:
6. CPD is used to determine the dynamic power consumption, per package.
7. PD = CPD VCC2 fi + Σ (CL + CS) VCC2 fo where fi = input frequency, fo = output frequency, CL = output load capacitance, CS = switch
capacitance, VCC = supply voltage.
9
CD54HC4351, CD74HC4351, CD74HCT4351, CD74HC4352
Analog Channel Specifications
PARAMETER
Switch Input Capacitance
Common Capacitance
Minimum Switch Frequency
Response at -3dB
(Figure 6, 8)
TA = 25oC
SYMBOL
TEST
CONDITIONS
TYPE
VEE (V)
VCC (V)
HC/HCT
UNITS
CI
All
-
-
5
pF
CCOM
4351
-
-
25
pF
4352
-
-
12
pF
4351
-
-
145
MHz
4352
-2.25
2.25
165
MHz
fMAX
Crosstalk Between Any Two Switches
(Note 11)
Sine-Wave Distortion
E or S to Switch Feedthrough Noise
Switch “OFF” Signal Feedthrough
(Figure 6, 8)
See Figure 11
(Notes 8, 9)
See Figure 10
(Notes 9, 10)
See Figure 12
See Figure 13
(Notes 9, 10)
See Figure 14
(Notes 9, 10)
NOTES:
8. Adjust input voltage to obtain 0dBm at VOS for, fin = 1MHz.
9. VIS is centered at (VCC - VEE)/2.
10. Adjust input for 0dBm.
11. Not applicable for ’HC4351 and CD74HCT4351.
10
4351
-
-
180
MHz
4352
-4.5
4.5
185
MHz
4351
-
-
N/A
dB
4352
-2.25
2.25
(TBE)
dB
4351
-
-
N/A
dB
4352
-4.5
4.5
(TBE)
dB
All
-2.25
2.25
0.035
%
All
-4.5
4.5
0.018
%
4351
-
-
-
mV
4352
-2.25
2.25
(TBE)
mV
4351
-
-
-
mV
4352
-4.5
4.5
(TBE)
mV
4351
-
-
-73
dB
4352
-2.25
2.25
-65
dB
4351
-
-
-75
dB
4352
-4.5
4.5
-67
dB
CD54HC4351, CD74HC4351, CD74HCT4351, CD74HC4352
Typical Performance Curves
0
0
VCC = 4.5V
GND = -4.5V
VEE = -4.5V
RL = 50Ω
PIN 12 TO 3
-2
-4
-40
dB
dB
VCC = 2.25V
GND = -2.25V
VEE = -2.25V
RL = 50Ω
PIN 12 TO 3
-6
VCC = 2.25V
GND = -2.25V
VEE = -2.25V
RL = 50Ω
PIN 12 TO 3
-20
-60
-8
VCC = 4.5V
GND = -4.5V
VEE = -4.5V
RL = 50Ω
PIN 12 TO 3
-80
-10
10K
100K
1M
10M
FREQUENCY, f (Hz)
-100
10K
100M
FIGURE 5. CHANNEL ON BANDWIDTH (’HC4351,
CD74HCT4351)
1M
10M
FREQUENCY, f (Hz)
100M
FIGURE 6. CHANNEL OFF FEEDTHROUGH (’HC4351,
CD74HCT4351)
0
0
VCC = 4.5V
GND = -4.5V
VEE = -4.5V
RL = 50Ω
PIN 4 TO 3
-2
-4
-40
dB
dB
VCC = 2.25V
GND = -2.25V
VEE = -2.25V
RL = 50Ω
PIN 4 TO 3
-20
VCC = 2.25V
GND = -2.25V
VEE = -2.25V
RL = 50Ω
PIN 4 TO 3
-6
-60
VCC = 4.5V
GND = -4.5V
VEE = -4.5V
RL = 50Ω
PIN 4 TO 3
-80
-8
-10
10K
100K
100K
1M
10M
FREQUENCY, f (Hz)
-100
10K
100M
100K
1M
10M
100M
FREQUENCY, f (Hz)
FIGURE 7. CHANNEL ON BANDWIDTH (CD74HC4352)
FIGURE 8. CHANNEL OFF FEEDTHROUGH (CD74HC4352)
11
CD54HC4351, CD74HC4351, CD74HCT4351, CD74HC4352
“ON” RESISTANCE, RON (Ω)
Typical Performance Curves
(Continued)
130
120
110
100
90
80
70
60
50
40
30
20
10
VCC - VEE = 4.5V
VCC - VEE = 6V
VCC - VEE = 9V
0
1
0
2
3
4
5
6
7
8
9
INPUT SIGNAL VOLTAGE, VIS (V)
FIGURE 9. TYPICAL ON RESISTANCE vs INPUT SIGNAL VOLTAGE
Analog Test Circuits
VIS
0.1µF
VCC
VCC
SWITCH
ON
VIS
R
VOS1
R
R
C
VOS2
SWITCH
OFF
R
VCC/2
VCC/2
C
dB
METER
VCC/2
fIS = 1MHz SINEWAVE
R = 50Ω
C = 10pF
FIGURE 10. CROSSTALK BETWEEN TWO SWITCHES TEST CIRCUIT
VCC
VCC
0.1µF
VIS
SINE
WAVE 10µF
VIS
VOS
SWITCH
ON
50Ω
VCC/2
VIS
SWITCH
ON
VI = VIH
VOS
10kΩ
10pF
dB
METER
VCC/2
50pF
DISTORTION
METER
fIS = 1kHz TO 10kHz
FIGURE 11. FREQUENCY RESPONSE TEST CIRCUIT
FIGURE 12. TOTAL HARMONIC DISTORTION TEST CIRCUIT
12
CD54HC4351, CD74HC4351, CD74HCT4351, CD74HC4352
Analog Test Circuits
(Continued)
E
VCC
600Ω
VCC/2
SWITCH
ALTERNATING
ON AND OFF
tr, tf ≤ 6ns
fCONT = 1MHz
50% DUTY
CYCLE
VCC
VP-P
VOS
0.1µF
600Ω
50pF
VCC/2
SCOPE
FIGURE 13. CONTROL-TO-SWITCH FEEDTHROUGH NOISE
TEST CIRCUIT
fIS ≥ 1MHz SINEWAVE
R = 50Ω
C = 10pF
VOS
SWITCH
OFF
VIS
VOS
VC = VIL
R
R
VCC/2
VCC/2
C
dB
METER
FIGURE 14. SWITCH OFF SIGNAL FEEDTHROUGH
13
CD54HC4351, CD74HC4351, CD74HCT4351, CD74HC4352
Test Circuits and Waveforms
tWL + tWH =
tfCL
trCL
tWL + tWH =
trCL = 6ns
tfCL = 6ns
50%
10%
10%
2.7V
CLOCK
50%
50%
1.3V
0.3V
0.3V
GND
1.3V
1.3V
GND
tWH
tWL
tWH
tWL
I
fCL
3V
VCC
90%
CLOCK
I
fCL
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 15. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
FIGURE 16. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
tr = 6ns
tf = 6ns
90%
50%
10%
INPUT
GND
tTLH
90%
INVERTING
OUTPUT
tPHL
FIGURE 17. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
trCL
VCC
90%
GND
tH(H)
3V
2.7V
1.3V
0.3V
GND
tH(H)
tH(L)
VCC
DATA
INPUT
DATA
INPUT
50%
tH(L)
3V
1.3V
1.3V
1.3V
GND
tSU(H)
tSU(H)
tSU(L)
tTLH
90%
OUTPUT
tTHL
90%
50%
10%
tTLH
90%
1.3V
OUTPUT
tREM
3V
SET, RESET
OR PRESET
GND
tTHL
1.3V
10%
FIGURE 19. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
tPHL
1.3V
GND
IC
CL
50pF
GND
90%
tPLH
50%
IC
tSU(L)
tPHL
tPLH
tREM
VCC
SET, RESET
OR PRESET
tfCL
CLOCK
INPUT
50%
10%
tPLH
FIGURE 18. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
tfCL
trCL
tTLH
1.3V
10%
tPLH
tPHL
GND
tTHL
90%
50%
10%
INVERTING
OUTPUT
3V
2.7V
1.3V
0.3V
INPUT
tTHL
CLOCK
INPUT
tf = 6ns
tr = 6ns
VCC
CL
50pF
FIGURE 20. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
14
CD54HC4351, CD74HC4351, CD74HCT4351, CD74HC4352
Test Circuits and Waveforms
6ns
(Continued)
6ns
OUTPUT
DISABLE
tr
VCC
90%
50%
10%
OUTPUTS
ENABLED
OUTPUT HIGH
TO OFF
50%
OUTPUTS
DISABLED
FIGURE 21. HC THREE-STATE PROPAGATION DELAY
WAVEFORM
OTHER
INPUTS
TIED HIGH
OR LOW
OUTPUT
DISABLE
IC WITH
THREESTATE
OUTPUT
GND
1.3V
tPZH
90%
OUTPUTS
ENABLED
OUTPUTS
ENABLED
0.3
10%
tPHZ
tPZH
90%
3V
tPZL
tPLZ
OUTPUT LOW
TO OFF
50%
OUTPUT HIGH
TO OFF
6ns
GND
10%
tPHZ
tf
2.7
1.3
tPZL
tPLZ
OUTPUT LOW
TO OFF
6ns
OUTPUT
DISABLE
1.3V
OUTPUTS
DISABLED
OUTPUTS
ENABLED
FIGURE 22. HCT THREE-STATE PROPAGATION DELAY
WAVEFORM
OUTPUT
RL = 1kΩ
CL
50pF
VCC FOR tPLZ AND tPZL
GND FOR tPHZ AND tPZH
NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL = 1kΩ to
VCC, CL = 50pF.
FIGURE 23. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT
15
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
CD54HC4351F3A
ACTIVE
CDIP
J
20
1
TBD
Call TI
Level-NC-NC-NC
CD74HC4351E
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
CD74HC4351EE4
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
CD74HC4351M
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4351M96
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4351M96E4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4351ME4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4352E
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
CD74HC4352EE4
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
CD74HCT4351E
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
CD74HCT4351EE4
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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Copyright  2005, Texas Instruments Incorporated
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