TI CD54HC4514F High-speed cmos logic 4- to 16-line decoder/demultiplexer with input latch Datasheet

[ /Title
(CD74
HC451
4,
CD74
HC451
5)
/Subject
(High
Speed
CMOS
CD54HC4514, CD74HC4514,
CD74HC4515
Data sheet acquired from Harris Semiconductor
SCHS280C
November 1997 - Revised July 2003
High-Speed CMOS Logic 4- to 16-Line
Decoder/Demultiplexer with Input Latches
Features
Description
• Multifunction Capability
- Binary to 1-of-16 Decoder
- 1-to-16 Line Demultiplexer
• Fanout (Over Temperature Range)
The CD54HC4514, CD74HC4514, and CD74HC4515 are
high-speed silicon gate devices consisting of a 4-bit strobed
latch and a 4- to 16-line decoder. The selected output is
enabled by a low on the enable input (E). A high on E inhibits
selection of any output. Demultiplexing is accomplished by
using the E input as the data input and the select inputs (A0A3) as addresses. This E input also serves as a chip select
when these devices are cascaded.
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
When Latch Enable (LE) is high the output follows changes
in the inputs (see truth table). When LE is low the output is
isolated from changes in the input and remains at the level
(high for the 4514, low for the 4515) it had before the latches
were enabled. These devices, enhanced versions of the
equivalent CMOS types, can drive 10 LSTTL loads.
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
Ordering Information
TEMP. RANGE (oC)
PACKAGE
CD54HC4514F3A
-55 to 125
24 Ld CERDIP
CD74HC4514E
-55 to 125
24 Ld PDIP
CD74HC4514EN
-55 to 125
24 Ld PDIP
CD74HC4514M
-55 to 125
24 Ld SOIC
CD74HC4514M96
-55 to 125
24 Ld SOIC
CD74HC4515E
-55 to 125
24 Ld PDIP
CD74HC4515EN
-55 to 125
24 Ld PDIP
PART NUMBER
Pinout
CD54HC4514
(CERDIP)
CD74HC4514, CD74HC4515
(PDIP, SOIC)
TOP VIEW
LE 1
24 VCC
A0 2
23 E
A1 3
22 A3
Y7 4
21 A2
CD74HC4515M
-55 to 125
24 Ld SOIC
Y6 5
20 Y10
CD74HC4515M96
-55 to 125
24 Ld SOIC
Y5 6
19 Y11
Y4 7
18 Y8
Y3 8
17 Y9
Y1 9
16 Y14
Y2 10
15 Y15
Y0 11
14 Y12
GND 12
13 Y13
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 2003, Texas Instruments Incorporated
1
CD54HC4514, CD74HC4514, CD74HC4515
Functional Diagram
A0
A1
A2
A3
2
3
21 LATCH
4-TO-16
DECODER
22
1
LE
23
HC
4514
11
Y0
9
Y1
10
Y2
8
Y3
7
Y4
6
Y5
5
Y6
4
Y7
18
Y8
17
Y9
20
Y10
19
Y11
14
Y12
13
Y13
16
Y14
15
Y15
HC
4515
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
GND = 12
VCC = 24
E
DECODE TRUTH TABLE (LE = 1)
DECODER INPUTS
ENABLE
A3
A2
A1
A0
ADDRESSED OUTPUT
4514 = LOGIC 1 (HIGH)
4515 = LOGIC 0 (HIGH)
0
0
0
0
0
Y0
0
0
0
0
1
Y1
0
0
0
1
0
Y2
0
0
0
1
1
Y3
0
0
1
0
0
Y4
0
0
1
0
1
Y5
0
0
1
1
0
Y6
0
0
1
1
1
Y7
0
1
0
0
0
Y8
0
1
0
0
1
Y9
0
1
0
1
0
Y10
0
1
0
1
1
Y11
0
1
1
0
0
Y12
0
1
1
0
1
Y13
0
1
1
1
0
Y14
0
1
1
1
1
Y15
1
X
X
X
X
All Outputs = 0, 4514
All Outputs = 1, 4515
X = Don’t Care; Logic 1 = High; Logic 0 = Low
2
CD54HC4514, CD74HC4514, CD74HC4515
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, IO
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Thermal Resistance (Typical)
θJA (oC/W)
E (PDIP) Package (Note 1) . . . . . . . . . . . . . . . . . . .
67
EN (PDIP) Package (Note 1) . . . . . . . . . . . . . . . . . .
67
M (SOIC) Package (Note 2). . . . . . . . . . . . . . . . . . .
46
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. The package thermal impedance is calculated in accordance with JESD 51-3.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
25oC
-40oC TO 85oC -55oC TO 125oC
SYMBOL
VI (V)
IO (mA)
VCC
(V)
VIH
-
-
2
1.5
-
-
1.5
-
1.5
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
6
5.9
-
-
5.9
-
5.9
-
V
-
-
-
-
-
-
-
-
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
-5.2
6
5.48
-
-
5.34
-
5.2
-
V
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
HC TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
VIL
VOH
-
VIH or VIL
-
3
CD54HC4514, CD74HC4514, CD74HC4515
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
PARAMETER
25oC
-40oC TO 85oC -55oC TO 125oC
SYMBOL
VI (V)
IO (mA)
VCC
(V)
VOL
VIH or VIL
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
-
-
-
-
-
-
-
-
-
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
5.2
6
-
-
0.26
-
0.33
-
0.4
V
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
II
VCC or
GND
-
6
-
-
±0.1
-
±1
-
±1
µA
ICC
VCC or
GND
0
6
-
-
8
-
80
-
160
µA
Prerequisite For Switching Specifications
PARAMETER
25oC
-40oC TO 85oC -55oC TO 125oC
SYMBOL
TEST
CONDITIONS
VCC
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
tW
-
2
75
-
-
95
-
110
-
ns
4.5
30
-
-
19
-
22
-
ns
6
35
-
-
16
-
19
-
ns
2
100
-
-
125
-
150
-
ns
4.5
20
-
-
25
-
30
-
ns
6
17
-
-
21
-
26
-
ns
HC TYPES
LE Pulse Width
Select to LE Set-Up Time
Select to LE Hold Time
Switching Specifications
PARAMETER
tSU
tH
-
-
2
0
-
-
0
-
0
-
ns
4.5
0
-
-
0
-
0
-
ns
6
0
-
-
0
-
0
-
ns
CL = 50pF, Input tr, tf = 6ns
SYMBOL
TEST
CONDITIONS
tPHL, tPLH
CL = 50pF
-40oC TO
85oC
25oC
-55oC TO
125oC
VCC (V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
2
-
-
275
-
345
-
415
ns
4.5
-
-
55
-
69
-
83
ns
CL = 15pF
5
-
23
-
-
-
-
-
ns
CL = 50pF
6
-
-
47
-
59
-
71
ns
CL = 50pF
2
-
-
225
-
280
-
340
ns
4.5
-
-
45
-
56
-
68
ns
CL = 15pF
5
-
19
-
-
-
-
-
ns
CL = 50pF
6
-
-
38
-
48
-
58
ns
HC TYPES
Propagation Delay
Select to Outputs
LE to Outputs
tPHL, tPLH
4
CD54HC4514, CD74HC4514, CD74HC4515
Switching Specifications
PARAMETER
E to Outputs
Output Transition Time
CL = 50pF, Input tr, tf = 6ns (Continued)
-40oC TO
85oC
25oC
-55oC TO
125oC
SYMBOL
TEST
CONDITIONS
VCC (V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
tPHL, tPLH
CL = 50pF
2
-
-
175
-
220
-
265
ns
4.5
-
-
35
-
44
-
53
ns
CL = 15pF
5
-
14
-
-
-
-
-
ns
CL = 50pF
6
-
-
30
-
37
-
45
ns
CL = 50pF
2
-
-
75
-
95
-
110
ns
4.5
-
-
15
-
19
-
22
ns
6
-
-
13
-
16
-
19
ns
tTHL, tTLH
Input Capacitance
CIN
CL = 50pF
-
10
-
10
-
10
-
10
pF
Power Dissipation Capacitance
(Notes 3, 4)
CPD
-
5
-
70
-
-
-
-
-
pF
NOTES:
3. CPD is used to determine the dynamic power consumption, per package.
4. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
Test Circuits and Waveforms
tr = 6ns
tfCL
trCL
CLOCK
90%
10%
I
tWL + tWH =
fCL
tf = 6ns
VCC
50%
10%
tWL
VCC
90%
50%
10%
INPUT
GND
50%
50%
GND
tTHL
tTLH
tWH
90%
50%
10%
INVERTING
OUTPUT
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
tPHL
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
tPLH
FIGURE 2. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
tr = 6ns
tf = 6ns
VCC
90%
50%
10%
INPUT
GND
tTHL
tTLH
90%
50%
10%
INVERTING
OUTPUT
tPLH
tPHL
FIGURE 3. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
5
CD54HC4514, CD74HC4514, CD74HC4515
Test Circuits and Waveforms
tfCL
trCL
CLOCK
INPUT
(Continued)
90%
CLOCK
INPUT
50%
10%
GND
tH(H)
tfCL
trCL
VCC
VCC
90%
50%
10%
GND
tH(H)
tH(L)
tH(L)
VCC
DATA
INPUT
GND
tSU(H)
tTLH
OUTPUT
tTHL
90%
50%
10%
tSU(L)
tTLH
90%
tTHL
90%
50%
10%
tPLH
tPHL
OUTPUT
tPHL
tPLH
tREM
VCC
SET, RESET
OR PRESET
50%
GND
IC
50%
GND
tSU(H)
tSU(L)
90%
tREM
VCC
SET, RESET
OR PRESET
VCC
DATA
INPUT
50%
50%
GND
IC
CL
50pF
FIGURE 4. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
CL
50pF
FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
6
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
5962-9865501QJA
ACTIVE
CDIP
J
24
1
TBD
Call TI
N / A for Pkg Type
-55 to 125
5962-9865501QJ
A
CD54HC4514F3A
CD54HC4514F3A
ACTIVE
CDIP
J
24
1
TBD
Call TI
N / A for Pkg Type
-55 to 125
5962-9865501QJ
A
CD54HC4514F3A
CD74HC4514E
ACTIVE
PDIP
N
24
15
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC4514E
CD74HC4514EE4
ACTIVE
PDIP
N
24
15
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC4514E
CD74HC4514EN
ACTIVE
PDIP
NT
24
15
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC4514EN
CD74HC4514ENE4
ACTIVE
PDIP
NT
24
15
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC4514EN
CD74HC4514M
ACTIVE
SOIC
DW
24
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4514M
CD74HC4514M96
ACTIVE
SOIC
DW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4514M
CD74HC4514M96E4
ACTIVE
SOIC
DW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4514M
CD74HC4514M96G4
ACTIVE
SOIC
DW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4514M
CD74HC4514ME4
ACTIVE
SOIC
DW
24
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4514M
CD74HC4514MG4
ACTIVE
SOIC
DW
24
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4514M
CD74HC4515E
ACTIVE
PDIP
N
24
15
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC4515E
CD74HC4515EE4
ACTIVE
PDIP
N
24
15
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC4515E
CD74HC4515EN
ACTIVE
PDIP
NT
24
15
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC4515EN
CD74HC4515ENE4
ACTIVE
PDIP
NT
24
15
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC4515EN
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
25-Sep-2013
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
CD74HC4515M
ACTIVE
SOIC
DW
24
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4515M
CD74HC4515M96
ACTIVE
SOIC
DW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4515M
CD74HC4515M96E4
ACTIVE
SOIC
DW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4515M
CD74HC4515M96G4
ACTIVE
SOIC
DW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4515M
CD74HC4515ME4
ACTIVE
SOIC
DW
24
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4515M
CD74HC4515MG4
ACTIVE
SOIC
DW
24
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4515M
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CD54HC4514, CD74HC4514 :
• Catalog: CD74HC4514
• Military: CD54HC4514
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
CD74HC4514M96
SOIC
DW
24
2000
330.0
24.4
10.75
15.7
2.7
12.0
24.0
Q1
CD74HC4515M96
SOIC
DW
24
2000
330.0
24.4
10.75
15.7
2.7
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CD74HC4514M96
SOIC
DW
24
2000
367.0
367.0
45.0
CD74HC4515M96
SOIC
DW
24
2000
367.0
367.0
45.0
Pack Materials-Page 2
MECHANICAL DATA
MCDI004A – JANUARY 1995 – REVISED NOVEMBER 1997
J (R-GDIP-T**)
CERAMIC DUAL-IN-LINE PACKAGE
24 PINS SHOWN
B
13
24
C
1
12
0.065 (1,65)
0.045 (1,14)
Lens Protrusion (Lens Optional)
0.010 (0.25) MAX
0.175 (4,45)
0.140 (3,56)
0.090 (2,29)
0.060 (1,53)
A
Seating Plane
0.018 (0,46) MIN
24
PINS **
DIM
”A”
”B”
”C”
NARR
0.125 (3,18) MIN
0.022 (0,56)
0.014 (0,36)
0.100 (2,54)
0.012 (0,30)
0.008 (0,20)
28
WIDE
NARR
40
32
WIDE
NARR
WIDE
NARR
WIDE
MAX
0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85)
MIN
0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99)
MAX
1.265(32,13) 1.265(32,13) 1.465(37,21) 1.465(37,21) 1.668(42,37) 1.668(42,37) 2.068(52,53) 2.068(52,53)
MIN
1.235(31,37) 1.235(31,37) 1.435(36,45) 1.435(36,45) 1.632(41,45) 1.632(41,45) 2.032(51,61) 2.032(51,61)
MAX
0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19)
MIN
0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50)
4040084/C 10/97
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Window (lens) added to this group of packages (24-, 28-, 32-, 40-pin).
This package can be hermetically sealed with a ceramic lid using glass frit.
Index point is provided on cap for terminal identification.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MPDI006B – SEPTEMBER 2001 – REVISED APRIL 2002
N (R–PDIP–T24)
PLASTIC DUAL–IN–LINE
1.222 (31,04) MAX
24
13
0.360 (9,14) MAX
1
12
0.070 (1,78) MAX
0.200 (5,08) MAX
0.425 (10,80) MAX
0.020 (0,51) MIN
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0’–15’
0.021 (0,53)
0.015 (0,38)
0.010 (0,25)
0.010 (0,25) NOM
4040051–3/D 09/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS–010
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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