TI CD74AC175 Quad d flip-flop with reset Datasheet

[ /Title
(CD74
AC175
,
CD74
ACT17
5
)
/Subject
(Quad
D FlipFlop
with
Reset)
/Autho
r ()
/Keywords
(Harris
Semiconductor,
Advan
ced
CMOS
, Harris
Semiconductor,
Advan
ced
TTL)
/Creator ()
/DOCI
NFO
CD74AC175,
CD74ACT175
Data sheet acquired from Harris Semiconductor
SCHS242
Quad D Flip-Flop with Reset
September 1998
Features
Description
• Buffered Inputs
The CD74AC175 and CD74ACT175 are quad D flip-flops
with reset that utilize the Harris Advanced CMOS Logic technology. Information at the D input is transferred to the Q and
Q outputs on the positive-going edge of the clock pulse. All
four flip-flops are controlled by a common clock (CP) and a
common reset (MR). Resetting is accomplished by a LOW
logic level independent of the clock.
• Typical Propagation Delay
- 6.4ns at VCC = 5V, TA = 25oC, CL = 50pF
• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015
• SCR-Latchup-Resistant CMOS Process and Circuit
Design
Ordering Information
• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption
PART
NUMBER
• Balanced Propagation Delays
• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply
• ±24mA Output Drive Current
- Fanout to 15 FAST™ ICs
- Drives 50Ω Transmission Lines
TEMP.
RANGE (oC)
PKG.
NO.
PACKAGE
CD74AC175E
-55 to 125
16 Ld PDIP
E16.3
CD74ACT175E
-55 to 125
16 Ld PDIP
E16.3
CD74AC175M
-55 to 125
16 Ld SOIC
M16.15
CD74ACT175M
-55 to 125
16 Ld SOIC
M16.15
NOTES:
13. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
14. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris
customer service for ordering information.
Pinout
CD74AC175, CD74ACT175
(PDIP, SOIC)
TOP VIEW
MR 1
16 VCC
Q0 2
15 Q3
Q0 3
14 Q3
D0 4
13 D3
D1 5
12 D2
Q1 6
11 Q2
Q1 7
10 Q2
GND 8
9 CP
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.
Copyright © Harris Corporation 1998
1
File Number
1964.1
CD74AC175, CD74ACT175
Functional Diagram
4
D0
CP
D
9
2
Q
CP
1
MR
R
Q
5
D1
D
7
D
Q
Q1
Q
10
Q2
Q
11
Q2
Q
15
Q3
Q
14
Q3
CP
R
13
D3
D
CP
R
GND = 8
VCC = 16
Q1
6
12
D2
Q0
Q
CP
R
Q0
3
TRUTH TABLE (EACH FLIP-FLOP)
INPUTS
OUTPUTS
RESET
(MR)
CLOCK
CP
DATA
Dn
Qn
Qn
L
X
X
L
H
H
↑
H
H
L
H
↑
L
L
H
H
L
X
Q0
Q0
H
= High Level (Steady State)
L
= Low Level (Steady State)
X
= Irrelevant
↑
= Transition from Low to High level
Q0, Q0 = Level before the Indicated Steady-State Input conditions
were established.
2
CD74AC175, CD74ACT175
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
DC VCC or Ground Current, ICC or IGND (Note 3) . . . . . . . . .±100mA
Thermal Resistance (Typical, Note 5)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
160
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC (Note 4)
AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V
ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Slew Rate, dt/dv
AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)
AC Types, 3.6V to 5.5V . . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)
ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
15. For up to 4 outputs per device, add ±25mA for each additional output.
16. Unless otherwise specified, all voltages are referenced to ground.
17. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
-40oC TO
85oC
25oC
-55oC TO
125oC
SYMBOL
VI (V)
IO (mA)
VCC
(V)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
VIH
-
-
1.5
1.2
-
1.2
-
1.2
-
V
AC TYPES
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
VIL
VOH
-
VIH or VIL
3
2.1
-
2.1
-
2.1
-
V
5.5
3.85
-
3.85
-
3.85
-
V
1.5
-
0.3
-
0.3
-
0.3
V
3
-
0.9
-
0.9
-
0.9
V
5.5
-
1.65
-
1.65
-
1.65
V
-0.05
1.5
1.4
-
1.4
-
1.4
-
V
-0.05
3
2.9
-
2.9
-
2.9
-
V
-0.05
4.5
4.4
-
4.4
-
4.4
-
V
-4
3
2.58
-
2.48
-
2.4
-
V
-24
4.5
3.94
-
3.8
-
3.7
-
V
-75
(Note 6, 7)
5.5
-
-
3.85
-
-
-
V
-50
(Note 6, 7)
5.5
-
-
-
-
3.85
-
V
-
3
CD74AC175, CD74ACT175
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
PARAMETER
Low Level Output Voltage
-40oC TO
85oC
25oC
-55oC TO
125oC
SYMBOL
VI (V)
IO (mA)
VCC
(V)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
VOL
VIH or VIL
0.05
1.5
-
0.1
-
0.1
-
0.1
V
0.05
3
-
0.1
-
0.1
-
0.1
V
0.05
4.5
-
0.1
-
0.1
-
0.1
V
12
3
-
0.36
-
0.44
-
0.5
V
24
4.5
-
0.36
-
0.44
-
0.5
V
75
(Note 6, 7)
5.5
-
-
-
1.65
-
-
V
50
(Note 6, 7)
5.5
-
-
-
-
-
1.65
V
II
VCC or
GND
-
5.5
-
±0.1
-
±1
-
±1
µA
ICC
VCC or
GND
0
5.5
-
8
-
80
-
160
µA
High Level Input Voltage
VIH
-
-
4.5 to
5.5
2
-
2
-
2
-
V
Low Level Input Voltage
VIL
-
-
4.5 to
5.5
-
0.8
-
0.8
-
0.8
V
High Level Output Voltage
VOH
VIH or VIL
-0.05
4.5
4.4
-
4.4
-
4.4
-
V
-24
4.5
3.94
-
3.8
-
3.7
-
V
-75
(Note 6, 7)
5.5
-
-
3.85
-
-
-
V
-50
(Note 6, 7)
5.5
-
-
-
-
3.85
-
V
Input Leakage Current
Quiescent Supply Current
MSI
ACT TYPES
Low Level Output Voltage
Input Leakage Current
Quiescent Supply Current
MSI
Additional Supply Current per
Input Pin TTL Inputs High
1 Unit Load
VOL
VIH or VIL
0.05
4.5
-
0.1
-
0.1
-
0.1
V
24
4.5
-
0.36
-
0.44
-
0.5
V
75
(Note 6, 7)
5.5
-
-
-
1.65
-
-
V
50
(Note 6, 7)
5.5
-
-
-
-
-
1.65
V
II
VCC or
GND
-
5.5
-
±0.1
-
±1
-
±1
µA
ICC
VCC or
GND
0
5.5
-
8
-
80
-
160
µA
∆ICC
VCC
-2.1
-
4.5 to
5.5
-
2.4
-
2.8
-
3
mA
NOTES:
18. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize
power dissipation.
19. Test verifies a minimum 50Ω transmission-line-drive capability at 85oC, 75Ω at 125oC.
ACT Input Load Table
INPUT
UNIT LOAD
Dn
0.58
MR
0.67
CP
0.92
NOTE: Unit load is ∆ICC limit specified in DC Electrical Specifications
Table, e.g., 2.4mA max at 25oC.
4
CD74AC175, CD74ACT175
Prerequisite For Switching Function
PARAMETER
AC TYPES
Data to CP Set-Up Time
Hold Time
VCC (V)
MIN
MAX
MIN
MAX
UNITS
tSU
1.5
2
-
2
-
ns
3.3
(Note 8)
2
-
2
-
ns
5
(Note 9)
2
-
2
-
ns
1.5
2
-
2
-
ns
3.3
2
-
2
-
ns
5
2
-
2
-
ns
1.5
1
-
1
-
ns
3.3
1
-
1
-
ns
5
1
-
1
-
ns
1.5
44
-
50
-
ns
3.3
4.9
-
5.6
-
ns
tREM
MR Pulse Width
-55oC TO 125oC
SYMBOL
tH
Removal Time, MR to CP
-40oC TO 85oC
tW
5
3.5
-
4
-
ns
1.5
55
-
63
-
ns
3.3
6.1
-
7
-
ns
5
4.4
-
5
-
ns
1.5
9
-
8
-
MHz
3.3
81
-
71
-
MHz
5
114
-
100
-
MHz
tSU
5
(Note 9)
2
-
2
-
ns
tH
5
2
-
2
-
ns
tREM
5
1
-
1
-
ns
MR Pulse Width
tW
5
3.5
-
4
-
ns
Clock Pulse Width
tW
5
4.4
-
5
-
ns
fMAX
5
114
-
114
-
MHz
CP Pulse Width
tW
CP Frequency
fMAX
ACT TYPES
Data to CP Set-Up Time
Hold Time
Removal Time, MR to CP
CP Frequency
NOTES:
20. 3.3V Min is at 3V.
21. 5V Min is at 4.5V.
Switching Specifications Input tr, tf = 3ns, CL = 50pF (Worst Case)
-40oC TO 85oC
PARAMETER
-55oC TO 125oC
SYMBOL
VCC (V)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
tPLH, tPHL
1.5
-
-
139
-
-
153
ns
3.3
(Note 11)
4.4
-
15.5
4.3
-
17.1
ns
5
(Note 12)
3.2
-
11.1
3.1
-
12.2
ns
AC TYPES
Propagation Delay, CP to Q, Q
5
CD74AC175, CD74ACT175
Switching Specifications Input tr, tf = 3ns, CL = 50pF (Worst Case)
(Continued)
-40oC TO 85oC
-55oC TO 125oC
PARAMETER
SYMBOL
VCC (V)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Propagation Delay, MR to Q, Q
tPLH, tPHL
1.5
-
-
139
-
-
153
ns
3.3
4.4
-
15.5
4.3
-
17.1
ns
5
3.2
-
11.1
3.1
-
12.2
ns
CI
-
-
-
10
-
-
10
pF
CPD
(Note 13)
-
-
55
-
-
55
-
pF
Propagation Delay, CP to Qn
tPLH, tPHL
5
(Note 12)
3
-
10.5
2.9
-
11.5
ns
Propagation Delay, MR to Qn
tPLH, tPHL
5
3.3
-
11.8
3.3
-
13
ns
CI
-
-
-
10
-
-
10
pF
CPD
(Note 13)
-
-
55
-
-
55
-
pF
Input Capacitance
Power Dissipation Capacitance
ACT TYPES
Input Capacitance
Power Dissipation Capacitance
NOTES:
22. Limits tested 100%.
23. 3.3V Min is at 3.6V, Max is at 3V.
24. 5V Min is at 5.5V, Max is at 4.5V.
25. CPD is used to determine the dynamic power consumption per flip-flop.
PD = CPD VCC2 fi + Σ (CL + VCC2 fo) + VCC ∆ICC where fi = input frequency, fo = output frequency, CL = output load capacitance, VCC =
supply voltage.
INPUT LEVEL
MR
VS
VS
GND
tREM
tW
INPUT
INPUT LEVEL
CP
VS
GND
VS
VS
tW
CP
VS
tPHL
tPLH
tPHL
Q
VS
VS
VS
Q
FIGURE 5. PROPAGATION DELAYS
FIGURE 6. RESET OR SET PREREQUISITE AND
PROPAGATION DELAYS
OUTPUT
RL (NOTE)
500Ω
DUT
INPUT LEVEL
D
OUTPUT
LOAD
VS
VS
GND
INPUT LEVEL
VS
tH(L)
tSU(L)
CP
VS
CL
50pF
VS
tH(H)
NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ.
tSU(H)
CD74AC
CD74ACT
VCC
3V
Input Switching Voltage, VS
0.5 VCC
1.5V
Output Switching Voltage, VS
0.5 VCC
0.5 VCC
VS
GND
Input Level
FIGURE 7.
FIGURE 8. PROPAGATION DELAY TIMES
6
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright  1999, Texas Instruments Incorporated
Similar pages