TI1 CD74FCT373M Bicmos octal transparent d-type latch with 3-state output Datasheet

CD74FCT373
BiCMOS OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCBS738 – JULY 2000
D
D
D
D
D
D
D
D
D
E, M, OR SM PACKAGE
(TOP VIEW)
BiCMOS Technology With Low Quiescent
Power
Buffered Inputs
Noninverted Outputs
Input/Output Isolation From VCC
48-mA Output Sink Current
Controlled Output Edge Rates
Output Voltage Swing Limited to 3.7 V
SCR Latch-Up-Resistant BiCMOS Process
and Circuit Design
Package Options Include Plastic
Small-Outline (M) and Shrink Small-Outline
(SM) Packages and Standard Plastic (E) DIP
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
description
The CD74FCT373 is an octal, transparent, D-type latch with 3-state outputs using a small-geometry BiCMOS
technology. The output stage is a combination of bipolar and CMOS transistors that limits the output high level
to two diode drops below VCC. This resultant lowering of output swing (0 V to 3.7 V) reduces power-bus ringing
[a source of electromagnetic interference (EMI)] and minimizes VCC bounce and ground bounce and their
effects during simultaneous output switching. The output configuration also enhances switching speed and is
capable of sinking 48 mA.
The outputs are transparent to the inputs when latch enable (LE) is high. When LE is high, the Q outputs follow
the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs. The latch
operation is independent of output-enable (OE) input.
OE can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state.
When OE is high, the outputs are in the high-impedance state. In the high-impedance state, the outputs neither
load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to
drive bus lines without interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The CD74FCT373 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
(each latch)
INPUTS
OE
LE
D
OUTPUT
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
CD74FCT373
BiCMOS OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCBS738 – JULY 2000
logic symbol†
1
OE
LE
1D
2D
3D
4D
5D
6D
7D
8D
11
3
EN
C1
2
1D
4
5
7
6
8
9
13
12
14
15
17
16
18
19
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
OE
LE
1
11
C1
1D
3
2
1D
1Q
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
DC supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
DC input diode current, IIK (VI < –0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA
DC output diode current, IOK (VO < –0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
DC output sink current per output pin, IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mA
DC output source current per output pin, IOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 mA
Continuous current through VCC, ICC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 mA
Continuous current through GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 mA
Package thermal impedance, θJA (see Note 1): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
SM package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51.
2
POST OFFICE BOX 655303
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CD74FCT373
BiCMOS OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCBS738 – JULY 2000
recommended operating conditions (see Note 2)
MIN
MAX
UNIT
4.75
5.25
V
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
0
VO
IOH
Output voltage
0
IOL
∆t/∆v
Low-level output current
High-level input voltage
2
High-level output current
Input transition rise or fall rate
0
V
0.8
V
VCC
VCC
V
–15
mA
V
48
mA
10
ns/V
TA
Operating free-air temperature
0
70
°C
NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25°C
MIN
MAX
VCC
MIN
UNIT
–1.2
V
VIK
VOH
II = –18 mA
IOH = –15 mA
4.75 V
VOL
II
IOL = 48 mA
VI = VCC or GND
4.75 V
0.55
0.55
V
5.25 V
±0.1
±1
mA
IOZ
IOS†
VO = VCC or GND
VI = VCC or GND,
ICC
VI = VCC or GND,
One input at 3.4 V,
Other inputs at VCC or GND
∆ICC‡
Ci
Co
4.75 V
–1.2
MAX
2.4
±0.5
5.25 V
VO = 0
IO = 0
5.25 V
2.4
V
±10
–60
–60
mA
mA
5.25 V
8
80
mA
5.25 V
1.6
1.6
mA
10
10
pF
15
15
pF
VI = VCC or GND
VO = VCC or GND
† Not more than one output should be tested at a time, and the duration of the test should not exceed 100 ms.
‡ This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC.
timing requirements over recommended operating conditions (unless otherwise noted) (see
Figure 1)
MIN
MAX
UNIT
tw
Pulse duration
LE high
6
ns
tsu
Setup time
Data before LE↓
2
ns
th
Hold time
Data after LE↓
1.5
ns
switching characteristics over recommended operating conditions (unless otherwise noted) (see
Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
D
Q
LE
ten
tdis
PARAMETER
tpd
d
TA = 25°C
TYP
MIN
MAX
5
1.5
8
Any Q
9
2
13
OE
Any Q
7
1.5
12
ns
OE
Any Q
6
1.5
7.5
ns
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
ns
3
CD74FCT373
BiCMOS OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCBS738 – JULY 2000
noise characteristics, VCC = 5 V, CL = 50 pF, TA = 25°C
PARAMETER
VOL(P)
VOH(V)
Quiet output, maximum dynamic VOL
VIH(D)
VIL(D)
High-level dynamic input voltage
MIN
Quiet output, minimum dynamic VOH
TYP
MAX
UNIT
1
V
0.5
V
2
Low-level dynamic input voltage
V
0.8
V
TYP
UNIT
operating characteristics, TA = 25°C
PARAMETER
Cpd
4
TEST CONDITIONS
Power dissipation capacitance
No load,
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
f = 1 MHz
33
pF
CD74FCT373
BiCMOS OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCBS738 – JULY 2000
PARAMETER MEASUREMENT INFORMATION
7V
CL = 50 pF
(see Note A)
500 Ω
From Output
Under Test
Test
Point
From Output
Under Test
Open
TEST
GND
CL = 50 pF
(see Note A)
500 Ω
S1
S1
Open
7V
Open
7V
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
500 Ω
Open Drain
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
90%
1.5 V
10%
3V
1.5 V
10% 0 V
90%
tr
tf
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
3V
Timing Input
1.5 V
0V
tw
tsu
3V
1.5 V
1.5 V
Input
th
3V
1.5 V
1.5 V
Data Input
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
1.5 V
1.5 V
Input
0V
tPLH
tPHL
1.5 V
1.5 V
VOL
tPHL
Out-of-Phase
Output
tPLZ
≈3.5 V
1.5 V
tPZH
VOH
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
0V
Output
Waveform 1
(see Note B)
tPLH
1.5 V
1.5 V
tPZL
VOH
In-Phase
Output
3V
Output
Control
Output
Waveform 2
(see Note B)
VOL + 0.3 V
VOL
tPHZ
1.5 V
V
VOH – 0.3 V OH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr and tf = 2.5 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPHL and tPLH are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
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5
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
CD74FCT373E
OBSOLETE
PDIP
N
20
TBD
Call TI
Call TI
0 to 70
CD74FCT373M
OBSOLETE
SOIC
DW
20
TBD
Call TI
Call TI
0 to 70
CD74FCT373M96
OBSOLETE
SOIC
DW
20
TBD
Call TI
Call TI
0 to 70
CD74FCT373SM
OBSOLETE
SSOP
DB
20
TBD
Call TI
Call TI
0 to 70
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OUTLINE
DW0020A
SOIC - 2.65 mm max height
SCALE 1.200
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
20
1
13.0
12.6
NOTE 3
18X 1.27
2X
11.43
10
11
B
7.6
7.4
NOTE 4
20X
0.51
0.31
0.25
C A B
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0 -8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
11
10
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
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