CS4351
192 kHz Stereo DAC with 2 Vrms Line Out
Features
Description
! Multi-Bit Delta-Sigma Modulator
The CS4351 is a complete stereo digital-to-analog system including digital interpolation, fifth-order multi-bit
delta-sigma digital-to-analog conversion, digital de-emphasis, volume control, channel mixing, analog filtering,
and on-chip 2 Vrms line-level driver. The advantages of
this architecture include ideal differential linearity, no
distortion mechanisms due to resistor matching errors,
no linearity drift over time and temperature, high tolerance to clock jitter, and a minimal set of external
components.
! 24-Bit Conversion
! Up to 192 kHz Sample Rates
! 112 dB Dynamic Range
! -100 dB THD+N
! +3.3 V, +9 to 12 V, and VL Power Supplies
! 2 Vrms Output into 5 kΩ AC Load
! Digital Volume Control with Soft Ramp
–
–
–
The CS4351 is available in a 20-pin TSSOP package in
both Commercial (-10°C - +70°C) and Automotive
grades (-40°C to +85°C). The CDB4351 Customer
Demonstration board is also available for device evaluation and implementation suggestions. Please see
“Ordering Information” on page 37 for complete details.
119 dB Attenuation
1/2 dB Step Size
Zero Crossing Click-Free Transitions
! ATAPI Mixing
! Low Clock Jitter Sensitivity
These features are ideal for cost-sensitive, 2-channel
audio systems including DVD players, A/V receivers,
set-top boxes, digital TVs and VCRs, mini-component
systems, and mixing consoles.
! Popguard® Technology for Control of Clicks
and Pops
8 V to 3.3V
9 V to 12 V
3.3 V
dware or I2C/SPI
Control Data
Register/Hardware
Configuration
erial Audio Input
Level Translator
Reset
Interpolation
Filter with
Volume Control
Multibit
∆Σ Modulator
DAC
Amp
+
Filter
2 Vrms Line Level
Left Channel Outpu
DAC
Amp
+
Filter
2 Vrms Line Level
Right Channel
Output
PCM
Serial
Interface
Interpolation
Filter with
Volume Control
Multibit
∆Σ Modulator
Auto Speed Mode
Detect
Internal Voltage
Reference
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
External
Mute
Control
Left and Right
Mute Controls
DECEMBER '05
DS566F1
CS4351
TABLE OF CONTENTS
1. PIN DESCRIPTION ............................................................................................................................... 5
2. CHARACTERISTICS AND SPECIFICATIONS ..................................................................................... 6
SPECIFIED OPERATING CONDITIONS .............................................................................................. 6
ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 6
DAC ANALOG CHARACTERISTICS .................................................................................................... 7
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ....................................... 8
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ....................................... 9
SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE ...................................................... 10
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C® FORMAT ........................................... 11
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ FORMAT......................................... 12
DIGITAL CHARACTERISTICS............................................................................................................ 13
POWER AND THERMAL CHARACTERISTICS ................................................................................. 13
3. TYPICAL CONNECTION DIAGRAM .................................................................................................. 14
4. APPLICATIONS .................................................................................................................................. 15
4.1 Sample Rate Range/Operational Mode Detect ............................................................................ 15
4.1.1 Auto-Detect Enabled ........................................................................................................ 15
4.1.2 Auto-Detect Disabled ....................................................................................................... 15
4.2 System Clocking ........................................................................................................................... 15
4.3 Digital Interface Format ................................................................................................................ 16
4.3.1 Stand-Alone Mode ........................................................................................................... 16
4.3.2 Control Port Mode ........................................................................................................... 16
4.4 De-Emphasis Control ................................................................................................................... 17
4.4.1 Stand-Alone Mode ........................................................................................................... 18
4.4.2 Control Port Mode ............................................................................................................ 18
4.5 Recommended Power-Up Sequence ........................................................................................... 18
4.5.1 Stand-Alone Mode ........................................................................................................... 18
4.5.2 Control Port Mode ............................................................................................................ 18
4.6 Popguard® Transient Control ....................................................................................................... 18
4.6.1 Power-Up ......................................................................................................................... 18
4.6.2 Power-Down .................................................................................................................... 19
4.6.3 Discharge Time ................................................................................................................ 19
4.7 Mute Control ................................................................................................................................. 19
4.8 Grounding and Power Supply Arrangements ............................................................................... 19
4.8.1 Capacitor Placement ........................................................................................................ 19
4.9 Control Port Interface ................................................................................................................... 20
4.9.1 MAP Auto Increment ........................................................................................................ 20
4.9.2 I²C Mode .......................................................................................................................... 20
4.9.3 SPI Mode ......................................................................................................................... 21
4.10 Memory Address Pointer (MAP) ................................................................................................. 22
4.10.1 INCR (Auto Map Increment Enable) .............................................................................. 22
4.10.2 MAP (Memory Address Pointer) .................................................................................... 22
5. REGISTER QUICK REFERENCE ....................................................................................................... 23
6. REGISTER DESCRIPTION ................................................................................................................. 24
6.1 Chip ID - Register 01h .................................................................................................................. 24
6.2 Mode Control 1 - Register 02h ..................................................................................................... 24
6.2.1 Digital Interface Format (DIF2:0) Bits 6-4 ........................................................................ 24
6.2.2 De-Emphasis Control (DEM1:0) Bits 3-2. ........................................................................ 24
6.2.3 Functional Mode (FM) Bits 1-0 ......................................................................................... 25
6.3 Volume Mixing and Inversion Control - Register 03h ................................................................... 25
6.3.1 Channel A Volume = Channel B Volume (VOLB=A) Bit 7 ............................................... 25
6.3.2 Invert Signal Polarity (Invert_A) Bit 6 ............................................................................... 25
6.3.3 Invert Signal Polarity (Invert_B) Bit 5 ............................................................................... 25
2
DS566F1
CS4351
6.3.4 ATAPI Channel Mixing and Muting (ATAPI3:0) Bits 3-0 .................................................. 26
6.4 Mute Control - Register 04h ........................................................................................................ 27
6.4.1 Auto-Mute (AMUTE) Bit 7 ................................................................................................ 27
6.4.2 AMUTEC = BMUTEC (MUTEC A=B) Bit 5 ...................................................................... 27
6.4.3 A Channel Mute (MUTE_A) Bit 4
B Channel Mute (MUTE_B) Bit 3 .................................................................................... 27
6.5 Channel A Volume Control - Register 05h
Channel B Volume Control - Register 06h ................................................................................ 27
6.5.1 Digital Volume Control (VOL7:0) Bits 7-0 ........................................................................ 28
6.6 Ramp and Filter Control - Register 07h ........................................................................................ 28
6.6.1 Soft Ramp and Zero Cross Control (SZC1:0) Bits 7-6 ..................................................... 28
6.6.2 Soft Volume Ramp-Up After Error (RMP_UP) Bit 5 ......................................................... 29
6.6.3 Soft Ramp-Down Before Filter Mode Change (RMP_DN) Bit 4 ....................................... 29
6.6.4 Interpolation Filter Select (FILT_SEL) Bit 2 ..................................................................... 29
6.7 Misc Control - Register 08h .......................................................................................................... 29
6.7.1 Power Down (PDN) Bit 7 ................................................................................................. 30
6.7.2 Control Port Enable (CPEN) Bit 6 .................................................................................... 30
6.7.3 Freeze Controls (Freeze) Bit 5 ......................................................................................... 30
7. DIGITAL FILTER RESPONSE PLOTS ............................................................................................. 31
8. PARAMETER DEFINITIONS ............................................................................................................... 35
9. PACKAGE DIMENSIONS .................................................................................................................. 36
10. ORDERING INFORMATION ............................................................................................................. 37
11. REVISION HISTORY ......................................................................................................................... 37
LIST OF FIGURES
Figure 1. Serial Input Timing ..................................................................................................................... 10
Figure 2. Control Port Timing - I²C Format................................................................................................ 11
Figure 3. Control Port Timing - SPI Format (Write)................................................................................... 12
Figure 4. Typical Connection Diagram...................................................................................................... 14
Figure 5. Left-Justified up to 24-Bit Data................................................................................................... 17
Figure 6. I²S, up to 24-Bit Data ................................................................................................................. 17
Figure 7. Right-Justified Data.................................................................................................................... 17
Figure 8. De-Emphasis Curve................................................................................................................... 17
Figure 9. Control Port Timing, I²C Mode ................................................................................................... 21
Figure 10.Control Port Timing, SPI mode .................................................................................................. 22
Figure 11.De-Emphasis Curve................................................................................................................... 24
Figure 12.ATAPI Block Diagram ................................................................................................................ 26
Figure 13.Single-Speed (fast) Stopband Rejection.................................................................................... 31
Figure 14.Single-Speed (fast) Transition Band .......................................................................................... 31
Figure 15.Single-Speed (fast) Transition Band (detail) .............................................................................. 31
Figure 16.Single-Speed (fast) Passband Ripple ........................................................................................ 31
Figure 17.Single-Speed (slow) Stopband Rejection .................................................................................. 31
Figure 18.Single-Speed (slow) Transition Band......................................................................................... 31
Figure 19.Single-Speed (slow) Transition Band (detail)............................................................................. 32
Figure 20.Single-Speed (slow) Passband Ripple....................................................................................... 32
Figure 21.Double-Speed (fast) Stopband Rejection .................................................................................. 32
Figure 22.Double-Speed (fast) Transition Band......................................................................................... 32
Figure 23.Double-Speed (fast) Transition Band (detail)............................................................................. 32
Figure 24.Double-Speed (fast) Passband Ripple....................................................................................... 32
Figure 25.Double-Speed (slow) Stopband Rejection ................................................................................. 33
Figure 26.Double-Speed (slow) Transition Band ....................................................................................... 33
Figure 27.Double-Speed (slow) Transition Band (detail) ........................................................................... 33
Figure 28.Double-Speed (slow) Passband Ripple ..................................................................................... 33
DS566F1
3
CS4351
Figure 29.Quad-Speed (fast) Stopband Rejection ..................................................................................... 33
Figure 30.Quad-Speed (fast) Transition Band ........................................................................................... 33
Figure 31.Quad-Speed (fast) Transition Band (detail) ............................................................................... 34
Figure 32.Quad-Speed (fast) Passband Ripple ......................................................................................... 34
Figure 33.Quad-Speed (slow) Stopband Rejection.................................................................................... 34
Figure 34.Quad-Speed (slow) Transition Band.......................................................................................... 34
Figure 35.Quad-Speed (slow) Transition Band (detail).............................................................................. 34
Figure 36.Quad-Speed (slow) Passband Ripple........................................................................................ 34
LIST OF TABLES
Table 1. CS4351 Auto-Detect .................................................................................................................... 15
Table 2. CS4351 Mode Select ................................................................................................................... 15
Table 3. Single-Speed Mode Standard Frequencies ................................................................................. 16
Table 4. Double-Speed Mode Standard Frequencies................................................................................ 16
Table 5. Quad-Speed Mode Standard Frequencies .................................................................................. 16
Table 6. Digital Interface Format - Stand-Alone Mode............................................................................... 16
Table 7. Digital Interface Formats .............................................................................................................. 24
Table 8. ATAPI Decode ............................................................................................................................. 26
Table 9. Example Digital Volume Settings ................................................................................................. 28
Table 10. Revision History ......................................................................................................................... 37
4
DS566F1
CS4351
1. PIN DESCRIPTION
SDIN
SCLK
LRCK
MCLK
VD
GND
DIF1(SCL/CCLK)
DIF0(SDA/CDIN)
DEM(AD0/CS)
RST
Pin Name
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
#
VL
AMUTEC
AOUTA
VA_H
GND
AOUTB
BMUTEC
VQ
VBIAS
VA
Pin Description
SDIN
1
Serial Audio Data Input (Input) - Input for two’s complement serial audio data.
SCLK
2
Serial Clock (Input) - Serial clock for the serial audio interface.
LRCK
3
Left / Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial
audio data line.
MCLK
4
Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.
VD
5
Digital Power (Input) - Positive power supply for the digital section.
GND
6
16
Ground (Input) - Ground reference.
RST
10
Reset (Input) - Powers down device and resets all internal resisters to their default settings when
enabled.
VA
11
Low Voltage Analog Power (Input) - Positive power supply for the analog section.
VBIAS
12
Positive Voltage Reference (Output) - Positive reference voltage for the internal DAC.
VQ
13
Quiescent Voltage (Output) - Filter connection for internal quiescent voltage.
VA_H
17
High Voltage Analog Power (Input) - Positive power supply for the analog section.
VL
20
Serial Audio Interface Power (Input) - Positive power for the serial audio interface
BMUTEC
AMUTEC
14
19
Mute Control (Output) - Control signal for optional mute circuit.
AOUTB
AOUTA
15
18
Analog Outputs (Output) - The full scale analog line output level is specified in the Analog Characteristics table.
Control Port Definitions
SCL/CCLK
7
Serial Control Port Clock (Input) - Serial clock for the control port interface.
SDA/CDIN
8
Serial Control Data (Input/Output) - Input/Output for I²C data. Input for SPI data.
AD0/CS
9
Address Bit 0 / Chip Select (Input) - Chip address bit in I²C Mode. Control Port enable in SPI Mode.
Stand-Alone Definitions
DIF0
DIF1
8
7
Digital Interface Format (Input) - Defines the required relationship between the Left Right Clock,
Serial Clock, and Serial Audio Data.
DEM
9
De-emphasis (Input) - Selects the standard 15 µs/50 µs digital de-emphasis filter response for 44.1
kHz sample rates
DS566F1
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CS4351
2. CHARACTERISTICS AND SPECIFICATIONS
(Min/Max performance characteristics and specifications are guaranteed over the Specified Operating Conditions.
Typical specifications are derived from performance measurements at TA = 25 °C, VA_H = 12 V, VA = 3.3 V,
VD = 3.3 V.)
SPECIFIED OPERATING CONDITIONS
(GND = 0 V; all voltages with respect to ground.)
Parameters
DC Power Supply
High Voltage Analog power
Low Voltage Analog power
Digital power
Interface power
-CZZ
-DZZ
Specified Temperature Range
Symbol
Min
Typ
Max
Units
VA_H
VA
VD
VL
TA
TA
8.55
3.13
3.13
1.7
-10
-40
12
3.3
3.3
3.3
-
12.6
3.47
3.47
3.47
70
85
V
V
V
V
°C
°C
ABSOLUTE MAXIMUM RATINGS
(GND = 0 V; all voltages with respect to ground.)
Parameters
DC Power Supply
High Voltage Analog power
Low Voltage Analog power
Digital power
Interface power
Input Current, Any Pin Except Supplies
Digital Input Voltage
Ambient Operating Temperature (power applied)
Storage Temperature
Digital Interface
Symbol
Min
Max
Units
VA_H
VA
VD
VL
Iin
VIN-L
TA
Tstg
-0.3
-0.3
-0.3
-0.3
-0.3
-55
-65
14
3.63
3.63
3.63
±10
VL+ 0.4
125
150
V
V
V
V
mA
V
°C
°C
Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
6
DS566F1
CS4351
DAC ANALOG CHARACTERISTICS
(Test conditions (unless otherwise specified): input test signal is a 997 Hz sine wave at 0 dBFS; measurement
bandwidth 10 Hz to 20 kHz)
Parameter
All Speed Modes
Dynamic Range (Note 1)
Symbol
Min
Typ
Max
Unit
99
102
-
109
112
95
98
-
dB
dB
dB
dB
-
-100
-89
-49
-92
-75
-35
-90
-79
-39
-
dB
dB
dB
dB
dB
dB
-
109
-
dB
-
100
-
dB
1.85
2.00
2.15
Vrms
Fs = 48, 96, and 192 kHz
24-bit
16-bit
Total Harmonic Distortion + Noise
24-bit
16-bit
unweighted
A-Weighted
unweighted
A-Weighted
(Note 1) THD+N
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
All Speed Modes
Idle Channel Noise / Signal-to-noise ratio
Interchannel Isolation
(1 kHz)
Analog Output - All Modes
Full Scale Output Voltage
Common Mode Voltage
Max DC Current draw from an AOUT pin
Max Current draw from VQ
VQ
-
4
-
Vdc
IOUTmax
-
10
-
µA
IQmax
-
1
-
µA
-
0.1
-
dB
Interchannel Gain Mismatch
Gain Drift
-
-100
-
ppm/°C
ZOUT
-
50
-
Ω
AC-Load Resistance
RL
5
-
-
kΩ
Load Capacitance
CL
-
-
100
pF
Output Impedance
Notes:
1.
DS566F1
One-half LSB of triangular PDF dither is added to data.
7
CS4351
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
(The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs. See (Note 6)
Fast Roll-Off
Parameter
Min
Typ
Combined Digital and On-Chip Analog Filter Response - Single-Speed Mode - 48 kHz
Passband (Note 3)
Frequency Response 10 Hz to 20 kHz
StopBand
StopBand Attenuation
Total Group Delay (Fs = Output Sample Rate)
Intra-channel Phase Deviation
Inter-channel Phase Deviation
De-emphasis Error (Note 5)
(Relative to 1 kHz)
to -0.01 dB corner
to -3 dB corner
(Note 4)
Fs = 32 kHz
Fs = 44.1 kHz
Fs = 48 kHz
0
0
-0.01
0.547
102
-
9.4/Fs
-
Max
Unit
.454
.499
+0.01
±0.56/Fs
0
±0.23
±0.14
±0.09
Fs
Fs
dB
Fs
dB
s
s
s
dB
dB
dB
.430
.499
0.01
±0.03/Fs
0
Fs
Fs
dB
Fs
dB
s
s
s
.105
.490
0.01
±0.01/Fs
0
Fs
Fs
dB
Fs
dB
s
s
s
Combined Digital and On-Chip Analog Filter Response - Double-Speed Mode - 96 kHz
Passband (Note 3)
Frequency Response 10 Hz to 20 kHz
StopBand
StopBand Attenuation
Total Group Delay (Fs = Output Sample Rate)
Intra-channel Phase Deviation
Inter-channel Phase Deviation
to -0.01 dB corner
to -3 dB corner
(Note 4)
0
0
-0.01
.583
80
-
4.6/Fs
-
Combined Digital and On-Chip Analog Filter Response - Quad-Speed Mode - 192 kHz
Passband (Note 3)
Frequency Response 10 Hz to 20 kHz
StopBand
StopBand Attenuation
Total Group Delay (Fs = Output Sample Rate)
Intra-channel Phase Deviation
Inter-channel Phase Deviation
8
to -0.01 dB corner
to -3 dB corner
(Note 4)
0
0
-0.01
.635
90
-
4.7/Fs
-
DS566F1
CS4351
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
(Continued)
Slow Roll-Off (Note 2)
Min
Typ
Max
Parameter
Single-Speed Mode - 48 kHz
Passband (Note 3)
Frequency Response 10 Hz to 20 kHz
StopBand
StopBand Attenuation
Total Group Delay (Fs = Output Sample Rate)
Intra-channel Phase Deviation
Inter-channel Phase Deviation
De-emphasis Error (Note 5)
(Relative to 1 kHz)
to -0.01 dB corner
to -3 dB corner
(Note 4)
Fs = 32 kHz
Fs = 44.1 kHz
Fs = 48 kHz
Unit
0
0
-0.01
.583
64
-
6.5/Fs
-
0.417
0.499
+0.01
±0.14/Fs
0
±0.23
±0.14
±0.09
Fs
Fs
dB
Fs
dB
s
s
s
dB
dB
dB
0
0
-0.01
.792
70
-
3.9/Fs
-
.296
.499
0.01
±0.01/Fs
0
Fs
Fs
dB
Fs
dB
s
s
s
0
0
-0.01
.868
75
-
4.2/Fs
-
.104
.481
0.01
±0.01/Fs
0
Fs
Fs
dB
Fs
dB
s
s
s
Double-Speed Mode - 96 kHz
Passband (Note 3))
Frequency Response 10 Hz to 20 kHz
StopBand
StopBand Attenuation
Total Group Delay (Fs = Output Sample Rate)
Intra-channel Phase Deviation
Inter-channel Phase Deviation
to -0.01 dB corner
to -3 dB corner
(Note 4)
Quad-Speed Mode - 192 kHz
Passband (Note 3))
Frequency Response 10 Hz to 20 kHz
StopBand
StopBand Attenuation
Group Delay
Intra-channel Phase Deviation
Inter-channel Phase Deviation
to -0.01 dB corner
to -3 dB corner
(Note 4)
-
Notes:
2. Slow Roll-off interpolation filter is only available in Control Port mode.
3.
Response is clock dependent and will scale with Fs.
4. For Single-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs.
For Double-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs.
For Quad-Speed Mode, the Measurement Bandwidth is from stopband to 1.34 Fs.
5. De-emphasis is available only in Single-Speed Mode; Only 44.1 kHz De-emphasis is available in StandAlone Mode.
6. Amplitude vs. Frequency plots of this data are available in the “Digital Filter Response Plots” on
page 31.
DS566F1
9
CS4351
SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE
Parameters
Min
Max
Units
MCLK Frequency
1.024
51.2
MHz
MCLK Duty Cycle
45
55
%
Input Sample Rate (Manual selection)
Symbol
Single-Speed Mode
Double-Speed Mode
Fs
Fs
Fs
4
50
100
50
100
200
kHz
kHz
kHz
Single-Speed Mode
Double-Speed Mode
Fs
Fs
Fs
4
84
170
50
100
200
kHz
kHz
kHz
40
60
%
Quad-Speed Mode
Input Sample Rate (Auto selection)
Quad-Speed Mode
LRCK Duty Cycle
SCLK Pulse Width Low
tsclkl
20
-
ns
SCLK Pulse Width High
tsclkh
20
-
ns
Single-Speed Mode
tsclkw
1
---------------------( 128 )Fs
-
-
Double-Speed Mode
tsclkw
1
-----------------( 64 )Fs
-
-
Quad-Speed Mode
tsclkw
2
----------------MCLK
-
-
SCLK rising to LRCK edge delay
tslrd
23
-
ns
SCLK rising to LRCK edge setup time
tslrs
20
-
ns
SDIN valid to SCLK rising setup time
tsdlrs
20
-
ns
SCLK rising to SDIN hold time
tsdh
20
-
ns
SCLK Period
LRCK
t sclkh
t slrs
t slrd
t sclkl
SCLK
t sdlrs
t sdh
SDATA
Figure 1. Serial Input Timing
10
DS566F1
CS4351
Switching Characteristics - Control Port - I²C® Format
(Inputs: Logic 0 = GND, Logic 1 = VL, CL = 20 pF)
Symbol
Min
Max
Unit
SCL Clock Frequency
Parameter
fscl
-
100
kHz
RST Rising Edge to Start
tirs
500
-
ns
Bus Free Time Between Transmissions
tbuf
4.7
-
µs
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
-
µs
Clock Low time
tlow
4.7
-
µs
Clock High Time
thigh
4.0
-
µs
tsust
4.7
-
µs
thdd
0
-
µs
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
(Note 7)
tsud
250
-
ns
Rise Time of SCL and SDA
SDA Setup time to SCL Rising
trc, trc
-
1
µs
Fall Time SCL and SDA
tfc, tfc
-
300
ns
Setup Time for Stop Condition
tsusp
4.7
-
µs
Acknowledge Delay from SCL Falling
tack
300
1000
ns
Notes:
7. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
RST
t
irs
Stop
R e p e ate d
S ta rt
Start
t rd
t fd
Stop
SDA
t
buf
t
t
hdst
t
high
t fc
hdst
t susp
SCL
t
lo w
t
hdd
t sud
t ack
t sust
t rc
Figure 2. Control Port Timing - I²C Format
DS566F1
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CS4351
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ FORMAT
(Inputs: Logic 0 = GND, Logic 1 = VL, CL = 20 pF)
Parameter
Symbol
Min
Max
Unit
CCLK Clock Frequency
fsclk
-
6
MHz
RST Rising Edge to CS Falling
tsrs
500
-
ns
tspi
500
-
ns
CS High Time Between Transmissions
tcsh
1.0
-
µs
CS Falling to CCLK Edge
tcss
20
-
ns
CCLK Low Time
tscl
66
-
ns
CCLK High Time
tsch
66
-
ns
CDIN to CCLK Rising Setup Time
tdsu
40
-
ns
(Note 9)
tdh
17
-
ns
Rise Time of CCLK and CDIN
(Note 10)
tr2
-
100
ns
Fall Time of CCLK and CDIN
(Note 10)
tf2
-
100
ns
CCLK Edge to CS Falling
(Note 8)
CCLK Rising to DATA Hold Time
Notes:
8. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.
9. Data must be held for sufficient time to bridge the transition time of CCLK.
10. For FSCK < 1 MHz.
RST
t srs
CS
t spi t css
t scl
t sch
t csh
CCLK
t r2
t f2
CDIN
t dsu t
dh
Figure 3. Control Port Timing - SPI Format (Write)
12
DS566F1
CS4351
DIGITAL CHARACTERISTICS
Parameters
High-Level Input Voltage
Symbol
Min
Typ
Max
Units
VIH
VIH
VIH
VIL
VIL
VIL
Iin
2.0
1.7
0.65•VL
-
8
2
VA_H
0
0.8
0.7
0.33•VL
±10
-
V
V
V
V
V
V
µA
pF
mA
V
V
VL = 3.3 V
VL = 2.5 V
VL = 1.8 V
VL = 3.3 V
VL = 2.5 V
VL = 1.8 V
Low-Level Input Voltage
Input Leakage Current
Input Capacitance
Maximum MUTEC Drive Current
MUTEC High-Level Output Voltage
MUTEC Low-Level Output Voltage
VOH
VOL
POWER AND THERMAL CHARACTERISTICS
Parameters
Symbol
Min
Typ
Max
Units
normal operation, VA_H = 12 V
VA_H = 9 V
VA= 3.3 V
VD= 3.3 V
Interface current (Note 12) VL= 3.3 V
power-down state, all supplies (Note 13)
Power Dissipation (all supplies)
(Note 11)
VA_H = 12 V
normal operation
power-down (Note 13)
VA_H = 9 V
normal operation
power-down (Note 13)
Power Supply Rejection Ratio (Note 14)
(1 kHz)
(60 Hz)
IA_H
IA_H
IA
ID
IL
Ipd
-
15
14
6
21
100
200
20
19
8
26
400
-
mA
mA
mA
mA
µA
µA
-
270
1
216
1
60
60
354
285
-
mW
mW
mW
mW
dB
dB
Power Supplies
Power Supply Current
(Note 11)
PSRR
Notes:
11. Current consumption increases with increasing FS and increasing MCLK. Typ and Max values are
based on highest FS and highest MCLK. Variance between speed modes is small.
12. IL measured with no external loading on pin 8 (SDA).
13. Power-Down Mode is defined as RES pin = Low with all clock and data lines held static.
14. Valid with the recommended capacitor values on VQ and VBIAS as shown in the typical connection diagram in Section 3.
DS566F1
13
CS4351
3. TYPICAL CONNECTION DIAGRAM
5.1Ω∗
+3.3 V
+3.3 V *
*Remove this supply if
optional resistor is present.
The decoupling caps should
remain.
10 µF
+
*Optional
+
0.1 µF
0.1 µF
10 µF
11
VA
5
VD
+ 3.3 µF
VBIAS+ 12
4
Digital
Audio
Source
3
2
1
MCLK
LRCK
VA_H
17
+9 V to +12 V
0.1 µF
SCLK
+
10 µF
SDIN
Optional Mute Circuit
+1.8 V to VD
20
AMUTEC
19
VL
0.1 µF
AOUTA
+
3.3 µF
CS4351
576 k Ω
560 Ω
18
412 k Ω
AOUTA
10 k Ω
2.2 nF*
Optional Mute Circuit
BMUTEC
10
µ C/
Mode
Configuration
7
8
9
14
RST
AOUTB
DIF1(SCL/CCLK)
+
3.3 µF
DIF0(SDA/CDIN)
576 k Ω
560 Ω
15
412 k Ω
AOUTA
10k Ω
2.2 nF*
DEM(AD0/CS)
VQ
*Shown value is
for fc=130kHz
13
+
GND
6
3.3 µF
GND
16
Figure 4. Typical Connection Diagram
14
DS566F1
CS4351
4. APPLICATIONS
4.1
Sample Rate Range/Operational Mode Detect
The device operates in one of three operational modes. The allowed sample rate range in each mode will
depend on whether the Auto-Detect Defeat bit is enabled/disabled.
4.1.1
Auto-Detect Enabled
The Auto-Detect feature is enabled by default. In this state, the CS4351 will auto-detect the correct mode
when the input sample rate (Fs), defined by the LRCK frequency, falls within one of the ranges illustrated
in Table 1. Sample rates outside the specified range for each mode are not supported.
Input Sample Rate (FS)
MODE
4 kHz - 50 kHz
84 kHz - 100 kHz
170 kHz - 200 kHz
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
Table 1. CS4351 Auto-Detect
4.1.2
Auto-Detect Disabled
The Auto-Detect feature can be defeated only by the format bits in the control port register 02h. In this
state, the CS4351 will not auto-detect the correct mode based on the input sample rate (Fs). The operational mode must then be set manually according to one of the ranges illustrated in Table 2. Please refer
to Section 6.2.3 for implementation details. Sample rates outside the specified range for each mode are
not supported. In stand-alone mode it is not possible to disable auto-detect of sample rates.
FM1
FM0
Input Sample Rate (FS)
MODE
0
0
1
1
0
1
0
1
Auto speed mode detect
4 kHz - 50 kHz
50 kHz - 100 kHz
100 kHz - 200 kHz
Auto
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
Table 2. CS4351 Mode Select
4.2
System Clocking
The device requires external generation of the master (MCLK), left/right (LRCK) and serial (SCLK) clocks.
The left/right clock, defined also as the input sample rate (Fs), must be synchronously derived from the
MCLK according to specified ratios. The specified ratios of MCLK to LRCK, along with several standard audio sample rates and the required MCLK frequency, are illustrated in Tables 3 through 5.
Refer to Section 4.3 for the required SCLK timing associated with the selected Digital Interface Format and
to the “Switching Specifications - Serial Audio Interface” section on page 10 for the maximum allowed clock
frequencies.
DS566F1
15
CS4351
Sample Rate
(kHz)
MCLK (MHz)
512x
768x
256x
384x
32
44.1
48
8.1920
11.2896
12.2880
12.2880
16.9344
18.4320
16.3840
22.5792
24.5760
24.5760
33.8688
36.8640
1024x
1152x
32.7680
45.1584
49.1520
36.8640
Table 3. Single-Speed Mode Standard Frequencies
Sample Rate
(kHz)
128x
192x
64
88.2
96
8.1920
11.2896
12.2880
12.2880
16.9344
18.4320
MCLK (MHz)
256x
16.3840
22.5792
24.5760
384x
512x
24.5760
33.8688
36.8640
32.7680
45.1584
49.1520
Table 4. Double-Speed Mode Standard Frequencies
Sample Rate
(kHz)
64x
96x
MCLK (MHz)
128x
192x
256x
176.4
192
11.2896
12.2880
16.9344
18.4320
22.5792
24.5760
33.8688
36.8640
45.1584
49.1520
Table 5. Quad-Speed Mode Standard Frequencies
= Denotes clock modes which are NOT auto detected
4.3
Digital Interface Format
The device will accept audio samples in 1 of 4 digital interface formats in Stand-Alone mode, as illustrated
in Table 6, and 1 of 6 formats in Control Port mode, as illustrated in Table 7.
4.3.1
Stand-Alone Mode
The desired format is selected via the DIF1 and DIF0 pins. For an illustration of the required relationship
between the LRCK, SCLK and SDIN, see Figures 5 through 7. For all formats, SDIN is valid on the rising
edge of SCLK. Also, SCLK must have at least 32 cycles per LRCK period in format 2, and 48 cycles per
LRCK period in format 3.
DIF0
DIF1
0
0
1
1
0
1
0
1
DESCRIPTION
I2S, up to 24-bit Data
Left Justified, up to 24-bit Data
Right Justified, 24-bit Data
Right Justified, 16-bit Data
FORMAT
FIGURE
0
1
2
3
6
5
7
7
Table 6. Digital Interface Format - Stand-Alone Mode
4.3.2
Control Port Mode
The desired format is selected via the DIF2, DIF1 and DIF0 bits in the Mode Control 2 register (see section
Section 6.2.1). For an illustration of the required relationship between LRCK, SCLK and SDIN, see
Figures 5 through 7. For all formats, SDIN is valid on the rising edge of SCLK. Also, SCLK must have at
16
DS566F1
CS4351
least 32 cycles per LRCK period in format 2, 48 cycles in format 3, 40 cycles in format 4, and 36 cycles
in format 5.
Left C ha nnel
LR C K
R ig ht C ha nnel
S C LK
SDIN
MSB
-1 -2 -3 -4 -5
+5 +4 +3 +2 +1
MSB
LSB
-1 -2 -3 -4
+5 +4 +3 +2 +1
LSB
Figure 5. Left-Justified up to 24-Bit Data
Left Channel
LR C K
R ight C ha nnel
S C LK
SDIN
M SB
-1 -2 -3 -4 -5
+5 +4 +3 +2 +1
LSB
M SB
-1 -2 -3 -4
+5 +4 +3 +2 +1
LSB
Figure 6. I²S, up to 24-Bit Data
LRCK
R ight Cha nnel
Left Channel
SCLK
SDIN
M SB
MSB
+1 +2 +3 +4 +5
-7 -6 -5 -4 -3 -2 -1
LSB
MSB
+1 +2 +3 +4 +5
-7 -6 -5 -4 -3 -2 -1
LSB
Figure 7. Right-Justified Data
4.4
De-Emphasis Control
The device includes on-chip digital de-emphasis. Figure 8 shows the de-emphasis curve for Fs equal to 44.1
kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in sample
rate, Fs.
Gain
dB
T1=50 µs
0dB
T2 = 15 µs
-10dB
F1
3.183 kHz
F2
Frequency
10.61 kHz
Figure 8. De-Emphasis Curve
Note:
DS566F1
De-emphasis is only available in Single-Speed Mode.
17
CS4351
4.4.1
Stand-Alone Mode
When pulled to VL the DEM pin activates the 44.1 kHz de-emphasis filter. When pulled to GND the DEM
pin turns off the de-emphasis filter.
4.4.2
Control Port Mode
The Mode Control bits selects either the 32, 44.1, or 48 kHz de-emphasis filter. Please see Section 6.2.2
for the desired de-emphasis control.
4.5
4.5.1
Recommended Power-Up Sequence
Stand-Alone Mode
1. Hold RST low until the power supplies and configuration pins are stable, and the master and left/right
clocks are locked to the appropriate frequencies, as discussed in Section 4.2. In this state, the control
port is reset to its default settings, VQ will remain low, and VBIAS will be connected to VA.
2. Bring RST high. The device will remain in a low power state with VQ low and will initiate the StandAlone power-up sequence after approximately 512 LRCK cycles in Single-Speed Mode (1024 LRCK
cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode).
4.5.2
Control Port Mode
1. Hold RST low until the power supply is stable, and the master and left/right clocks are locked to the
appropriate frequencies, as discussed in Section 4.2. In this state, the control port is reset to its
default settings, VQ will remain low, and VBIAS will be connected to VA.
2. Bring RST high. The device will remain in a low power state with VQ low.
3. Perform a control port write to the CP_EN bit prior to the completion of approximately 512 LRCK
cycles in Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in
Quad-Speed Mode). The desired register settings can be loaded while keeping the PDN bit set to 1.
4. Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximately 50 µs when
the POPG bit is set to 0. If the POPG bit is set to 1, see Section 4.6 for a complete description of
power-up timing.
4.6
Popguard® Transient Control
The CS4351 uses a novel technique to minimize the effects of output transients during power-up and powerdown. This technology, when used with external DC-blocking capacitors in series with the audio outputs,
minimizes the audio transients commonly produced by single-ended single-supply converters. It is activated
inside the DAC when the RST pin is toggled and requires no other external control, aside from choosing the
appropriate DC-blocking capacitors.
4.6.1
Power-Up
When the device is initially powered-up, the audio outputs, AOUTA and AOUTB, are clamped to GND.
Following a delay of approximately 1000 sample periods, each output begins to ramp toward the quiescent voltage. Approximately 10,000 LRCK cycles later, the outputs reach VQ and audio output begins.
This gradual voltage ramping allows time for the external DC-blocking capacitors to charge to the quiescent voltage, minimizing audible power-up transients.
18
DS566F1
CS4351
4.6.2
Power-Down
To prevent audible transients at power-down, the device must first enter its power-down state. When this
occurs, audio output ceases and the internal output buffers are disconnected from AOUTA and AOUTB.
In their place, a soft-start current sink is substituted which allows the DC-blocking capacitors to slowly discharge. Once this charge is dissipated, the power to the device may be turned off and the system is ready
for the next power-on.
4.6.3
Discharge Time
To prevent an audio transient at the next power-on, the DC-blocking capacitors must fully discharge before turning on the power or exiting the power-down state. If full discharge does not occur, a transient will
occur when the audio outputs are initially clamped to GND. The time that the device must remain in the
power-down state is related to the value of the DC-blocking capacitance and the output load. For example,
with a 3.3 µF capacitor, the minimum power-down time will be approximately 0.4 seconds.
4.7
Mute Control
The Mute Control pins go active during power-up initialization, reset, muting (see Section 6.4.3), or if the
MCLK to LRCK ratio is incorrect. These pins are intended to be used as control for external mute circuits to
prevent the clicks and pops that can occur in any single-ended single supply system.
Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer
to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit.
Please see the “Typical Connection Diagram” on page 14 for a suggested mute circuit for single supply systems. This FET circuit must be placed in series after the RC filter, otherwise noise may occur during muting
conditions. Further ESD protection will need to be taken into consideration for the FET used. If dual supplies
are available, the BJT mute circuit from Figure 12 in the CS4398 datasheet (active Low) may be used.
4.8
Grounding and Power Supply Arrangements
As with any high resolution converter, the CS4351 requires careful attention to power supply and grounding
arrangements if its potential performance is to be realized. Figure 4 shows the recommended power arrangements, with VA_H, VA, VD, and VL connected to clean supplies. If the ground planes are split between
digital ground and analog ground, the GND pins of the CS4351 should be connected to the analog ground
plane.
All signals, especially clocks, should be kept away from the VBIAS and VQ pins in order to avoid unwanted
coupling into the DAC.
4.8.1
Capacitor Placement
Decoupling capacitors should be placed as close to the DAC as possible, with the low value ceramic capacitor being the closest. To further minimize impedance, these capacitors should be located on the same
layer as the DAC. If desired, all supply pins may be connected to the same supply, but a decoupling capacitor should still be placed on each supply pin.
Note:
All decoupling capacitors should be referenced to analog ground.
The CDB4351 evaluation board demonstrates the optimum layout and power supply arrangements.
DS566F1
19
CS4351
4.9
Control Port Interface
The control port is used to load all the internal register settings (see Section 6). The operation of the control
port may be completely asynchronous with the audio sample rate. However, to avoid potential interference
problems, the control port pins should remain static if no operation is required.
The control port operates in one of two modes: I²C or SPI.
4.9.1
MAP Auto Increment
The device has MAP (memory address pointer) auto increment capability enabled by the INCR bit (also
the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive I²C writes or reads and
SPI writes. If INCR is set to 1, MAP will auto increment after each byte is written, allowing block reads or
writes of successive registers.
4.9.2
I²C Mode
In the I²C mode, data is clocked into and out of the bi-directional serial control data line, SDA, by the serial
control port clock, SCL (see Figure 9 for the clock to data relationship). There is no CS pin. Pin AD0 enables the user to alter the chip address (100110[AD0][R/W]) and should be tied to VL or GND as required,
before powering up the device. If the device ever detects a high to low transition on the AD0/CS pin after
power-up, SPI mode will be selected.
4.9.2.1
I²C Write
To write to the device, follow the procedure below while adhering to the control port Switching Specifications in Section 8.
1. Initiate a START condition to the I²C bus followed by the address byte. The upper 6 bits must be
100110. The seventh bit must match the setting of the AD0 pin, and the eighth must be 0. The eighth
bit of the address byte is the R/W bit.
2. Wait for an acknowledge (ACK) from the part, then write to the memory address pointer, MAP. This
byte points to the register to be written.
3. Wait for an acknowledge (ACK) from the part, then write the desired data to the register pointed to
by the MAP.
4. If the INCR bit (see Section 4.9.1) is set to 1, repeat the previous step until all the desired registers
are written, then initiate a STOP condition to the bus.
5. If the INCR bit is set to 0 and further I²C writes to other registers are desired, it is necessary to initiate
a repeated START condition and follow the procedure detailed from step 1. If no further writes to other registers are desired, initiate a STOP condition to the bus.
20
DS566F1
CS4351
4.9.2.2
I²C Read
To read from the device, follow the procedure below while adhering to the control port Switching Specifications.
1. Initiate a START condition to the I²C bus followed by the address byte. The upper 6 bits must be
100110. The seventh bit must match the setting of the AD0 pin, and the eighth must be 1. The eighth
bit of the address byte is the R/W bit.
2. After transmitting an acknowledge (ACK), the device will then transmit the contents of the register
pointed to by the MAP. The MAP register will contain the address of the last register written to the
MAP, or the default address (see Section 4.10.2) if an I²C read is the first operation performed on
the device.
3. Once the device has transmitted the contents of the register pointed to by the MAP, issue an ACK.
4. If the INCR bit is set to 1, the device will continue to transmit the contents of successive registers.
Continue providing a clock and issue an ACK after each byte until all the desired registers are read,
then initiate a STOP condition to the bus.
5. If the INCR bit is set to 0 and further I²C reads from other registers are desired, it is necessary to
initiate a repeated START condition and follow the procedure detailed from steps 1 and 2 from the
I²C Write instructions followed by step 1 of the I²C Read section. If no further reads from other registers are desired, initiate a STOP condition to the bus.
NOTE
SDA
100110
AD0
R/W
ACK
DATA
1-8
ACK
DATA
1-8
ACK
SCL
S ta rt
Stop
NOTE: If operation is a write, this byte contains the M em ory Address Pointer, MAP. If
operation is a read, this byte contains the data of the register pointed to by the MAP.
Figure 9. Control Port Timing, I²C Mode
4.9.3
SPI Mode
In SPI mode, data is clocked into the serial control data line, CDIN, by the serial control port clock, CCLK
(see Figure 10 for the clock to data relationship). There is no AD0 pin. Pin CS is the chip select signal and
is used to control SPI writes to the control port. When the device detects a high to low transition on the
AD0/CS pin after power-up, SPI mode will be selected. All signals are inputs and data is clocked in on the
rising edge of CCLK.
4.9.3.1
SPI Write
To write to the device, follow the procedure below while adhering to the control port Switching Specifications in Section 8.
1. Bring CS low.
2. The address byte on the CDIN pin must then be 10011000.
3. Write to the memory address pointer, MAP. This byte points to the register to be written.
DS566F1
21
CS4351
4. Write the desired data to the register pointed to by the MAP.
5. If the INCR bit (see Section 4.9.1) is set to 1, repeat the previous step until all the desired registers
are written, then bring CS high.
6. If the INCR bit is set to 0 and further SPI writes to other registers are desired, it is necessary to bring
CS high, and follow the procedure detailed from step 1. If no further writes to other registers are desired, bring CS high.
)
CS
CCLK
CHIP
ADDRESS
CDIN
1001100
MAP
R/W
DATA
LSB
M SB
byte 1
byte n
M AP = M em ory Address Pointer
Figure 10. Control Port Timing, SPI mode
4.10
Memory Address Pointer (MAP)
7
INCR
0
4.10.1
6
Reserved
0
5
Reserved
0
4
Reserved
0
3
MAP3
0
2
MAP2
0
1
MAP1
0
0
MAP0
0
INCR (AUTO MAP INCREMENT ENABLE)
Default = ‘0’
0 - Disabled
1 - Enabled
4.10.2
MAP (MEMORY ADDRESS POINTER)
Default = ‘0000’
22
DS566F1
CS4351
5. REGISTER QUICK REFERENCE
Addr
Function
1h
Chip ID
2h
Mode Control
3h
Volume, Mixing,
and Inversion
Control
default
default
default
4h
Mute Control
5h
Channel A Volume
Control
6h
Channel B Volume
Control
default
default
default
7h
Ramp and Filter
Control
default
8h
Misc. Control
default
DS566F1
7
6
5
4
3
2
1
0
PART4
PART3
PART2
PART1
PART0
REV2
REV1
REV0
1
1
1
1
1
-
-
-
Reserved
DIF2
DIF1
DIF0
DEM1
DEM0
FM1
FM0
0
0
0
0
0
0
0
0
VOLB=A
INVERTA
INVERTB
Reserved
ATAPI3
ATAPI2
ATAPI1
ATAPI0
0
0
0
0
1
0
0
1
AMUTE
Reserved
MUTEC
A=B
MUTE_A
MUTE_B
Reserved
Reserved
Reserved
1
0
0
0
0
0
0
0
VOL7
VOL6
VOL5
VOL4
VOL3
VOL2
VOL1
VOL0
0
0
0
0
0
0
0
0
VOL7
VOL6
VOL5
VOL4
VOL3
VOL2
VOL1
VOL0
0
0
0
0
0
0
0
0
SZC1
SZC0
RMP_UP
RMP_DN
Reserved
FILT_SEL
Reserved
Reserved
1
0
1
1
0
0
0
1
PDN
CPEN
FREEZE
Reserved
Reserved
Reserved
Reserved
Reserved
1
0
0
0
0
0
0
0
23
CS4351
6. REGISTER DESCRIPTION
** All register access is R/W unless specified otherwise**
6.1
Chip ID - Register 01h
7
PART4
1
6
PART3
1
5
PART2
1
4
PART1
1
3
PART0
1
2
REV2
-
1
REV1
-
0
REV0
-
Function:
This register is Read-Only. Bits 7 through 3 are the part number ID which is 11111b and the remaining Bits
(2 through 0) are for the chip revision (Rev. A = 000, Rev. B = 001, ...)
6.2
Mode Control 1 - Register 02h
7
Reserved
0
6.2.1
6
DIF2
0
5
DIF1
0
4
DIF0
0
3
DEM1
0
2
DEM0
0
1
FM1
0
0
FM0
0
Digital Interface Format (DIF2:0) Bits 6-4
Function:
These bits select the interface format for the serial audio input.
The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital
Interface Format and the options are detailed in Figures 5 through 7.
DIF2
DIF1
DIF0
DESCRIPTION
Format
FIGURE
0
0
0
5
Left Justified, up to 24-bit data
0 (Default)
1
6
0
0
1
I2S, up to 24-bit data
0
1
0
2
7
Right Justified, 16-bit data
3
7
0
1
1
Right Justified, 24-bit data
4
7
1
0
0
Right Justified, 20-bit data
1
0
1
5
7
Right Justified, 18-bit data
1
1
0
Reserved
1
1
1
Reserved
Table 7. Digital Interface Formats
6.2.2
De-Emphasis Control (DEM1:0) Bits 3-2.
Default = 0
00 - No De-emphasis
01 - 44.1 kHz De-emphasis
10 - 48 kHz De-emphasis
11 - 32 kHz De-emphasis
Gain
dB
T1=50 µs
0dB
T2 = 15 µs
Function:
Selects the appropriate digital filter to maintain the standard 15 µs/50 µs digital de-emphasis filter response at
32, 44.1 or 48 kHz sample rates. (See Figure 11.)
-10dB
F1
3.183 kHz
F2
Frequency
10.61 kHz
Figure 11. De-Emphasis Curve
Note:
24
De-emphasis is only available in Single-Speed Mode
DS566F1
CS4351
6.2.3
Functional Mode (FM) Bits 1-0
Default = 00
00 - Auto speed mode detect
01 - Single-Speed Mode (4 to 50 kHz sample rates)
10 - Double-Speed Mode (50 to 100 kHz sample rates)
11 - Quad-Speed Mode (100 to 200 kHz sample rates)
Function:
Selects the required range of input sample rates or DSD Mode.
6.3
Volume Mixing and Inversion Control - Register 03h
B7
VOLB=A
0
6.3.1
B6
INVERT A
0
B5
INVERT B
0
B4
Reserved
0
B3
ATAPI3
1
B2
ATAPI2
0
B1
ATAPI1
0
B0
ATAPI0
1
Channel A Volume = Channel B Volume (VOLB=A) Bit 7
Function:
When set to 0 (default) the AOUTA and AOUTB volume levels are independently controlled by the A and
the B Channel Volume Control Bytes.
When set to 1 the volume on both AOUTA and AOUTB are determined by the A Channel Attenuation and
Volume Control Bytes, and the B Channel Bytes are ignored.
6.3.2
Invert Signal Polarity (Invert_A) Bit 6
Function:
When set to 1, this bit inverts the signal polarity of channel A.
When set to 0 (default), this function is disabled.
6.3.3
Invert Signal Polarity (Invert_B) Bit 5
Function:
When set to 1, this bit inverts the signal polarity of channel B.
When set to 0 (default), this function is disabled.
DS566F1
25
CS4351
6.3.4
ATAPI Channel Mixing and Muting (ATAPI3:0) Bits 3-0
Default = 1001 - AOUTA=aL, AOUTB=bR (Stereo)
Function:
The CS4351 implements the channel mixing functions of the ATAPI CD-ROM specification. Refer to
Table 8 and Figure 12 for additional information.
A Channel
Volume
Control
Left Channel
Audio Data
Σ
MUTE
AoutA
MUTE
AoutB
Σ
B Channel
Volume
Control
Right Channel
Audio Data
Figure 12. ATAPI Block Diagram
ATAPI3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
ATAPI2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
ATAPI1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
ATAPI0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
AOUTA
MUTE
MUTE
MUTE
MUTE
aR
aR
aR
aR
aL
aL
aL
aL
a[(L+R)/2]
a[(L+R)/2]
a[(L+R)/2]
a[(L+R)/2]
AOUTB
MUTE
bR
bL
b[(L+R)/2]
MUTE
bR
bL
b[(L+R)/2]
MUTE
bR
bL
b[(L+R)/2]
MUTE
bR
bL
b[(L+R)/2]
Table 8. ATAPI Decode
26
DS566F1
CS4351
6.4
Mute Control - Register 04h
7
AMUTE
1
6.4.1
6
Reserved
0
5
MUTEC A=B
0
4
MUTE_A
0
3
MUTE_B
0
2
Reserved
0
1
Reserved
0
0
Reserved
0
Auto-Mute (AMUTE) Bit 7
Function:
When set to 1 (default), the Digital-to-Analog converter output will mute following the reception of 8192
consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be
retained and the Mute Control pin will go active during the mute period. When set to 0, this function is
disabled
6.4.2
AMUTEC = BMUTEC (MUTEC A=B) Bit 5
Function:
When set to 0 (default), the AMUTEC and BMUTEC pins operate independently.
When set to 1, the individual controls for AMUTEC and BMUTEC are internally connected through an
AND gate prior to the output pins. Therefore, the external AMUTEC and BMUTEC pins will go active only
when the requirements for both AMUTEC and BMUTEC are valid.
6.4.3
A Channel Mute (MUTE_A) Bit 4
B Channel Mute (MUTE_B) Bit 3
Function:
When set to 1, the Digital-to-Analog converter output will mute. The quiescent voltage on the output will
be retained. The muting function is effected, similar to attenuation changes, by the Soft and Zero Cross
bits in the Volume and Mixing Control register. The corresponding MUTEC pin will go active following any
ramping due to the soft and zero cross function.
When set to 0 (default), this function is disabled.
6.5
Channel A Volume Control - Register 05h
Channel B Volume Control - Register 06h
7
VOL7
0
DS566F1
6
VOL6
0
5
VOL5
0
4
VOL4
0
3
VOL3
0
2
VOL2
0
1
VOL1
0
0
VOL0
0
27
CS4351
6.5.1
Digital Volume Control (VOL7:0) Bits 7-0
Default = 00h (0 dB)
Function:
The Digital Volume Control registers allow independent control of the signal levels in 1/2 dB increments
from 0 to -127.5 dB. Volume settings are decoded as shown in Table 9. The volume changes are implemented as dictated by the Soft and Zero Cross bits in the Power and Muting Control register.
The actual attenuation is determined by taking the decimal value of the volume register and multiplying
by 6.02/12.
Binary Code
Decimal Value
Volume Setting
00000000
00000001
00000110
11111111
0
1
6
255
0 dB
-0.5 dB
-3.0 dB
-127.5 dB
Table 9. Example Digital Volume Settings
6.6
Ramp and Filter Control - Register 07h
7
SZC1
1
6.6.1
6
SZC0
0
5
RMP_UP
1
4
RMP_DN
1
3
Reserved
0
2
FILT_SEL
0
1
Reserved
0
0
Reserved
1
Soft Ramp and Zero Cross Control (SZC1:0) Bits 7-6
Default = 10
SZC1 SZC0
Description
0
0
Immediate Change
0
1
Zero Cross
1
0
Soft Ramp
1
1
Soft Ramp on Zero Crossings
Function:
Immediate Change
When Immediate Change is selected all level changes will take effect immediately in one step.
Zero Cross
Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur
on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal
does not encounter a zero crossing. The zero cross function is independently monitored and implemented
for each channel.
Soft Ramp PCM
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.
28
DS566F1
CS4351
Soft Ramp and Zero Cross
Soft Ramp and Zero Cross Enable dictate that signal level changes, either by attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will
occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample
rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored
and implemented for each channel.
6.6.2
Soft Volume Ramp-Up After Error (RMP_UP) Bit 5
Function:
When set to 1 (default), an un-mute will be performed after executing a filter mode change, after a
LRCK/MCLK ratio change or error, and after changing the Functional Mode. This un-mute is affected, similar to attenuation changes, by the Soft and Zero Cross bits in the Volume and Mixing Control register.
When set to 0, an immediate un-mute is performed in these instances.
Note:
6.6.3
For best results, it is recommended this feature be used in conjunction with the RMP_DN bit.
Soft Ramp-Down Before Filter Mode Change (RMP_DN) Bit 4
Function:
When set to 1 (default), a mute will be performed prior to executing a filter mode change. This mute is
affected, similar to attenuation changes, by the Soft and Zero Cross bits in the Volume and Mixing Control
register.
When set to 0, an immediate mute is performed prior to executing a filter mode change.
Note:
6.6.4
For best results, it is recommended that this feature be used in conjunction with the RMP_UP bit.
Interpolation Filter Select (FILT_SEL) Bit 2
Function:
When set to 0 (default), the Interpolation Filter has a fast roll off.
When set to 1, the Interpolation Filter has a slow roll off.
The specifications for each filter can be found in the “Combined Interpolation & On-Chip Analog Filter Response” section on page 8, and response plots can be found in Figures 15 to 36.
6.7
Misc Control - Register 08h
7
PDN
1
DS566F1
6
CPEN
0
5
FREEZE
0
4
Reserved
0
3
Reserved
0
2
Reserved
0
1
Reserved
0
0
Reserved
0
29
CS4351
6.7.1
Power Down (PDN) Bit 7
Function:
When set to 1 (default), the entire device will enter a low-power state and the contents of the control registers will be retained. The power-down bit defaults to ‘1’ on power-up and must be disabled before normal
operation in Control Port mode can occur. This bit is ignored if CPEN is not set.
6.7.2
Control Port Enable (CPEN) Bit 6
Function:
This bit is set to 0 by default, allowing the device to power-up in Stand-Alone Mode. Control Port Mode
can be accessed by setting this bit to 1. This will allow operation of the device to be controlled by the registers and the pin definitions will conform to Control Port Mode.
6.7.3
Freeze Controls (Freeze) Bit 5
Function:
When set to 1, this function allows modifications to be made to the registers without the changes taking
effect until FREEZE is set back to 0. To make multiple changes in the Control Port registers take effect
simultaneously, enable the FREEZE bit, make all register changes, then disable the FREEZE bit.
When set to 0 (default), register changes take effect immediately.
30
DS566F1
CS4351
0
0
−20
−20
−40
−40
Amplitude (dB)
Amplitude (dB)
7. DIGITAL FILTER RESPONSE PLOTS
−60
−60
−80
−80
−100
−100
−120
0.4
0.5
0.6
0.7
0.8
Frequency(normalized to Fs)
0.9
−120
0.4
1
Figure 13. Single-Speed (fast) Stopband Rejection
0.42
0.44
0.46
0.48
0.5
0.52
Frequency(normalized to Fs)
0.54
0.56
0.58
0.6
Figure 14. Single-Speed (fast) Transition Band
0.02
0
−1
0.015
−2
0.01
0.005
−4
Amplitude (dB)
Amplitude (dB)
−3
−5
−6
0
−0.005
−7
−0.01
−8
−0.015
−9
−10
0.45
0.46
0.47
0.48
0.49
0.5
0.51
Frequency(normalized to Fs)
0.52
0.53
0.54
−0.02
0.55
0
0
−20
−20
−40
−40
−60
−80
−100
−100
0.5
0.6
0.7
0.8
Frequency(normalized to Fs)
0.9
1
Figure 17. Single-Speed (slow) Stopband Rejection
DS566F1
0.1
0.15
0.2
0.25
0.3
Frequency(normalized to Fs)
0.35
0.4
0.45
0.5
−60
−80
−120
0.4
0.05
Figure 16. Single-Speed (fast) Passband Ripple
Amplitude (dB)
Amplitude (dB)
Figure 15. Single-Speed (fast) Transition Band (detail)
0
−120
0.4
0.42
0.44
0.46
0.48
0.5
0.52
Frequency(normalized to Fs)
0.54
0.56
0.58
0.6
Figure 18. Single-Speed (slow) Transition Band
31
CS4351
0.02
0
−1
0.015
−2
0.01
0.005
−4
Amplitude (dB)
Amplitude (dB)
−3
−5
−6
0
−0.005
−7
−0.01
−8
−0.015
−9
−10
0.45
0.46
0.47
0.48
0.49
0.5
0.51
Frequency(normalized to Fs)
0.52
0.53
0.54
−0.02
0.55
Figure 19. Single-Speed (slow) Transition Band (detail)
0.1
0.15
0.2
0.25
0.3
Frequency(normalized to Fs)
0.35
0.4
0.45
0.5
0
20
20
40
40
Amplitude (dB)
Amplitude (dB)
0.05
Figure 20. Single-Speed (slow) Passband Ripple
0
60
60
80
80
100
100
120
0
120
0.4
0.5
0.6
0.7
0.8
Frequency(normalized to Fs)
0.9
1
Figure 21. Double-Speed (fast) Stopband Rejection
0.4
0.42
0.44
0.46
0.48
0.5
0.52
Frequency(normalized to Fs)
0.54
0.56
0.58
0.6
Figure 22. Double-Speed (fast) Transition Band
0
0.02
1
0.015
2
0.01
0.005
4
Amplitude (dB)
Amplitude (dB)
3
5
6
0
0.005
7
0.01
8
0.015
9
10
0.45
0.46
0.47
0.48
0.49
0.5
0.51
Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
Figure 23. Double-Speed (fast) Transition Band (detail)
32
0.02
0
0.05
0.1
0.15
0.2
0.25
0.3
Frequency(normalized to Fs)
0.35
0.4
0.45
0.5
Figure 24. Double-Speed (fast) Passband Ripple
DS566F1
CS4351
0
20
20
40
40
Amplitude (dB)
Amplitude (dB)
0
60
60
80
80
100
100
120
120
0.2
0.3
0.4
0.5
0.6
0.7
Frequency(normalized to Fs)
0.8
0.9
1
Figure 25. Double-Speed (slow) Stopband Rejection
0.2
0.3
0.4
0.5
0.6
Frequency(normalized to Fs)
0.7
0.8
Figure 26. Double-Speed (slow) Transition Band
0
0.02
1
0.015
2
0.01
0.005
4
Amplitude (dB)
Amplitude (dB)
3
5
6
0
0.005
7
0.01
8
0.015
9
10
0.45
0.46
0.47
0.48
0.49
0.5
0.51
Frequency(normalized to Fs)
0.52
0.53
0.54
0.02
0.55
Figure 27. Double-Speed (slow) Transition Band (detail)
40
40
Amplitude (dB)
Amplitude (dB)
20
60
0.15
0.2
Frequency(normalized to Fs)
0.25
0.3
0.35
60
80
80
100
100
120
0.3
0.4
0.5
0.6
0.7
Frequency(normalized to Fs)
0.8
0.9
1
Figure 29. Quad-Speed (fast) Stopband Rejection
DS566F1
0.1
0
20
0.2
0.05
Figure 28. Double-Speed (slow) Passband Ripple
0
120
0
0.2
0.3
0.4
0.5
0.6
Frequency(normalized to Fs)
0.7
0.8
Figure 30. Quad-Speed (fast) Transition Band
33
CS4351
0.2
0
1
0.15
2
0.1
3
Amplitude (dB)
Amplitude (dB)
0.05
4
5
6
0
0.05
7
0.1
8
0.15
9
10
0.45
0.2
0.46
0.47
0.48
0.49
0.5
0.51
Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
Figure 31. Quad-Speed (fast) Transition Band (detail)
0
0.05
0.1
0.15
Frequency(normalized to Fs)
0.2
0.25
Figure 32. Quad-Speed (fast) Passband Ripple
0
0
20
40
40
Amplitude (dB)
Amplitude (dB)
20
60
60
80
80
100
100
120
120
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Frequency(normalized to Fs)
0.8
0.9
1
Figure 33. Quad-Speed (slow) Stopband Rejection
0.1
0.2
0.3
0.4
0.5
0.6
Frequency(normalized to Fs)
0.7
0.8
0.9
Figure 34. Quad-Speed (slow) Transition Band
0.02
0
1
0.015
2
0.01
0.005
4
Amplitude (dB)
Amplitude (dB)
3
5
6
0
0.005
7
0.01
8
0.015
9
10
0.45
0.46
0.47
0.48
0.49
0.5
0.51
Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
Figure 35. Quad-Speed (slow) Transition Band (detail)
34
0.02
0
0.02
0.04
0.06
0.08
Frequency(normalized to Fs)
0.1
0.12
Figure 36. Quad-Speed (slow) Passband Ripple
DS566F1
CS4351
8. PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N)
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels.
Dynamic Range
The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the
specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made
with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full
scale. This technique ensures that the distortion components are below the noise level and do not effect the
measurement. This measurement technique has been accepted by the Audio Engineering Society, AES171991, and the Electronic Industries Association of Japan, EIAJ CP-307.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Error
The deviation from the nominal full scale analog output for a full scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
Intra-Channel Phase Deviation
The deviation from linear phase within a given channel.
Inter-Channel Phase Deviation
The difference in phase between channels.
DS566F1
35
CS4351
9. PACKAGE DIMENSIONS
20L TSSOP (4.4 mm BODY) PACKAGE DRAWING
N
D
E11
A2
E
A
∝
e
b2
A1
SIDE VIEW
END VIEW
L
SEATING
PLANE
1 2 3
TOP VIEW
INCHES
MILLIMETERS
NOTE
DIM
MIN
NOM
MAX
MIN
NOM
MAX
A
A1
A2
b
D
E
E1
e
L
µ
-0.002
0.03346
0.00748
0.252
0.248
0.169
-0.020
0°
-0.004
0.0354
0.0096
0.256
0.2519
0.1732
-0.024
4°
0.043
0.006
0.037
0.012
0.259
0.256
0.177
0.026
0.028
8°
-0.05
0.85
0.19
6.40
6.30
4.30
-0.50
0°
--0.90
0.245
6.50
6.40
4.40
-0.60
4°
1.10
0.15
0.95
0.30
6.60
6.50
4.50
0.65
0.70
8°
2,3
1
1
JEDEC #: MO-153
Controlling Dimension is Millimeters.
Notes:
1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side.
2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm
total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition.
3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
Parameters
Package Thermal Resistance
36
20L TSSOP
Symbol
Min
Typ
Max
Units
θJA
-
72
-
°C/Watt
DS566F1
CS4351
10.ORDERING INFORMATION
Product
CS4351
Description
192 kHz Stereo DAC
with 2 Vrms Line Out
CDB4351
Package Pb-Free
20-pin
TSSOP
CS4351 Evaluation Board
Grade
Temp Range Container
Commercial
-10° to +70° C
Automotive
-40° to +85° C
-
-
YES
-
Rail
Order #
CS4351-CZZ
Tape & Reel CS4351-CZZR
Rail
CS4351-DZZ
Tape & Reel CS4351-DZZR
-
CDB4351
11.REVISION HISTORY
Release
PP3
PP4
F1
Date
March 2005
Changes
Removed CS4351-CZ ordering option.
Added CS4351-DZZ ordering option.
Updated Tslrd spec on page 10.
Updated Tdh spec on page 12.
Updated VIL specification on page 13.
Updated legal text.
July 2005
Updated full-scale output specification on page 7.
Updated gain drift on page 7
Updated ordering information.
December 2005 Updated status to final
Updated legal text
Table 10. Revision History
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find one nearest you, go to www.cirrus.com/corporate/contacts/sales.cfm
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
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IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD
TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE
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IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER
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Cirrus Logic, Cirrus, the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be
trademarks or service marks of their respective owners.
SPI is a trademark of Motorola, Inc.
I²C is a registered trademark of Philips Semiconductor.
DS566F1
37