CDCE937 CDCEL937 www.ti.com SLAS564F – AUGUST 2007 – REVISED MARCH 2010 Programmable 3-PLL VCXO Clock Synthesizer With 1.8-V, 2.5-V and 3.3-V LVCMOS Outputs Check for Samples: CDCE937, CDCEL937 FEATURES • • 1 • Member of Programmable Clock Generator Family – CDCE913/CDCEL913: 1-PLL, 3 Outputs – CDCE925/CDCEL925: 2-PLL, 5 Outputs – CDCE937/CDCEL937: 3-PLL, 7 Outputs – CDCE949/CDCEL949: 4-PLL, 9 Outputs • In-System Programmability and EEPROM – Serial Programmable Volatile Register – Nonvolatile EEPROM to Store Customer Setting • Flexible Input Clocking Concept – External Crystal: 8 MHz to 32 MHz – On-Chip VCXO: Pull Range ±150 ppm – Single-Ended LVCMOS up to 160 MHz • Selectable Output Frequency up to 230 MHz • Low-Noise PLL Core – Integrated PLL Loop Filter Components – Low Period Jitter (Typ 60 ps) • Separate Output Supply Pins – CDCE937: 3.3 V and 2.5 V – CDCEL937: 1.8 V 234 VDD • • • 1.8-V Device Power Supply Flexible Clock Driver – Three User-Definable Control Inputs [S0/S1/S2] e.g., SSC Selection, Frequency Switching, Output Enable or Power Down – Generates Highly Accurate Clocks for Video, Audio, USB, IEEE1394, RFID, Bluetooth™, WLAN, Ethernet™, and GPS – Generates Common Clock Frequencies Used With TI DaVinci™, OMAP™, DSPs – Programmable SSC Modulation – Enables 0-PPM Clock Generation Wide Temperature Range –40° C to 85° C Packaged in TSSOP Development and Programming Kit for Easy PLL Design and Programming (TI Pro-Clock™) APPLICATIONS • D-TV, HD-TV, STB, IP-STB, DVD-Player, DVD-Recorder, Printer Vddout GND Crystal or Clock Input Vctr S2/S1/S0 or SDA/SCL VCXO LV CMOS Y1 LV CMOS Y2 LV CMOS Y3 LV CMOS Y4 LV CMOS Y5 LV CMOS Y6 LV CMOS Y7 XO LVCMOS 3 EEPROM PLL1 with SSC Programming and Control Register PLL2 with SSC Divider and Output Control Xin/Clk S0 Vdd Vctr GND Vddout Y4 Y5 GND Vddout 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Xout S1/SDA S2/SCL Y1 GND Y2 Y3 Vddout Y6 Y7 PLL3 with SSC 1 2 3 4 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DaVinci, OMAP, Pro-Clock are trademarks of Texas Instruments. Bluetooth is a trademark of Bluetooth SIG. Ethernet is a trademark of Xerox Corporattion. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2010, Texas Instruments Incorporated CDCE937 CDCEL937 SLAS564F – AUGUST 2007 – REVISED MARCH 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. DESCRIPTION The CDCE937 and CDCEL937 are modular PLL-based low cost, high-performance, programmable clock synthesizers, multipliers and dividers. They generate up to 7 output clocks from a single input frequency. Each output can be programmed in-system for any clock frequency up to 230 MHz, using up to three independent configurable PLLs. The CDCx937 has separate output supply pins, VDDOUT, which is 1.8 V for CDCEL937 and to 2.5 V to 3.3 V for CDCE937. The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 to 20 pF. Additionally, an on-chip VCXO is selectable which allows synchronization of the output frequency to an external control signal, that is, PWM signal. The deep M/N divider ratio allows the generation of zero ppm audio/video, networking (WLAN, BlueTooth, Ethernet, GPS) or Interface (USB, IEEE1394, Memory Stick) clocks from a reference input frequency such as 27 MHz. All PLLs supports SSC (Spread-Spectrum Clocking). SSC can be Center-Spread or Down-Spread clocking which is a common technique to reduce electro-magnetic interference (EMI). Based on the PLL frequency and the divider settings, the internal loop filter components are automatically adjusted to achieve high stability and optimized jitter transfer characteristic of each PLL. The device supports non-volatile EEPROM programming for ease-customized application. It is preset to a factory default configuration (see the Default Device Configuration section). It can be reprogrammed to a different application configuration before PCB assembly, or reprogrammed by in-system programming. All device settings are programmable through SDA/SCL bus, a 2-wire serial interface. Three programmable control inputs, S0, S1 and S2, can be used to control various aspects of operation including frequency selection changing the SSC parameters to lower EMI, PLL bypass, power down, and choosing between low level or 3-state for output-disable function. The CDCx937 operates in 1.8 V environment. It is characterized for operation from –40°C to 85°C. Terminal Functions for CDCE937, CDCEL937 2 NAME PIN TSSOP24 TYPE Y1, Y2, ... Y7 17, 15, 14, 7, 8, 12, 11 O LVCMOS outputs Xin/CLK 1 I Crystal Oscillator Input or LVCMOS Clock Input (selectable via SDA/SCL bus) Xout 20 O Crystal Oscillator Output (leave open or pull-up (~500k) when not used) VCtrl 4 I VCXO Control Voltage (leave open or pull-up (~500k) when not used) VDD 3 Power Vddout 6, 10, 13 Power GND 5, 9, 16 Ground S0 2 I SDA/S1 19 I/O or I SCL/S2 18 I Submit Documentation Feedback DESCRIPTION 1.8V Power Supply for the device CDCEL937: 1.8V Supply for all Outputs CDCE937: 3.3V or 2.5V Supply for all Outputs Ground User Programmable Control Input S0; LVCMOS inputs; Internal Pull-up 500k SDA: Bi-Directional Serial Data Input/Output (default configuration). LVCMOS; Internal Pull-up 500k; or S1: User Programmable Control Input; LVCMOS inputs; Internal Pull-up 500k SCL: Serial Clock Input(default configuration), LVCMOS; Internal Pull-up 500k; or S2: User Programmable Control Input; LVCMOS inputs; Internal Pull-up 500k Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): CDCE937 CDCEL937 CDCE937 CDCEL937 www.ti.com SLAS564F – AUGUST 2007 – REVISED MARCH 2010 FUNCTIONAL BLOCK DIAGRAM VDD Vddout GND Input Clock LV CMOS Y1 M2 LV CMOS Y2 M3 LV CMOS Y3 M4 LV CMOS Y4 M5 LV CMOS Y5 M6 Xin/CLK LV CMOS Y6 M7 Pdiv1 M1 Vctr LV CMOS Y7 10-Bit VCXO XO EEPROM S0 S1/SDA S2/SCL Programming and SDA/SCL Register 7-Bit Pdiv3 PLL Bypass 7-Bit PLL 2 Pdiv4 with SSC 7-Bit MUX2 Xout Pdiv2 MUX1 PLL1 with SSC LVCMOS Pdiv5 7-Bit PLL Bypass Pdiv6 with SSC MUX3 PLL 3 7-Bit Pdiv7 PLL Bypass 7-Bit ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VDD Supply voltage range (2) (3) VI Input voltage range VO Output voltage range (2) II Input current (VI < 0, VI > VDD) IO Tstg TJ Maximum junction temperature (1) (2) (3) VALUE UNIT –0.5 to 2.5 V –0.5 to VDD + 0.5 V –0.5 to Vddout + 0.5 V 20 mA Continuous output current 50 mA Storage temperature range –65 to 150 °C 125 °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed. SDA and SCL can go up to 3.6V as stated in the Recommended Operating Conditions table. Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): CDCE937 CDCEL937 Submit Documentation Feedback 3 CDCE937 CDCEL937 SLAS564F – AUGUST 2007 – REVISED MARCH 2010 www.ti.com PACKAGE THERMAL RESISTANCE for TSSOP (PW) PACKAGE (1) over operating free-air temperature range (unless otherwise noted) PARAMETER TJA AIRFLOW (lfm) TSSOP20 °C/W Thermal Resistance Junction to Ambient 0 89 150 75 200 74 250 74 500 69 31 TJC Thermal Resistance Junction to Case — TJB Thermal Resistance Junction to Board — 55 RqJT Thermal Resistance Junction to Top — 0.8 RqJB Thermal Resistance Junction to Bottom — 49 (1) The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board). RECOMMENDED OPERATING CONDITIONS VDD VO MIN NOM MAX Device supply voltage 1.7 1.8 1.9 Output Yx supply voltage for CDCE937, Vddout 2.3 Output Yx supply voltage for CDCEL937, Vddout 1.7 VIL Low-level input voltage LVCMOS VIH High-level input voltage LVCMOS VI(thresh) Input voltage threshold LVCMOS VIS VI(CLK) IOH /IOL 1.9 V 0.3 VDD V 0.7 VDD V 0.5 VDD V 0 1.9 Input voltage range S1, S2, SDA, SCL; VI(thresh) = 0.5 VDD 0 3.6 Input voltage range CLK 0 1.9 Output current (Vddout = 3.3 V) ±12 Output current (Vddout = 2.5 V) ±10 Output current (Vddout = 1.8 V) ±8 Output load LVCMOS TA Operating free-air temperature V 3.6 Input voltage range S0 CL UNIT –40 V V mA 10 pF 85 °C RECOMMENDED CRYSTAL/VCXO SPECIFICATIONS (1) fXtal Crystal input frequency range (fundamental mode) ESR Effective series resistance Pulling range (0 V ≤ Vctrl ≤ 1.8 V) fPR (2) NOM MAX UNIT 8 27 32 MHz 100 Ω ±120 Frequency control voltage, Vctrl ±150 0 C0/C1 Pullability ratio CL On-chip load capacitance at Xin and Xout (1) (2) MIN ppm VDD V 220 0 20 pF For more information about VCXO configuration, and crystal recommendation, see application report (SCAA085). Pulling range depends on crystal-type, on-chip crystal load capacitance and PCB stray capacitance; pulling range of min ±120 ppm applies for crystal listed in the application report (SCAA085). EEPROM SPECIFICATION MIN EEcyc Programming cycles of EEPROM EEret Data retention 4 Submit Documentation Feedback TYP MAX UNIT 1000 cycles 10 years Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): CDCE937 CDCEL937 CDCE937 CDCEL937 www.ti.com SLAS564F – AUGUST 2007 – REVISED MARCH 2010 TIMING REQUIREMENTS over recommended ranges of supply voltage, load, and operating free-air temperature MIN NOM MAX UNIT CLK_IN REQUIREMENTS PLL bypass mode 0 160 PLL mode 8 160 40% 60% fCLK LVCMOS clock input frequency tr / tf Rise and fall time CLK signal (20% to 80%) dutyCLK Duty cycle CLK at VDD/2 3 STANDARD MODE FAST MODE MHz ns UNIT MIN MAX MIN MAX 0 100 0 400 SDA/SCL TIMING REQUIREMENTS (see Figure 12) fSCL SCL clock frequency tsu(START) START setup time (SCL high before SDA low) th(START) START hold time (SCL low after SDA low) tw(SCLL) SCL low-pulse duration tw(SCLH) SCL high-pulse duration 4 th(SDA) SDA hold time (SDA valid after SCL low) 0 tsu(SDA) SDA setup time tr SCL/SDA input rise time 1000 300 tf SCL/SDA input fall time 300 300 tsu(STOP) STOP setup time tBUS Bus free time between a STOP and START condition 4.7 0.6 ms 4 0.6 ms 4.7 1.3 ms 0.6 3.45 250 Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): CDCE937 CDCEL937 kHz 0 ms 0.9 100 ms ns ns ns 4 0.6 ms 4.7 1.3 ms Submit Documentation Feedback 5 CDCE937 CDCEL937 SLAS564F – AUGUST 2007 – REVISED MARCH 2010 www.ti.com DEVICE CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT OVERALL PARAMETER IDD Supply current (see Figure 3) All outputs off, f(CLK) = 27 MHz, All PLLS on f(VCO) = 135 MHz Per PLL IDDOUT Output supply current (see Figure 4 and Figure 5 No load, all outputs on, fOUT = 27 MHz IDD(PD) Power-down current. Every circuit powered down except SDA/SCL fIN = 0 MHz, V(PUC) Supply voltage Vdd threshold for power-up control circuit f(VCO) VCO frequency range of PLL fOUT LVCMOS output frequency 29 mA 9 CDCE937, VDDOUT = 3.3 V 3.1 CDCEL937, VDDOUT = 1.8 V 1.5 VDD = 1.9 V 50 mA mA 0.85 1.45 V 80 230 MHz Vddout = 3.3 V 230 Vddout = 1.8 V 230 MHz LVCMOS PARAMETER VIK LVCMOS input voltage VDD = 1.7 V; II = –18 mA II LVCMOS Input current VI = 0 V or VDD; VDD = 1.9 V IIH LVCMOS Input current for S0/S1/S2 IIL LVCMOS Input current for S0/S1/S2 Input capacitance at Xin/Clk VI(Clk) = 0 V or VDD 6 Input capacitance at Xout VI(Xout) = 0 V or VDD 2 Input capacitance at S0/S1/S2 VIS = 0 V or VDD 3 CI –1.2 V ±5 mA VI = VDD; VDD = 1.9 V 5 mA VI = 0 V; VDD = 1.9 V –4 mA pF CDCE937 - LVCMOS PARAMETER FOR Vddout = 3.3 V – MODE VOH LVCMOS high-level output voltage VOL LVCMOS low-level output voltage tPLH, tPHL Propagation delay tr/tf Rise and fall time (2) (3) tjit(cc) Cycle-to-cycle jitter tjit(per) Peak-to-peak period jitter (3) tsk(o) Output skew odc Output duty cycle (1) (2) (3) (4) (5) 6 (4) , See Table 2 (5) Vddout = 3 V, IOH = –0.1 mA 2.9 Vddout = 3 V, IOH = –8 mA 2.4 Vddout = 3 V, IOH = –12 mA 2.2 V Vddout = 3 V, IOL = 0.1 mA 0.1 Vddout = 3 V, IOL = 8 mA 0.5 Vddout = 3 V, IOL = 12 mA 0.8 All PLL bypass 3.2 Vddout= 3.3 V (20%–80%) 0.6 1 PLL switching, Y2-to-Y3 60 90 3 PLL switching, Y2-to-Y7 100 150 1 PLL switching, Y2-to-Y3 70 100 3 PLL switching, Y2-to-Y7 120 180 ns ns fOUT = 50 MHz; Y1-to-Y3 60 fOUT = 50 MHz; Y2-to-Y5 160 fVCO = 100 MHz; Pdiv = 1 45% V ps ps ps 55% All typical values are at respective nominal VDD. 10000 cycles. Jitter depends on configuration. Data is taken under the following conditions: 1-PLL : fIN = 27MHz, Y2/3 = 27 MHz, (measured at Y2), 3-PLL: fIN = 27 MHz, Y2/3 = 27 MHz (measured at Y2), Y4/5 = 16.384 MHz, Y6/7 = 74.25 MHz The tsk(o) specification is only valid for equal loading of each bank of outputs, and outputs are generated from the same divider; data taking on rising edge (tr). odc depends on output rise and fall time (tr/tf). Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): CDCE937 CDCEL937 CDCE937 CDCEL937 www.ti.com SLAS564F – AUGUST 2007 – REVISED MARCH 2010 DEVICE CHARACTERISTICS (continued) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT CDCE937 – LVCMOS PARAMETER for Vddout = 2.5 V – Mode VOH VOL LVCMOS high-level output voltage LVCMOS low-level output voltage Vddout = 2.3 V, IOH = –0.1 mA 2.2 Vddout = 2.3 V, IOH = –6 mA 1.7 Vddout = 2.3 V, IOH = –10 mA 1.6 V Vddout = 2.3 V, IOL = 0.1 mA 0.1 Vddout = 2.3 V, IOL = 6 mA 0.5 Vddout = 2.3 V, IOL = 10 mA 0.7 tPLH, tPHL Propagation delay All PLL bypass 3.4 tr/tf Rise and fall time Vddout = 2.5 V (20%–80%) 0.8 1 PLL switching, Y2-to-Y3 60 90 3 PLL switching, Y2-to-Y7 100 150 1 PLL switching, Y2-to-Y3 70 100 3 PLL switching, Y2-to-Y7 120 180 tjit(cc) Cycle-to-cycle jitter (6) (7) tjit(per) Peak-to-peak period jitter (8) tsk(o) Output skew (8), See Table 2 odc Output duty cycle (9) ns ns fOUT = 50 MHz; Y1-to-Y3 60 fOUT = 50 MHz; Y2-to-Y5 160 f(VCO) = 100 MHz; Pdiv = 1 45% V ps ps ps 55% CDCEL937 — LVCMOS PARAMETER for Vddout = 1.8 V – Mode VOH VOL LVCMOS high-level output voltage LVCMOS low-level output voltage Vddout = 1.7 V, IOH = –0.1 mA 1.6 Vddout = 1.7 V, IOH = –4 mA 1.4 Vddout = 1.7 V, IOH = –8 mA 1.1 V Vddout = 1.7 V, IOL = 0.1 mA 0.1 Vddout = 1.7 V, IOL = 4 mA 0.3 Vddout = 1.7 V, IOL = 8 mA 0.6 tPLH, tPHL Propagation delay All PLL bypass 2.6 tr/tf Rise and fall time Vddout= 1.8 V (20%–80%) 0.7 1 PLL switching, Y2-to-Y3 70 120 3 PLL switching, Y2-to-Y7 100 150 1 PLL switching, Y2-to-Y3 90 140 3 PLL switching, Y2-to-Y7 120 190 tjit(cc) Cycle-to-cycle jitter (6) (7) tjit(per) Peak-to-peak period jitter (7) tsk(o) Output skew (8), See Table 2 odc Output duty cycle (9) ns ns fOUT = 50 MHz; Y1-to-Y3 60 fOUT = 50 MHz; Y2-to-Y5 160 f(VCO) = 100 MHz; Pdiv = 1 45% V ps ps ps 55% SDA/SCL PARAMETER VIK SCL and SDA input clamp voltage VDD = 1.7 V; II = –18 mA –1.2 V IIH SCL and SDA input current VI = VDD; VDD = 1.9 V ±10 mA VIH SDA/SCL input high voltage (10) VIL SDA/SCL input low voltage (10) VOL SDA low-level output voltage IOL = 3 mA, VDD = 1.7 V CI SCL/SDA Input capacitance VI = 0 V or VDD 0.7 VDD V 0.3 VDD 3 V 0.2 VDD V 10 pF (6) (7) 10000 cycles. Jitter depends on configuration. Data is taken under the following conditions: 1-PLL : fIN = 27MHz, Y2/3 = 27 MHz, (measured at Y2), 3-PLL: fIN = 27 MHz, Y2/3 = 27 MHz (measured at Y2), Y4/5 = 16.384 MHz, Y6/7 = 74.25 MHz (8) The tsk(o) specification is only valid for equal loading of each bank of outputs, and outputs are generated from the same divider; data taking on rising edge (tr). (9) odc depends on output rise and fall time (tr/tf). (10) SDA and SCL pins are 3.3 V tolerant. Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): CDCE937 CDCEL937 Submit Documentation Feedback 7 CDCE937 CDCEL937 SLAS564F – AUGUST 2007 – REVISED MARCH 2010 www.ti.com PARAMETER MEASUREMENT INFORMATION CDCE937 CDCEL937 1 kW LVCMOS 1 kW 10 pF Figure 1. Test Load CDCE937 CDCEL937 LVCMOS Typical Driver Impedance ~ 32 W LVCMOS Series Termination ~ 18 W Line Impedance Zo = 50 W Figure 2. Test Load for 50-Ω Board Environment 8 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): CDCE937 CDCEL937 CDCE937 CDCEL937 www.ti.com SLAS564F – AUGUST 2007 – REVISED MARCH 2010 TYPICAL CHARACTERISTICS CDCE937, CDCEL937 SUPPLY CURRENT vs PLL FREQUENCY CDCE937 OUTPUT CURRENT vs OUTPUT FREQUENCY 30 80 VDD = 1.8 V 70 25 7 Outputs on 60 20 2 PLL on 50 IDDOUT - mA IDD - Supply Current - mA 3 PLL on VDD = 1.8 V, VDDOUT = 3.3 V, No Load 40 30 1 PLL on 5 Outputs on 15 1 Output on 10 3 Outputs on 20 all PLL off 5 10 0 10 60 110 160 fVCO - Frequency - MHz All Outputs off 0 10 210 30 50 70 90 110 130 150 170 190 210 230 fOUT - Output Frequency - MHz Figure 3. Figure 4. CDCEL937 OUTPUT CURRENT vs OUTPUT FREQUENCY 12 VDD = 1.8 V, VDDOUT = 1.8 V, No Load 10 7 Outputs IDDOUT - mA 8 5 Outputs on 6 3 Output on 4 1 Output on 2 all Outputs 0 10 30 50 70 90 110 130 150 170 190 210 230 fOUT - Output Frequency - MHz Figure 5. Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): CDCE937 CDCEL937 Submit Documentation Feedback 9 CDCE937 CDCEL937 SLAS564F – AUGUST 2007 – REVISED MARCH 2010 www.ti.com APPLICATION INFORMATION CONTROL TERMINAL SETTING The CDCE937/CDCEL937 has three user-definable control terminals (S0, S1, and S2) which allow external control of device settings. They can be programmed to any of the following setting: • Spread spectrum clocking selection → spread type and spread amount selection • Frequency selection → switching between any of two user-defined frequencies • Output state selection → output configuration and power down control The user can predefine up to eight different control settings. Table 1 and Table 2 explain these settings. Table 1. Control Terminal Definition External Control Bits Control Function PLL1 Setting PLL Frequency Selection PLL2 Setting Output Y2/Y3 Selection SSC Selection PLL Frequency Selection SSC Selection PLL3 Setting Output Y4/Y5 Selection PLL Frequency Selection SSC Selection Y1 Setting Output Y6/Y7 Selection Output Y1 and Power-Down Selection Table 2. PLLx Setting (can be selected for each PLL individual) (1) SSC Selection (Center/Down) Center Down 0 SSCx [3-bits] 0 0 0% (off) 0% (off) 0 0 1 ±0.25% –0.25% 0 1 0 ±0.5% –0.5% 0 1 1 ±0.75% –0.75% 1 0 0 ±1.0% –1.0% 1 0 1 ±1.25% –1.25% 1 1 0 ±1.5% –1.5% 1 1 1 ±2.0% –2.0% FREQUENCY SELECTION (2) FSx FUNCTION 0 Frequency0 1 Frequency1 OUTPUT SELECTION (1) (2) (3) (3) (Y2 ... Y7) YxYx FUNCTION 0 State0 1 State1 Center/Down-Spread, Frequency0/1 and State0/1 are user-definable in PLLx Configuration Register; Frequency0 and Frequency1 can be any frequency within the specified fVCO range. State0/1 selection is valid for both outputs of the corresponding PLL module and can be power down, 3-state, low or active Table 3. Y1 Setting (1) Y1 SELECTION (1) 10 Y1 FUNCTION 0 State 0 1 State 1 State0 and State1 are user definable in Generic Configuration Register and can be power down, 3-state, low, or active. Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): CDCE937 CDCEL937 CDCE937 CDCEL937 www.ti.com SLAS564F – AUGUST 2007 – REVISED MARCH 2010 S1/SDA and S2/SCL pins of the CDCE937/CDCEL937 are dual function pins. In default configuration they are defined as SDA/SCL for the serial interface. They can be programmed as control-pins (S1/S2) by setting the relevant bits in the EEPROM. Note that the changes to the Control register (Bit [6] of Byte [02]) have no effect until they are written into the EEPROM. Once they are set as control pins, the serial programming interface is no longer available. However, if VDDOUT is forced to GND, the two control-pins, S1 and S2, temporally act as serial programming pins (SDA/SCL). S0 is not a multi-use pin, it is a control pin only. DEFAULT DEVICE SETTING The internal EEPROM of CDCE937/CDCEL937 is preconfigured as shown in Figure 6. (The input frequency is passed through to the output as a default). This allows the device to operate in default mode without the extra production step of program it. The default setting appears after power is supplied or after power-down/up sequence until it is re-programmed by the user to a different application configuration. A new register setting is programmed via the serial SDA/SCL Interface. VDD Vddout GND SCL M2 Programming Bus LV CMOS Y3 = 27 MHz LV CMOS Y4 = 27 MHz LV CMOS Y5 = 27 MHz LV CMOS Y6 = 27 MHz LV CMOS Y7 = 27 MHz MUX1 PLL 2 Pdiv4 = 1 power down MUX2 SDA M3 Programming and SDA/SCA Register S0 “0” = outputs 3-State Pdiv3 = 1 PLL Bypass EEPROM M4 Pdiv2 = 1 Xout “1” = outputs enabled Y2 = 27 MHz M5 PLL1 LV CMOS Pdiv1 =1 X-tal power down Y1 = 27MHz M6 27 MHz Crystal LV CMOS M7 M1 Input Clock Xin Pdiv5 = 1 PLL Bypass PLL3 Pdiv6 = 1 MUX3 power down Pdiv7 = 1 PLL Bypass Figure 6. Default Device Setting Table 4 shows the factory default setting for the Control Terminal Register (external control pins). In normal operation, all 8 register settings are available, but in the default configuration only the first two settings (0 and 1) can be selected with S0, as S1 and S2 configured as programming pins in default mode. Table 4. Factory Default Setting for Control Terminal Register (1) Y1 Output Selection External Control Pins PLL1 Settings Frequency Selection SSC Selection PLL2 Settings Output Selection Frequenc y Selection SSC Selection PLL3 Settings Output Selection Frequenc y Selection SSC Selection Output Selection S2 S1 S0 Y1 FS1 SSC1 Y2Y3 FS2 SSC2 Y4Y5 FS3 SSC3 Y6Y7 SCL (I2C) SDA (I2C) 0 3-state fVCO1_0 off 3-state fVCO2_0 off 3-state fVCO1_0 off 3-state SCL (I2C) SDA (I2C) 1 enabled fVCO1_0 off enabled fVCO2_0 off enabled fVCO1_0 off enabled (1) In default mode or when programmed respectively, S1 and S2 act as serial programming interface, SDA/SCL. They do not have any control-pin function but they are internally interpreted as if S1=0 and S2=0. S0, however, is a control-pin which in the default mode switches all outputs ON or OFF (as previously predefined). Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): CDCE937 CDCEL937 Submit Documentation Feedback 11 CDCE937 CDCEL937 SLAS564F – AUGUST 2007 – REVISED MARCH 2010 www.ti.com SDA/SCL SERIAL INTERFACE The CDCE937/CDCEL937 operates as a slave device of the 2-wire serial SDA/SCL bus, compatible with the popular SMBus or I2C specification. It operates in the standard-mode transfer (up to 100kbit/s) and fast-mode transfer (up to 400kbit/s) and supports 7-bit addressing. The S1/SDA and S2/SCL pins of the CDC9xx are dual function pins. In the default configuration they are used as SDA/SCL serial programming interface. They can be re-programmed as general purpose control pins, S1 and S2, by changing the corresponding EEPROM setting, Byte 02, Bit [6]. DATA PROTOCOL The device supports Byte Write and Byte Read and Block Write and Block Read operations. For Byte Write/Read operations, the system controller can individually access addressed bytes. For Block Write/Read operations, the bytes are accessed in sequential order from lowest to highest byte (with most significant bit first) with the ability to stop after any complete byte has been transferred. The numbers of Bytes read-out are defined by Byte Count in the Generic Configuration Register. At Block Read instruction all bytes defined in the Byte Count has to be readout to correctly finish the read cycle. Once a byte has been sent, it is written into the internal register and is effective immediately. This applies to each transferred byte independent of whether this is a Byte Write or a Block Write sequence. If the EEPROM Write Cycle is initiated, the internal SDA register contents are written into the EEPROM. During this write cycle, data is not accepted at the SDA/SCL bus until the write cycle is completed. However, data can be read during the programming sequence (Byte Read or Block Read). The programming status can be monitored by reading EEPIP, Byte 01–Bit [6]. The offset of the indexed byte is encoded in the command code, as described in Table 5. Table 5. Slave Receiver Address (7 Bits) A6 A5 A4 A3 A2 A1 (1) A0 (1) R/W CDCE913/CDCEL913 1 1 0 0 1 0 1 1/0 CDCE925/CDCEL925 1 1 0 0 1 0 0 1/0 CDCE937/CDCEL937 1 1 0 1 1 0 1 1/0 CDCE949/CDCEL949 1 1 0 1 1 0 0 1/0 DEVICE (1) Address bits A0 and A1 are programmable via the SDA/SCL bus (Byte 01, Bit [1:0]). This allows addressing up to 4 devices connected to the same SDA/SCL bus. The least-significant bit of the address byte designates a write or read operation. COMMAND CODE DEFINITION Table 6. Command Code Definition BIT DESCRIPTION 0 = Block Read or Block Write operation 1 = Byte Read or Byte Write operation 7 (6:0) 12 Byte Offset for Byte Read, Block Read, Byte Write and Block Write operation. Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): CDCE937 CDCEL937 CDCE937 CDCEL937 www.ti.com SLAS564F – AUGUST 2007 – REVISED MARCH 2010 Generic Programming Sequence 1 S 7 Slave Address 1 R/W MSB LSB S Start Condition Sr Repeated Start Condition 1 A 8 Data Byte 1 A MSB 1 P LSB 1 = Read (Rd) From CDCE9xx Device; 0 = Write (Wr) to CDCE9xxx R/W A Acknowledge (ACK = 0 and NACK =1) P Stop Condition Master-to-Slave Transmission Slave-to-Master Transmission Figure 7. Generic Programming Sequence Byte Write Programming Sequence 1 S 7 Slave Address 1 Wr 1 A 8 CommandCode 1 A 8 Data Byte 1 A 1 P 7 Slave Address 1 Rd 1 A 1 A 1 P Figure 8. Byte Write Protocol Byte Read Programming Sequence 1 S 7 Slave Address 1 Wr 1 A 8 Data Byte 1 A 1 P 8 CommandCode 1 A 1 S Figure 9. Byte Read Protocol Block Write Programming Sequence 1 S (1) 7 Slave Address 1 Wr 8 Data Byte 0 1 A 1 A 8 CommandCode 8 Data Byte 1 1 A 1 A 8 Byte Count = N 8 Data Byte N-1 … 1 A Data byte 0 bits [7:0] is reserved for Revision Code and Vendor Identification. Also, it is used for internal test purpose and should not be overwritten. Figure 10. Block Write Protocol Block Read Programming Sequence 1 S 7 Slave Address 1 Wr 8 Byte Count N 1 A 1 A 8 CommandCode 8 Data Byte 0 1 A 1 A 1 Sr … 7 Slave Address 1 Rd 1 A 8 Data Byte N-1 1 A 1 P Figure 11. Block Read Protocol Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): CDCE937 CDCEL937 Submit Documentation Feedback 13 CDCE937 CDCEL937 SLAS564F – AUGUST 2007 – REVISED MARCH 2010 www.ti.com Timing Diagram for the SDA/SCL Serial Control Interface P S Bit 7 (MSB) tw(SCLH) tw(SCLL) Bit 6 tr Bit 0 (LSB) A P tf VIH SCL VIL tsu(START) th(START) tsu(SDA) th(SDA) t(BUS) tsu(STOP) tf tr VIH SDA VIL Figure 12. Timing Diagram for SDA/SCL Serial Control Interface SDA/SCL HARDWARE INTERFACE Figure 13 shows how the CDCE937/CDCEL937 clock synthesizer is connected to the SDA/SCL serial interface bus. Multiple devices can be connected to the bus but the speed may need to be reduced (400 kHz is the maximum) if many devices are connected. Note that the pullup resistors (RP) depends on the supply voltage, bus capacitance, and number of connected devices. The recommended pullup value is 4.7 kΩ. It must meet the minimum sink current of 3 mA at VOLmax = 0.4 V for the output stages (for more details see SMBus or I2C Bus specification). CDCE937 CDCEL937 RP RP Master Slave SDA SCL CBUS CBUS Figure 13. SDA / SCL Hardware Interface 14 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): CDCE937 CDCEL937 CDCE937 CDCEL937 www.ti.com SLAS564F – AUGUST 2007 – REVISED MARCH 2010 SDA/SCL CONFIGURATION REGISTERS The clock input, control pins, PLLs, and output stages are user configurable. The following tables and explanations describe the programmable functions of the CDCE937/CDCEL937. All settings can be manually written into the device via the SDA/SCL bus or easily programmed by using the TI Pro-Clock™ software. TI Pro-Clock™ software allows the user to quickly make all settings and automatically calculates the values for optimized performance at lowest jitter. Table 7. SDA/SCL Registers Address Offset Register Description Table 00h Generic Configuration Register Table 9 10h PLL1 Configuration Register Table 10 20h PLL2 Configuration Register Table 11 30h PLL3 Configuration Register Table 12 The grey-highlighted bits, described in the Configuration Registers tables in the following pages, belong to the Control Terminal Register. The user can predefine up to eight different control settings. These settings then can be selected by the external control pins, S0, S1, and S2 (see the Control Terminal Configuration section). Table 8. Configuration Register, External Control Terminals Y1 External Control Pins S2 S1 Output Selection PLL1 Settings Freq. Selection SSC Selection PLL2 Settings Output Selection Freq. Selection SSC Selection PLL3 Settings Output Selection Freq. Selection SSC Selection Output Selection S0 Y1 FS1 SSC1 Y2Y3 FS2 SSC2 Y4Y5 FS3 SSC3 Y6Y7 0 0 0 0 Y1_0 FS1_0 SSC1_0 Y2Y3_0 FS2_0 SSC2_0 Y4Y5_0 FS3_0 SSC3_0 Y6Y7_0 1 0 0 1 Y1_1 FS1_1 SSC1_1 Y2Y3_1 FS2_1 SSC2_1 Y4Y5_1 FS3_1 SSC3_1 Y6Y7_1 2 0 1 0 Y1_2 FS1_2 SSC1_2 Y2Y3_2 FS2_2 SSC2_2 Y4Y5_2 FS3_2 SSC3_2 Y6Y7_2 3 0 1 1 Y1_3 FS1_3 SSC1_3 Y2Y3_3 FS2_3 SSC2_3 Y4Y5_3 FS3_3 SSC3_3 Y6Y7_3 4 1 0 0 Y1_4 FS1_4 SSC1_4 Y2Y3_4 FS2_4 SSC2_4 Y4Y5_4 FS3_4 SSC3_4 Y6Y7_4 5 1 0 1 Y1_5 FS1_5 SSC1_5 Y2Y3_5 FS2_5 SSC2_5 Y4Y5_5 FS3_5 SSC3_5 Y6Y7_5 6 1 1 0 Y1_6 FS1_6 SSC1_6 Y2Y3_6 FS2_6 SSC2_6 Y4Y5_6 FS3_6 SSC3_6 Y6Y7_6 7 1 1 1 Y1_7 FS1_7 SSC1_7 Y2Y3_7 FS2_7 SSC2_7 Y4Y5_7 FS3_7 SSC3_7 Y6Y7_7 04h 13h 10h–12h 15h 23h 20h–22h 25h 33h 30h–32h 35h Address Offset (1) (1) Address Offset refers to the byte address in the Configuration Register in the following pages. Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): CDCE937 CDCEL937 Submit Documentation Feedback 15 CDCE937 CDCEL937 SLAS564F – AUGUST 2007 – REVISED MARCH 2010 www.ti.com Table 9. Generic Configuration Register Offset 00h (1) Bit (2) Acronym Default (3) Description 7 E_EL Xb Device identification (read-only): 1 is CDCE937 (3.3 V), 0 is CDCEL937 (1.8 V) 6:4 RID Xb Revision Identification Number (read only) 3:0 VID 1h Vendor Identification Number (read only) 7 – 0b Reserved – always write 0 6 EEPIP 0b 5 EELOCK 0b 4 PWDN 0b 01h EEPROM Programming Status: (4) (read only) 0 – EEPROM programming is completed 1 – EEPROM is in programming mode Permanently Lock EEPROM Data (5) 0 – EEPROM is not locked 1 – EEPROM will be permanently locked Device Power Down (overwrites S0/S1/S2 setting; configuration register settings are unchanged) Note: PWDN cannot be set to 1 in the EEPROM. 0 – device active (PLL1 and all outputs are enabled) 1 – device power down (PLL1 in power down and all outputs in 3-state) 3:2 INCLK 00b Input clock selection: 1:0 SLAVE_ADR 01b Programmable Address Bits A0 and A1 of the Slave Receiver Address 00 – Xtal 01 – VCXO 10 – LVCMOS 7 M1 1b Clock source selection for output Y1: 0 – input clock 11 – reserved 1 – PLL1 clock Operation mode selection for pin 18/19 (6) 6 SPICON 0b 5:4 Y1_ST1 11b 3:2 Y1_ST0 01b 1:0 Pdiv1 [9:8] 7:0 Pdiv1 [7:0] 7 Y1_7 0b 6 Y1_6 0b 5 Y1_5 0b 4 Y1_4 0b 3 Y1_3 0b 2 Y1_2 0b 1 Y1_1 1b 0 Y1_0 0b 0 – serial programming interface SDA (pin 19) and SCL (pin 18) 1 – control pins S1 (pin 19) and S2 (pin 18) 02h Y1-State0/1 Definition 00 – device power down (all PLLs in power down and all outputs in 3-State) 01 – Y1 disabled to 3-state 10-Bit Y1-Output-Divider Pdiv1: 0 – divider reset and stand-by 1-to-1023 – divider value 001h 03h 10 – Y1 disabled to low 11 – Y1 enabled Y1_ST0/Y1_ST1 State Selection (7) 0 – State0 (predefined by Y1_ST0) 1 – State1 (predefined by Y1_ST1) 04h 00h → 0 pF 01h → 1 pF 02h → 2 pF : 14h-to-1Fh → 20 pF Crystal Load Capacitor Selection (8) 7:3 XCSEL 0Ah 05h Vctr Xin 20pF 6pF* C1 XO Xout 2pF* 0b Reserved – do not write other than 0 i.e. XCSEL = 10pF C2 * Input Capacitance 2:0 VCXO 20pF 7:1 BCOUNT 40h 7-Bit Byte Count (defines the number of bytes which will be sent from this device at the next Block Read transfer); all bytes have to be read out to correctly finish the read cycle.) 0 EEWRITE 0b Initiate EEPROM Write Cycle(4) 06h (1) (2) (3) (4) (5) (6) (7) (8) (9) 16 (9) 0– no EEPROM write cycle 1 – start EEPROM write cycle (internal configuration register is saved to the EEPROM) Writing data beyond ‘40h’ may affect device function. All data transferred with the MSB first. Unless customer-specific setting. During EEPROM programming, no data is allowed to be sent to the device via the SDA/SCL bus until the programming sequence is completed. Data, however, can be read out during the programming sequence (Byte Read or Block Read). If this bit is set to high in the EEPROM, the actual data in the EEPROM will be permanently locked. There is no further programming possible. Data, however can still be written via SDA/SCL bus to the internal register to change device function on the fly. But new data can no longer be saved to the EEPROM. EELOCK is effective only, if written into the EEPROM! Selection of “control pins” is effective only if written into the EEPROM. Once written into the EEPROM, the serial programming pins are no longer available. However, if VDDOUT is forced to GND, the two control pins, S1 and S2, temporally act as serial programming pins (SDA/SCL), and the two slave receiver address bits are reset to A0=”0” and A1=“0”. These are the bits of the Control Terminal Register. The user can predefine up to eight different control settings. These settings then can be selected by the external control pins, S0, S1, and S2. The internal load capacitor (C1, C2) has to be used to achieve the best clock performance. External capacitors should be used only to finely adjust CL by a few pF's. The value of CL can be programmed with a resolution of 1 pF for a crystal load range of 0 pF to 20 pF. For CL > 20 pF, use additional external capacitors. Also, the value of the device input capacitance has to be considered which always adds 1.5 pF (6 pF//2 pF) to the selected CL. For more information about VCXO configuration and crystal recommendation, see application report SCAA085. Note: The EEPROM WRITE bit must be sent last. This ensures that the content of all internal registers are stored in the EEPROM. The EEWRITE cycle is initiated with the rising edge of the EEWRITE bit. A static level high does not trigger an EEPROM WRITE cycle. The EEWRITE bit has to be reset to low after the programming is completed. The programming status can be monitored by reading out EEPIP. If EELOCK is set to high, no EEPROM programming is possible. Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): CDCE937 CDCEL937 CDCE937 CDCEL937 www.ti.com SLAS564F – AUGUST 2007 – REVISED MARCH 2010 Table 9. Generic Configuration Register (continued) Offset (1) Bit (2) Acronym Default (3) — 0h 07h-0Fh Description Unused address range Table 10. PLL1 Configuration Register OFFSET 10h 11h 12h 13h 14h 15h (1) (2) (3) (4) (1) Acronym Default (3) 7:5 SSC1_7 [2:0] 000b 4:2 SSC1_6 [2:0] 000b 1:0 SSC1_5 [2:1] 7 SSC1_5 [0] 6:4 SSC1_4 [2:0] 000b 3:1 SSC1_3 [2:0] 000b 0 SSC1_2 [2] 7:6 SSC1_2 [1:0] 5:3 SSC1_1 [2:0] 000b 2:0 SSC1_0 [2:0] 000b 7 FS1_7 0b 6 FS1_6 0b 5 FS1_5 0b 4 FS1_4 0b 3 FS1_3 0b 2 FS1_2 0b 1 FS1_1 0b 0 FS1_0 0b 7 MUX1 1b PLL1 Multiplexer: 0 – PLL1 1 – PLL1 Bypass (PLL1 is in power down) 6 M2 1b Output Y2 Multiplexer: 0 – Pdiv1 1 – Pdiv2 5:4 M3 10b Output Y3 Multiplexer: 00 – 01 – 10 – 11 – 3:2 Y2Y3_ST1 11b Y2, Y3-State0/1definition: 00 – Y2/Y3 disabled to 3-State (PLL1 is in power down) 01 – Y2/Y3 disabled to 3-State 10–Y2/Y3 disabled to low 11 – Y2/Y3 enabled Bit (2) 000b 000b 1:0 Y2Y3_ST0 01b 7 Y2Y3_7 0b 6 Y2Y3_6 0b 5 Y2Y3_5 0b 4 Y2Y3_4 0b 3 Y2Y3_3 0b 2 Y2Y3_2 0b 1 Y2Y3_1 1b 0 Y2Y3_0 0b DESCRIPTION SSC1: PLL1 SSC Selection (Modulation Amount) (4) Down 000 (off) 001 – 0.25% 010 – 0.5% 011 – 0.75% 100 – 1.0% 101 – 1.25% 110 – 1.5% 111 – 2.0% Center 000 (off) 001 ± 0.25% 010 ± 0.5% 011 ± 0.75% 100 ± 1.0% 101 ± 1.25% 110 ± 1.5% 111 ± 2.0% FS1_x: PLL1 Frequency Selection(4) 0 – fVCO1_0 (predefined by PLL1_0 – Multiplier/Divider value) 1 – fVCO1_1 (predefined by PLL1_1 – Multiplier/Divider value) Pdiv1-Divider Pdiv2-Divider Pdiv3-Divider reserved Y2Y3_x Output State Selection(4) 0 – state0 (predefined by Y2Y3_ST0) 1 – state1 (predefined by Y2Y3_ST1) Writing data beyond 40h may adversely affect device function. All data is transferred MSB-first. Unless a custom setting is used The user can predefine up to eight different control settings. In normal device operation, these settings can be selected by the external control pins, S0, S1, and S2. Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): CDCE937 CDCEL937 Submit Documentation Feedback 17 CDCE937 CDCEL937 SLAS564F – AUGUST 2007 – REVISED MARCH 2010 www.ti.com Table 10. PLL1 Configuration Register (continued) OFFSET (1) 16h 17h 18h 19h 1Ah Bit (2) Acronym Default (3) 7 SSC1DC 0b PLL1 SSC down/center selection: 0 – down 6:0 Pdiv2 01h 7-Bit Y2-Output-Divider Pdiv2: 0 – reset and stand-by 7 — 0b Reserved – do not write others than 0 6:0 Pdiv3 01h 7-Bit Y3-Output-Divider Pdiv3: 7:0 PLL1_0N [11:4] 7:4 PLL1_0N [3:0] 004h PLL1_0 (5): 30-Bit Multiplier/Divider value for frequency fVCO1_0 (for more information, see paragraph PLL Multiplier/Divider Definition). 3:0 PLL1_0R [8:5] 7:3 PLL1_0R[4:0] 2:0 PLL1_0Q [5:3] 7:5 PLL1_0Q [2:0] 4:2 PLL1_0P [2:0] 010b 1:0 VCO1_0_RANGE 00b 7:0 PLL1_1N [11:4] 1Dh 7:4 PLL1_1N [3:0] 3:0 PLL1_1R [8:5] 7:3 PLL1_1R[4:0] 1Eh 2:0 PLL1_1Q [5:3] 7:5 PLL1_1Q [2:0] 4:2 PLL1_1P [2:0] 010b 1:0 VCO1_1_RANGE 00b 18 0 – reset and stand-by 1-to-127 is divider value 1-to-127 is divider value 10h fVCO1_0 range selection: 004h 00 – 01 – 10 – 11 – fVCO1_0 < 125 MHz 125 MHz ≤ fVCO1_0 < 150 MHz 150 MHz ≤ fVCO1_0 < 175 MHz fVCO1_0 ≥ 175 MHz PLL1_1 (5): 30-Bit Multiplier/Divider value for frequency fVCO1_1 (for more information see paragraph PLL Multiplier/Divider Definition) 000h 10h 1Fh (5) 1 – center 000h 1Bh 1Ch DESCRIPTION fVCO1_1 range selection: 00 – 01 – 10 – 11 – fVCO1_1 < 125 MHz 125 MHz ≤ fVCO1_1 < 150 MHz 150 MHz ≤ fVCO1_1 < 175 MHz fVCO1_1 ≥ 175 MHz PLL settings limits: 16≤q≤63, 0≤p≤7, 0≤r≤511, 0<N<4096 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): CDCE937 CDCEL937 CDCE937 CDCEL937 www.ti.com SLAS564F – AUGUST 2007 – REVISED MARCH 2010 Table 11. PLL2 Configuration Register OFFSET (1) 20h 21h 22h 23h 24h 25h (1) (2) (3) (4) Bit (2) Acronym Default (3) 7:5 SSC2_7 [2:0] 000b 4:2 SSC2_6 [2:0] 000b 1:0 SSC2_5 [2:1] 7 SSC2_5 [0] 6:4 SSC2_4 [2:0] 000b 3:1 SSC2_3 [2:0] 000b 0 SSC2_2 [2] 7:6 SSC2_2 [1:0] 5:3 SSC2_1 [2:0] 000b 2:0 SSC2_0 [2:0] 000b 7 FS2_7 0b 6 FS2_6 0b 5 FS2_5 0b 4 FS2_4 0b 3 FS2_3 0b 2 FS2_2 0b 1 FS2_1 0b 0 FS2_0 0b 7 MUX2 1b 6 M4 1b 5:4 M5 10b 3:2 Y4Y5_ST1 11b 1:0 Y4Y5_ST0 01b 7 Y4Y5_7 0b 6 Y4Y5_6 0b 5 Y4Y5_5 0b 4 Y4Y5_4 0b 3 Y4Y5_3 0b 2 Y4Y5_2 0b 1 Y4Y5_1 1b 0 Y4Y5_0 0b 000b 000b DESCRIPTION SSC2: PLL2 SSC Selection (Modulation Amount) (4) Down 000 (off) 001 – 0.25% 010 – 0.5% 011 – 0.75% 100 – 1.0% 101 – 1.25% 110 – 1.5% 111 – 2.0% Center 000 (off) 001 ± 0.25% 010 ± 0.5% 011 ± 0.75% 100 ± 1.0% 101 ± 1.25% 110 ± 1.5% 111 ± 2.0% FS2_x: PLL2 Frequency Selection(4) 0 – fVCO2_0 (predefined by PLL2_0 – Multiplier/Divider value) 1 – fVCO2_1 (predefined by PLL2_1 – Multiplier/Divider value) PLL2 Multiplexer: 0 – PLL2 1 – PLL2 Bypass (PLL2 is in power down) Output Y4 Multiplexer: 0 – Pdiv2 1 – Pdiv4 Output Y5 Multiplexer: 00 – 01 – 10 – 11 – Y4, Y5-State0/1definition: 00 – Y4/Y5 disabled to 3-State (PLL2 is in power down) 01 – Y4/Y5 disabled to 3-State 10–Y4/Y5 disabled to low 11 – Y4/Y5 enabled Pdiv2-Divider Pdiv4-Divider Pdiv5-Divider reserved Y4Y5_x Output State Selection(4) 0 – state0 (predefined by Y4Y5_ST0) 1 – state1 (predefined by Y4Y5_ST1) Writing data beyond 40h may adversely affect device function. All data is transferred MSB-first. Unless a custom setting is used The user can predefine up to eight different control settings. In normal device operation, these settings can be selected by the external control pins, S0, S1, and S2. Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): CDCE937 CDCEL937 Submit Documentation Feedback 19 CDCE937 CDCEL937 SLAS564F – AUGUST 2007 – REVISED MARCH 2010 www.ti.com Table 11. PLL2 Configuration Register (continued) OFFSET (1) 26h 27h 28h 29h 2Ah Bit (2) Acronym Default (3) 2Dh 2Eh 20 0 – reset and stand-by SSC2DC 0b 6:0 Pdiv4 01h 7-Bit Y4-Output-Divider Pdiv4: 7 — 0b Reserved – do not write others than 0 6:0 Pdiv5 01h 7-Bit Y5-Output-Divider Pdiv5: 7:0 PLL2_0N [11:4 7:4 PLL2_0N [3:0] 004h PLL2_0 (5): 30-Bit Multiplier/Divider value for frequency fVCO2_0 (for more information see paragraph PLL Multiplier/Divider Definition) 3:0 PLL2_0R [8:5] 7:3 PLL2_0R[4:0] 2:0 PLL2_0Q [5:3] 7:5 PLL2_0Q [2:0] 4:2 PLL2_0P [2:0] 010b 1:0 VCO2_0_RANGE 00b 7:0 PLL2_1N [11:4] 7:4 PLL2_1N [3:0] 3:0 PLL2_1R [8:5] 7:3 PLL2_1R[4:0] 2:0 PLL2_1Q [5:3] 7:5 PLL2_1Q [2:0] 4:2 PLL2_1P [2:0] 010b 1:0 VCO2_1_RANGE 00b 0 – reset and stand-by 1-to-127 – divider value 1-to-127 – divider value 000h 10h fVCO2_0 range selection: 004h 00 – 01 – 10 – 11 – fVCO2_0 < 125 MHz 125 MHz ≤ fVCO2_0 < 150 MHz 150 MHz ≤ fVCO2_0 < 175 MHz fVCO2_0 ≥ 175 MHz PLL2_1 (5): 30-Bit Multiplier/Divider value for frequency fVCO2_1 (for more information see paragraph PLL Multiplier/Divider Definition) 000h 10h 2Fh (5) 0 – down 1 – center 7 2Bh 2Ch DESCRIPTION PLL2 SSC down/center selection: fVCO2_1 range selection: 00 – 01 – 10 – 11 – fVCO2_1 < 125 MHz 125 MHz ≤ fVCO2_1 < 150 MHz 150 MHz ≤ fVCO2_1 < 175 MHz fVCO2_1 ≥ 175 MHz PLL settings limits: 16≤q≤63, 0≤p≤7, 0≤r≤511, 0<N<4096 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): CDCE937 CDCEL937 CDCE937 CDCEL937 www.ti.com SLAS564F – AUGUST 2007 – REVISED MARCH 2010 Table 12. PLL3 Configuration Register OFFSET (1) 30h 31h 32h 33h 34h 35h (1) (2) (3) (4) Bit (2) Acronym Default (3) 7:5 SSC3_7 [2:0] 000b 4:2 SSC3_6 [2:0] 000b 1:0 SSC3_5 [2:1] 7 SSC3_5 [0] 6:4 SSC3_4 [2:0] 000b 3:1 SSC3_3 [2:0] 000b 0 SSC3_2 [2] 7:6 SSC3_2 [1:0] 5:3 SSC3_1 [2:0] 000b 2:0 SSC3_0 [2:0] 000b 7 FS3_7 0b 6 FS3_6 0b 5 FS3_5 0b 4 FS3_4 0b 3 FS3_3 0b 2 FS3_2 0b 1 FS3_1 0b 0 FS3_0 0b 7 MUX3 1b PLL3 Multiplexer: 0 – PLL3 1 – PLL3 Bypass (PLL3 is in power down) 6 M6 1b Output Y6 Multiplexer: 0 – Pdiv4 1 – Pdiv6 5:4 M7 10b Output Y7 Multiplexer: 00 – 01 – 10 – 11 – 3:2 Y6Y7_ST1 11b 00 – Y6/Y7 disabled to 3-State and PLL3 power down 01 – Y6/Y7 disabled to 3-State 10 –Y6/Y7 disabled to low 11 – Y6/Y7 enabled 000b 000b DESCRIPTION SSC3: PLL3 SSC Selection (Modulation Amount) (4) Down 000 (off) 001 – 0.25% 010 – 0.5% 011 – 0.75% 100 – 1.0% 101 – 1.25% 110 – 1.5% 111 – 2.0% Center 000 (off) 001 ± 0.25% 010 ± 0.5% 011 ± 0.75% 100 ± 1.0% 101 ± 1.25% 110 ± 1.5% 111 ± 2.0% FS3_x: PLL3 Frequency Selection(4) 0 – fVCO3_0 (predefined by PLL3_0 – Multiplier/Divider value) 1 – fVCO3_1 (predefined by PLL3_1 – Multiplier/Divider value) Pdiv4-Divider Pdiv6-Divider Pdiv7-Divider reserved 1:0 Y6Y7_ST0 01b Y6, Y7-State0/1definition: 7 Y6Y7_7 0b Y6Y7_x Output State Selection(4) 6 Y6Y7_6 0b 5 Y6Y7_5 0b 4 Y6Y7_4 0b 3 Y6Y7_3 0b 2 Y6Y7_2 0b 1 Y6Y7_1 1b 0 Y6Y7_0 0b 0 – state0 (predefined by Y6Y7_ST0) 1 – state1 (predefined by Y6Y7_ST1) Writing data beyond 40h may affect device function. All data is transferred MSB-first. Unless a custom setting is used These are the bits of the Control Terminal Register. The user can pre-define up to eight different control settings. At normal device operation, these setting can be selected by the external control pins, S0, S1, and S2. Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): CDCE937 CDCEL937 Submit Documentation Feedback 21 CDCE937 CDCEL937 SLAS564F – AUGUST 2007 – REVISED MARCH 2010 www.ti.com Table 12. PLL3 Configuration Register (continued) OFFSET (1) 36h 37h 38h 39h 3Ah Bit (2) Acronym Default (3) 7 SSC3DC 0b PLL3 SSC down/center selection: 0 – down 6:0 Pdiv6 01h 7-Bit Y6-Output-Divider Pdiv6: 0 – reset and stand-by 1-to-127 – divider value 7 — 0b Reserved – do not write others than 0 6:0 Pdiv7 01h 7-Bit Y7-Output-Divider Pdiv7: 0 – reset and stand-by 1-to-127 – divider value 7:0 PLL3_0N [11:4] 7:4 PLL3_0N [3:0] 004h PLL3_0 (5): 30-Bit Multiplier/Divider value for frequency fVCO3_0 (for more information see paragraph PLL Multiplier/Divider Definition) 3:0 PLL3_0R [8:5] 7:3 PLL3_0R[4:0] 2:0 PLL3_0Q [5:3] 7:5 PLL3_0Q [2:0] 4:2 PLL3_0P [2:0] 010b 1:0 VCO3_0_RANGE 00b 7:0 PLL3_1N [11:4] 3Dh 7:4 PLL3_1N [3:0] 3:0 PLL3_1R [8:5] 7:3 PLL3_1R[4:0] 3Eh 2:0 PLL3_1Q [5:3] 7:5 PLL3_1Q [2:0] 4:2 PLL3_1P [2:0] 010b 1:0 VCO3_1_RANGE 00b 10h fVCO3_0 range selection: 004h 22 00 – 01 – 10 – 11 – fVCO3_0 < 125 MHz 125 MHz ≤ fVCO3_0 < 150 MHz 150 MHz ≤ fVCO3_0 < 175 MHz fVCO3_0 ≥ 175 MHz PLL3_1 (5): 30-Bit Multiplier/Divider value for frequency fVCO3_1 (for more information see paragraph PLL Multiplier/Divider Definition) 000h 10h 3Fh (5) 1 – center 000h 3Bh 3Ch DESCRIPTION fVCO3_1 range selection: 00 – 01 – 10 – 11 – fVCO3_1 < 125 MHz 125 MHz ≤ fVCO3_1 < 150 MHz 150 MHz ≤ fVCO3_1 < 175 MHz fVCO3_1 ≥ 175 MHz PLL settings limits: 16≤q≤63, 0≤p≤7, 0≤r≤511, 0<N<4096 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): CDCE937 CDCEL937 CDCE937 CDCEL937 www.ti.com SLAS564F – AUGUST 2007 – REVISED MARCH 2010 PLL Multiplier/Divider Definition At a given input frequency (ƒIN), the output frequency (ƒOUT) of the CDCE937/CDCEL937 can be calculated: ƒ N ƒ OUT + IN Pdiv M (1) where M (1 to 511) and N (1 to 4095) are the multiplier/divide values of the PLL; Pdiv (1 to 127) is the output divider. The target VCO frequency (ƒVCO) of each PLL can be calculated: N ƒ VCO + ƒIN M (2) The PLL internally operates as fractional divider and needs the following multiplier/divider settings: N ǒlog MN Ǔ [if P t 0 then P + 0] ǒNȀǓ Q = int M 2 P = 4 – int R = N′ – M × Q where N′ = N × 2P N≥M 100 MHz < ƒVCO > 200 MHz 16 ≤ q ≤63 0≤p≤7 0 ≤ r ≤ 511 Example: for ƒIN = 27 MHz; M = 1; N = 4; Pdiv = 2; for ƒIN = 27 MHz; M = 2; N = 11; Pdiv = 2; → fOUT = 54 MHz → fOUT = 74.25 MHz → fVCO = 108 MHz → fVCO = 148.50 MHz → P = 4 – int(log24) = 4 – 2 = 2 → P = 4 – int(log25.5) = 4 – 2 = 2 2 → N′ = 4 × 2 = 16 → N′ = 11 × 22 = 44 → Q = int(16) = 16 → Q = int(22) = 22 → R = 16 – 16 = 0 → R = 44 – 44 = 0 The values for P, Q, R, and N’ is automatically calculated when using TI Pro-Clock™ software. Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): CDCE937 CDCEL937 Submit Documentation Feedback 23 CDCE937 CDCEL937 SLAS564F – AUGUST 2007 – REVISED MARCH 2010 www.ti.com REVISION HISTORY Changes from Original (August 2007) to Revision A • Page Changed from the device status Product preview to Production. ......................................................................................... 1 Changes from Revision A (September 2007) to Revision B Page • Changed Terminal Functions Table - the pin numbers to correpond with pin outs on the package .................................... 2 • Changed the PACKAGE THERMAL RESISTANCE table .................................................................................................... 4 • Changed Table 9 RID default From: 0h To: Xb .................................................................................................................. 16 • Added note to PWDN description, Table 9 ......................................................................................................................... 16 Changes from Revision B (December 2007) to Revision C • Page Changed Table 9 - SLAVE_ADR default value From: 00b To: 01b ................................................................................... 16 Changes from Revision C (January 2009) to Revision D • Page Added Note 3: SDA and SCL can go up to 3.6V as stated in the Recommended Operating Conditions table ................... 3 Changes from Revision D (September 2009) to Revision E • Page Deleted sentence - A different default setting can be programmed on customer request. Contact Texas Instruments sales or marketing representative for more information. .................................................................................................... 11 Changes from Revision E (October 2009) to Revision F Page • Added PLL settings limits: 16≤q≤63, 0≤p≤7, 0≤r≤511, 0<N<4096 foot to PLL1, PLL2, and PLL3 Configure Register Table ................................................................................................................................................................................... 18 • Added PLL settings limits: 16≤q≤63, 0≤p≤7, 0≤r≤511 to PLL Multiplier/Divider Definition Section .................................... 23 24 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): CDCE937 CDCEL937 PACKAGE OPTION ADDENDUM www.ti.com 15-Jan-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty CDCE937PW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CDCE937PWG4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CDCE937PWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CDCE937PWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CDCEL937PW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CDCEL937PWG4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CDCEL937PWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CDCEL937PWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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OTHER QUALIFIED VERSIONS OF CDCE937 : • Automotive: CDCE937-Q1 NOTE: Qualified Version Definitions: Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 15-Jan-2010 • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 15-Jan-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CDCE937PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 CDCEL937PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 15-Jan-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDCE937PWR TSSOP PW 20 2000 346.0 346.0 33.0 CDCEL937PWR TSSOP PW 20 2000 346.0 346.0 33.0 Pack Materials-Page 2 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. 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