NSC COP982C-XXX/N Microcontroller Datasheet

COP680C/COP681C/COP682C/COP880C/COP881C/
COP882C/COP980C/COP981C/COP982C
Microcontrollers
General Description
The COP680C/COP681C/COP682C/COP880C/COP881C
/COP882C/COP980C/COP981C and COP982C are members of the COPSTM microcontroller family. They are fully
static parts, fabricated using double-metal silicon gate
microCMOS technology. This low cost microcontroller is a
complete microcomputer containing all system timing, interrupt logic, ROM, RAM, and I/O necessary to implement
dedicated control functions in a variety of applications. Features include an 8-bit memory mapped architecture, MICROWIRE/PLUSTM serial I/O, a 16-bit timer/counter with
capture register and a multi-sourced interrupt. Each I/O pin
has software selectable options to adapt the device to the
specific application. The part operates over a voltage range
of 2.5 to 6.0V. High throughput is achieved with an efficient,
regular instruction set operating at a 1 microsecond per instruction rate.
Y
Y
Y
CPU/Instruction Set Features
Y
Y
Y
Y
Y
Key Features
Y
Y
Y
16-bit multi-function timer supporting
Ð PWM mode
Ð External event counter mode
Ð Input capture mode
4 kbytes of ROM
128 bytes of RAM
Y
Y
1 ms instruction cycle time
Three multi-source interrupts servicing
Ð External interrupt with selectable edge
Ð Timer interrupt
Ð Software interrupt
Versatile and easy to use instruction set
8-bit Stack Pointer (SP)Ðstack in RAM
Two 8-bit Register Indirect Data Memory Pointers
(B and X)
Fully Static CMOS
Y
Y
Y
Low current drain (typically k 1 mA)
Single supply operation: 2.5V to 6.0V
Temperature ranges: 0§ C to 70§ C, b40§ C to a 85§ C,
b 55§ C to a 125§ C.
Development Support
I/O Features
Y
Schmitt trigger inputs on Port G
MICROWIRE PLUS serial I/O
Packages:
Ð 20 DIP/SO with 16 I/O pins
Ð 28 DIP/SO with 24 I/O pins
Ð 40 DIP, 36 I/O pins
Ð 44 PLCC, 36 I/O pins
Y
Memory mapped I/O
Software selectable I/O options (TRI-STATEÉ, PushPull, Weak Pull-Up Input, High Impedance Input)
High current outputs (8 pins)
Y
Emulation and OTP devices
Real time emulation and full program debug offered by
MetaLink’s development system
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
COPSTM , HPCTM , MICROWIRETM and MICROWIRE/PLUSTM are trademarks of National Semiconductor Corporation.
iceMASTERTM is a trademark of MetaLink Corporation.
PC-XTÉ and PC-ATÉ are registered trademarks of International Business Machines Corporation.
C1996 National Semiconductor Corporation
TL/DD10802
RRD-B30M106/Printed in U. S. A.
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COP680C/COP681C/COP682C/COP880C/COP881C/COP882C/COP980C/COP981C/COP982C
Microcontrollers
August 1996
Block Diagram
TL/DD/10802 – 1
FIGURE 1
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2
Connection Diagrams
Dual-In-Line Package (N)
and 28 Wide SO (WM)
Dual-In-Line Package
TL/DD/10802 – 23
Top View
Order Number COP882C-XXX/N, COP982C-XXX/N,
COP882C-XXX/WM, COP982C-XXX/WM,
COP982C-XXX/N or COP982CH-XXX/WM
TL/DD/10802 – 5
Top View
Order Number COP881C-XXX/N, COP981C-XXX/N,
COP881C-XXX/WM, COP981C-XXX/WM,
COP981CH-XXX/N or COP981CH-XXX/WM
Plastic Chip Carrier
Dual-In-Line Package
TL/DD/10802 – 3
Top View
Order Number COP680C-XXX/V, COP880C-XXX/V,
COP980C-XXX/V or COP980CH-XXX/V
TL/DD/10802 – 4
Top View
Order Number COP680C-XXX/N, COP880C-XXX/N,
COP980C-XXX/N or COP980CH-XXX/N
FIGURE 3. Connection Diagrams
3
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COP980C/COP981C/COP982C
Absolute Maximum Ratings
Total Current out of GND Pin (Sink)
Storage Temperature Range
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (VCC)
7V
Voltage at any Pin
Total Current into VCC Pin (Source)
60 mA
b 65§ C to a 140§ C
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
b 0.3V to VCC a 0.3V
50 mA
DC Electrical Characteristics COP98xC; 0§ C s TA s a 70§ C unless otherwise specified
Parameter
Operating Voltage
98XC
98XCH
Power Supply Ripple (Note 1)
Supply Current
CKI e 10 MHz
CKI e 4 MHz
CKI e 4 MHz
CKI e 1 MHz
(Note 2)
HALT Current
(Note 3)
Condition
Min
2.3
4.0
Peak to Peak
VCC
VCC
VCC
VCC
e
e
e
e
6V, tc e 1 ms
6V, tc e 2.5 ms
4.0V, tc e 2.5 ms
4.0V, tc e 10 ms
VCC e 6V, CKI e 0 MHz
VCC e 4.0V, CKI e 0 MHz
Input Levels
RESET, CKI
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low
Hi-Z Input Leakage
Input Pullup Current
k 0.7
k 0.4
Sink
All Others
Source (Weak Pull-Up)
Source (Push-Pull Mode)
Sink (Push-Pull Mode)
TRI-STATE Leakage
Units
4.0
6.0
0.1 VCC
V
V
V
6.0
4.4
2.2
1.4
mA
mA
mA
mA
8
5
mA
mA
0.1 VCC
V
V
0.2 VCC
V
V
a 1.0
b 250
mA
mA
0.35 VCC
V
0.7 VCC
VCC e 6.0V
VCC e 6.0V, VIN e 0V
b 1.0
b 40
VCC
VCC
VCC
VCC
e
e
e
e
4.5V, VOH e 3.8V
2.3V, VOH e 1.6V
4.5V, VOL e 1.0V
2.3V, VOL e 0.4V
b 0.4
b 0.2
VCC
VCC
VCC
VCC
VCC
VCC
VCC
e
e
e
e
e
e
e
4.5V, VOH e 3.2V
2.3V, VOH e 1.6V
4.5V, VOH e 3.8V
2.3V, VOH e 1.6V
4.5V, VOL e 0.4V
2.3V, VOL e 0.4V
6.0V
b 10
b 2.5
b 0.4
b 0.2
Maximum Input Current (Note 4)
Without Latchup (Room Temp)
Room Temp
RAM Retention Voltage, Vr
(Note 5)
500 ns Rise and
Fall Time (Min)
mA
mA
mA
mA
10
2
1.6
0.7
b 1.0
Allowable Sink/Source
Current Per Pin
D Outputs (Sink)
All Others
b 110
b 33
Load Capacitance on D2
4
mA
mA
mA
mA
a 1.0
mA
15
3
mA
mA
g 100
mA
7
pF
1000
pF
2.0
Input Capacitance
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Max
0.9 VCC
G Port Input Hysteresis
Output Current Levels
D Outputs
Source
Typ
V
COP980C/COP981C/COP982C
DC Electrical Characteristics
(Continued)
Note 1: Rate of voltage change must be less than 0.5V/ms.
Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to VCC, L, C and G ports TRI-STATE
and tied to ground, all outputs low and tied to ground.
Note 4: Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than VCC and the pins will
have sink current to VCC when biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC). The effective
resistance to VCC is 750X (typ). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
Note 5: To maintain RAM integrity, the voltage must not be dropped or raised instantaneously.
AC Electrical Characteristics 0§ C s TA s a 70§ C unless otherwise specified
Parameter
Condition
Max
Units
1
2.5
3
7.5
DC
DC
DC
DC
ms
ms
ms
ms
fr e Max
fr e 10 MHz Ext Clock
fr e 10 MHz Ext Clock
40
60
12
8
%
ns
ns
VCC t 4.0V
2.3V s VCC s 4.0V
VCC t 4.0V
2.3V s VCC s 4.0V
200
500
60
150
Instruction Cycle Time (tc)
Crystal/Resonator or External
(Div-by 10)
R/C Oscillator Mode
(Div-by 10)
VCC t 4.0V
2.3V s VCC s 4.0V
VCC t 4.0V
2.3V s VCC s 4.0V
CKI Clock Duty Cycle (Note 6)
Rise Time (Note 6)
Fall Time (Note 6)
Inputs
tSETUP
tHOLD
Output Propagation Delay
tPD1, tPD0
SO, SK
All Others
Min
Typ
ns
ns
ns
ns
CL e 100 pF, RL e 2.2 kX
VCC t 4.0V
2.3V s VCC s 4.0V
VCC t 4.0V
2.3V s VCC s 4.0V
MICROWIRETM Setup Time (tUWS)
MICROWIRE Hold Time (tUWH)
MICROWIRE Output
Propagation Delay (tUPD)
0.7
1.75
1
2.5
20
56
ns
ns
220
Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time
tC
tC
tC
tC
Reset Pulse Width
1.0
ms
ms
ms
ms
ns
ms
Note 6: Parameter characterized but not production tested.
5
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COP880C/COP881C/COP882C
Absolute Maximum Ratings
Total Current out of GND Pin (Sink)
Storage Temperature Range
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (VCC)
7V
Voltage at any Pin
Total Current into VCC Pin (Source)
60 mA
b 65§ C to a 140§ C
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
b 0.3V to VCC a 0.3V
50 mA
DC Electrical Characteristics COP88xC; b40§ C s TA s a 85§ C unless otherwise specified
Parameter
Operating Voltage
Power Supply Ripple (Note 1)
Supply Current
CKI e 10 MHz
CKI e 4 MHz
CKI e 4 MHz
CKI e 1 MHz
(Note 2)
HALT Current
(Note 3)
Condition
Min
Peak to Peak
VCC
VCC
VCC
VCC
e
e
e
e
6V, tc e 1 ms
6V, tc e 2.5 ms
4.0V, tc e 2.5 ms
4.0V, tc e 10 ms
VCC e 6V, CKI e 0 MHz
VCC e 3.5V, CKI e 0 MHz
Input Levels
RESET, CKI
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low
Hi-Z Input Leakage
Input Pullup Current
k1
k 0.5
Sink
All Others
Source (Weak Pull-Up)
Source (Push-Pull Mode)
Sink (Push-Pull Mode)
TRI-STATE Leakage
Units
6.0
0.1 VCC
V
V
6.0
4.4
2.2
1.4
mA
mA
mA
mA
10
6
mA
mA
0.1 VCC
V
V
0.2 VCC
V
V
a2
b 250
mA
mA
0.35 VCC
V
0.7 VCC
VCC e 6.0V
VCC e 6.0V, VIN e 0V
b2
b 40
VCC
VCC
VCC
VCC
e
e
e
e
4.5V, VOH e 3.8V
2.5V, VOH e 1.8V
4.5V, VOL e 1.0V
2.5V, VOL e 0.4V
b 0.4
b 0.2
VCC
VCC
VCC
VCC
VCC
VCC
VCC
e
e
e
e
e
e
e
4.5V, VOH e 3.2V
2.5V, VOH e 1.8V
4.5V, VOH e 3.8V
2.5V, VOH e 1.8V
4.5V, VOL e 0.4V
2.5V, VOL e 0.4V
6.0V
b 10
b 2.5
b 0.4
b 0.2
Maximum Input Current (Note 4)
Without Latchup (Room Temp)
Room Temp
RAM Retention Voltage, Vr
(Note 5)
500 ns Rise and
Fall Time (Min)
mA
mA
mA
mA
10
2
1.6
0.7
b 2.0
Allowable Sink/Source
Current Per Pin
D Outputs (Sink)
All Others
b 110
b 33
Load Capacitance on D2
6
mA
mA
mA
mA
a 2.0
mA
15
3
mA
mA
g 100
mA
7
pF
1000
pF
2.0
Input Capacitance
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Max
0.9 VCC
G Port Input Hysteresis
Output Current Levels
D Outputs
Source
Typ
2.5
V
COP880C/COP881C/COP882C
DC Electrical Characteristics
(Continued)
Note 1: Rate of voltage change must be less than 0.5V/ms.
Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to VCC, L, C and G ports TRI-STATE
and tied to ground, all outputs low and tied to ground.
Note 4: Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than VCC and the pins will
have sink current to VCC when biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC). The effective
resistance to VCC is 750X (typ). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
Note 5: To maintain RAM integrity, the voltage must not be dropped or raised instantaneously.
AC Electrical Characteristics b40§ C s TA s a 85§ C unless otherwise specified
Parameter
Condition
Max
Units
1
2.5
3
7.5
DC
DC
DC
DC
ms
ms
ms
ms
fr e Max
fr e 10 MHz Ext Clock
fr e 10 MHz Ext Clock
40
60
12
8
%
ns
ns
VCC t 4.5V
2.5V s VCC k 4.5V
VCC t 4.5V
2.5V s VCC k 4.5V
200
500
60
150
Instruction Cycle Time (tc)
Crystal/Resonator or External
(Div-by 10)
R/C Oscillator Mode
(Div-by 10)
VCC t 4.5V
2.5V s VCC k 4.5V
VCC t 4.5V
2.5V s VCC k 4.5V
CKI Clock Duty Cycle (Note 6)
Rise Time (Note 6)
Fall Time (Note 6)
Inputs
tSETUP
tHOLD
Output Propagation Delay
tPD1, tPD0
SO, SK
All Others
Min
Typ
ns
ns
ns
ns
CL e 100 pF, RL e 2.2 kX
VCC t 4.5V
2.5V s VCC k 4.5V
VCC t 4.5V
2.5V s VCC k 4.5V
MICROWIRETM Setup Time (tUWS)
MICROWIRE Hold Time (tUWH)
MICROWIRE Output
Propagation Delay (tUPD)
0.7
1.75
1
2.5
20
56
ns
ns
220
Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time
tC
tC
tC
tC
Reset Pulse Width
1.0
ms
ms
ms
ms
ns
ms
Note 6: Parameter characterized but not production tested.
Timing Diagram
TL/DD/10802 – 2
FIGURE 2. MICROWIRE/PLUS Timing
7
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COP680C/COP681C/COP682C
Absolute Maximum Ratings
Total Current Out of GND Pin (Sink)
Storage Temperature Range
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (VCC)
6V
Voltage at Any Pin
Total Current into VCC Pin (Source)
48 mA
b 65§ C to a 140§ C
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
b 0.3V to VCC a 0.3V
40 mA
DC Electrical Characteristics COP68xC: b55§ C s TA s a 125§ C unless otherwise specified
Parameter
Condition
Operating Voltage
Power Supply Ripple (Note 1)
Peak to Peak
Supply Current (Note 2)
CKI e 10 MHz
CKI e 4 MHz
HALT Current (Note 3)
VCC e 5.5V, tc e 1 ms
VCC e 5.5V, tc e 2.5 ms
VCC e 5.5V, CKI e 0 MHz
Max
Units
5.5
0.1 VCC
V
V
8.0
4.4
30
mA
mA
mA
0.1 VCC
V
V
0.2 VCC
V
V
a5
b 300
mA
mA
0.35 VCC
V
k 10
0.9 VCC
0.7 VCC
VCC e 5.5V
VCC e 5.5V, VIN e 0V
b5
b 35
G Port Input Hysteresis
Output Current Levels
D Outputs
Source
Sink
All Others
Source (Weak Pull-Up)
Source (Push-Pull Mode)
Sink (Push-Pull Mode)
TRI-STATE Leakage
Typ
4.5
Input Levels
RESET, CKI
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low
Hi-Z Input Leakage
Input Pullup Current
Min
VCC e 4.5V, VOH e 3.8V
VCC e 4.5V, VOL e 1.0V
b 0.35
VCC
VCC
VCC
VCC
b9
b 0.35
e
e
e
e
4.5V, VOH e 3.2V
4.5V, VOH e 3.2V
4.5V, VOL e 0.4V
5.5V
mA
mA
9
b 120
a 5.0
mA
mA
mA
mA
12
2.5
mA
mA
g 100
mA
7
pF
1000
pF
1.4
b 5.0
Allowable Sink/Source Current per Pin
D Outputs (Sink)
All Others
Maximum Input Current (Room Temp)
without Latchup (Note 4)
Room Temp
RAM Retention Voltage, Vr (Note 5)
500 ns Rise and Fall Time (Min)
2.5
V
Input Capacitance
Load Capacitance on D2
Note 1: Rate of voltage change must be less than 0.5V/ms.
Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to VCC, L and G ports TRI-STATE
and tied to ground, all outputs low and tied to ground.
Note 4: Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than VCC and the pins will
have sink current to VCC when biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC). The effective
resistance to VCC is 750X (typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
Note 5: To maintain RAM integrity, the voltage must not be dropped or raised instantaneously.
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8
COP680C/COP681C/COP682C
AC Electrical Characteristics b55§ C s TA s a 125§ C unless otherwise specified
Parameter
Instruction Cycle Time (tc)
Ext. or Crystal/Resonant
(Div-by 10)
CKI Clock Duty Cycle
(Note 6)
Rise Time (Note 6)
Fall Time (Note 6)
Condition
Min
Typ
Max
Units
VCC t 4.5V
1
DC
ms
fr e Max
40
60
%
12
8
ns
ns
fr e 10 MHz Ext Clock
fr e 10 MHz Ext Clock
MICROWIRE Setup Time (tUWS)
MICROWIRE Hold Time (tUWH)
MICROWIRE Output Valid
Time (tUPD)
20
56
ns
ns
220
Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time
tC
tC
tC
tC
Reset Pulse Width
1
ns
ms
Note 6: Parameter characterized but not production tested.
9
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Typical Performance Characteristics (b40§ C s TA s a 85§ C)
DynamicÐIDD (Crystal Clock Option)
HallÐIDD
TL/DD/10802–16
TL/DD/10802 – 17
Port L/C/G Weak Pull-Up
Source Current
Port L/C/G Push-Pull Source Current
TL/DD/10802 – 19
TL/DD/10802–18
Port L/C/G Push-Pull Sink Current
Port D Source Current
TL/DD/10802–20
TL/DD/10802 – 21
Port D Sink Current
TL/DD/10802 – 22
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10
PORT D is an 8-bit output port that is preset high when
RESET goes low. Care must be exercised with the D2 pin
operation. At RESET, the external loads on this pin must
ensure that the output voltages stay above 0.9 VCC to prevent the chip from entering special modes. Also, keep the
external loading on D2 to less than 1000 pF.
Pin Descriptions
VCC and GND are the power supply pins.
CKI is the clock input. This can come from an external
source, a R/C generated oscillator or a crystal (in conjunction with CKO). See Oscillator description.
RESET is the master reset input. See Reset description.
Functional Description
PORT I is an 8-bit Hi-Z input port. The 28-pin device does
not have a full complement of Port I pins. The unavailable
pins are not terminated i.e., they are floating. A read operation for these unterminated pins will return unpredictable
values. The user must ensure that the software takes this
into account by either masking or restricting the accesses to
bit operations. The unterminated Port I pins will draw power
only when addressed.
PORT L is an 8-bit I/O port.
PORT C is a 4-bit I/O port.
Three memory locations are allocated for the L, G and C
ports, one each for data register, configuration register and
the input pins. Reading bits 4–7 of the C-Configuration register, data register, and input pins returns undefined data.
There are two registers associated with the L and C ports: a
data register and a configuration register. Therefore, each L
and C I/O bit can be individually configured under software
control as shown below:
Config.
Data
Ports L and C Setup
0
0
1
1
0
1
0
1
Hi-Z Input (TRI-STATE Output)
Input with Pull-Up (Weak One Output)
Push-Pull Zero Output
Push-Pull One Output
Figure 1 shows the block diagram of the internal architecture. Data paths are illustrated in simplified form to depict
how the various logic elements communicate with each other in implementing the instruction set of the device.
ALU AND CPU REGISTERS
The ALU can do an 8-bit addition, subtraction, logical or
shift operation in one cycle time.
There are five CPU registers:
A is the 8-bit Accumulator register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
B is the 8-bit address register, can be auto incremented or
decremented.
X is the 8-bit alternate address register, can be incremented
or decremented.
SP is the 8-bit stack pointer, points to subroutine stack (in
RAM).
B, X and SP registers are mapped into the on chip RAM.
The B and X registers are used to address the on chip RAM.
The SP register is used to address the stack in RAM during
subroutine calls and returns.
PROGRAM MEMORY
Program memory consists of 4096 bytes of ROM. These
bytes may hold program instructions or constant data. The
program memory is addressed by the 15-bit program counter (PC). ROM can be indirectly read by the LAID instruction
for table lookup.
On the 28-pin part, it is recommended that all bits of Port C
be configured as outputs.
PORT G is an 8-bit port with 6 I/O pins (G0–G5) and 2 input
pins (G6, G7). All eight G-pins have Schmitt Triggers on the
inputs.
There are two registers associated with the G port: a data
register and a configuration register. Therefore, each G port
bit can be individually configured under software control as
shown below:
Config.
Data
Port G Setup
0
0
1
1
0
1
0
1
Hi-Z Input (TRI-STATE Output)
Input with Pull-Up (Weak One Output)
Push-Pull Zero Output
Push-Pull One Output
DATA MEMORY
The data memory address space includes on chip RAM, I/O
and registers. Data memory is addressed directly by the instruction or indirectly by the B, X and SP registers.
The device has 128 bytes of RAM. Sixteen bytes of RAM
are mapped as ‘‘registers’’ that can be loaded immediately,
decremented or tested. Three specific registers: B, X and
SP are mapped into this space, the other bytes are available
for general usage.
The instruction set permits any bit in memory to be set,
reset or tested. All I/O and registers (except the A & PC) are
memory mapped; therefore, I/O bits and register bits can be
directly and individually set, reset and tested. A is not memory mapped, but bit operations can be still performed on it.
Since G6 and G7 are input only pins, any attempt by the
user to configure them as outputs by writing a one to the
configuration register will be disregarded. Reading the G6
and G7 configuration bits will return zeros. The device will
be placed in the HALT mode by writing to the G7 bit in the
G-port data register.
Six pins of Port G have alternate features:
G0 INTR (an external interrupt)
G3 TIO (timer/counter input/output)
G4 SO (MICROWIRE serial data output)
G5 SK (MICROWIRE clock I/O)
G6 SI (MICROWIRE serial data input)
G7 CKO crystal oscillator output (selected by mask option)
or HALT restart input (general purpose input)
Pins G1 and G2 currently do not have any alternate functions.
Note: RAM contents are undefined upon power-up.
RESET
The RESET input when pulled low initializes the microcontroller. Initialization will occur whenever the RESET input is
pulled low. Upon initialization, the ports L, G and C are
placed in the TRI-STATE mode and the Port D is set high.
The PC, PSW and CNTRL registers are cleared. The data
and configuration registers for Ports L, G and C are cleared.
The external RC network shown in Figure 4 should be used
to ensure that the RESET pin is held low until the power
supply to the chip stabilizes.
11
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Functional Description (Continued)
Table II shows the variation in the oscillator frequencies as
functions of the component (R and C) values.
TL/DD/10802–6
RC t 5X Power Supply Rise Time
FIGURE 4. Recommended Reset Circuit
OSCILLATOR CIRCUITS
Figure 5 shows the three clock oscillator configurations.
A. CRYSTAL OSCILLATOR
The device can be driven by a crystal clock. The crystal
network is connected between the pins CKI and CKO.
Table I shows the component values required for various
standard crystal values.
B. EXTERNAL OSCILLATOR
CKI can be driven by an external clock signal. CKO is available as a general purpose input and/or HALT restart control.
TL/DD/10802 – 7
FIGURE 5. Crystal and R-C Connection Diagrams
OSCILLATOR MASK OPTIONS
The device can be driven by clock inputs between DC and
10 MHz.
C. R/C OSCILLATOR
CKI is configured as a single pin RC controlled Schmitt trigger oscillator. CKO is available as a general purpose input
and/or HALT restart control.
TABLE I. Crystal Oscillator Configuration, TA e 25§ C
R1
(kX)
R2
(MX)
C1
(pF)
C2
(pF)
CKI Freq
(MHz)
Conditions
0
0
5.6
1
1
1
30
30
200
30 – 36
30 – 36
100 – 150
10
4
0.455
VCC e 5V
VCC e 2.5V
VCC e 5V
TABLE II. RC Oscillator Configuration, TA e 25§ C
R
(kX)
C
(pF)
CKI Freq.
(MHz)
Instr. Cycle
(ms)
Conditions
3.3
5.6
6.8
82
100
100
2.2 to 2.7
1.1 to 1.3
0.9 to 1.1
3.7 to 4.6
7.4 to 9.0
8.8 to 10.8
VCC e 5V
VCC e 5V
VCC e 5V
Note: (R/C Oscillator Configuration): 3k s R s 200k, 50 pF s C s 200 pF.
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12
Functional Description (Continued)
The device has three mask options for configuring the clock
input. The CKI and CKO pins are automatically configured
upon selecting a particular option.
ENI and ENTI bits select external and timer interrupt respectively. Thus the user can select either or both sources
to interrupt the microcontroller when GIE is enabled.
Ð Crystal (CKI/10); CKO for crystal configuration
Ð External (CKI/10); CKO available as G7 input
Ð R/C (CKI/10); CKO available as G7 input
G7 can be used either as a general purpose input or as a
control input to continue from the HALT mode.
IEDG selects the external interrupt edge (0 e rising edge,
1 e falling edge). The user can get an interrupt on both
rising and falling edges by toggling the state of IEDG bit
after each interrupt.
IPND and TPND bits signal which interrupt is pending. After
interrupt is acknowledged, the user can check these two
bits to determine which interrupt is pending. This permits the
interrupts to be prioritized under software. The pending flags
have to be cleared by the user. Setting the GIE bit high
inside the interrupt subroutine allows nested interrupts.
The software interrupt does not reset the GIE bit. This
means that the controller can be interrupted by other interrupt sources while servicing the software interrupt.
HALT MODE
The device supports a power saving mode of operation:
HALT. The controller is placed in the HALT mode by setting
the G7 data bit, alternatively the user can stop the clock
input. In the HALT mode all internal processor activities including the clock oscillator are stopped. The fully static architecture freezes the state of the controller and retains all
information until continuing. In the HALT mode, power requirements are minimal as it draws only leakage currents
and output current. The applied voltage (VCC) may be decreased down to Vr (minimum RAM retention voltage) without altering the state of the machine.
There are two ways to exit the HALT mode: via the RESET
or by the CKO pin. A low on the RESET line reinitializes the
microcontroller and starts executing from the address
0000H. A low to high transition on the CKO pin (only if the
external or R/C clock option selected) causes the microcontroller to continue with no reinitialization from the address following the HALT instruction. This also resets the
G7 data bit.
INTERRUPT PROCESSING
The interrupt, once acknowledged, pushes the program
counter (PC) onto the stack and the stack pointer (SP) is
decremented twice. The Global Interrupt Enable (GIE) bit is
reset to disable further interrupts. The microcontroller then
vectors to the address 00FFH and resumes execution from
that address. This process takes 7 cycles to complete. At
the end of the interrupt subroutine, any of the following
three instructions return the processor back to the main program: RET, RETSK or RETI. Either one of the three instructions will pop the stack into the program counter (PC). The
stack pointer is then incremented twice. The RETI instruction additionally sets the GIE bit to re-enable further interrupts.
Any of the three instructions can be used to return from a
hardware interrupt subroutine. The RETSK instruction
should be used when returning from a software interrupt
subroutine to avoid entering an infinite loop.
INTERRUPTS
There are three interrupt sources, as shown below.
A maskable interrupt on external G0 input (positive or negative edge sensitive under software control)
A maskable interrupt on timer underflow or timer capture
A non-maskable software/error interrupt on opcode zero
Note: There is always the possibility of an interrupt occurring during an instruction which is attempting to reset the GIE bit or any other interrupt
enable bit. If this occurs when a single cycle instruction is being used
to reset the interrupt enable bit, the interrupt enable bit will be reset
but an interrupt may still occur. This is because interrupt processing is
started at the same time as the interrupt bit is being reset. To avoid
this scenario, the user should always use a two, three or four cycle
instruction to reset interrupt enable bits.
INTERRUPT CONTROL
The GIE (global interrupt enable) bit enables the interrupt
function. This is used in conjunction with ENI and ENTI to
select one or both of the interrupt sources. This bit is reset
when interrupt is acknowledged.
13
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Functional Description (Continued)
TL/DD/10802 – 8
FIGURE 6. Interrupt Block Diagram
TABLE III
DETECTION OF ILLEGAL CONDITIONS
The device contains a hardware mechanism that allows it to
detect illegal conditions which may occur from coding errors, noise and ‘brown out’ voltage drop situations. Specifically it detects cases of executing out of undefined ROM
area and unbalanced stack situations.
Reading an undefined ROM location returns 00 (hexadecimal) as its contents. The opcode for a software interrupt is
also ‘00’. Thus a program accessing undefined ROM will
cause a software interrupt.
Reading an undefined RAM location returns an FF (hexadecimal). The subroutine stack grows down for each subroutine call. By initializing the stack pointer to the top of RAM,
the first unbalanced return instruction will cause the stack
pointer to address undefined RAM. As a result the program
will attempt to execute from FFFF (hexadecimal), which is
an undefined ROM location and will trigger a software interrupt.
SL0
SK Cycle Time
0
0
1
0
1
x
2tC
4tC
8tC
where,
tC is the instruction cycle clock.
MICROWIRE/PLUS OPERATION
Setting the BUSY bit in the PSW register causes the MICROWIRE/PLUS arrangement to start shifting the data. It
gets reset when eight data bits have been shifted. The user
may reset the BUSY bit by software to allow less than 8 bits
to shift. The devoce may enter the MICROWIRE/PLUS
mode either as a Master or as a Slave. Figure 8 shows how
two COP880C microcontrollers and several peripherals may
be interconnected using the MICROWIRE/PLUS arrangement.
MICROWIRE/PLUSTM
Master MICROWIRE/PLUS Operation
In the MICROWIRE/PLUS Master mode of operation the
shift clock (SK) is generated internally. The MICROWIRE/
PLUS Master always initiates all data exchanges. (See Figure 8 ). The MSEL bit in the CNTRL register must be set to
enable the SO and SK functions onto the G Port. The SO
and SK pins must also be selected as outputs by setting
appropriate bits in the Port G configuration register. Table IV
summarizes the bit settings required for Master mode of
operation.
MICROWIRE/PLUS is a serial synchronous bidirectional
communications interface. The MICROWIRE/PLUS capability enables the device to interface with any of National
Semiconductor’s MICROWIRE peripherals (i.e. A/D converters, display drivers, EEPROMS, etc.) and with other microcontrollers which support the MICROWIRE/PLUS interface. It consists of an 8-bit serial shift register (SIO) with
serial data input (SI), serial data output (SO) and serial shift
clock (SK). Figure 7 shows the block diagram of the MICROWIRE/PLUS interface.
The shift clock can be selected from either an internal
source or an external source. Operating the MICROWIRE/
PLUS interface with the internal clock source is called the
Master mode of operation. Similarly, operating the MICROWIRE/PLUS interface with an external shift clock is called
the Slave mode of operation.
The CNTRL register is used to configure and control the
MICROWIRE/PLUS mode. To use the MICROWIRE/PLUS ,
the MSEL bit in the CNTRL register is set to one. The SK
clock rate is selected by the two bits, SL0 and SL1, in the
CNTRL register. Table III details the different clock rates
that may be selected.
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SL1
SLAVE MICROWIRE/PLUS OPERATION
In the MICROWIRE/PLUS Slave mode of operation the SK
clock is generated by an external source. Setting the MSEL
bit in the CNTRL register enables the SO and SK functions
onto the G Port. The SK pin must be selected as an input
and the SO pin is selected as an output pin by appropriately
setting up the Port G configuration register. Table IV summarizes the settings required to enter the Slave mode of
operation.
The user must set the BUSY flag immediately upon entering
the Slave mode. This will ensure that all data bits sent by
the Master will be shifted properly. After eight clock pulses
the BUSY flag will be cleared and the sequence may be
repeated. (See Figure 8 .)
14
Functional Description (Continued)
MODE 1. TIMER WITH AUTO-LOAD REGISTER
TABLE IV
G4
G5
Config. Config.
Bit
Bit
1
1
0
1
1
0
0
0
G4
G5
G6
Fun.
Fun.
Fun.
SO
Int. SK
SI
TRI-STATE Int. SK
SI
MICROWIRE Master
Ext. SK
SI
MICROWIRE Slave
TRI-STATE Ext. SK
SI
MICROWIRE Slave
SO
In this mode of operation, the timer T1 counts down at the
instruction cycle rate. Upon underflow the value in the register R1 gets automatically reloaded into the timer which continues to count down. The timer underflow can be programmed to interrupt the microcontroller. A bit in the control
register CNTRL enables the TIO (G3) pin to toggle upon
timer underflows. This allow the generation of square-wave
outputs or pulse width modulated outputs under software
control. (See Figure 9. )
Operation
MICROWIRE Master
MODE 2. EXTERNAL COUNTER
In this mode, the timer T1 becomes a 16-bit external event
counter. The counter counts down upon an edge on the TIO
pin. Control bits in the register CNTRL program the counter
to decrement either on a positive edge or on a negative
edge. Upon underflow the contents of the register R1 are
automatically copied into the counter. The underflow can
also be programmed to generate an interrupt. (See Figure 9 )
TIMER/COUNTER
The device has a powerful 16-bit timer with an associated
16-bit register enabling them to perform extensive timer
functions. The timer T1 and its register R1 are each organized as two 8-bit read/write registers. Control bits in the
register CNTRL allow the timer to be started and stopped
under software control. The timer-register pair can be operated in one of three possible modes. Table V details various
timer operating modes and their requisite control settings.
MODE 3. TIMER WITH CAPTURE REGISTER
Timer T1 can be used to precisely measure external frequencies or events in this mode of operation. The timer T1
counts down at the instruction cycle rate. Upon the occurrence of a specified edge on the TIO pin the contents of the
timer T1 are copied into the register R1. Bits in the control
register CNTRL allow the trigger edge to be specified either
as a positive edge or as a negative edge. In this mode the
user can elect to be interrupted on the specified trigger
edge. (See Figure 10 .)
TL/DD/10802 – 9
FIGURE 7. MICROWIRE/PLUS Block Diagram
TL/DD/10802 – 10
FIGURE 8. MICROWIRE/PLUS Application
15
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Functional Description (Continued)
TABLE V. Timer Operating Modes
CNTRL
Bits
765
Operation Mode
T Interrupt
Timer
Counts
On
000
001
010
011
100
101
110
111
External Counter W/Auto-Load Reg.
External Counter W/Auto-Load Reg.
Not Allowed
Not Allowed
Timer W/Auto-Load Reg.
Timer W/Auto-Load Reg./Toggle TIO Out
Timer W/Capture Register
Timer W/Capture Register
Timer Underflow
Timer Underflow
Not Allowed
Not Allowed
Timer Underflow
Timer Underflow
TIO Pos. Edge
TIO Neg. Edge
TIO Pos. Edge
TIO Neg. Edge
Not Allowed
Not Allowed
tC
tC
tC
tC
TIMER PWM APPLICATION
Figure 11 shows how a minimal component D/A converter
can be built out of the Timer-Register pair in the Auto-Reload mode. The timer is placed in the ‘‘Timer with auto reload’’ mode and the TIO pin is selected as the timer output.
At the outset the TIO pin is set high, the timer T1 holds the
on time and the register R1 holds the signal off time. Setting
TRUN bit starts the timer which counts down at the instruction cycle rate. The underflow toggles the TIO output and
copies the off time into the timer, which continues to run. By
alternately loading in the on time and the off time at each
successive interrupt a PWM frequency can be easily generated.
TL/DD/10802–11
FIGURE 9. Timer/Counter Auto
Reload Mode Block Diagram
TL/DD/10802 – 13
TL/DD/10802–12
FIGURE 11. Timer Application
FIGURE 10. Timer Capture Mode Block Diagram
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16
RELATIVE
Control Registers
This mode is used for the JP instruction, the instruction field
is added to the program counter to get the new program
location. JP has a range of from b31 to a 32 to allow a one
byte relative jump (JP a 1 is implemented by a NOP instruction). There are no ‘pages’ when using JP, all 15 bits of PC
are used.
CNTRL REGISTER (ADDRESS X’00EE)
The Timer and MICROWIRE/PLUS control register contains
the following bits:
SL1 & SL0 Select the MICROWIRE/PLUS clock divide-by
IEDG
External interrupt edge polarity select
(0 e rising edge, 1 e falling edge)
MSEL
TRUN
TC3
TC2
TC1
TC1
Memory Map
Enable MICROWIRE/PLUS functions SO and
SK
Start/Stop the Timer/Counter (1 e run, 0 e
stop)
Timer input edge polarity select (0 e rising
edge, 1 e falling edge)
Selects the capture mode
Selects the timer mode
TC2
TC3
TRUN
MSEL
IEDG
SL1
BIT 7
All RAM, ports and registers (except A and PC) are mapped
into data memory address space.
Address
80 to BF Expansion Space for future use
C0 to CF Expansion Space for I/O and Registers
SL0
BIT 0
PSW REGISTER (ADDRESS X’00EF)
The PSW register contains the following select bits:
GIE
Global interrupt enable
ENI
External interrupt enable
BUSY MICROWIRE/PLUS busy shifting
IPND External interrupt pending
ENTI Timer interrupt enable
TPND Timer interrupt pending
C
Carry Flag
HC
Half carry Flag
HC
C
TPND
ENTI
IPND
Bit 7
BUSY
ENI
Contents
00 to 6F On Chip RAM Bytes
70 to 7F Unused RAM Address Space (Reads as all Ones)
GIE
Bit 0
Addressing Modes
REGISTER INDIRECT
This is the ‘‘normal’’ mode of addressing. The operand is
the memory addressed by the B register or X register.
DIRECT
The instruction contains an 8-bit address field that directly
points to the data memory for the operand.
IMMEDIATE
The instruction contains an 8-bit immediate field as the operand.
REGISTER INDIRECT
(AUTO INCREMENT AND DECREMENT)
This is a register indirect mode that automatically increments or decrements the B or X register after executing the
instruction.
D0 to DF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD – DF
On Chip I/O and Registers
Port L Data Register
Port L Configuration Register
Port L Input Pins (Read Only)
Reserved for Port L
Port G Data Register
Port G Configuration Register
Port G Input Pins (Read Only)
Port I Input Pins (Read Only)
Port C Data Register
Port C Configuration Register
Port C Input Pins (Read Only)
Reserved for Port C
Port D Data Register
Reserved for Port D
E0 to EF
E0 – E7
E8
E9
EA
EB
EC
ED
EE
EF
On Chip Functions and Registers
Reserved for Future Parts
Reserved
MICROWIRE/PLUS Shift Register
Timer Lower Byte
Timer Upper Byte
Timer Autoload Register Lower Byte
Timer Autoload Register Upper Byte
CNTRL Control Register
PSW Register
F0 to FF
FC
FD
FE
On Chip RAM Mapped as Registers
X Register
SP Register
B Register
Reading unused memory locations below 7FH will return all
ones. Reading other unused memory locations will return
undefined data.
17
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Instruction Set
REGISTER AND SYMBOL DEFINITIONS
Symbols
[B]
Memory indirectly addressed by B register
[X]
Memory indirectly addressed by X register
Mem Direct address memory or [B]
MemI Direct address memory or [B] or Immediate data
Imm 8-bit Immediate data
Reg
Register memory: addresses F0 to FF (Includes B, X
and SP)
Bit
Bit number (0 to 7)
w Loaded with
Ý Exchanged with
Registers
A
8-bit Accumulator register
B
8-bit Address register
X
8-bit Address register
SP
8-bit Stack pointer register
PC
15-bit Program counter register
PU
upper 7 bits of PC
PL
lower 8 bits of PC
C
1-bit of PSW register for carry
HC
Half Carry
GIE
1-bit of PSW register for global interrupt enable
Instruction Set
A w A a MemI
A w A a MemI a C, C w Carry
HC w Half Carry
A w A a MemI a C, C w Carry
HC w Half Carry
A w A and MemI
A w A or MemI
A w A xor MemI
Compare A and MemI, Do next if A e MemI
Compare A and MemI, Do next if A l MemI
Do next if lower 4 bits of B i Imm
Reg w Reg b 1, skip if Reg goes to 0
1 to bit,
Mem (bit e 0 to 7 immediate)
0 to bit,
Mem
If bit,
Mem is true, do next instr.
ADD
ADC
add
add with carry
SUBC
subtract with carry
AND
OR
XOR
IFEQ
IFGT
IFBNE
DRSZ
SBIT
Logical AND
Logical OR
Logical Exclusive-OR
IF equal
IF greater than
IF B not equal
Decrement Reg. ,skip if zero
Set bit
RBIT
Reset bit
IFBIT
If bit
X
LD A
LD mem
LD Reg
Exchange A with memory
Load A with memory
Load Direct memory Immed.
Load Register memory Immed.
A Ý Mem
A w MemI
Mem w Imm
Reg w Imm
X
X
LD A
LD A
LD M
Exchange A with memory [B]
Exchange A with memory [X]
Load A with memory [B]
Load A with memory [X]
Load Memory Immediate
A Ý [B]
(B w B g 1)
A Ý [X]
(X w X g 1)
A w [B]
(B w B g 1)
A w [X]
(X w X g 1)
[B] w Imm (B w B g 1)
CLRA
INCA
DECA
LAID
DCORA
RRCA
SWAPA
SC
RC
IFC
IFNC
Clear A
Increment A
Decrement A
Load A indirect from ROM
DECIMAL CORRECT A
ROTATE A RIGHT THRU C
Swap nibbles of A
Set C
Reset C
If C
If not C
Aw0
AwAa1
AwAb1
A w ROM(PU,A)
A w BCD correction (follows ADC, SUBC)
C x A7 x . . . x A0 x C
A7 . . . A4 Ý A3 . . . A0
C w 1, HC w 1
C w 0, HC w 0
If C is true, do next instruction
If C is not true, do next instruction
JMPL
JMP
JP
JSRL
JSR
JID
RET
RETSK
RETI
INTR
NOP
Jump absolute long
Jump absolute
Jump relative short
Jump subroutine long
Jump subroutine
Jump indirect
Return from subroutine
Return and Skip
Return from Interrupt
Generate an interrupt
No operation
PC w ii (ii e 15 bits, 0 to 32k)
PC11..0 w i (i e 12 bits)
PC w PC a r (r is b 31 to a 32, not 1)
[SP] w PL,[SP-1] w PU,SP-2,PC w ii
[SP] w PL,[SP-1] w PU,SP-2,PC11.. 0 w i
PL w ROM(PU,A)
SP a 2,PL w [SP],PU w [SP-1]
SP a 2,PL w [SP],PU w [SP-1],Skip next instruction
SP a 2,PL w [SP],PU w [SP-1],GIE w 1
[SP] w PL,[SP b 1] w PU,SP-2,PC w 0FF
PC w PC a 1
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18
19
JP -18
JP -17
JP -2
JP -1
where,
i
D
LD 0FF,Ý1
LD 0FE,Ýi
LD 0FD,Ýi
LD 0FC,Ýi
LD 0FB,Ýi
LD 0FA,Ýi
LD 0F9,Ýi
LD 0F8,Ýi
LD 0F7,Ýi
LD 0F6,Ýi
LD 0F5,Ýi
LD 0F4,Ýi
LD 0F3,Ýi
LD 0F2,Ýi
LD 0F1,Ýi
LD 0F0,Ýi
C
B
*
LD A,
[X]
DIR
LD Md,
Ýi
LD A,
[Xb]
LD A,
[X a ]
*
NOP
*
X A,
[X]
*
*
X A,
[Xb]
X A,
[X a ]
*
RRCA
A
*
LD A,
[B]
JSRL
JMPL
LD A,
[Bb]
LD A,
[B a ]
*
*
*
X A,
[B]
JID
LAID
X A,
[Bb]
X A,
[B a ]
SC
RC
9
*
LD
[B], Ýi
LD A,
Md
X A,Md
LD
[Bb],Ýi
LD
[B a ],Ýi
*
LD A,
Ýi
OR A,
Ýi
XOR A,
Ýi
AND A,
Ýi
ADD A,
Ýi
IFGT A,
Ýi
IFEQ A,
Ýi
SUBC A,
Ýi
ADC A,
Ýi
8
RETI
RET
RETSK
*
DECA
INCA
IFNC
IFC
OR
A,[B]
XOR
A,[B]
AND
A,[B]
ADD
A,[B]
IFGT
A,[B]
IFEQ
A,[B]
SUBC
A,[B]
ADC A,
[B]
Md is a directly addressed memory location
DRSZ 0FF
DRSZ 0FE
DRSZ 0FD
DRSZ 0FC
DRSZ 0FB
DRSZ 0FA
DRSZ 0F9
DRSZ 0F8
DRSZ 0F7
DRSZ 0F6
DRSZ 0F5
DRSZ 0F4
DRSZ 0F3
DRSZ 0F2
DRSZ 0F1
DRSZ 0F0
is the immediate data
JP -16
JP -19
JP -3
JP -0
JP -20
JP -24
JP -8
JP -4
JP -25
JP -9
JP -21
JP -26
JP -10
JP -5
JP -27
JP -11
JP -22
JP -28
JP -12
JP -6
JP -29
JP -13
JP -23
JP -30
JP -14
JP -7
E
JP -31
F
JP -15
RBIT
7,[B]
RBIT
6, [B]
RBIT
5,[B]
RBIT
4,[B]
RBIT
3,[B]
RBIT
2,[B]
RBIT
1,[B]
RBIT
0,[B]
*
DCORA
SWAPA
CLRA
*
*
*
*
6
5
LD B, 0
LD B, 1
LD B, 2
LD B, 3
LD B, 4
LD B, 5
LD B, 6
LD B, 7
LD B, 8
LD B, 9
LD B, 0A
LD B, 0B
LD B, 0C
LD B, 0D
LD B, 0E
LD B, 0F
4
IFBNE 0F
IFBNE 0E
IFBNE 0D
IFBNE 0C
IFBNE 0B
IFBNE 0A
IFBNE 9
IFBNE 8
IFBNE 7
IFBNE 6
IFBNE 5
IFBNE 4
IFBNE 3
IFBNE 2
IFBNE 1
IFBNE 0
* is an unused opcode (see following table)
SBIT
7,[B]
SBIT
6, [B]
SBIT
5,[B]
SBIT
4,[B]
SBIT
3,[B]
SBIT
2,[B]
SBIT
1,[B]
SBIT
0,[B]
IFBIT
7,[B]
IFBIT
6,[B]
IFBIT
5,[B]
IFBIT
4,[B]
IFBIT
3,[B]
IFBIT
2,[B]
IFBIT
1,[B]
IFBIT
0,[B]
7
Bits 7 – 4
3
JSR
0F00-0FFF
JSR
0E00 –0EFF
JSR
0D00-0DFF
JSR
0C00-0CFF
JSR
0B00-0BFF
JSR
0A00-0AFF
JSR
0900-09FF
JSR
0800-08FF
JSR
0700-07FF
JSR
0600-06FF
JSR
0500-05FF
JSR
0400-04FF
JSR
0300-03FF
JSR
0200-02FF
JSR
0100-01FF
JSR
0000-00FF
2
JMP
0F00-0FFF
JMP
0E00 –0EFF
JMP
0D00-0DFF
JMP
0C00-0CFF
JMP
0B00-0BFF
JMP
0A00-0AFF
JMP
0900-09FF
JMP
0800-08FF
JMP
0700-07FF
JMP
0600-06FF
JMP
0500-05FF
JMP
0400-04FF
JMP
0300-03FF
JMP
0200-02FF
JMP
0100-01FF
JMP
0000-00FF
1
JP a 32
JP a 31
JP a 30
JP a 29
JP a 28
JP a 27
JP a 26
JP a 25
JP a 24
JP a 23
JP a 22
JP a 21
JP a 20
JP a 19
JP a 18
JP a 17
0
JP a 16
JP a 15
JP a 14
JP a 13
JP a 12
JP a 11
JP a 10
JP a 9
JP a 8
JP a 7
JP a 6
JP a 5
JP a 4
JP a 3
JP a 2
INTR
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
OPCODE LIST
Bits 3 – 0
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Instruction Execution Time
BYTES and CYCLES per
INSTRUCTION
Most instructions are single byte (with immediate addressing mode instruction taking two bytes).
Most single instructions take one cycle time to execute.
Skipped instructions require x number of cycles to be
skipped, where x equals the number of bytes in the skipped
instruction opcode.
See the BYTES and CYCLES per INSTRUCTION table for
details.
The following table shows the number of bytes and cycles
for each instruction in the format of byte/cycle.
Arithmetic and Logic Instructions
[B]
Direct
Immed.
ADD
ADC
SUBC
AND
OR
XOR
IFEQ
IFGT
IFBNE
DRSZ
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
SBIT
RBIT
IFBIT
1/1
1/1
1/1
1/3
3/4
3/4
3/4
Memory Transfer Instructions
Register
Register Indirect
Indirect Direct Immed.
Auto Incr & Decr
[B] [X]
[B a , Bb] [X a , Xb]
X A,*
1/1 1/3
LD A,*
1/1 1/3
LD B,Imm
LD B,Imm
LD Mem,Imm
2/2
LD Reg,Imm
2/3
2/3
1/2
1/2
2/2
1/1
2/3
1/3
1/3
(If B k 16)
(If B l 15)
3/3
2/2
2/3
* e l Memory location addressed by B or X or directly.
Instructions Using A & C
CLRA
INCA
DECA
LAID
DCORA
RRCA
SWAPA
SC
RC
IFC
IFNC
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Transfer of Control Instructions
1/1
1/1
1/1
1/3
1/1
1/1
1/1
1/1
1/1
1/1
1/1
JMPL
JMP
JP
JSRL
JSR
JID
RET
RETSK
RETI
INTR
NOP
20
3/4
2/3
1/3
3/5
2/5
1/3
1/5
1/5
1/5
1/7
1/1
BYTES and CYCLES per
INSTRUCTION (Continued)
Development Support
SUMMARY
The following table shows the instructions assigned to unused opcodes. This table is for information only. The operations performed are subject to change without notice. Do
not use these opcodes.
Unused
Opcode
Instruction
60
61
62
63
67
8C
99
9F
A7
A8
NOP
NOP
NOP
NOP
NOP
RET
NOP
LD [B], Ýi
X A, [B]
NOP
# iceMASTERTM : IM-COP8/400ÐFull feature in-circuit emulation for all COP8 products. A full set of COP8 Basic
and Feature Family device and package specific probes
are available.
# COP8 Debug Module: Moderate cost in-circuit emulation
Unused
Opcode
Instruction
A9
AF
B1
B4
B5
B7
B9
BF
NOP
LD A, [B]
C x HC
NOP
NOP
X A, [X]
NOP
LD A, [X]
and development programming unit.
# COP8
Evaluation and Programming Unit: EPUCOP880CÐlow cost In-circuit simulation and development programming unit.
# Assembler: COP8-DEV-IBMA. A DOS installable cross
development Assembler, Linker, Librarian and Utility
Software Development Tool Kit.
# C Compiler: COP8C. A DOS installable cross development Software Tool Kit.
# OTP/EPROM Programmer Support: Covering needs
from engineering prototype, pilot production to full production environments.
Option List
The mask programmable options are listed out below. The
options are programmed at the same time as the ROM pattern to provide the user with hardware flexibility to use a
variety of oscillator configuration.
OPTION 1: CKI INPUT
e 1 Crystal
(CKI/10) CKO for crystal configuration
e 2 External (CKI/10) CKO available as G7
input
e 3 R/C
(CKI/10) CKO available as G7
input
OPTION 2: BONDING
e 1 44-Pin PLCC
e 2 40-Pin DIP
e 3 28-Pin SO
e 4 28-Pin DIP
The following option information is to be sent to National
along with the EPROM.
Option Data
Option 1 ValueÐis: CKI Input
Option 2 ValueÐis: COP Bonding
21
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Development Support (Continued)
# Watch windows, content updated automatically at each
iceMASTER (IM) IN-CIRCUIT EMULATION
The iceMASTER IM-COP8/400 is a full feature, PC based,
in-circuit emulation tool developed and marketed by MetaLink Corporation to support the whole COP8 family of products. National is a resale vendor for these products.
See Figure 12 for configuration.
execution break.
# Instruction by instruction memory/register changes displayed on source window when in single step operation.
# Single base unit and debugger software reconfigurable to
support the entire COP8 family; only the probe personality needs to change. Debugger software is processor customized, and reconfigured from a master model file.
The iceMASTER IM-COP8/400 with its device specific
COP8 Probe provides a rich feature set for developing, testing and maintaining product:
# Processor specific symbolic display of registers and bit
level assignments, configured from master model file.
# Real-time in-circuit emulation; full 2.4V–5.5V operation
# Halt/Idle mode notification.
# On-line HELP customized to specific processor using
range, full DC-10 MHz clock. Chip options are programmable or jumper selectable.
master model file.
# Direct connection to application board by package com-
# Includes a copy of COP8-DEV-IBMA assembler and link-
patible socket or surface mount assembly.
er SDK.
IM Order Information
# Full 32 kbyte of loadable programming space that overlays (replaces) the on-chip ROM or EPROM. On-chip
RAM and I/O blocks are used directly or recreated on
the probe as necessary.
Base Unit
# Full 4k frame synchronous trace memory. Address, in-
IM-COP8/400-1
struction, and 8 unspecified, circuit connectable trace
lines. Display can be HLL source (e.g., C source), assembly or mixed.
iceMASTER base unit,
110V power supply
IM-COP8/400-2
iceMASTER base unit,
220V power supply
# A full 64k hardware configurable break, trace on, trace
off control, and pass count increment events.
iceMASTER Probe
# Tool set integrated interactive symbolic debuggerÐsupports both assembler (COFF) and C Compiler (.COD)
linked object formats.
# Real time performance profiling analysis; selectable
bucket definition.
MHW-880C20DWPC
20 DIP
MHW-880C28DWPC
28 DIP
MHW-880CJ40DWPC
40 DIP
MHW-880CJ44PWPC
44 PLCC
DIP to SO Adapters
MHW-SOIC20
20 SO
MHW-SOIC28
28 DIP
TL/DD/10802 – 24
FIGURE 12. COP8 iceMASTER Environment
http://www.national.com
22
Development Support (Continued)
# Processor specific symbolic display of registers and bit
iceMASTER DEBUG MODULE (DM)
level assignments, configured from master model file.
The iceMASTER Debug Module is a PC based, combination
in-circuit emulation tool and COP8 based OTP/EPROM programming tool developed and marketed by MetaLink Corporation to support the whole COP8 family of products. National is a resale vendor for these products.
See Figure 13 for configuration.
# Halt/Idle mode notification.
# Programming menu supports full product line of programmable OTP and EPROM COP8 products. Program data
is taken directly from the overlay RAM.
# Programming of 44 PLCC and 68 PLCC parts requires
external programming. adapters.
The iceMASTER Debug Module is a moderate cost development tool. It has the capability of in-circuit emulation for a
specific COP8 microcontroller and in addition serves as a
programming tool for COP8 OTP and EPROM product families. Summary of features is as follows:
# Includes wallmount power supply.
# On-board VPP generator from 5V input or connection to
external supply supported. Rquires VPP level adjustment
per the family programming specification (correct level is
provided on an on-screen pop-down display).
# Real-time in-circuit emulation; full operating voltage
range operation, full DC-10 MHz clock.
# On-line HELP customized to specific processor using
# All processor I/O pins can be cabled to an application
master model file.
development board with package compatible cable to
socket and surface mount assembly.
# Includes a copy of COP8-DEV-IBMA assembler and linker SDK.
DM Order Information
# Full 32 kbyte of loadable programming space that overlays (replaces) the on-chip ROM or EPROM. On-chip
RAM and I/O blocks are used directly or recreated as
necessary.
Debug Model Unit
COP8-DM/880C
# 100 frames of synchronous trace memory. The display
can be HLL source (C source), assembly or mixed. The
most recent history prior to a break is available in the
trace memory.
Cable Adapters
# Configured break points; uses INTR instruction which is
modestly intrusive.
# SoftwareÐonly supported features are selectable.
# Tool set integrated interactive symbolic debuggerÐsupports both assembler (COFF) and C Compiler (.COD)
SDK linked object formats.
DM-COP8/20D
20 DIP
DM-COP8/28D
28 DIP
DM-COP8/40D
40 DIP
DM-COP8/44P
44 PLCC
DIP to SO Adapters
# Instruction by instruction memory/register changes displayed when in single step operation.
DM-COP8/20D-SO
20 SO
DM-COP8/28D-SO
28 SO
# Debugger software is processor customized, and reconfigured from a master model file.
TL/DD/10802 – 25
FIGURE 13. COP8-DM Environment
23
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Development Support (Continued)
# Tool set integrated interactive symbolic debuggerÐsup-
iceMASTER EVALUATION PROGRAMMING UNIT (EPU)
The iceMASTER EPU-COP880C is a PC based, in-circuit
simulation tool to support the feature family COP8 products.
See Figure 14 for configuration.
ports both assembler (COFF) and C Compiler (.COD)
SDK linked object formats.
# Instruction by instruction memory/register changes displayed when in single step operation.
The simulation capability is a very low cost means of evaluating the general COP8 architecture. In addition, the EPU
has programming capability, with added adapters, for programming the whole COP8 product family of OTP and
EPROM products. The product includes the following features:
# Processor specific symbolic display of registers and bit
level assignments, configured from master model file.
# Halt/Idle mode notification. Restart requires special handling.
# Programming menu supports full product line of programmable OTP and EPROM COP8 products. Only a 40 ZIF
socket is available on the EPU unit. Adapters are available for other part package configurations.
# Non-real-time in-circuit simulation. Program overlay
memory is PC resident; instructions are downloaded over
RS-232 as executed. Approximate performance is
20 kHz.
# Integral wall mount power supply provides 5V and develops the required VPP to program parts.
# Includes a 40 pin DIP cable adapter. Other target pack-
# Includes a copy of COP8-DEV-IBMA assembler, linker
ages are not supported. All processor I/O pins are cabled to the application development environment.
SDK.
EPU Order Information
# Full 32 kbyte of loadable programmable space that overlays (replaces) the on-chip ROM or EPROM. On-chip
RAM and I/O blocks are used directly or recreated as
necessary.
Evaluation Programming Unit
EPU-COP880C
# On-chip timer and WATCHDOG execution are not well
synchronized to the instruction simulation.
# 100 frames of synchronous trace memory. The display
Evaluation Programming Unit
with debugger and programmer
control software with 40 ZIF
programming socket.
General Programming Adapters
can be HLL source (e.g., C source), assembly or mixed.
The most recent history prior to a break is available in the
trace memory.
# Up to eight software configured break points; uses INTR
COP8-PGMA-DS
28 and 20 DIP and SOIC adapter
COP8-PGMA-DS44P
28 and 20 DIP and SOIC plus 44
PLCC adapter
instruction which is modestly intrusive.
# Common look-feel debugger software across all MetaLink productsÐonly supported features are selectable.
TL/DD/10802 – 26
FIGURE 14. EPU-COP8 Tool Environment
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24
Development Support (Continued)
COP8 C COMPILER
COP8 ASSEMBLER/LINKER SOFTWARE
DEVELOPMENT TOOL KIT
National Semiconductor offers a relocateable COP8 macro
cross assembler, linker, librarian and utility software development tool kit. Features are summarized as follows:
A C Compiler is developed and marketed by Byte Craft Limited. The COP8C compiler is a fully integrated development
tool specifically designed to support the compact embedded configuration of the COP8 family of products.
Features are summarized as follows:
# Basic and Feature Family instruction set by ‘‘device’’
type.
# ANSI C with some restrictions and extensions that opti-
#
#
#
#
#
#
#
mize development for the COP8 embedded application.
Nested macro capability.
Extensive set of assembler directives.
Supported on PC/DOS platform.
Generates National standard COFF output files.
Integrated Linker and Librarian.
Integrated utilities to generate ROM code file outputs.
DUMPCOFF utility.
This product is integrated as a part of MetaLink tools as a
development kit, fully supported by the MetaLink debugger.
It may be ordered separately or it is bundled with the MetaLink products at no additional cost.
# BITS data type extension. Register declaration Ýpragma
with direct bit level definitions.
# C language support for interrupt routines.
# Expert system, rule based code geration and optimization.
# Performs consistency checks against the architectural
definitions of the target COP8 device.
# Generates program memory code.
# Supports linking of compiled object or COP8 assembled
object formats.
# Global optimization of linked code.
# Symbolic debug load format fully sourced level support-
Order Information
ed by the MetaLink debugger.
Assembler SDK:
COP8-DEV-IBMA
INDUSTRY WIDE OTP/EPROM PROGRAMMING
SUPPORT
Programming support, in addition to the MetaLink development tools, is provided by a full range of independent approved vendors to meet the needs from the engineering
laboratory to full production.
Assembler SDK on installable 3.5×
PC/DOS Floppy Disk Drive format.
Periodic upgrades and most recent
version is available on National’s
BBS and Internet.
Approved List
Manufacturer
North
America
Europe
Asia
BP
Microsystems
(800) 225-2102
(713) 688-4600
Fax: (713) 688-0920
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Data I/O
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Call Asia
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Needhams
(916) 924-8037
Fax: (916) 924-8065
25
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Development Support (Continued)
DIAL-A-HELPER via WorldWide Web Browser
ftp://nscmicro.nsc.com
AVAILABLE LITERATURE
For more information, please see the COP8 Basic Family
User’s Manual, Literature Number 620895, COP8 Feature
Family User’s Manual, Literature Number 620897 and National’s Family of 8-bit Microcontrollers COP8 Selection
Guide, Literature Number 630009.
National Semiconductor on the WorldWide Web
See us on the WorldWide Web at: http://www.national.com
CUSTOMER RESPONSE CENTER
Complete product information and technical support is available from National’s customer response centers.
DIAL-A-HELPER SERVICE
Dial-A-Helper is a service provided by the Microcontroller
Applications group. The Dial-A-Helper is an Electronic Information System that may be accessed as a Bulletin Board
System (BBS) via data modem, as an FTP site on the Internet via standard FTP client application or as an FTP site on
the Internet using a standard Internet browser such as Netscape or Mosaic.
The Dial-A-Helper system provides access to an automated
information storage and retrieval system . The system capabilities include a MESSAGE SECTION (electronic mail,
when accessed as a BBS) for communications to and from
the Microcontroller Applications Group and a FILE SECTION which consists of several file areas where valuable
application software and utilities could be found.
CANADA/U.S.: Tel:
EUROPE:
support @ tevm2.nsc.com
email:
europe.support @ nsc.com
Deutsch Tel:
a 49 (0) 180-530 85 85
English Tel:
a 49 (0) 180-532 78 32
Fran3ais Tel:
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JAPAN:
Tel:
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S.E. ASIA:
Beijing Tel:
( a 86) 10-6856-8601
Shanghai Tel:
( a 86) 21-6415-4092
DIAL-A-HELPER BBS via a Standard Modem
Modem: CANADA/U.S.: (800) NSC-MICRO
(800) 672-6427
EUROPE:
( a 49) 0-8141-351332
Baud:
14.4k
Set-Up:
Length:
8-Bit
Parity:
None
Stop Bit:
1
Operation:
24 Hours, 7 Days
Hong Kong Tel: ( a 852) 2737-1600
DIAL-A-HELPER via FTP
ftp nscmicro.nsc.com
user:
anonymous
password:
username @ yourhost.site.domain
http://www.national.com
(800)272-9959
email:
26
Korea Tel:
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a 886-2-521-3288
AUSTRALIA:
Tel:
( a 61) 3-9558-9999
INDIA:
Tel:
( a 91) 80-559-9467
Physical Dimensions inches, (millimeters)
Small Outline Molded Dual-In-Line Package (M)
Order Number COP882C-XXX/WM, COP982C-XXX/WM, COP682C-XXX/WM or COP982CH-XXX/WM
NS Package Number M20B
Small Outline Molded Dual-In-Line Package (M)
Order Number COP881C-XXX/WM, COP981C-XXX/WM, COP681C-XXX/WM or COP981CH-XXX/WM
NS Package Number M28B
27
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Physical Dimensions inches, (millimeters)
Molded Dual-In-Line Package (N)
Order Number COP882C-XXX/N, COP682C-XXX/N, COP982C-XXX/N or COP982CH-XXX/N
NS Package Number N20B
Molded Dual-In-Line Package (N)
Order Number COP881C-XXX/N, COP681C-XXX/N, COP981C-XXX/N or COP981CH-XXX/N
NS Package Number N28B
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28
Physical Dimensions inches, (millimeters) (Continued)
Molded Dual-In-Line Package (N)
Order Number COP880C-XXX/N, COP680C-XXX/N, COP980C-XXX/N or COP980CH-XXX/N
NS Package Number N40A
29
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COP680C/COP681C/COP682C/COP880C/COP881C/COP882C/COP980C/COP981C/COP982C
Microcontrollers
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Plastic Leaded Chip Carrier (V)
Order Number COP880C-XXX/V, COP680C-XXX/V, COP980C-XXX/V or COP980CH-XXX/V
NS Package Number V44A
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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
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Tel: 81-043-299-2308
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.