PROCESS CP310 Central Small Signal Transistor TM Semiconductor Corp. NPN - High Voltage Transistor Chip PROCESS DETAILS Process EPITAXIAL PLANAR Die Size 26 x 26 MILS Die Thickness 9.0 MILS Base Bonding Pad Area 6.1 x 4.9 MILS Emitter Bonding Pad Area 5.2 x 5.2 MILS Top Side Metalization Al - 30,000Å Back Side Metalization Au - 18,000Å GEOMETRY GROSS DIE PER 4 INCH WAFER 16,880 BACKSIDE COLLECTOR 145 Adams Avenue Hauppauge, NY 11788 USA Tel: (631) 435-1110 Fax: (631) 435-1824 www.centralsemi.com PRINCIPAL DEVICE TYPES 2N3439 2N3440 CMPTA42 CMPTA44 CMPT6517 CXTA44 CZTA42 CZTA44 MPSA42 MPSA44 R2 (1-August 2002) Central TM Semiconductor Corp. 145 Adams Avenue Hauppauge, NY 11788 USA Tel: (631) 435-1110 Fax: (631) 435-1824 www.centralsemi.com PROCESS CP310 Typical Electrical Characteristics R2 (1-August 2002)