Intersil CP82C59A Cmos priority interrupt controller Datasheet

82C59A
®
Data Sheet
March 17, 2006
FN2784.5
CMOS Priority Interrupt Controller
Features
The Intersil 82C59A is a high performance CMOS Priority
Interrupt Controller manufactured using an advanced 2µm
CMOS process. The 82C59A is designed to relieve the
system CPU from the task of polling in a multilevel
priority system. The high speed and industry standard
configuration of the 82C59A make it compatible with
microprocessors such as 80C286, 80286, 80C86/88,
8086/88, 8080/85 and NSC800.
• Pb-Free Plus Anneal Available (RoHS Compliant)
The 82C59A can handle up to eight vectored priority
interrupting sources and is cascadable to 64 without
additional circuitry. Individual interrupting sources can be
masked or prioritized to allow custom system configuration.
Two modes of operation make the 82C59A compatible with
both 8080/85 and 80C86/88/286 formats.
Static CMOS circuit design ensures low operating power.
The Intersil advanced CMOS process results in performance
equal to or greater than existing equivalent products at a
fraction of the power.
• 12.5MHz, 8MHz and 5MHz Versions Available
• High Speed, “No Wait-State” Operation with 12.5MHz
80C286 and 8MHz 80C86/88
• Pin Compatible with NMOS 8259A
• 80C86/88/286 and 8080/85/86/88/286 Compatible
• Eight-Level Priority Controller, Expandable to
64 Levels
• Programmable Interrupt Modes
• Individual Request Mask Capability
• Fully Static Design
• Fully TTL Compatible
• Low Power Operation
- ICCSB. . . . . . . . . . . . . . . . . . . . . . . . . . 10µA Maximum
- ICCOP . . . . . . . . . . . . . . . . . . . . . . 1mA/MHz Maximum
• Single 5V Power Supply
• Commercial, Industrial and Military Operating
Temperature Ranges Available
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2002, 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
82C59A
Ordering Information
PART NUMBER
5MHz
PART
MARKING
8MHz
PART
MARKING
12.5MHz
PART
MARKING
CP82C59A
CP82C59A
CP82C59A-12
CP82C59A-12
CP82C59AZ
(Note)
CP82C59AZ
CP82C59A-12Z
(Note)
CS82C59A
CS82C59A
CS82C59A96
PACKAGE
28 Ld PDIP
TEMP
RANGE (°C)
PKG.
DWG. #
0 to +70
E28.6
CP82C59A-12Z 28 Ld PDIP*
(Pb-Free)
0 to +70
E28.6
CS82C59A-12
CS82C59A-12
28 Ld PLCC
0 to +70
N28.45
CS82C59A
CS82C59A-1296
CS82C59A-12
28 Ld PLCC
(Tape & Reel)
0 to +70
N28.45
CS82C59AZ
(Note)
CS82C59AZ
CS82C59A-12Z
(Note)
CS82C59A-12Z 28 Ld PLCC
(Pb-Free)
0 to +70
N28.45
CS82C59AZ96
(Note)
CS82C59AZ
CS82C59A-12Z96 CS82C59A-12Z 28 Ld PLCC
(Note)
(Pb-Free, Tape
& Reel)
0 to +70
N28.45
IS82C59A
IS82C59A
IS82C59A-12
IS82C59A-12
28 Ld PLCC
-40 to +85
N28.45
IS82C59AX96
IS82C59A
IS82C59A-12X96
IS82C59A-12
28 Ld PLCC
(Tape & Reel)
-40 to +85
N28.45
IS82C59AZ
(Note)
IS82C59AZ
IS82C59A-12Z
(Note)
IS82C59A-12Z
28 Ld PLCC
(Pb-Free)
-40 to +85
N28.45
IS82C59AZX96
(Note)
IS82C59AZ
IS82C59A-12Z96
(Note)
IS82C59A-12Z
28 Ld PLCC
(Pb-Free, Tape
& Reel)
-40 to +85
N28.45
ID82C59A
ID82C59A
28 Ld CERDIP
-40 to +85
F28.6
MD82C59A/B
MD82C59A/B
-55 to +125
F28.6
5962-8501601YA 59625962-8501602YA
8501601YA
59628501602YA
SMD#
-55 to +125
F28.6
5962-85016023A
596285016023A
28 Pad CLCC SMD#
-55 to +125
J28.A
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2
FN2784.5
March 17, 2006
82C59A
Pinouts
D7 4
25 IR7
D6 5
24 IR6
D5 6
INTA
26 INTA
A0
RD 3
VCC
27 A0
CS
28 VCC
WR 2
WR
CS 1
D7
82C59A (PLCC, CLCC)
TOP VIEW
RD
82C59A (PDIP, CERDIP)
TOP VIEW
4
3
2
1
28
27
26
D6 5
25 IR7
D5 6
24 IR6
23 IR5
D4 7
23 IR5
D4 7
22 IR4
D3 8
22 IR4
D3 8
21 IR3
D2 9
21 IR3
D2 9
20 IR2
D1 10
20 IR2
D1 10
19 IR1
D0 11
18 IR0
CAS 0 12
17 INT
CAS 1 13
16 SP/EN
GND 14
15 CAS 2
D0 11
PIN
17
18
IR0
GND
16
INT
CAS 1
15
SP/ EN
14
CAS 2
13
CAS 0
19 IR1
12
DESCRIPTION
D7 - D0
Data Bus (Bidirectional)
RD
Read Input
WR
Write Input
A0
Command Select Address
CS
Chip Select
CAS 2 - CAS 0
Cascade Lines
SP/EN
Slave Program Input Enable
INT
Interrupt Output
INTA
Interrupt Acknowledge Input
IR0 - IR7
Interrupt Request Inputs
Functional Diagram
INT
INTA
DATA
BUS
BUFFER
D7-D0
RD
WR
A0
CONTROL LOGIC
READ/
WRITE
LOGIC
IN SERVICE
REG
(ISR)
CS
CAS 0
CAS 1
CAS 2
CASCADE
BUFFER
COMPARATOR
SP/EN
PRIORITY
RESOLVER
INTERRUPT
REQUEST
REG
(IRR)
IR0
IR1
IR2
IR3
IR4
IR5
IR6
IR7
INTERRUPT MASK REG
(IMR)
INTERNAL BUS
FIGURE 1.
3
FN2784.5
March 17, 2006
82C59A
Pin Description
SYMBOL
TYPE
DESCRIPTION
VCC
I
VCC: The +5V power supply pin. A 0.1µF capacitor between pins 28 and 14 is recommended for decoupling.
GND
I
GROUND
CS
I
CHIP SELECT: A low on this pin enables RD and WR communications between the CPU and the 82C59A. INTA
functions are independent of CS.
WR
I
WRITE: A low on this pin when CS is low enables the 82C59A to accept command words from the CPU.
RD
I
READ: A low on this pin when CS is low enables the 82C59A to release status onto the data bus for the CPU.
D7 - D0
I/O
BIDIRECTIONAL DATA BUS: Control, status, and interrupt-vector information is transferred via this bus.
CAS0 - CAS2
I/O
CASCADE LINES: The CAS lines form a private 82C59A bus to control a multiple 82C59A structure. These
pins are outputs for a master 82C59A and inputs for a slave 82C59A.
SP/EN
I/O
SLAVE PROGRAM/ENABLE BUFFER: This is a dual function pin. When in the Buffered Mode it can be used
as an output to control buffer transceivers (EN). When not in the Buffered Mode it is used as an input to
designate a master (SP = 1) or slave (SP = 0).
INT
O
INTERRUPT: This pin goes high whenever a valid interrupt request is asserted. It is used to interrupt the CPU,
thus, it is connected to the CPU's interrupt pin.
IR0 - IR7
I
INTERRUPT REQUESTS: Asynchronous inputs. An interrupt request is executed by raising an IR input (low to
high), and holding it high until it is acknowledged (Edge Triggered Mode), or just by a high level on an IR input
(Level Triggered Mode). Internal pull-up resistors are implemented on IR0 - 7.
INTA
I
INTERRUPT ACKNOWLEDGE: This pin is used to enable 82C59A interrupt-vector data onto the data bus by
a sequence of interrupt acknowledge pulses issued by the CPU.
A0
I
ADDRESS LINE: This pin acts in conjunction with the CS, WR, and RD pins. It is used by the 82C59A to
decipher various Command Words the CPU writes and status the CPU wishes to read. It is typically connected
to the CPU A0 address line (A1 for 80C86/88/286).
Functional Description
CPU - DRIVEN
MULTIPLEXER
Interrupts in Microcomputer Systems
Microcomputer system design requires that I/O devices such
as keyboards, displays, sensors and other components
receive servicing in an efficient manner so that large
amounts of the total system tasks can be assumed by the
microcomputer with little or no effect on throughput.
The most common method of servicing such devices is the
Polled approach. This is where the processor must test each
device in sequence and in effect “ask” each one if it needs
servicing. It is easy to see that a large portion of the main
program is looping through this continuous polling cycle and
that such a method would have a serious, detrimental effect
on system throughput, thus, limiting the tasks that could be
assumed by the microcomputer and reducing the cost
effectiveness of using such devices.
CPU
RAM
I/O (1)
ROM
I/O (2)
I/O (N)
FIGURE 2. POLLED METHOD
4
FN2784.5
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82C59A
The Programmable Interrupt Controller (PlC) functions as an
overall manager in an Interrupt-Driven system. It accepts
requests from the peripheral equipment, determines which of
the incoming requests is of the highest importance (priority),
ascertains whether the incoming request has a higher
priority value than the level currently being serviced, and
issues an interrupt to the CPU based on this determination.
A more desirable method would be one that would allow the
microprocessor to be executing its main program and only
stop to service peripheral devices when it is told to do so by
the device itself. In effect, the method would provide an
external asynchronous input that would inform the processor
that it should complete whatever instruction that is currently
being executed and fetch a new routine that will service the
requesting device. Once this servicing is complete, however,
the processor would resume exactly where it left off.
Each peripheral device or structure usually has a special
program or “routine” that is associated with its specific
functional or operational requirements; this is referred to as a
“service routine”. The PlC, after issuing an interrupt to the
CPU, must somehow input information into the CPU that can
“point” the Program Counter to the service routine
associated with the requesting device. This “pointer” is an
address in a vectoring table and will often be referred to, in
this document, as vectoring data.
This is the Interrupt-driven method. It is easy to see that
system throughput would drastically increase, and thus,
more tasks could be assumed by the microcomputer to
further enhance its cost effectiveness.
INT
CPU
82C59A Functional Description
The 82C59A is a device specifically designed for use in real
time, interrupt driven microcomputer systems. It manages
eight levels of requests and has built-in features for
expandability to other 82C59As (up to 64 levels). It is
programmed by system software as an I/O peripheral. A
selection of priority modes is available to the programmer so
that the manner in which the requests are processed by the
82C59A can be configured to match system requirements.
The priority modes can be changed or reconfigured
dynamically at any time during main program operation. This
means that the complete interrupt structure can be defined
as required, based on the total system environment.
PIC
RAM
I/O (1)
ROM
I/O (2)
I/O (N)
FIGURE 3. INTERRUPT METHOD
INT
INTA
DATA
BUS
BUFFER
D 7 - D0
CONTROL LOGIC
READ/
WRITE
LOGIC
RD
WR
A0
IN
SERVICE
REG
(ISR)
CS
CAS 0
CAS 1
CAS 2
CASCADE
BUFFER
COMPARATOR
PRIORITY
RESOLVER
INTERRUPT
REQUEST
REG
(IRR)
IR0
IR1
IR2
IR3
IR4
IR5
IR6
IR7
INTERRUPT MASK REG
(IMR)
INTERNAL BUS
SP/EN
FIGURE 4. 82C59A FUNCTIONAL DIAGRAM
5
FN2784.5
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82C59A
Interrupt Request Register (IRR) and In-Service Register
(ISR)
The interrupts at the IR input lines are handled by two registers
in cascade, the Interrupt Request Register (lRR) and the InService Register (lSR). The IRR is used to indicate all the
interrupt levels which are requesting service, and the ISR is
used to store all the interrupt levels which are currently being
serviced.
Priority Resolver
This logic block determines the priorities of the bits set in the
lRR. The highest priority is selected and strobed into the
corresponding bit of the lSR during the INTA sequence.
Interrupt Mask Register (IMR)
The lMR stores the bits which disable the interrupt lines to be
masked. The IMR operates on the output of the IRR.
Masking of a higher priority input will not affect the interrupt
request lines of lower priority.
Interrupt (INT)
This output goes directly to the CPU interrupt input. The
VOH level on this line is designed to be fully compatible with
the 8080, 8085, 8086/88, 80C86/88, 80286, and 80C286
input levels.
Interrupt Acknowledge (INTA)
INTA pulses will cause the 82C59A to release vectoring
information onto the data bus. The format of this data
depends on the system mode (µPM) of the 82C59A.
Data Bus Buffer
Read (RD)
A LOW on this input enables the 82C59A to send the status
of the Interrupt Request Register (lRR), In-Service Register
(lSR), the Interrupt Mask Register (lMR), or the interrupt
level (in the poll mode) onto the Data Bus.
A0
This input signal is used in conjunction with WR and RD
signals to write commands into the various command
registers, as well as to read the various status registers of
the chip. This line can be tied directly to one of the system
address lines.
The Cascade Buffer/Comparator
This function block stores and compares the IDs of all
82C59As used in the system. The associated three I/O pins
(CAS0 - 2) are outputs when the 82C59A is used as a
master and are inputs when the 82C59A is used as a slave.
As a master, the 82C59A sends the ID of the interrupting
slave device onto the CAS0 - 2 lines. The slave, thus
selected will send its preprogrammed subroutine address
onto the Data Bus during the next one or two consecutive
INTA pulses. (See section “Cascading the 82C59A”.)
Interrupt Sequence
The powerful features of the 82C59A in a microcomputer
system are its programmability and the interrupt routine
addressing capability. The latter allows direct or indirect
jumping to the specified interrupt routine requested without
any polling of the interrupting devices. The normal sequence
of events during an interrupt depends on the type of CPU
being used.
This 3-state, bidirectional 8-bit buffer is used to interface the
82C59A to the System Data Bus. Control words and status
information are transferred through the Data Bus Buffer.
Read/Write Control Logic
The function of this block is to accept output commands from
the CPU. It contains the Initialization Command Word (lCW)
registers and Operation Command Word (OCW) registers
which store the various control formats for device operation.
This function block also allows the status of the 82C59A to
be transferred onto the Data Bus.
Chip Select (CS)
A LOW on this input enables the 82C59A. No reading or
writing of the device will occur unless the device is selected.
Write (WR)
A LOW on this input enables the CPU to write control words
(lCWs and OCWs) to the 82C59A.
6
FN2784.5
March 17, 2006
82C59A
ADDRESS BUS (16)
CONTROL BUS
I/OR
I/OW
INT
INTA
DATA BUS (8)
CS
CAS 0
CAS 1
CAS 2
CASCADE
LINES
SP/EN
A0
D7 - D 0
RD
WR
INT
INTA
IRQ
2
IRQ
IRQ
1
0
82C59A
IRQ
7
SLAVE PROGRAM/
ENABLE BUFFER
IRQ
6
IRQ
IRQ
IRQ
5
4
3
INTERRUPT
REQUESTS
FIGURE 5. 82C59A STANDARD SYSTEM BUS INTERFACE
These events occur in an 8080/8085 system:
1. One or more of the INTERRUPT REQUEST lines
(IR0 - IR7) are raised high, setting the corresponding IRR
bit(s).
2. The 82C59A evaluates those requests in the priority
resolver and sends an interrupt (INT) to the CPU, if
appropriate.
3. The CPU acknowledges the lNT and responds with an
INTA pulse.
4. Upon receiving an lNTA from the CPU group, the highest
priority lSR bit is set, and the corresponding lRR bit is
reset. The 82C59A will also release a CALL instruction
code (11001101) onto the 8-bit data bus through D0 - D7.
5. This CALL instruction will initiate two additional INTA
pulses to be sent to 82C59A from the CPU group.
6. These two INTA pulses allow the 82C59A to release its
preprogrammed subroutine address onto the data bus.
The lower 8-bit address is released at the first INTA pulse
and the higher 8-bit address is released at the second
INTA pulse.
7. This completes the 3-byte CALL instruction released by
the 82C59A. In the AEOI mode, the lSR bit is reset at the
end of the third INTA pulse. Otherwise, the lSR bit
remains set until an appropriate EOI command is issued
at the end of the interrupt sequence.
The events occurring in an 80C86/88/286 system are the
same until step 4.
7
4. The 82C59A does not drive the data bus during the first
INTA pulse.
5. The 80C86/88/286 CPU will initiate a second INTA pulse.
During this INTA pulse, the appropriate ISR bit is set and
the corresponding bit in the IRR is reset. The 82C59A
outputs the 8-bit pointer onto the data bus to be read by
the CPU.
6. This completes the interrupt cycle. In the AEOI mode, the
ISR bit is reset at the end of the second INTA pulse. Otherwise, the ISR bit remains set until an appropriate EOI
command is issued at the end of the interrupt subroutine.
If no interrupt request is present at step 4 of either sequence
(i.e., the request was too short in duration), the 82C59A will
issue an interrupt level 7. If a slave is programmed on IR bit
7, the CAS lines remain inactive and vector addresses are
output from the master 82C59A.
Interrupt Sequence Outputs
8080, 8085 Interrupt Response Mode
This sequence is timed by three INTA pulses. During the first
lNTA pulse, the CALL opcode is enabled onto the data bus.
First Interrupt Vector Byte Data: Hex CD
Call Code
D7
D6
D5
D4
D3
D2
D1
D0
1
1
0
0
1
1
0
1
During the second INTA pulse, the lower address of the
appropriate service routine is enabled onto the data bus.
FN2784.5
March 17, 2006
82C59A
When interval = 4 bits, A5 - A7 are programmed, while
A0 - A4 are automatically inserted by the 82C59A. When
interval = 8, only A6 and A7 are programmed, while A0 - A5
are automatically inserted.
slave if so programmed) will send a byte of data to the
processor with the acknowledged interrupt code composed
as follows (note the state of the ADI mode control is ignored
and A5 - A11 are unused in the 86/88/286 mode).
CONTENT OF SECOND INTERRUPT VECTOR BYTE
CONTENT OF INTERRUPT VECTOR BYTE FOR
80C86/88/286 SYSTEM MODE
IR
INTERVAL = 4
D7
D6
D5
D4
D3
D2
D1
D0
7
A7
A6
A5
1
1
1
0
0
6
A7
A6
A5
1
1
0
0
0
5
A7
A6
A5
1
0
1
0
0
4
A7
A6
A5
1
0
0
0
0
3
A7
A6
A5
0
1
1
0
0
2
A7
A6
A5
0
1
0
0
0
1
A7
A6
A5
0
0
1
0
0
0
A7
A6
A5
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
lR7
T7
T6
T5
T4
T3
1
1
1
lR6
T7
T6
T5
T4
T3
1
1
0
IR5
T7
T6
T5
T4
T3
1
0
1
IR4
T7
T6
T5
T4
T3
1
0
0
IR3
T7
T6
T5
T4
T3
0
1
1
IR2
T7
T6
T5
T4
T3
0
1
0
IR1
T7
T6
T5
T4
T3
0
0
1
IR0
T7
T6
T5
T4
T3
0
0
0
Programming the 82C59A
IR
INTERVAL = 8
D7
D6
DS
D4
D3
D2
D1
D0
7
A7
A6
1
1
1
0
0
0
6
A7
A6
1
1
0
0
0
0
5
A7
A6
1
0
1
0
0
0
4
A7
A6
1
0
0
0
0
0
3
A7
A6
0
1
1
0
0
0
2
A7
A6
0
1
0
0
0
0
1
A7
A6
0
0
1
0
0
0
0
A7
A6
0
0
0
0
0
0
During the third INTA pulse, the higher address of the
appropriate service routine, which was programmed as byte 2
of the initialization sequence (A8 - A15), is enabled onto the
bus.
The 82C59A accepts two types of command words
generated by the CPU:
1. Initialization Command Words (ICWs): Before normal
operation can begin, each 82C59A in the system must be
brought to a starting point - by a sequence of 2 to 4 bytes
timed by WR pulses.
2. Operation Command Words (OCWs): These are the
command words which command the 82C59A to operate
in various interrupt modes. Among these modes are:
a. Fully nested mode.
b. Rotating priority mode.
c. Special mask mode.
d. Polled mode.
The OCWs can be written into the 82C59A anytime after
initialization.
Initialization Command Words (lCWs)
CONTENT OF THIRD INTERRUPT VECTOR BYTE
D7
D6
D5
D4
D3
D2
D1
D0
General
A15
A14
A13
A12
A11
A10
A9
A8
Whenever a command is issued with A0 = 0 and D4 = 1, this
is interpreted as Initialization Command Word 1 (lCW1).
lCW1 starts the initialization sequence during which the
following automatically occur:
80C86, 8OC88, 80C286 Interrupt Response Mode
80C86/88/286 mode is similar to 8080/85 mode except that
only two Interrupt Acknowledge cycles are issued by the
processor and no CALL opcode is sent to the processor. The
first interrupt acknowledge cycle is similar to that of 8080/85
systems in that the 82C59A uses it to internally freeze the
state of the interrupts for priority resolution and, as a master,
it issues the interrupt code on the cascade lines. On this first
cycle, it does not issue any data to the processor and leaves
its data bus buffers disabled. On the second interrupt
acknowledge cycle in the 86/88/286 mode, the master (or
8
a. The edge sense circuit is reset, which means that following initialization, an interrupt request (IR) input must make
a low-to-high transition to generate an interrupt.
b. The Interrupt Mask Register is cleared.
c. lR7 input is assigned priority 7.
d. Special Mask Mode is cleared and Status Read is set to
lRR.
FN2784.5
March 17, 2006
82C59A
e. If lC4 = 0, then all functions selected in lCW4 are set to
zero. (Non-Buffered mode (see note), no Auto-EOI,
8080/85 system).
LTlM:
If LTlM = 1, then the 82C59A will operate in the level
interrupt mode. Edge detect logic on the interrupt
inputs will be disabled.
NOTE:
ADI:
ALL address interval. ADI = 1 then interval = 4; ADI
= 0 then interval = 8.
Master/Slave in ICW4 is only used in the buffered mode.
ICW1
SNGL: Single. Means that this is the only 82C59A in the
system. If SNGL = 1, no ICW3 will be issued.
IC4:
ICW2
If this bit is set - lCW4 has to be issued. If lCW4 is
not needed, set lC4 = 0.
Initialization Command Word 3 (ICW3)
NO (SNGL = 1)
IN
CASCADE
MODE
YES (SNGL = 0))
ICW3
NO (IC4 = 0)
IS ICW4
NEEDED
YES (IC4 = 1)
ICW4
READY TO ACCEPT
INTERRUPT REQUESTS
This word is read only when there is more than one 82C59A
in the system and cascading is used, in which case
SNGL = 0. It will load the 8-bit slave register. The functions of
this register are:
a. In the master mode (either when SP = 1, or in buffered
mode when M/S = 1 in lCW4) a “1” is set for each slave in
the bit corresponding to the appropriate IR line for the
slave. The master then will release byte 1 of the call
sequence (for 8080/85 system) and will enable the corresponding slave to release bytes 2 and 3 (for 80C86/88/
286, only byte 2) through the cascade lines.
b. In the slave mode (either when SP = 0, or if BUF = 1 and
M/S = 0 in lCW4), bits 2 - 0 identify the slave. The slave
compares its cascade input with these bits and if they are
equal, bytes 2 and 3 of the call sequence (or just byte 2 for
80C86/88/286) are released by it on the Data Bus.
NOTE: (The slave address must correspond to the IR line it is
connected to in the master ID).
Initialization Command Word 4 (ICW4)
FIGURE 6. 82C59A INITIALIZATION SEQUENCE
Initialization Command Words 1 and 2 (ICW1, lCW2)
A5 - A15: Page starting address of service routines. In an
8080/85 system the 8 request levels will generate CALLS to
8 locations equally spaced in memory. These can be
programmed to be spaced at intervals of 4 or 8 memory
locations, thus, the 8 routines will occupy a page of 32 or 64
bytes, respectively.
The address format is 2 bytes long (A0 - A15). When the
routine interval is 4, A0 - A4 are automatically inserted by the
82C59A, while A5 - A15 are programmed externally. When
the routine interval is 8, A0 - A5 are automatically inserted by
the 82C59A while A6 - A15 are programmed externally.
The 8-byte interval will maintain compatibility with current
software, while the 4-byte interval is best for a compact jump
table.
SFNM: If SFNM = 1, the special fully nested mode is programmed.
BUF:
If BUF = 1, the buffered mode is programmed. In
buffered mode, SP/EN becomes an enable output
and the master/slave determination is by M/S.
M/S:
If buffered mode is selected: M/S = 1 means the
82C59A is programmed to be a master, M/S = 0
means the 82C59A is programmed to be a slave. If
BUF = 0, M/S has no function.
AEOI:
If AEOI = 1, the automatic end of interrupt mode is
programmed.
µPM:
Microprocessor mode: µPM = 0 sets the 82C59A for
8080/85 system operation, µPM = 1 sets the
82C59A for 80C86/88/286 system operation.
In an 80C86/88/286 system, A15 - A11 are inserted in the
five most significant bits of the vectoring byte and the
82C59A sets the three least significant bits according to the
interrupt level. A10 - A5 are ignored and ADI (Address
interval) has no effect.
9
FN2784.5
March 17, 2006
82C59A
ICW1
A0
0
D7
A7
D6
A6
D5
D4
D3
D2
D1
D0
A5
1
LTIM
ADI
SNGL
IC4
1 = ICW4 needed
0 = No ICW4 needed
1 = Single
0 = Cascade Mode
CALL address interval
1 = Interval of 4
0 = Interval of 8
1 = Level triggered mode
0 = Edge triggered mode
A7 - A5 of Interrupt vector address
(MCS-80/85 mode only)
ICW2
A0
1
D7
D6
A14
A15
T7
D5
D4
A13
T6
A12
T5
D3
D2
A11
A10
T4
D1
A9
D0
A8
T3
A15 - A8 of interrupt vector address
(MCS80/85 mode)
T7 - T3 of interrupt vector address
(8086/8088 mode)
ICW3 (MASTER DEVICE)
A0
D7
D6
D5
D4
D3
D2
D1
D0
1
S7
S6
S5
S4
S3
S2
S1
S0
1 = IR input has a slave
0 = IR input does not have a slave
ICW3 (SLAVE DEVICE)
A0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
0
0
ID2
ID1
ID0
SLAVE ID (NOTE)
0
1
2
3
4
5
6
7
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
ICW4
A0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
SFNM
BUF
M/S
AEOI
µPM
1 = 8086/8088 mode
0 = MCS-80/85 mode
1 = Auto EOI
0 = Normal EOI
0
X
- Non buffered mode
1
0
- Buffered mode slave
1
1
- Buffered mode master
1 = Special fully nested moded
0 = Not special fully nested mode
NOTE:
Slave ID is equal to the corresponding master IR input.
FIGURE 7. 82C59A INITIALIZATION COMMAND WORD FORMAT
10
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March 17, 2006
82C59A
Operation Command Words (OCWs)
After the Initialization Command Words (lCWs) are
programmed into the 82C59A, the device is ready to accept
interrupt requests at its input lines. However, during the
82C59A operation, a selection of algorithms can command
the 82C59A to operate in various modes through the
Operation Command Words (OCWs).
OPERATION COMMAND WORDS (OCWs)
A0
D7
D6
D5
D4
D3
D2
D1
D0
M3
M2
M1
M0
0
L2
L1
L0
1
P
RR
RIS
trailing edge of the last INTA. While the IS bit is set, all
further interrupts of the same or lower priority are inhibited,
while higher levels will generate an interrupt (which will be
acknowledged only if the microprocessor internal interrupt
enable flip-flop has been re-enabled through software).
After the initialization sequence, IR0 has the highest priority
and IR7 the lowest. Priorities can be changed, as will be
explained in the rotating priority mode or via the set priority
command.
OCW1
1
M7
M6
M5
M4
OCW2
0
R
SL
EOI
0
OCW3
0
0
ESMM SMM
0
Operation Command Word 1 (OCW1)
OCW1 sets and clears the mask bits in the Interrupt Mask
Register (lMR) M7 - M0 represent the eight mask bits. M = 1
indicates the channel is masked (inhibited), M = 0 indicates
the channel is enabled.
Operation Command Word 2 (OCW2)
R, SL, EOI - These three bits control the Rotate and End of
Interrupt modes and combinations of the two. A chart of
these combinations can be found on the Operation
Command Word Format.
L2, L1, L0 - These bits determine the interrupt level acted
upon when the SL bit is active.
Operation Command Word 3 (OCW3)
ESMM - Enable Special Mask Mode. When this bit is set to 1
it enables the SMM bit to set or reset the Special Mask
Mode. When ESMM = 0, the SMM bit becomes a “don’t
care”.
SMM - Special Mask Mode. If ESMM = 1 and SMM = 1, the
82C59A will enter Special Mask Mode. If ESMM = 1 and
SMM = 0, the 82C59A will revert to normal mask mode.
When ESMM = 0, SMM has no effect.
Fully Nested Mode
This mode is entered after initialization unless another mode
is programmed. The interrupt requests are ordered in priority
from 0 through 7 (0 highest). When an interrupt is
acknowledged the highest priority request is determined and
its vector placed on the bus. Additionally, a bit of the Interrupt
Service register (IS0 - 7) is set. This bit remains set until the
microprocessor issues an End of Interrupt (EOI) command
immediately before returning from the service routine, or if
the AEOI (Automatic End of Interrupt) bit is set, until the
11
FN2784.5
March 17, 2006
82C59A
OCW1
A0
D7
D6
D5
D4
D3
D2
D1
D0
1
M7
M6
M5
M4
M3
M2
M1
M0
Interrupt Mask
1 = Mask set
0 = Mask reset
OCW2
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
R
SL
EOI
0
0
L2
L1
L0
0
0
Non-specific EOI command
1
IR LEVEL TO BE
ACTED UPON
0
1
2
3
4
5
6
7
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
End of interrupt
† Specific EOI command
0
1
1
1
0
1
Rotate on non-specific EOI command
1
0
0
Rotate in automatic EOI mode (set)
0
0
0
Rotate in automatic EOI mode (clear)
1
1
1
† Rotate on specific EOI command
1
1
0
† Set priority command
0
1
0
Automatic rotation
Specific rotation
No operation
† L0 - L2 are used
OCW3
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
ESMM
SMM
0
1
P
RR
RIS
READ REGISTER COMMAND
0
1
0
1
0
0
1
1
Read IR reg on Read IS reg on
No Action next RD pulse next RD pulse
1 = Poll command
0 = No poll command
SPECIAL MASK MODE
0
1
0
1
0
0
1
1
Reset special
No Action mask
Set special
mask
FIGURE 8. 82C59A OPERATION COMMAND WORD FORMAT
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82C59A
End of Interrupt (EOI)
The In-Service (IS) bit can be reset either automatically
following the trailing edge of the last in sequence INTA pulse
(when AEOI bit in lCW1 is set) or by a command word that
must be issued to the 82C59A before returning from a
service routine (EOI Command). An EOI command must be
issued twice if servicing a slave in the Cascade mode, once
for the master and once for the corresponding slave.
There are two forms of EOl command: Specific and NonSpecific. When the 82C59A is operated in modes which
preserve the fully nested structure, it can determine which IS
bit to reset on EOI. When a Non-Specific command is issued
the 82C59A will automatically reset the highest IS bit of
those that are set, since in the fully nested mode the highest
IS level was necessarily the last level acknowledged and
serviced. A non-specific EOI can be issued with OCW2
(EOl = 1, SL = 0, R = 0).
IS7
IS6
IS5
IS4
IS3
IS2
IS1
IS0
“IS” Status
0
1
0
1
0
0
0
0
Priority
Status
7
6
5
4
3
2
1
0
lowest
highest
After Rotate (lR4 was serviced, all other priorities rotated
correspondingly)
IS7
IS6
IS5
IS4
IS3
IS2
IS1
IS0
“IS” Status
0
1
0
0
0
0
0
0
Priority
Status
2
1
0
7
6
5
4
3
highest
lowest
When a mode is used which may disturb the fully nested
structure, the 82C59A may no longer be able to determine
the last level acknowledged. In this case a Specific End of
Interrupt must be issued which includes as part of the
command the IS level to be reset. A specific EOl can be
issued with OCW2 (EOI = 1, SL = 1, R = 0, and L0 - L2 is the
binary level of the IS bit to be reset).
There are two ways to accomplish Automatic Rotation using
OCW2, the Rotation on Non-Specific EOI Command (R = 1,
SL = 0, EOI = 1) and the Rotate in Automatic EOI Mode
which is set by (R = 1, SL = 0, EOI = 0) and cleared by
(R = 0, SL = 0, EOl = 0).
An lRR bit that is masked by an lMR bit will not be cleared by
a non-specific EOI if the 82C59A is in the Special Mask
Mode.
The programmer can change priorities by programming the
lowest priority and thus, fixing all other priorities; i.e., if IR5 is
programmed as the lowest priority device, then IR6 will have
the highest one.
Automatic End of Interrupt (AEOI) Mode
If AEOI = 1 in lCW4, then the 82C59A will operate in AEOl
mode continuously until reprogrammed by lCW4. In this
mode the 82C59A will automatically perform a non-specific
EOI operation at the trailing edge of the last interrupt
acknowledge pulse (third pulse in 8080/85, second in
80C86/88/286). Note that from a system standpoint, this
mode should be used only when a nested multilevel interrupt
structure is not required within a single 82C59A.
Automatic Rotation (Equal Priority Devices)
In some applications there are a number of interrupting
devices of equal priority. In this mode a device, after being
serviced, receives the lowest priority, so a device requesting
an interrupt will have to wait, in the worst case until each of 7
other devices are serviced at most once. For example, if the
priority and “in service” status is:
Before Rotate (lR4 the highest priority requiring service)
Specific Rotation (Specific Priority)
The Set Priority command is issued in OCW2 where: R = 1,
SL = 1, L0 - L2 is the binary priority level code of the lowest
priority device.
Observe that in this mode internal status is updated by software control during OCW2. However, it is independent of the
End of Interrupt (EOI) command (also executed by OCW2).
Priority changes can be executed during an EOI command
by using the Rotate on Specific EOl command in OCW2
(R = 1, SL = 1, EOI = 1, and L0 - L2 = IR level to receive
lowest priority).
Interrupt Masks
Each Interrupt Request input can be masked individually by
the Interrupt Mask Register (IMR) programmed through
OCW1. Each bit in the lMR masks one interrupt channel if it
is set (1). Bit 0 masks IR0, Bit 1 masks IR1 and so forth.
Masking an IR channel does not affect the operation of other
channels.
Special Mask Mode
Some applications may require an interrupt service routine
to dynamically alter the system priority structure during its
execution under software control. For example, the routine
may wish to inhibit lower priority requests for a portion of its
execution but enable some of them for another portion.
13
FN2784.5
March 17, 2006
82C59A
disabling its interrupt input. Service to devices is achieved by
software using a Poll command.
The difficulty here is that if an Interrupt Request is
acknowledged and an End of Interrupt command did not
reset its IS bit (i.e., while executing a service routine), the
82C59A would have inhibited all lower priority requests with
no easy way for the routine to enable them.
The Poll command is issued by setting P = 1 in OCW3. The
82C59A treats the next RD pulse to the 82C59A (i.e., RD =
0, CS = 0) as an interrupt acknowledge, sets the appropriate
IS bit if there is a request, and reads the priority level.
Interrupt is frozen from WR to RD.
That is where the Special Mask Mode comes in. In the
Special Mask Mode, when a mask bit is set in OCW1, it
inhibits further interrupts at that level and enables interrupts
from all other levels (lower as well as higher) that are not
masked.
The word enabled onto the data bus during RD is:
Thus, any interrupts may be selectively enabled by loading
the mask register.
The Special Mask Mode is set by OCW3 where: ESMM = 1,
SMM = 1, and cleared where ESMM = 1, SMM = 0.
D7
D6
D5
D4
D3
D2
D1
D0
I
-
-
-
-
W2
W1
W0
W0 - W2: Binary code of the highest priority level requesting service.
I:
Poll Command
This mode is useful if there is a routine command common to
several levels so that the INTA sequence is not needed
(saves ROM space). Another application is to use the poll
mode to expand the number of priority levels to more than 64.
In this mode, the INT output is not used or the
microprocessor internal Interrupt Enable flip flop is reset,
LTIM BIT
0 = EDGE
1 = LEVEL
TO OTHER PRIORITY CELLS
CLR ISR
EDGE
SENSE
LATCH
CLR
Q
SET ISR
REQUEST
LATCH
D Q
IR
D Q
INTA
CONTROL
LOGIC
NONMASKED
REQ
MASK LATCH
C Q
80C86/
88/286
MODE
PRIORITY
RESOLVER
IN - SERVICE
LATCH
SET
8080/85
MODE
ISR BIT
SET
CLR
Q
VCC
Equal to a “1” if there is an interrupt.
C
CLR
FREEZE
INTA
FREEZE
FREEZE
READ WRITE
IRR MASK
READ IMR
READ ISR
MASTER CLEAR
NOTES:
1. Master clear active only during ICW1.
2. FREEZE is active during INTA and poll sequence only.
3. Truth Table for D-latch.
C
D
Q
Operation
1
D1
D1
Follow
0
X
Qn-1
Hold
14
FN2784.5
March 17, 2006
82C59A
Reading the 82C59A Status
Edge and Level Triggered Modes
The input status of several internal registers can be read to
update the user information on the system. The following
registers can be read via OCW3 (lRR and ISR) or OCW1
(lMR).
This mode is programmed using bit 3 in lCW1.
Interrupt Request Register (IRR): 8-bit register which
contains the levels requesting an interrupt to be
acknowledged. The highest request level is reset from the
lRR when an interrupt is acknowledged. lRR is not affected
by lMR.
In-Service Register (ISR): 8-bit register which contains the
priority levels that are being serviced. The ISR is updated
when an End of Interrupt Command is issued.
Interrupt Mask Register: 8-bit register which contains the
interrupt request lines which are masked.
The lRR can be read when, prior to the RD pulse, a Read
Register Command is issued with OCW3 (RR = 1, RIS = 0).
The ISR can be read when, prior to the RD pulse, a Read
Register Command is issued with OCW3 (RR = 1, RIS = 1).
There is no need to write an OCW3 before every status read
operation, as long as the status read corresponds with the
previous one: i.e., the 82C59A “remembers” whether the lRR
or ISR has been previously selected by the OCW3. This is
not true when poll is used. In the poll mode, the 82C59A
treats the RD following a “poll write” operation as an INTA.
After initialization, the 82C59A is set to lRR.
For reading the lMR, no OCW3 is needed. The output data bus
will contain the lMR whenever RD is active and A0 = 1 (OCW1).
Polling overrides status read when P = 1, RR = 1 in OCW3.
If LTlM = “0”, an interrupt request will be recognized by a low to
high transition on an IR input. The IR input can remain high
without generating another interrupt.
If LTIM = “1”, an interrupt request will be recognized by a “high”
level on an IR input, and there is no need for an edge detection.
The interrupt request must be removed before the EOI
command is issued or the CPU interrupt is enabled to prevent a
second interrupt from occurring.
The priority cell diagram shows a conceptual circuit of the level
sensitive and edge sensitive input circuitry of the 82C59A. Be
sure to note that the request latch is a transparent D type latch.
In both the edge and level triggered modes the IR inputs
must remain high until after the falling edge of the first INTA.
If the IR input goes low before this time a DEFAULT lR7 will
occur when the CPU acknowledges the interrupt. This can
be a useful safeguard for detecting interrupts caused by
spurious noise glitches on the IR inputs. To implement this
feature the lR7 routine is used for “clean up” simply
executing a return instruction, thus, ignoring the interrupt. If
lR7 is needed for other purposes a default lR7 can still be
detected by reading the ISR. A normal lR7 interrupt will set
the corresponding ISR bit, a default IR7 won’t. If a default
IR7 routine occurs during a normal lR7 routine, however, the
ISR will remain set. In this case it is necessary to keep track
of whether or not the IR7 routine was previously entered. If
another lR7 occurs it is a default.
In power sensitive applications, it is advisable to place the
82C59A in the edge-triggered mode with the IR lines
normally high. This will minimize the current through the
internal pull-up resistors on the IR pins.
80C86/88/286
8080/85
IR
INT
80C86/88/286
INTA
LATCH
ARM
(NOTE 1)
LATCH
ARM
(NOTE 1)
EARLIEST IR
CAN BE
REMOVED
8080/85
LATCH
ARM
(NOTE 1)
NOTE:
1. Edge triggered mode only.
FIGURE 10. IR TRIGGERING TIMING REQUIREMENTS
15
FN2784.5
March 17, 2006
82C59A
The Special Fully Nested Mode
This modification forces the use of software programming to
determine whether the 82C59A is a master or a slave. Bit 3
in ICW4 programs the buffered mode, and bit 2 in lCW4
determines whether it is a master or a slave.
This mode will be used in the case of a big system where
cascading is used, and the priority has to be conserved
within each slave. In this case the special fully nested mode
will be programmed to the master (using lCW4). This mode
is similar to the normal nested mode with the following
exceptions:
Cascade Mode
The 82C59A can be easily interconnected in a system of one
master with up to eight slaves to handle up to 64 priority
levels.
a. When an interrupt request from a certain slave is in service, this slave is not locked out from the master’s priority
logic and further interrupt requests from higher priority
IRs within the slave will be recognized by the master and
will initiate interrupts to the processor. (In the normal
nested mode a slave is masked out when its request is in
service and no higher requests from the same slave can
be serviced.
The master controls the slaves through the 3 line cascade
bus (CAS2 - 0). The cascade bus acts like chip selects to the
slaves during the INTA sequence.
In a cascade configuration, the slave interrupt outputs (INT)
are connected to the master interrupt request inputs. When a
slave request line is activated and afterwards acknowledged,
the master will enable the corresponding slave to release the
device routine address during bytes 2 and 3 of INTA. (Byte 2
only for 80C86/88/286).
b. When exiting the Interrupt Service routine the software
has to check whether the interrupt serviced was the only
one from that slave. This is done by sending a non-specific End of Interrupt (EOI) command to the slave and
then reading its In-Service register and checking for zero.
If it is empty, a non-specified EOI can be sent to the master, too. If not, no EOI should be sent.
The cascade bus lines are normally low and will contain the
slave address code from the leading edge of the first INTA
pulse to the trailing edge of the last INTA pulse. Each
82C59A in the system must follow a separate initialization
sequence and can be programmed to work in a different
mode. An EOI command must be issued twice: once for the
master and once for the corresponding slave. Chip select
decoding is required to activate each 82C59A.
Buffered Mode
When the 82C59A is used in a large system where bus
driving buffers are required on the data bus and the
cascading mode is used, there exists the problem of
enabling buffers
NOTE:
The buffered mode will structure the 82C59A to send an
enable signal on SP/EN to enable the buffers. In this mode,
whenever the 82C59A’s data bus outputs are enabled, the
SP/EN output becomes active.
Auto EOI is supported in the slave mode for the 82C59A.
The cascade lines of the Master 82C59A are activated only
for slave inputs, non-slave inputs leave the cascade line
inactive (low). Therefore, it is necessary to use a slave
address of 0 (zero) only after all other addresses are used.
ADDRESS BUS (16)
CONTROL BUS
INT REQ
DATA BUS (8)
A0 D7 - D0 INTA
SP/EN 7
6
5
4
3
INT
CAS 0
CAS 1
CAS 2
2 1 0
7
6
5
4
3
2
CS
SLAVE A
82C59A
GND
1
0
A0 D7 - D0 INTA
SP/EN 7
6
5
4
3
INT
CAS 0
CAS 1
CAS 2
2 1 0
7
6
5
4
3
2
CS
82C59A
GND
SLAVE B
1
0
CS A0 D7 - D0 INTA
CAS 0
CAS 1 MASTER 82C59A
CAS 2
SP/EN 7 6 5 4 3 2
VCC
7
6
5
4
3
2
INT
1
0
1
0
INTERRUPT REQUESTS
FIGURE 11. CASCADING THE 82C59A
16
FN2784.5
March 17, 2006
82C59A
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V
Input, Output or I/O Voltage . . . . . . . . . . . . . GND-0.5V to VCC+0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class I
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
CERDIP Package. . . . . . . . . . . . . . . . .
55
12
CLCC Package. . . . . . . . . . . . . . . . . . .
65
14
PDIP Package*. . . . . . . . . . . . . . . . . . .
55
N/A
PLCC Package. . . . . . . . . . . . . . . . . . .
65
N/A
Storage Temperature Range . . . . . . . . . . . . . . . . . . -65°C to +150°C
Maximum Junction Temperature Ceramic Package. . . . . . . . +175°C
Maximum Junction Temperature Plastic Package . . . . . . . . . +150°C
Maximum Lead Temperature Package (Soldering 10s). . . . . +300°C
(PLCC - Lead Tips Only)
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
Operating Conditions
Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range
CX82C59A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
IX82C59A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
MX82C59A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1250 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications
SYMBOL
VCC = +5.0V ±10%, TA = Operating Temperature Range
PARAMETER
MIN
MAX
UNITS
VlH
Logical One Input Voltage
2.0
2.2
-
V
V
VIL
Logical Zero Input Voltage
-
0.8
V
3.0
VCC -0.4
-
V
V
IOH = -2.5mA
lOH = -100µA
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
II
TEST CONDITIONS
C82C59A, I82C59A
M82C59A
-
0.4
V
lOL = +2.5mA
Input Leakage Current
-1.0
+1.0
µA
VIN = GND or VCC, Pins 1-3, 26-27
Output Leakage Current
-10.0
+10.0
µA
VOUT = GND or VCC, Pins 4-13, 15-16
IR Input Load Current
-
-200
10
µA
µA
VIN = 0V
VIN = VCC
lCCSB
Standby Power Supply Current
-
10
µA
VCC = 5.5V, VIN = VCC or GND Outputs
Open, (Note 1)
ICCOP
Operating Power Supply Current
-
1
mA/MHz
IO
ILIR
VCC = 5.0V, VIN = VCC or GND, Outputs Open,
TA = 25°C, (Note 2)
NOTES:
1. Except for IR0 - lR7 where VIN = VCC or open.
2. ICCOP = 1mA/MHz of peripheral read/write cycle time. (ex: 1.0µs I/O read/write cycle time = 1mA).
Capacitance TA = +25°C
SYMBOL
CIN
COUT
CI/O
PARAMETER
Input Capacitance
TYP
UNITS
15
pF
Output Capacitance
15
pF
I/O Capacitance
15
pF
AC Electrical Specifications
TEST CONDITIONS
FREQ = 1MHz, all measurements reference to
device GND.
VCC = +5.0V ±10%, GND = 0V, TA = Operating Temperature Range
5MHz
SYMBOL
PARAMETER
8MHz
12.5MHz
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
TEST
CONDITIONS
TIMING REQUIREMENTS
(1) TAHRL
A0/CS Setup to RD/INTA
10
-
10
-
5
-
ns
(2) TRHAX
A0/CS Hold after RD/INTA
5
-
5
-
0
-
ns
(3) TRLRH
RD/lNTA Pulse Width
235
-
160
-
60
-
ns
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82C59A
AC Electrical Specifications
VCC = +5.0V ±10%, GND = 0V, TA = Operating Temperature Range (Continued)
5MHz
SYMBOL
PARAMETER
8MHz
12.5MHz
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
(4) TAHWL
A0/CS Setup to WR
0
-
0
-
0
-
ns
(5) TWHAX
A0/CS Hold after WR
5
-
5
-
0
-
ns
(6) TWLWH
WR Pulse Width
165
-
95
-
60
-
ns
(7) TDVWH
Data Setup to WR
240
-
160
-
70
-
ns
5
-
5
-
0
-
ns
Interrupt Request Width Low
100
-
100
-
40
-
ns
(10) TCVlAL
Cascade Setup to Second or Third INTA (Slave
Only)
55
-
40
-
30
-
ns
(11) TRHRL
End of RD to next RD, End of INTA (within an
INTA sequence only)
160
-
160
-
90
-
ns
(12) TWHWL
End of WR to next WR
190
-
190
-
60
-
ns
(13) TCHCL
(Note 1)
End of Command to next command (not same
command type), End of INTA
sequence to next INTA sequence
500
-
400
-
90
-
ns
Data Valid from RD/INTA
-
160
-
120
-
40
ns
(8) TWHDX
(9) TJLJH
Data Hold after WR
TEST
CONDITIONS
TIMING RESPONSES
(14) TRLDV
1
Data Float after RD/INTA
5
100
5
85
5
22
ns
2
Interrupt Output Delay
-
350
-
300
-
90
ns
1
(17) TlALCV
Cascade Valid from First INTA
(Master Only)
-
565
-
360
-
50
ns
1
(18) TRLEL
Enable Active from RD or INTA
-
125
-
100
-
40
ns
1
(19) TRHEH
Enable Inactive from RD or INTA
-
60
-
50
-
22
ns
1
(20) TAHDV
Data Valid from Stable Address
-
210
-
200
-
60
ns
1
(21) TCVDV
Cascade Valid to Valid Data
-
300
-
200
-
70
ns
1
(15) TRHDZ
(16) TJHlH
NOTE:
1. Worst case timing for TCHCL in an actual microprocessor system is typically greater than the values specified for the 82C59A,
(i.e. 8085A = 1.6µs, 8085A -2 = 1µs, 80C86 = 1µs, 80C286 -10 = 131ns, 80C286 -12 = 98ns).
AC Test Circuit
V1
R1
OUTPUT FROM
DEVICE UNDER
TEST
NOTE:
TEST
POINT
R2
C1
(NOTE)
Includes stray and jig capacitance.
TEST CONDITION DEFINITION TABLE
18
TEST
CONDITION
V1
R1
R2
C1
1
1.7V
523Ω
Open
100pF
2
VCC
1.8kΩ
1.8kΩ
50pF
FN2784.5
March 17, 2006
82C59A
AC Testing Input, Output Waveform
INPUT
VIH +0.4V
OUTPUT
VOH
1.5V
1.5V
VOL
VIL - 0.4V
NOTE:
AC Testing: All input signals must switch between VIL - 0.4V and VIH + 0.4V. Input rise and fall times are driven at 1ns/V.
Timing Waveforms
(6)
TWLWH
WR
(5)
TWHAX
(4)
TAHWL
CS
ADDRESS BUS
A0
(7)
TDVWH
(8)
TWHDX
DATA BUS
FIGURE 12. WRITE
(3)
TRLRH
RD/INTA
(18)
TRLEL
(19)
TRHEH
EN
(2)
TRHAX
(1)
TAHRL
CS
ADDRESS BUS
A0
DATA BUS
(14)
TRLDV
(15)
TRHDZ
(20)
TAHDV
FIGURE 13. READ/INTA
RD
INTA
(11)
TRHRL
WR
RD
INTA
WR
(12)
TWHWL
(13)
TCHCL
RD
INTA
WR
FIGURE 14. OTHER TIMING
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82C59A
Timing Waveforms
(Continued)
(16)
TJHIH
IR
SEE NOTE 3
(9)
TJLJH
SEE NOTE 4
INT
INTA
SEE NOTE 1
SEE
NOTE 2
DB
TCVIAL
CAS 0 - 2
(17)
TIALCV
(10)
(10)
TCVIAL
(21)
TCVDV
NOTES:
1. Interrupt Request (IR) must remain HIGH until leading edge of first INTA.
2. During first INTA the Data Bus is not active in 80C86/88/286 mode.
3. 80C86/88/286 mode.
4. 8080/8085 mode.
FIGURE 15. INTA SEQUENCE
Burn-In Circuits
MD82C59A CERDIP
GND
WR
RD
D7
D6
D5
D4
D3
D2
D1
D0
CAS 0
CAS 1
GND
20
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
R3
R3
1
28
2
27 R1
26 R1
3
4
5
6
7
8
9
25 R2
24 R2
23 R2
22 R2
21 R2
20 R2
11
19 R2
18 R2
12
17
13
16 R3
15 R3
10
14
VCC
A0
C1
INTA
IR7
VCC
IR6
IR5
IR4
R3
IR3
IR2
IR1
A
R3
IR0
A
SP/EN
CAS 2
FN2784.5
March 17, 2006
82C59A
Burn-In Circuits
5962-850160X3A CLCC
VCC
D7
RD WR GND
R1
4
R1
D6
R1
3
R1
2
C1
A0 INTA
R1
1
R1
28
27
R1
26
25
5
R1
D2
D1
D0
R1
R1
R1
22
8
21
9
10
20
11
19
12
13
15
R1
CAS1
CAS0
R1
14
16
R1
17
R1
IR7
R2
IR6
R2
IR5
R2
IR4
R2
R2
R2
IR3
IR2
IR1
18
R4
R2
IR0
D3
7
23
VCC/2
R1
24
SP/EN
D4
6
CAS2
R1
GND
D5
R2
NOTES:
1. VCC = 5.5V ±0.5V.
7. R3 = 10kΩ ±5%.
2. VIH = 4.5V ±10%.
8. R4 = 1.2kΩ ±5%.
3. VIL = -0.2V to 0.4V.
4. GND = 0V.
10. F0 = 100kHz ±10%.
5. R1 = 47kΩ ±5%.
11. F1 = F0/2, F2 = F1/2, ...F8 = F7/2.
9. C1 = 0.01µF min.
6. R2 = 510Ω ±5%.
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FN2784.5
March 17, 2006
82C59A
Die Characteristics
METALLIZATION:
Type: Si-Al-Cu
Thickness: Metal 1: 8kÅ ± 0.75kÅ
Metal 2: 12kÅ ± 1.0kÅ
GLASSIVATION:
Type: Nitrox
Thickness: 10kÅ ± 3.0kÅ
Metallization Mask Layout
82C59A
D0
D1
D2
D3
D4
D5
D6
CAS0
D7
CAS1
RD
GND
WR
CS
CAS2
VCC
SP/EN
INT
A0
IR0
INTA
IR1
IR2
IR3
IR4
IR5
IR6
IR7
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FN2784.5
March 17, 2006