CPLL66-2175-2175 0.60" SQ SMD Features 1GHz-5GHz Range Standard 3 Wire Interface Small layout 0.6" x 0.6" Applications Digital Radio Equipment Fixed Wireless Access Satellite Communications Systems Base Stations Personal Communications Systems Portable Radios Test Instruments Wireless Infrastructure The CPLL66 is a complete PLL/Synthesizer needing only an external frequency reference and supply voltages for the internal PLL (phase lock loop) and VCO (voltage controlled oscillator). The Crystek CPLL66 is programmed using a standard three line interface (Data, Clock and Load Enable). The newly introduced CPLL66 family has been initially released to cover 1GHz to 5GHz in bands. It is housed in a compact 0.6-in. x 0.6-in. x 0.15-in. SMD package which saves board space. Typical phase noise at 4GHz is -90dBc/Hz at 10KHz offset with 0dBm minimum output power. Rev. B Page 1 of 6 CPLL66-2175-2175 0.60" SQ SMD PERFORMANCE SPECIFICATION Frequency Range: Step Size Settling Time Output Pow er: Output Phase Noise @1KHz offset @10KHz offset @100KHz offset @1MHz offset Pow er Supply V1=VCO Supply V2=PLL Supply Supply Current I1=VCO Input Current I2=PLL Input Current Spurious Suppression PFDSpur Reference Feedthru Harmonic Suppression (2nd Harmonic): 2nd 3rd Reference Frequency RF Output Level Input Impedance Rf Output Impedance Operating Temperature Range: MIN 0 4.75 2.7 TYP 2.175 100 1 3 MAX 6 UNITS GHz KHz msec dBm -75 -95 -120 -145 -70 -90 -115 -140 dBc/Hz dBc/Hz dBc/Hz dBc/Hz 5 3 5.25 3.3 Volts Volts 50 25 -5 -40 mA mA -70 -80 -60 -70 dBc dBc -15 -25 10 0 100K 50 -10 -15 dBc dBc MHz dBm Ohm Ohm °C 5 +85 Output Phase Noise: Page 2 of 6 CPLL66-2175-2175 0.60" SQ SMD BOTTOM VIEW GND GND GND GND GND GND 0.00 0.500 0.420 0.340 0.260 0.180 0.100 0.600 TOP VIEW 0.00 CPLL66 2175-2175 Date Code 0.140 0.220 0.300 0.380 0.460 0.600 TOP ORIENTATION MARK GND REF V2 V1 RF LE DATA CLK LD N/C GND GND GND GND GND GND CRYSTEK LE= Load Enable, CMOS Input DATA= Serial Data Input CLK= Serial Data Input LD= Lock Detect REF= Reference Input V1= Analog Supply Input (VCO) V2= Digital Supply Input (PLL) RF= RF Output BOTTOM ORIENTATION MARK 0.042 Pad Detail 0.000 0.220 0.000 0.030 0.060 0.000 RECOMMENDED REFLOW SOLDERING PROFILE Ramp-Up 3°C/Sec Max. Critical Temperature Zone TEMPERATURE 260°C Ramp-Down 6°C/Sec. 217°C 200°C 150°C Preheat 180 Secs. Max. 90 Secs. Max. 8 Minutes Max. 260°C for 10 Secs. Max. Page 3 of 6 CPLL66-2175-2175 0.60" SQ SMD ENVIRONMENTAL COMPLIANCE Parameter Conditions Mechanical Shock MIL-STD-883, Method 2002 Mechanical Vibration MIL-STD-883, Method 2007 Solderability MIL-STD-883, Method 1014 Resistance to Solvents MIL-STD-883, Method 2016 Programming Guide for CPLL66-XXXX Introduction The CPLL66 uses a simple 3 wire interface to program four internal registers. See Figure 1. Figure 1. Timing Diagram There are four 24 bit registers that need to be programmed. Which register is written into is simply controlled by Control Bits C1 and C2. Table I summarizes the Truth Table for Control Bits C1 and C2. Table I. C2, C1 Truth Table Control Bits C2 C1 0 0 0 1 1 0 1 1 Data Latch R Counter N Counter (A and B) Function Latch (Including Prescaler) Initialization Latch Table II shows the details of the four 24 bit registers. Page 4 of 6 CPLL66-2175-2175 0.60" SQ SMD Table II. Latch Summary LOCK DETECT PRECISION REFERENCE COUNTER LATCH RESERVED TEST MODE BITS ANTIBACKLASH WIDTH CONTROL BITS 14-BIT REFERENCE COUNTER DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X 0 0 LDP T2 T1 ABP2 ABP1 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 C2 (0) C1 (0) RESERVED DB23 DB22 CP GAIN N COUNTER LATCH 13-BIT B COUNTER CONTROL BITS 6-BIT A COUNTER DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 G1 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 A6 A5 A4 A3 A2 A1 C2 (0) C1 (1) PRESCALER VALUE POWERDOWN 2 FASTLOCK MODE FASTLOCK ENABLE CP THREESTATE PD POLARITY POWERDOWN 1 COUNTER RESET FUNCTION LATCH DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 P2 P1 PD2 CP16 CP15 CP14 CP13 CP12 CP11 TC4 TC3 TC2 TC1 F5 F4 F3 F2 M3 M2 M1 PD1 F1 C2 (1) C1 (0) CURRENT SETTING 1 CURRENT SETTING 2 TIMER COUNTER CONTROL MUXOUT CONTROL CONTROL BITS PRESCALER VALUE POWERDOWN 2 FASTLOCK MODE FASTLOCK ENABLE CP THREESTATE PD POLARITY POWERDOWN 1 COUNTER RESET INITIALIZATION LATCH DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 P2 P1 PD2 CP16 CP15 CP14 CP13 CP12 CP11 TC4 TC3 TC2 TC1 F5 F4 F3 F2 M3 M2 M1 PD1 F1 C2 (1) C1 (1) CURRENT SETTING 2 CURRENT SETTING 1 TIMER COUNTER CONTROL MUXOUT CONTROL CONTROL BITS When using the CPLL66 family in a synthesizer application, all four 24 bit registers need to be written into after power-up. After writing all four latches the first time, subsequent frequency step changes can be accomplished by changing the N Counter Latch only. Page 5 of 6 CPLL66-4240-4240 0.60" SQ SMD Programming Crystek p/n: CPLL66-2175-2175 The following is specific programming for CPLL66-2175-2175 (2.175GHz fixed freq. with 100KHz Step Size and 10MHz input reference frequency). Program all three registers with the following: Function Latch: 9F8083 H N Counter Latch: 02A759 H R Counter Latch: 000190 H The above values will set the CPLL66-2175-2175 to 2.175GHz Page 6 of 6