CS1610/11 CS1612/13 TRIAC Dimmable LED Driver IC Features & Description Overview • Best-in-Class Dimmer Compatibility - Leading-edge (TRIAC) Dimmers - Trailing-edge Dimmers - Digital Dimmers (with Integrated Power Supply) • Up to 90% Efficiency • Flicker-free Dimming • 0% Minimum Dimming Level • Quasi-resonant Second Stage with Constant-current Output - Flyback and Buck • Fast Startup • Tight LED Current Regulation: Better than ±5% • Primary-side Regulation (PSR) • >0.9 Power Factor • IEC-61000-3-2 Compliant • Soft Start • Protections: - Output Open/Short - Current-sense Resistor Open/Short - External Overtemperature Using NTC The CS1610/11/12/13 is a digital control IC engineered to deliver a high-efficiency, cost-effective, flicker-free, phase-dimmable, solid-state lighting (SSL) solution for the incandescent lamp replacement market. The CS1610/11 is designed to control a quasi-resonant flyback topology. The CS1612/13 is designed to control a buck topology. The CS1610/12 and CS1611/13 are designed for 120VAC and 230VAC line voltage applications, respectively. The CS1610/11/12/13 integrates a critical conduction mode (CRM) boost converter that provides power factor correction and dimmer compatibility with a constant output current, quasiresonant second stage. An adaptive dimmer compatibility algorithm controls the boost stage and dimmer compatibility operation mode to enable flicker-free operation to <2% output current with leading-edge, trailing-edge, and digital dimmers (dimmers with an integrated power supply). Applications & Description • • • • Dimmable Retrofit LED Lamps Dimmable LED Luminaries Offline LED Drivers Commercial Lighting Ordering Information See page 14. L1 L2 Vrect T1 VB S T D8 LED+ D6 R8 C3 BR1 R2 BR1 R3 R5 R4 D3 R6 C6 1 R7 16 D4 2 CS1610 /11 5 Q1 C1 BR1 D1 Z1 SOURCE GD FBAUX FBSENSE VDD eOTP C4 8 Q4 13 R12 15 RIP K 11 R13 10 RS IPK SGND C7 Cirrus Logic, Inc. http://www.cirrus.com Q3 D5 14 BR1 3 IAC Q2 D2 LED- BSTOUT CLAMP C2 Z2 D7 R1 AC Mains C8 R9 BSTAUX C5 R10 C9 4 GND C NTC FBGAIN 12 Copyright Cirrus Logic, Inc. 2012 (All Rights Reserved) R11 NTC 9 RFB GA IN MAR’12 DS929F3 CS1610/11/12/13 1. INTRODUCTION BSTOUT 15k 16 Iref MUX IAC BSTAUX ADC POR 15k 2 1 VFB ZCD(th) Voltage Regulator + + Boost ZCD - tLE B t B S TZCD OLP 5 V S OURCE(th ) OCP + + - - Peak Control GD 12 GND 11 FBSENSE 15 FBAUX 3 CLAMP VOLP (th) VOCP (th ) + - I S OURCE SGND 13 + SOURCE VDD VZ V S T(th ) VS TP(th ) - 14 DAC V P k_Max (th) 4 Output Open VDD IPK 8 eOTP 10 FBGAIN 9 t FB ZCD Second Stage ZCD + + - I CONNE CT VOV P (th ) VFB ZCD(th) MUX VDD V CONNE CT(th ) - ICLA MP + Figure 1. CS1610/11/12/13 Block Diagram A typical schematic using the CS1610/11 for flyback applications is shown on the previous page. Startup current is provided from a patent-pending, external high-voltage source-follower network. In addition to providing startup current, this unique topology is integral in providing compatibility with digital dimmers by ensuring VDD power is always available to the IC. During steady-state operation, an auxiliary winding on the boost inductor back-biases the source-follower circuit and provides steady-state operating current to the IC to improve system efficiency. The rectified input voltage is sensed as a current into pin IAC and is used to control the adaptive dimmer compatibility algorithm and extract the phase of the input voltage for output dimming control. During steady-state operation, the external high-voltage, source-follower circuit is source-switched in critical conduction mode (CRM) to boost the input voltage. This allows the boost stage to maintain good power factor, provides dimmer compatibility, reduces bulk capacitor ripple current, and provides a regulated input voltage to the second stage. 2 The output voltage of the CRM boost is sensed by the current into the boost output voltage sense pin (BSTOUT). The quasiresonant second stage is implemented with peak-current mode primary-side control, which eliminates the need for additional components to provide feedback from the secondary and reduces system cost and complexity. Voltage across an external user-selected resistor is sensed through pin FBSENSE to control the peak current through the second stage inductor. Leading-edge and trailing-edge blanking on pin FBSENSE prevents false triggering. Pin FBAUX is used to sense the second stage inductor demagnetization to ensure quasi-resonant switching of the output stage. When an external negative temperature coefficient (NTC) thermistor is connected to the eOTP pin, the CS1610/11/12/13 monitors the system temperature, allowing the controller to reduce the output current of the system. If the temperature reaches a designated high set point, the IC is shutdown and stops switching. DS929F3 CS1610/11/12/13 2. PIN DESCRIPTION Boost Zero-current Detect BSTAUX 1 16 BSTOUT Boost Output Voltage Sense Rectifier Voltage Sense IAC 2 15 FBAUX Second Stage Zero-current Detect Voltage Clamp Current Source CLAMP 3 14 VDD IC Supply Voltage Source Ground SGND 4 13 GD Gate Driver Source Switch SOURCE 5 12 GND Ground No Connect NC 6 11 FBSENSE Second Stage Current Sense No Connect NC 7 10 Boost Peak Current IPK 8 9 eOTP External Overtemperature Protection FBGAIN Second Stage Gain 16-lead SOICN Figure 2. CS1610/11/12/13 Pin Assignments Pin Name Pin # I/O BSTAUX 1 IN Boost Zero-current Detect — Boost Inductor demagnetization sensing input for zero-current detection (ZCD) information. The pin is connected to the PFC boost inductor auxiliary winding through an external resistor divider. IAC 2 IN Rectifier Voltage Sense — A current proportional to the rectified line voltage is fed into this pin. The current is measured with an A/D converter. CLAMP 3 OUT Voltage Clamp Current Source — Connect to a voltage clamp circuit on the output of the boost stage. SGND 4 PWR Source Ground — Common reference current return for the SOURCE pin. SOURCE 5 IN Source Switch — Connected to the source of the boost stage external high-voltage FET. NC 6 IN No Connect — Connect this pin to VDD using a pull-up resistor. NC 7 IN No Connect — Connect this pin to VDD using a pull-up resistor. IPK 8 IN Boost Peak Current — Connect a resistor to this pin to set the peak current of the boost circuit. FBGAIN 9 IN Second Stage Gain — Connect a resistor to this pin to set the switching frequency gain for the second stage. eOTP 10 IN External Overtemperature Protection — Connect an external NTC thermistor to this pin, allowing the internal A/D converter to sample the change to NTC resistance. FBSENSE 11 IN Second Stage Current Sense — The current flowing in the second stage FET is sensed across a resistor. The resulting voltage is applied to this pin and digitized for use by the second stage computational logic to determine the FET's duty cycle. GND 12 PWR Ground — Common reference. Current return for both the input signal portion of the IC and the gate driver. GD 13 OUT Gate Driver — Gate drive for the second stage power FET. VDD 14 PWR IC Supply Voltage — Connect a storage capacitor to this pin to serve as a reservoir for operating current for the device, including the gate drive current to the power transistor. FBAUX 15 IN Second Stage Zero-current Detect — Second stage inductor sensing input. The pin is connected to the second stage inductor’s auxiliary winding through an external resistor divider. BSTOUT 16 IN Boost Output Voltage Sense — A current proportional to the boost output is fed into this pin. The current is measured with an A/D converter. DS929F3 Description 3 CS1610/11/12/13 3. CHARACTERISTICS AND SPECIFICATIONS 3.1 Electrical Characteristics Typical characteristics conditions: • TA = 25 °C, VDD = 12V, GND = 0 V • All voltages are measured with respect to GND. • Unless otherwise specified, all currents are positive when flowing into the IC. Parameter Minimum/Maximum characteristics conditions: • TJ = -40°C to +125 °C, VDD = 11V to 17V, GND = 0 V Condition Symbol Min Typ Max Unit VDD Supply Voltage After Turn-on VDD 11 - 17 V Turn-on Threshold Voltage VDD Increasing VST(th) - 8.5 - V Turn-off Threshold Voltage (UVLO) VDD Decreasing VSTP(th) - 7.5 - V IDD = 20mA VZ 18.5 - 19.8 V VDD <VST(th) IST - - 200 A - 4.5 - mA Iref - 133 133 - A A fBST(Max) - - 200 kHz ICLAMP - -3.7 - mA - 590 508 - mA mA VBSTZCD(th) - 200 - mV tBSTZCD - 3.5 - s IZCD -2 - - mA - VDD +0.6 - V - 162 148 - A A - 147 143 - A A VFBZCD(th) - 200 - mV tFBZCB - 2 - s IZCD -2 - - mA - VDD +0.6 - V Operating Range Zener Voltage (Note 1) VDD Supply Current Startup Supply Current Operating Supply Current (Note 5) CL = 0.25nF, fsw 70 kHz Reference Reference Current CS1610/12 CS1611/13 VBST = 200 V VBST = 400 V Boost Maximum Switching Frequency Clamp Current Dimmer Attach Peak Current CS1610/12 CS1611/13 108 Vline 132 207 Vline 253 Boost Zero-Current Detect BSTZCD Threshold BSTZCD Blanking ZCD Sink Current (Note 2) BSTAUX Upper Voltage IZCD = 1 mA Boost Protection Boost Overvoltage Protection (BOP) CS1610/12 CS1611/13 108 Vline 132 207 Vline 253 Clamp Turn On CS1610/12 CS1611/13 108 Vline 132 207 Vline 253 VBOP(th) Second Stage Zero-Current Detect FBZCD Threshold FBZCD Blanking ZCD Sink Current FBAUX Upper Voltage 4 (Note 2) IZCD = 1mA CS1610/11/12/13 CS1610/11/12/13 Parameter Condition Symbol Min Typ Max Unit Overcurrent Protection Threshold VOCP(th) - 1.69 - V Sense Resistor Short Threshold VOLP(th) - 200 - mV Peak Control Threshold VPk_Max(th) - 1.4 - V Leading-edge Blanking tLEB - 550 - ns - - 100 ns Minimum On Time - 0.55 - s Maximum On Time - 8.8 - s Second Stage Current Sense Delay to Output Second Stage Pulse Width Modulator Minimum Switching Frequency tFB(Min) - 625 - Hz Maximum Switching Frequency tFB(Max) - 200 - kHz Second Stage Gate Driver Output Source Resistance VDD = 12V ZOUT - 24 - Output Sink Resistance VDD = 12V ZOUT - 11 - Rise Time (Note 5) CL = 0.25nF - - 30 ns Fall Time (Note 5) CL = 0.25nF - - 20 ns Second Stage Protection Overcurrent Protection (OCP) VOCP(th) - 1.69 - V Overvoltage Protection (OVP) VOVP(th) - 1.25 - V Open Loop Protection (OLP) VOLP(th) - 200 - mV External Overtemperature Protection (eOTP), Boost Peak Current, Second Stage Frequency Gain Pull-up Current Source – Maximum ICONNECT Conductance Accuracy (Note 3) Conductance Offset (Note 3) Current Source Voltage Threshold - 80 - A - - ±5 - ±250 - nS VCONNECT(th) - 1.25 - V Internal Overtemperature Protection (iOTP) Thermal Shutdown Threshold (Note 4) TSD - 135 - ºC Thermal Shutdown Hysteresis (Note 4) TSD(Hy) - 14 - ºC Notes: 1. 2. 3. 4. 5. The CS1610/11/12/13 has an internal shunt regulator that limits the voltage on the VDD pin. VZ, the shunt regulation voltage, is defined in the VDD Supply Voltage section on page 4. External circuitry should be designed to ensure that the ZCD current drawn from the internal clamp diode when it is forward biased does not exceed specification. The conductance is specified in Siemens (S or 1/). Each LSB of the internal ADC corresponds to 250nS or one parallel 4M resistor. Full scale corresponds to 256 parallel 4M resistors or 15.625k. Specifications are guaranteed by design and are characterized and correlated using statistical process methods. For test purposes, load capacitance (CL) is 0.25nF and is connected as shown in the following diagram. V DD +15V VDD CS GND DS929F3 TP Buffer GD S1 R1 CL 0.25nF R3 R2 GD OUT S2 -15V 5 CS1610/11/12/13 3.2 Thermal Resistance Symbol Parameter Value Unit JA Junction-to-Ambient Thermal Impedance 2 Layer PCB 4 Layer PCB 84 47 °C/W °C/W JC Junction-to-Case Thermal Impedance 2 Layer PCB 4 Layer PCB 39 31 °C/W °C/W 3.3 Absolute Maximum Ratings Characteristics conditions: All voltages are measured with respect to GND. Pin Symbol 14 VDD Parameter IC Supply Voltage Value Unit 18.5 V 1, 2, 5, 8, 9, 10,11,15,16 Analog Input Maximum Voltage -0.5 to (VDD +0.5) V 1, 2, 8, 9, 10, 11, 15, 16 Analog Input Maximum Current 5 mA 13 VGD Gate Drive Output Voltage -0.3 to (VDD +0.3) V 13 IGD Gate Drive Output Current -1.0 / +0.5 A 1.1 A 5 mA 100 mW -40 to +125 °C -40 to +125 °C -65 to +150 °C 2000 500 V V 5 ISOURCE Current into Pin 3 ICLAMP - PD Total Power Dissipation @ TA = 50 °C - TA Operating Ambient Temperature Range - TJ Junction Temperature Operating Range - TStg All Pins ESD Note: 6. Clamp Output Current (Note 6) Storage Temperature Range Electrostatic Discharge Capability Human Body Model Charged Device Model Long-term operation at the maximum junction temperature will result in reduced product life. Derate internal power dissipation at the rate of 50 mW /°C for variation over temperature. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 6 CS1610/11/12/13 CS1610/11/12/13 4. TYPICAL PERFORMANCE PLOTS 3 0.008 2 0.004 IDD (mA) UVLO Hysteresis 0.006 Falling Edge Rising Edge 0.002 1 0 0 -50 0 50 100 -0.002 150 0 Temperature (ºC) 2 4 6 8 10 12 14 16 18 20 VDD (V) Figure 4. Supply Current vs. Voltage Figure 3. UVLO Characteristics 10 20 19.5 VDD (V) 9 VZ (V) Turn On 19 8 18.5 Turn Oī 18 7 -50 0 50 100 -50 150 0 50 150 Figure 6. Zener Voltage vs. Temperature Figure 5. Turn On/Off Threshold Voltage vs. Temperature 40 0.5 0.0 Drift (%) 30 ZOUT (:) 100 Temperature (ºC) Temperature (ºC) Source 20 -0.5 -1.0 Sink 10 -1.5 -2.0 0 -50 0 50 100 Temperature (ºC) Figure 7. Gate Drive Resistance vs. Temperature DS929F3 150 -50 0 50 100 150 Temperature (ºC) Figure 8. Reference Current (Iref) Drift vs. Temperature 7 CS1610/11/12/13 5. GENERAL DESCRIPTION 5.1 Overview The CS1610/11/12/13 is a digital control IC engineered to deliver a high-efficiency, cost-effective, flicker-free, phasedimmable, solid-state lighting (SSL) solution for the incandescent lamp replacement market. The CS1610/11 is designed to control a quasi-resonant flyback topology. The CS1612/13 is designed to control a buck topology. The CS1610/12 and CS1611/13 are designed for 120VAC and 230VAC line voltage applications, respectively. The CS1610/11/12/13 integrates a critical conduction mode (CRM) boost converter that provides power factor correction and dimmer compatibility with a constant output current, quasiresonant second stage. An adaptive dimmer compatibility algorithm controls the boost stage and dimmer compatibility operation mode to enable flicker-free operation to <2% output current with leading-edge, trailing-edge, and digital dimmers (dimmers with an integrated power supply). 5.2 Startup Circuit An external, high-voltage source-follower circuit is used to deliver startup current to the IC. During steady-state operation, an auxiliary winding on the boost inductor biases this circuit to an off state to improve system efficiency, and all IC supply current is generated from the auxiliary winding. The patentpending technology of the external, high-voltage sourcefollower circuit enables system compatibility with digital dimmers (dimmers containing an internal power supply) by providing a continuous path for the dimmer’s power supply to recharge during its off state. During steady-state operation, the high-voltage FET, Q2, in this circuit is source-switched by a variable internal current source on the SOURCE pin to create the boost circuit. A Schottky diode with a forward voltage less than 0.6V is recommended for D5. Schottky diode D5 will limit inrush current through the internal diode preventing damage to the IC. 5.3 Dimmer Switch Detection The CS1610/11/12/13 dimmer switch detection algorithm determines if the SSL system is controlled by a regular switch, a leading-edge dimmer, or a trailing-edge dimmer. Dimmer switch detection is implemented using two modes: Dimmer Learn Mode and Dimmer Validate Mode. These assist in limiting the system power losses. Once the IC reaches its UVLO start threshold, VST(th), and begins operating, the CS1610/11/12/13 is in Dimmer Learn Mode, allowing the dimmer switch detection circuit to set the operating state of the IC to one of three modes: No-dimmer Mode, Leading-edge Mode, or Trailing-edge Mode. 5.3.1 Dimmer Learn Mode In Dimmer Learn Mode, the dimmer detection circuit spends approximately two line-cycles learning whether there is a dimmer switch and, if present, whether it is a trailing-edge or leading-edge dimmer. In Dimmer Learn Mode, a modified version of the leading-edge algorithm is used. The trailing-side 8 slope of the input line voltage is sensed to decide whether the dimmer switch is a trailing-edge dimmer. The dimmer detection circuit transitions to Dimmer Validate Mode once the circuit detects a dimmer is present. 5.3.2 Dimmer Validate Mode During normal operation, CS1610/11/12/13 is in Dimmer Validate Mode. This instructs the dimmer detection circuit to periodically validate that the IC is executing the correct algorithm for the attached dimmer. The dimmer detection algorithm periodically verifies the IC operating state as a protection against incorrect detection. As additional protection, the output of the dimmer detection algorithm is low-pass filtered to prevent noise or transient events from changing the IC’s operating mode. The IC will return to Dimmer Learn Mode when it has determined that the wrong algorithm is being executed. 5.3.3 No-dimmer Mode Upon detection that the line is not phase cut with a dimmer, the CS1610/11/12/13 operates in No-Dimmer Mode, where it provides a power factor that is in excess of 0.9. The CS1610/11/12/13 accomplishes this by boosting in CRM and DCM mode. The peak current is modulated to provide link regulation. The CS1610/11/12/13 alternates between two settings of peak current. To regulate the boost output voltage, the device uses a peak current set by the RIPK resistor. The time that this current is used is determined by an internal compensation loop to regulate the boost output voltage. The internal algorithm will reduce the peak current of the boost stage to maintain output voltage regulation and obtain the desired power factor. 5.3.4 Leading-edge Mode In Leading-edge Mode, the CS1610/11/12/13 regulates the link voltage while maintaining the dimmer phase angle. To accomplish this, the CS1610/11/12/13 uses CCM boosting with dimmer attach current as the initial peak current on the initial firing event of the dimmer. After gaining control of the incoming current, the CS1610/11/12/13 transitions to a CRM boost algorithm to regulate the link voltage. The CS1610/11/12/13 periodically executes a probe event on the incoming waveform. The information from the probe event is beneficial to maintaining proper operation with the dimmer circuitry. 5.3.5 Trailing-edge Mode In Trailing-edge Mode, the CS1610/11/12/13 determines its operation based on the falling edge of the input voltage waveform. To allow the dimmer to operate properly, the CS1610/11/12/13 must charge the capacitor in the dimmer on the falling edge of the input voltage. To accomplish this, the CS1610/11/12/13 always executes the boost algorithm on this falling edge. To ensure maximum compatibility with dimmer components, the device boosts during this falling edge event using a peak current that must meet a minimum value. In Trailing-edge Mode, only CRM boosting is used. CS1610/11/12/13 CS1610/11/12/13 5.4 Boost Stage The high-voltage FET in the source-follower startup circuit is source-switched by a variable current source on the SOURCE pin to operate a boost circuit. Peak FET switching current is set with an external resistor on pin IPK. VB S T R8 IB S TOUT In No-Dimmer Mode, the boost stage begins operating when the start threshold is reached during each rectified half line-cycle and is disabled at the nominal boost output voltage. The peak FET switching current determines the percentage of the rectified input voltage conduction angle over which the boost stage will operate. The control algorithm adjusts the peak FET switching current to maximize the operating time of the boost stage, thus improving the input power factor. When operating in Leading-edge Dimmer Mode, the boost stage ensures the hold current requirement of the dimmer is met from the initiation of each half-line dimmer conduction cycle until the peak of the rectified input voltage. Trailing-edge Dimmer Mode boost stage ensures that the trailing-edge is exposed at the correct time with the correct current. 5.4.1 Maximum Peak Current The maximum boost inductor peak current is set using an external resistor, R IPK , on pin IPK, which is sampled periodically by an ADC. Maximum power output is proportional to I PK(code). See Equation 1: I PK BST Vrms, typical P in, max = -------------------------------------------------------------------2 [Eq.1] where, = correction term = 0.55 V rms, typical = nominal operating input RMS voltage I PK(BST) = IPK(code) x 4.1mA RB S T R9 CS1610 /11/12/13 Iref 16 BSTOUT 15k ADC 12 Figure 9. BSTOUT Input Pin Model Resistor RBST sets the feedback current at the nominal boost output voltage. For the CS1611/13, RBST is calculated as shown in Equation 3: V BST 400V R BST = -------------- = ------------------ 3M [Eq.3] I ref 133A where, VBST = Nominal boost output voltage Iref = Internal reference current For 120 VAC line voltage applications (CS1610/12), nominal boost output voltage, VBST, is 200V, and resistor RBST is 1.5M. By using digital loop compensation, the voltage feedback signal does not require an external compensation network. A current proportional to the AC input voltage is supplied to the IC on pin IAC and is used by the boost control algorithm. V rec t R3 IA C The external resistor, RIPK , is calculated using the peak current code, I PK(code). See Equation 2: R IA C R4 CS1610 /11/12/13 Iref R IPK 4000000 = ----------------------I PK code [Eq.2] 2 IA C 15k ADC 12 5.4.2 Output BSTOUT Sense and Input IAC Sense A current proportional to the boost output voltage, VBST, is supplied to the IC on pin BSTOUT and is used as a feedback control signal. The ADC is used to measure the magnitude of the I BSTOUT current through resistor R BST. The magnitude of the I BSTOUT current is then compared to an internal reference current (I ref) of 133A. Figure 10. IAC Input Pin Model Resistor RIAC sets the IAC current and is defined in Equation 4: R IAC = R BST [Eq.4] For optimal performance, RIAC and RBST should use 1% or better resistors for best VBST voltage accuracy. 5.4.3 Boost Auxiliary Winding The boost auxiliary winding is used for zero-current detection (ZCD). The voltage on the auxiliary winding is sensed through the BSTAUX pin of the IC. It is also used to deliver current during steady-state operation, as mentioned in section 5.2 Startup Circuit on page 8. DS929F3 9 CS1610/11/12/13 5.4.4 Boost Overvoltage Protection 5.5.1 Clamp Overpower Protection The CS1610/11/12/13 supports boost overvoltage protection (BOP) to protect the bulk capacitor C8 (see Figure 12. Flyback Model). If the boost output voltage exceeds the overvoltage protection thresholds of 249V for a 120V system, or 448V for a 230V system, a BOP fault signal is generated. The control logic continuously averages this BOP fault signal, and if at any point in time the average exceeds a set event threshold, the boost stage is disabled. The BOP fault averaging algorithm sets the event threshold such that the boost output voltage is never allowed to stay above the BOP threshold for more than 1.6ms. The CS1610/11/12/13 clamp overpower protection (COP) control logic averages the ‘ON’ time of the clamp circuit. If the output of the averaging logic exceeds 49%, a COP event is actuated, disabling the boost and second stages. The clamp circuitry is turned off during the fault event. The ‘ON’ time averaging algorithm sets the COP threshold such that the clamp circuit cannot be continuously ‘ON’ for more than 13.8ms. During a boost overvoltage protection event, the second stage is kept enabled, and its dim input is railed to full scale. This allows the second stage to dissipate the stored energy on the bulk capacitor (C8) quickly, bringing down the boost output voltage to a safe value. A visible flash on the LED might appear, indicating that an overvoltage event has occurred. When the boost output voltage drops to 195V for a 120V application or 368V for a 230V application, the boost stage is enabled, and the system returns to normal operation. When operating with a dimmer, the dimming signal is extracted in the time domain and is proportional to the conduction angle of the dimmer. A control variable is passed to the quasi-resonant second stage to achieve 2% to 100% output currents. 5.5 Voltage Clamp Circuit To keep dimmers conducting and prevent them from misfiring, a minimum power needs to be delivered from the dimmer to the load. This power is nominally around 2W for 230V and 120 V TRIAC dimmers. At low dim angles (< 90°), this excess power cannot be converted into light by the second output stage due to the dim mapping at light loads. The output voltage of the boost stage (VBST) can rise above the safe operating voltage of the primary-side bulk capacitor (C6). The CS1610/11/12/13 provides active clamp circuitry on the CLAMP pin, as shown in Figure 11. 5.6 Dimming Signal Extraction and the Dim Mapping Algorithm 5.7 Quasi-resonant Second Stage The second stage is a quasi-resonant current-regulated DCDC Converter capable of flyback or buck operation, delivering the highest possible efficiency at a constant current while minimizing line frequency ripple. Primary-side control is used to simplify system design and reduce system cost and complexity. C8 D8 Z2 LED + C9 LED - D7 CS1610/11 GD 13 Q4 R12 V BST FBAUX 15 R13 VDD FBSENSE R10 ICLAM P GND 12 CLAMP S1 Q3 3 11 FBGAIN 9 R11 RFB GA IN V BE CS1610 /11/12/13 Figure 11. CLAMP Pin Model A PWM control loop ensures that the voltage on VBST (the boost output) does not exceed 227 V for 120VAC applications or 424 V for 230VAC applications. This control turns on the BJT of the voltage clamp circuit, allowing the clamp circuit to sink current through the load resistor, preventing VBST from exceeding the maximum safe voltage. 10 T1 VB S T Figure 12. Flyback Model The digital algorithm ensures monotonic dimming from 2% to 100% of the dimming range with a linear relationship between the dimming signal and the LED current. The flyback stage is controlled by sensing current in the transformer primary. CS1610/11/12/13 CS1610/11/12/13 A quasi-resonant buck stage is illustrated in Figure 13. The buck stage is controlled by measuring current in the buck inductor and voltage on the auxiliary winding. VB S T T total T critical = T 1 + T 2 LED + D8 C9 LED L3 CS1612/13 GD FBAUX FBSENSE FBGAIN 9 RFB GA IN 13 Q4 R12 T1 = gate turn-on time T2 = demagnetization time The switching period Ttotal is computed using the formula shown in Equation 6: 15 T total FB gain IPK FB T2 ----------------- R13 11 [Eq.5] where, Tcritical = resonant switching period at max power C8 GND 12 switching period Ttotal is greater than the resonant switching period Tcritical at maximum output power. See Equation 5: [Eq.6] where, R11 = dimming factor, proportional to the duty cycle of the dimmer, between 0 and 1 IPK(FB) = transformer primary winding current Figure 13. Buck Model FBgain = Ttotal /T2 The digital buck algorithm ensures monotonic dimming from 2% to 100% of the dimming range with a linear relationship between the dimming signal and the LED current. An appropriate value for RFBGAIN needs to be selected to provide the correct FBgain. Resistor RFBGAIN is calculated using the formula shown in Equation 7: Quasi-resonant operation is achieved by detecting second stage inductor demagnetization via an auxiliary winding. The digital control algorithm rejects line-frequency ripple created on the second stage input by the front-end boost stage, resulting in the highest possible LED efficiency and long LED life. 4000000 R FBGAIN = --------------------------------------------------- FB gain 128 – 64 5.7.1 Auxiliary Winding Configuration The auxiliary winding is also used for zero-current detection (ZCD) and overvoltage protection (OVP). The auxiliary winding is sensed through the FBAUX pin of the IC. 5.7.2 Control Parameters The second stage control parameters assure: • Line Regulation — The LED current remains constant despite a ±10% AC line voltage variation. • Effect of Variation in Transformer Magnetizing Inductance — The LED current remains constant over a ±20% variation in magnetizing inductance. The second stage requires three inputs and generates one key output. The FBSENSE input is used to sense the current in the second stage inductor. When the current reaches a certain threshold, the gate drive turns off (output on pin GD). The sensed current and the FBGAIN input are used to determine the switching period Ttotal . The zero-current detect input on pin FBAUX is used to determine the demagnetization period T2 . The controller then uses the time Ttotal to determine gate turn-on time. The FBGAIN input is set using an external resistor, RFBGAIN . Resistor RFBGAIN must be selected to ensure that the DS929F3 [Eq.7] The value of FBgain also has a bearing on the linearity of the dimming factor versus the LED current curve and must be chosen using Application Note AN364: CS1610/11 Design Guide. 5.7.3 Output Open Circuit Protection Output open circuit protection and output overvoltage protection (OVP) is implemented by monitoring the output voltage through the transformer auxiliary winding. If the voltage on the FBAUX pin exceeds a threshold (VOVP(th)) of 1.25V, a fault condition occurs. The IC output is disabled and the controller attempts to restart after one second. 5.7.4 Overcurrent Protection (OCP) Overcurrent protection is implemented by monitoring the voltage across the second stage sense resistor. If this voltage exceeds a threshold (VOCP(th)) of 1.69V, a fault condition occurs. The IC output is disabled and the controller attempts to restart after one second. 5.7.5 Open Loop Protection (OLP) Both open loop protection and protection against a short of the second stage sense resistor are implemented by monitoring the voltage across the resistor. If the voltage on pin FBSENSE does not reach the protection threshold (VOLP(th)) of 200mV, the IC output is disabled and the controller attempts to restart after one second. 11 CS1610/11/12/13 Overtemperature Protection The CS1610/11/12/13 incorporates both internal overtemperature protection (iOTP) and the ability to connect an external overtemperature sense circuit for IC protection. Typically, a NTC thermistor is used. 5.8.1 Internal Overtemperature Protection Internal overtemperature protection (iOTP) is activated, and switching is disabled when the die temperature of the devices exceeds 135°C. There is a hysteresis of about 14°C before resuming normal operation. 5.8.2 External Overtemperature Protection The external overtemperature protection (eOTP) pin is used to implement overtemperature protection using an external negative temperature coefficient (NTC) thermistor. The total resistance on the eOTP pin is converted to an 8-bit digital ‘CODE’ (which gives an indication of the temperature) using a digital feedback loop, which adjusts the current (ICONNECT) into the NTC and series resistor (RS) to maintain a constant reference voltage of 1.25V (VCONNECT(th)). Figure 14 illustrates the functional block diagram when connecting an optional external NTC temperature sensor to the eOTP circuit. CS1610/11/12/13 eOTP Control VDD ICONNE CT Comp_Out eOTP + - 10 VCONNE CT(th) RS NTC C NTC (Optional ) Figure 14. eOTP Functional Diagram Current ICONNECT is generated from an 8-bit controlled current source with a full-scale current of 80A. See Equation 8: V CONNECT th I CONNECT = ------------------------------------R [Eq.8] When the loop is in equilibrium, the voltage on the eOTP pin fluctuates around VCONNECT(th). The digital ‘CODE’ output by the ADC is used to generate ICONNECT. In normal operating mode, the ICONNECT current is updated once every seventh half line-cycle by a single ± LSB step. See Equation 9: V CONNECT th I CONNECT - = ------------------------------------CODE -------------------------N R NTC + R S 2 [Eq.9] Solving Equation 9 for CODE: N 2 V CONNECT th CODE = ------------------------------------------------------------------I CONNECT R NTC + R S 256 1.25 V = ---------------------------------------------------------- 80A R NTC + R S 6 4 10 = -------------------------------- R NTC + R S 12 The tracking range of this resistance ADC is approximately 15.5k to 4M. The series resistor RS is used to adjust the resistance of the NTC to fall within this ADC tracking range so that the entire 8-bit dynamic range of the ADC is well used. A 14k (±1% tolerance) series resistor is required to allow measurements of up to 130°C to be within the eOTP tracking range when a 100k NTC with a Beta of 4334 is used. The eOTP tracking circuit is designed to function accurately with external capacitance up to 470pF. A higher 8-bit code output reflects a lower resistance and hence a higher external temperature. The ADC output code is filtered to suppress noise and compared against a reference code that corresponds to 125/130°C. If the temperature exceeds this threshold, the chip enters an external overtemperature state and shuts down. This is not a latched protection state, and the ADC keeps tracking the temperature in this state in order to clear the fault state once the temperature drops below 110°C. If an external overtemperature protection thermistor is not used, connect the eOTP pin to GND using a 50k to 500k resistor to disable the eOTP feature. When exiting reset, the chip enters startup and the ADC quickly (<5ms) tracks the external temperature to check if it is below the 110°C reference code before the boost and second stages are powered up. If this check fails, the chip will wait until this condition becomes true before initializing the rest of the system. For external overtemperature protection, a second low-pass filter with a time constant of two seconds filters the ADC output and uses it to scale down the internal dim level of the system (and hence the LED current, ILED) if the temperature exceeds 95 °C (see Figure 15). The large time constant for this filter ensures that the dim scaling does not happen spontaneously and is not noticeable (suppress spurious glitches). The ILED starts reducing when RNTC ~ 6.3k (assuming a 14k1% tolerance, series resistor), which corresponds to a temperature of 95°C for a 100k NTC (100k at 25°C). The ILED current is scaled until the NTC value reaches 2.5k (125°C). The CS1610/11/12/13 uses this calculated value to scale the output LED current, ILED, as shown in Figure 15. Current (ILED, Nom.) 5.8 100% 50% 0 25 95 Temperature (°C) 125 Figure 15. LED Current vs. eOTP Temperature [Eq.10] Beyond this temperature, the IC shuts down using the mechanism discussed above. If the external overtemperature protection feature is not required, connect the eOTP pin to GND using a 50k-to-500k resistor to disable the eOTP feature. CS1610/11/12/13 CS1610/11/12/13 6. PACKAGE DRAWING 16 SOICN (150 MIL BODY WITH EXPOSED PAD) mm MIN NOM MAX MIN NOM MAX A -- -- 1.75 -- -- 0.069 A1 0.10 -- 0.25 0.004 -- 0.010 b 0.31 -- 0.51 0.012 -- 0.020 c 0.10 -- 0.25 0.004 -- 0.010 D D1 9.90BSC 4.95 5.25 0.195 0.201 E 6.00BSC 0.236BSC 3.90BSC 0.154BSC 2.35 e DS929F3 5.10 0.390BSC E1 E2 1. 2. 3. 4. inch Dimension 2.50 2.65 0.093 1.27BSC 0.098 0.207 0.104 0.05BSC L 0.40 -- 1.27 0.016 -- 0.050 Θ 0° -- 8° 0° -- 8° aaa 0.10 0.004 bbb 0.25 0.010 ddd 0.25 0.010 Controlling dimensions are in millimeters. Dimensions and tolerances per ASME Y14.5M. This drawing conforms to JEDEC outline MS-012, variation AC for standard 16 SOICN narrow body. Recommended reflow profile is per JEDEC/IPC J-STD-020. 13 CS1610/11/12/13 7. ORDERING INFORMATION Part # AC Line Voltage Temperature Range Package Description CS1610-FSZ 120VAC -40 °C to +125 °C 16-lead SOICN, Lead (Pb) Free CS1611-FSZ 230VAC -40 °C to +125 °C 16-lead SOICN, Lead (Pb) Free CS1612-FSZ 120VAC -40 °C to +125 °C 16-lead SOICN, Lead (Pb) Free CS1613-FSZ 230VAC -40 °C to +125 °C 16-lead SOICN, Lead (Pb) Free 8. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number Peak Reflow Temp MSL Ratinga Max Floor Lifeb CS1610-FSZ 260 °C 3 7 Days CS1611-FSZ 260 °C 3 7 Days CS1612-FSZ 260 °C 3 7 Days CS1613-FSZ 260 °C 3 7 Days a. MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. b. Stored at 30°C, 60% relative humidity. 14 CS1610/11/12/13 CS1610/11/12/13 REVISION HISTORY Revision Date PP1 MAR 2011 Added second stage gain section. Preliminary Status. PP2 MAY 2011 Added CS1611 230V device. PP3 OCT 2011 Moved power supply to boost auxiliary winding. PP4 NOV 2011 Added CS1612/13. Edited for content and clarity. F1 DEC 2011 Edited for clarity and typographical error. F2 FEB 2012 Corrected typographical errors. F3 MAR 2012 Edited for content and clarity. DS929F3 Changes 15 CS1610/11/12/13 Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to http://www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. 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IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, the Cirrus Logic logo designs, EXL Core, the EXL Core logo design, TruDim, and the TruDim logo design are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. 16 CS1610/11/12/13