Cirrus CS4228-KS 24-bit, 96 khz surround sound codecã Datasheet

CS4228
24-Bit, 96 kHz Surround Sound Codec
Features
Description
l Two
The CS4228 codec provides two analog-to-digital and
six digital-to-analog delta-sigma converters, along with
volume controls, in a compact +5/+3.3 V, 28-pin SSOP
device. Combined with an IEC958 (SPDIF) receiver (like
the CS8414) and surround sound decoder (such as one
of the CS492x or CS493xx families), it is ideal for use in
DVD player, A/V receiver and car audio systems supporting multiple standards such as Dolby Digital AC-3,
AAC, DTS, Dolby ProLogic, THX, and MPEG.
24-bit A/D Converters
- 102 dB dynamic range
- 90 dB THD+N
l Six
24-bit D/A Converters
- 103 dB dynamic range and SNR
- 90 dB THD+N
l Sample
rates up to 100 kHz
l Pop-free Digital Output Volume Controls
A flexible serial audio interface allows operation in Left
Justified, Right Justified, I2S, or One Line Data modes.
- 90.5 dB range, 0.5 dB resolution (182 levels)
- Variable smooth ramp rate, 0.125 dB steps
ORDERING INFORMATION
CS4228-KS -10° to +70° C 28-pin SSOP
CDB4228
Evaluation Board
l Mute
Control pin for off-chip muting circuits
l On-chip Anti-alias and Output Filters
l De-emphasis filters for 32, 44.1 and 48 kHz
I
SDA/CDIN
AD0/CS
MUTEC
SDIN3
VL
VA
FILT
DIGITAL VOLUME
∆Σ DAC #1
DIGITAL VOLUME
∆Σ DAC #2
DIGITAL VOLUME
∆Σ DAC #3
DIGITAL VOLUME
∆Σ DAC #4
DIGITAL VOLUME
∆Σ DAC #5
DIGITAL VOLUME
∆Σ DAC #6
DIGITAL FILTERS
SDOUT
DIGITAL FILTERS
WITH DE-EMPHASIS
SDIN2
SERIAL AUDIO
DATA INTERFACE
SDIN1
VD
MUTE CONTROL
CONTROL PORT
LRCK
SCLK
RST
ANALOG LOW PASS AND
OUTPUT STAGE
SCL/CCLK
AOUT1
AOUT2
AOUT3
AOUT4
AOUT5
AOUT6
AINL+
LEFT ADC
AINLAINR+
AINR-
RIGHT ADC
CLOCK MANAGER
MCLK
Advance Product Information
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
DGND
AGND
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright  Cirrus Logic, Inc. 1999
(All Rights Reserved)
JUL ‘99
DS307PP1
1
CS4228
TABLE OF CONTENTS
CHARACTERISTICS AND SPECIFICATIONS ................................................... 4
ANALOG CHARACTERISTICS................................................................... 4
DIGITAL CHARACTERISTICS.................................................................... 6
SWITCHING CHARACTERISTICS ............................................................. 6
SWITCHING CHARACTERISTICS - CONTROL PORT ............................. 8
ABSOLUTE MAXIMUM RATINGS ............................................................ 10
RECOMMENDED OPERATING CONDITIONS ........................................ 10
TYPICAL CONNECTION DIAGRAM ................................................................. 11
FUNCTIONAL DESCRIPTION .......................................................................... 12
Overview ................................................................................................... 12
Analog Inputs ............................................................................................ 12
Line Level Inputs ................................................................................ 12
High Pass Filter .................................................................................. 12
Analog Outputs ......................................................................................... 12
Line Level Outputs ............................................................................. 12
Digital Volume Control ....................................................................... 13
Mute Control ............................................................................................. 13
Clock Generation ...................................................................................... 14
Clock Source ...................................................................................... 14
Synchronization .................................................................................. 14
Digital Interfaces ....................................................................................... 14
Serial Audio Interface Signals ............................................................ 14
Serial Audio Interface Formats ........................................................... 14
Control Port Signals .................................................................................. 14
SPI Mode ........................................................................................... 16
I2C Mode ............................................................................................ 16
Control Port Bit Definitions ........................................................................ 17
Power-up/Reset/Power Down Mode ......................................................... 17
Power Supply, Layout, and Grounding ..................................................... 18
REGISTER DESCRIPTION ................................................................................ 19
PIN DESCRIPTION............................................................................................. 24
PARAMETER DEFINITIONS ............................................................................. 28
PACKAGE DIMENSIONS .................................................................................. 29
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/
Dolby, Pro Logic, and AC-3 are trademarks of Dolby Laboratories Licensing Corporation.
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of
any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights
of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of
this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or
otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no
part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical,
photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture
or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing
in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
2
DS307PP1
CS4228
LIST OF FIGURES
Figure 1. Serial Audio Port Master Mode Timing ...................................................... 7
Figure 2. Serial Audio Port Slave Mode Timing ........................................................ 7
Figure 3. SPI Control Port Timing ............................................................................. 8
Figure 4. I2C Control Port Timing .............................................................................. 9
Figure 5. Recommended Connection Diagram ....................................................... 11
Figure 6. Optional Line Input Buffer ........................................................................ 12
Figure 7. Passive Output Filter with Mute ............................................................... 13
Figure 8. Butterworth Output Filter with Mute .......................................................... 13
Figure 9. Right Justified Serial Audio Formats ........................................................ 15
Figure 10.I2S Serial Audio Formats .......................................................................... 15
Figure 11.Left Justified Serial Audio Formats .......................................................... 15
Figure 12.One Line Data Serial Audio Format ......................................................... 16
Figure 13.Control Port Timing, SPI mode ................................................................ 17
Figure 14.Control Port Timing, I2C Mode ................................................................. 17
DS307PP1
3
CS4228
CHARACTERISTICS AND SPECIFICATIONS
ANALOG CHARACTERISTICS (Unless otherwise specified TA = 25°C; VA = +5V, VD = VL = +3.3V;
Full Scale Input Sine wave, 1kHz; Fs = 44.1 kHz BRM, 96 kHz HRM; Measurement Bandwidth is 20 Hz to 20 kHz;
Local components as shown in "Recommended Connection Diagram"; SPI control mode, Left Justified serial format, MCLK = 256 Fs BRM, 128 Fs HRM, SCLK = 64 Fs)
Base Rate Mode
High Rate Mode
Parameter
Symbol Min
Typ Max Min
Typ Max
Units
Analog Input Characteristics - Minimum gain setting (0 dB) Differential Input; unless otherwise specified.
16
24
16
24
Bits
ADC Resolution
Stereo Audio channels
THD
-
0.003
-
-
0.003
-
%
TBD
-
102
99
-
TBD
TBD
102
99
-
dB
dB
Total Harmonic Distortion + Noise -1dB (Note 1) THD+N
-
-90
TBD
-
-90
TBD
dB
Interchannel Isolation
-
90
-
-
90
-
dB
Interchannel Gain Mismatch
-
0.1
-
-
0.1
-
dB
Offset Error (with high pass filter)
-
-
0
-
-
0
LSB
Total Harmonic Distortion
Dynamic Range
(A weighted)
(unweighted)
5.66
Full Scale Input Voltage (Differential):
Gain Drift
Input Resistance
Input Capacitance
5.66
Vp-p
-
100
-
-
100
-
ppm/°C
10
-
-
10
-
-
kΩ
-
-
15
15
pF
0.02
-
20.0
0.02
-
40
kHz
-
-
0.01
-
-
0.05
dB
5617 66.53
-
5578
kHz
A/D Decimation Filter Characteristics
Passband
(Note 2)
Passband Ripple
Stopband
(Note 2)
27.56
-
Stopband Attenuation
(Note 3)
80
-
-
45
-
-
dB
Group Delay
(Note 4)
tgd
-
15/Fs
-
-
15/Fs
-
s
∆ tgd
-
-
0
-
-
0
µs
(Note 2)
-0.13 dB
-
3.4
20
-
-
3.4
20
-
Hz
Hz
@ 20 Hz
(Note 2)
-
10
-
-
10
-
Degree
-
-
0
-
-
0
dB
Group Delay Variation vs. Frequency
High Pass Filter Characteristics
Frequency Response:
Phase Deviation
Passband Ripple
-3 dB
Notes: 1. Referenced to typical full-scale differential input voltage (2 Vrms).
2. Filter characteristics scale with output sample rate.
3. The analog modulator samples the input at 5.6448 MHz for an output sample rate of 44.1 kHz. There is
no rejection of input signals which are multiples of the sampling frequency (n × 5.6448 MHz ±20.0 kHz
where n = 0,1,2,3...).
4. Group delay for Fs = 44.1 kHz, tgd = 15/44.1 kHz = 340 µs. Fs = sample rate.
Specifications are subject to change without notice
4
DS307PP1
CS4228
ANALOG CHARACTERISTICS
(Continued)
Base Rate Mode
Parameter
Symbol
Min
Typ
Max
High Rate Mode
Min
Typ
Max
Units
Analog Output Characteristics - Minimum Attenuation, 10 kΩ, 100 pF load; unless otherwise specified.
16
24
16
24
DAC Resolution
Bits
Signal-to-Noise/Idle Channel Noise
(DAC muted, A weighted)
TBD
103
-
TBD
103
-
dB
Dynamic Range
TBD
-
103
100
-
-
103
100
-
dB
dB
THD
-
0.003
-
-
0.003
-
%
THD+N
-
-90
TBD
-
-90
-
dB
Interchannel Isolation
-
90
-
-
90
-
dB
Interchannel Gain Mismatch
-
0.1
-
-
0.1
-
dB
TBD
0.5
TBD
TBD
0.5
TBD
dB
TBD
-90.5
-
TBD
-90.5
-
dB
-
10
-
-
10
-
mV
TBD
1.3
TBD
-
1.3
-
Vrms
-
100
-
-
100
-
ppm/°C
-
10
100
-
-
10
100
-
kΩ
pF
(DAC not muted, A weighted)
(DAC not muted, unweighted)
Total Harmonic Distortion
Total Harmonic Distortion + Noise
Attenuation Step Size
(All Outputs)
Programmable Output Attenuation Span
Offset Voltage
Full Scale Output Voltage
Gain Drift
Analog Output Load
Minimum Load Resistance:
Maximum Load Capacitance:
Combined Digital and Analog Filter Characteristics
Frequency Response
±0.1
10 Hz to 20 kHz
dB
-
±0.5
-
-
±0.5
-
Degrees
(Notes 5, 6)
0
-
20.0
0
-
40
kHz
(Note 6)
-
-
±0.01
-
-
±0.01
dB
Deviation from Linear Phase
Passband: to 0.01 dB corner
±0.1
Passband Ripple
Stopband
(Notes 5, 6)
24.1
-
-
56
-
-
kHz
Stopband Attenuation
(Notes 4, 7)
70
-
-
65
-
-
dB
tgd
-
16/Fs
-
-
16/Fs
-
s
CCIR-2K
-
TBD
-
-
TBD
-
dB
Group Delay (Fs = Input Word Rate)
Analog Loopback Performance
Signal-to-noise Ratio
(CCIR-2K weighted, -20 dB FS input)
Notes: 5. The passband and stopband edges scale with frequency. For input word rates, Fs, other than 44.1 kHz,
the 0.01 dB passband edge is 0.4535×Fs and the stopband edge is 0.5465×Fs.
6. Digital filter characteristics.
7. Measurement bandwidth is 10 Hz to 3 Fs.
Specifications are subject to change without notice
DS307PP1
5
CS4228
ANALOG CHARACTERISTICS
(Continued)
Power Supply
Power Supply Current
VA = 5V, VD = VL = 3.3V
Power Supply Rejection
Symbol
Min
Typ
Max
Min
Typ
Max
Units
-
25
2
42
TBD
TBD
TBD
-
25
2
48
TBD
TBD
TBD
mA
mA
mA
-
TBD
2
0.1
TBD
TBD
TBD
-
TBD
2
0.1
TBD
TBD
TBD
mA
mA
mA
-
50
-
Operating
VA
VL
VD
Power Down
VA
VL
VD
(1 kHz, 10 mVrms)
50
dB
DIGITAL CHARACTERISTICS Unless otherwise specified (TA = 25 °C; VD = VL = +3.3V;
VA =+ 5V)
Parameter
Symbol
Min
Typ
Max
Units
High-level Input Voltage
VIH
0.7xVL
-
-
V
Low-level Input Voltage
VIL
-
0.3xVL
V
High-level Output Voltage at I0 = -2.0 mA
VOH
VL - 1.0
-
-
V
Low-level Output Voltage at I0 = 2.0 mA
VOL
-
-
0.4
V
(Digital Inputs)
-
-
10
µA
(High-Impedance Digital Outputs)
-
-
10
µA
Input Leakage Current
Output Leakage Current
SWITCHING CHARACTERISTICS
(TA = 25°C; VD = VL = +3.3V, VA = +5V, outputs loaded with
30 pF)
Parameter
Audio ADC's & DAC's Sample Rate
Symbol
Min
Typ
Max
Units
Fs
30
60
-
50
100
kHz
kHz
3.84
-
25.6
MHz
BRM
MCLK =128, 384 Fs
MCLK = 256, 512 Fs
TBD
40
50
TBD
60
%
%
HRM
MCLK = 64, 192 Fs
MCLK = 128, 256 Fs
TBD
40
50
-
TBD
60
%
%
-
500
-
ps
BRM
HRM
MCLK Frequency
MCLK Duty Cycle
MCLK Jitter Tolerance
6
DS307PP1
CS4228
SWITCHING CHARACTERISTICS (Continued)
Parameter
Symbol
Typ
Max
Units
-
-
ms
tdpd
-
TBD
ns
LRCK Edge to MSB Valid
tlrpd
-
TBD
ns
SDIN Setup Time Before SCLK Rising Edge
tds
-
TBD
ns
SDIN Hold Time After SCLK Rising Edge
tdh
-
TBD
ns
tmslr
+10
-
ns
50
-
%
-
-
ns
RST Low Time
1
(Note 8)
SCLK Falling Edge to SDOUT Output Valid
(DSCK=0)
Master Mode
SCLK Falling to LRCK Edge
SCLK Duty Cycle
Slave Mode
SCLK Period
tsckw
SCLK High Time
tsckh
TBD
-
-
ns
SCLK Low Time
tsckl
TBD
-
-
ns
SCLK rising to LRCK Edge
(DSCK=0)
tlrckd
TBD
-
-
ns
LRCK Edge to SCLK Rising
(DSCK=0)
tlrcks
TBD
-
-
ns
Notes: 8. After powering up the CS4228, RST should be held low until the power supplies and clocks are settled.
LRCK
(input)
t lrckd
SCLK*
(output)
t lrcks
t sckh
t sckl
SCLK*
(input)
t sckw
t mslr
LRCK
(output)
SDIN1
SDIN2
SDIN3
t lrpd t ds
SDOUT
SDOUT
t dh
MSB
t dpd
MSB-1
*SCLK shown for DSCK = 0.
SCLK inverted for DSCK = 1.
Figure 1. Serial Audio Port Master Mode Timing
DS307PP1
Figure 2. Serial Audio Port Slave Mode Timing
7
CS4228
SWITCHING CHARACTERISTICS - CONTROL PORT (TA = 25°C, VD = VL = +3.3V,
VA = +5V; Inputs: logic 0 = DGND, logic 1 = VL+, CL = 30 pF)
Parameter
Symbol
Min
Max
Units
CCLK Clock Frequency
fsck
-
6
MHz
CS High Time Between Transmissions
tcsh
1.0
µs
CS Falling to CCLK Edge
tcss
20
ns
CCLK Low Time
tscl
66
ns
CCLK High Time
tsch
66
ns
CDIN to CCLK Rising Setup Time
tdsu
40
ns
(Note 9)
tdh
15
ns
Rise Time of CCLK and CDIN
(Note 10)
tr2
100
ns
Fall Time of CCLK and CDIN
(Note 10)
tf2
100
ns
SPI Mode (SDOUT > 47kΩ to GND)
CCLK Rising to DATA Hold Time
Notes: 9. Data must be held for sufficient time to bridge the transition time of CCLK.
10. For FSCK < 1 MHz
CS
t css
t scl
t sch
t csh
CCLK
t r2
t f2
CDIN
t dsu
t dh
Figure 3. SPI Control Port Timing
8
DS307PP1
CS4228
SWITCHING CHARACTERISTICS - CONTROL PORT (TA = 25°C; VD = VL = +3.3V,
VA = +5V; Inputs: logic 0 = DGND, logic 1 = VL, CL = 30 pF)
Parameter
Symbol
Min
Max
Units
SCL Clock Frequency
fscl
-
100
kHz
Bus Free Time Between Transmissions
tbuf
4.7
µs
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
µs
Clock Low Time
tlow
4.7
µs
Clock High Time
thigh
4.0
µs
Setup Time for Repeated Start Condition
tsust
4.7
µs
thdd
0
µs
tsud
250
ns
2 ®
I C Mode (SDOUT < 47kΩ to ground)
(Note 11)
SDA Hold Time from SCL Falling
(Note 12)
SDA Setup Time to SCL Rising
Rise Time of Both SDA and SCL Lines
tr
1
µs
Fall Time of Both SDA and SCL Lines
tf
300
ns
tsusp
Setup Time for Stop Condition
µs
4.7
Notes: 11. Use of the I2C bus interface requires a license from Philips. I2C is a registered trademark of Philips
Semiconductors.
12. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Stop
Repeated
Start
Start
Stop
SDA
t buf
t
t high
t hdst
tf
hdst
t susp
SCL
t
low
t
hdd
t sud
t sust
tr
Figure 4. I2C Control Port Timing
DS307PP1
9
CS4228
ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0 V, all voltages with respect to 0 V.)
Parameter
Symbol
Min
Typ
Max
Units
VD
VA
VL
-0.3
-0.3
-0.3
-
6.0
6.0
6.0
V
V
V
Power Supplies
Digital
Analog
Interface
Input Current
(Note 13)
-
-
±10
mA
Analog Input Voltage
(Note 14)
-0.7
-
VA + 0.7
V
Digital Input Voltage
(Note 14)
-0.7
-
VL + 0.7
V
(Power Applied)
-55
-
+125
°C
-65
-
+150
°C
Ambient Temperature
Storage Temperature
Notes: 13. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause
SCR latch-up.
14. The maximum over or under voltage is limited by the input current.
Warning:
Operation at or beyond these limits may result in permanent damage to the device. Normal operation
is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AGND, DGND = 0 V, all voltages with respect
to 0 V.)
Parameter
Power Supplies
Operating Ambient Temperature
10
Digital
Analog
Interface
Symbol
Min
Typ
Max
Units
VD
VA
VL
TBD
4.75
2.7
3.3
5.0
5.0
TBD
5.25
5.25
V
V
V
TA
-10
25
70
°C
DS307PP1
CS4228
TYPICAL CONNECTION DIAGRAM
Ferrite Bead
+5V
Supply
+ 1 µF
0.1 µF
+ 1 µF
21
VA
From Analog Input Stage
0.1 µF
8
+3.3V
Supply
Ferrite Bead
+ 1 µF
19
2.2 nf
+
100 µF
22 µF
150 Ω
+
VL
17
2.2 nf
AOUT3
AINR-
AOUT4
AOUT5
18
24
ANALOG
FILTER
25
ANALOG
FILTER
26
ANALOG
FILTER
27
ANALOG
FILTER
28
ANALOG
FILTER
CS4228
16
0.1µF
10 µF +
ANALOG
FILTER
AINL+
AINR+
+
23
AINLAOUT2
20
0.1µF
+3.3V or 5 V
Supply
0.1 µF
9
VD
AOUT1
22 µF 150 Ω
+
100 µF
VL
Ferrite Bead
FILT
AOUT6
MUTEC
VL
15
50 Ω
2.2 K*
Microcontroller
LRCK
SDA/CDIN
12
SCL/CCLK
11
AD0/CS
13
RST
14
SCLK
SDIN1
SDIN2
SDIN3
SDOUT
6
50 Ω
5
Digital Audio
Peripheral
or
DSP
3
2
1
4
50 Ω
33 K*
All unused inputs
should be tied to 0V.
AGND
22
DGND
7
2
MCLK
10
External
Clock Input
* Required for I C
control port mode
only
Figure 5. Recommended Connection Diagram
DS307PP1
11
CS4228
FUNCTIONAL DESCRIPTION
4.7 k
Overview
10 µF
signal
The CS4228 is a 24-bit audio codec comprised of 2
analog-to-digital converters (ADC) and 6 digitalto-analog converters (DAC), all implemented using single-bit delta-sigma techniques. Other functions integrated with the codec include independent
digital volume controls for each DAC, digital DAC
de-emphasis filters, ADC high-pass filters, an onchip voltage reference, and a flexible serial audio
interface. All functions are configured through a
serial control port operable in SPI and I2C compatible modes. Figure 5 shows the recommended connections for the CS4228.
Analog Inputs
Line Level Inputs
AINR+, AINR-, AINL+, and AINL- are the line
level analog inputs (See Figure 5). These pins are
internally biased to a DC operating voltage of approximately 2.3 VDC. AC coupling the inputs preserves this bias and minimizes signal distortion.
Figure 5 shows operation with a single-ended input
source. This source may be supplied to either the
positive or negative input as long as the unused input is connected to ground through capacitors as
shown. When operated with single-ended inputs,
distortion will increase at input levels higher than
-1 dBFS. Figure 6 shows an example of a differential input circuit.
Muting of the stereo ADC is possible through the
ADC Control Byte.
The ADC output data is in 2’s complement binary
format. For inputs above positive full scale or below negative full scale, the ADC will output
7FFFFFH or 800000H, respectively.
High Pass Filter
Digital high pass filters in the signal path after the
ADCs remove any DC offsets present on the analog
12
10 k
-
150
+
AIN +
10 k
2.2 nf
10 k
+
10 k
150
AIN +
-
VA
+
~ 8.5 k
10 µf
0.1µF
Figure 6. Optional Line Input Buffer
inputs. This helps to prevent audible "clicks" when
switching the audio in devices downstream from
the ADCs. The high pass filter response, given in
“High Pass Filter Characteristics” on page 4, scales
linearly with sample rate. Thus, for High Rate
Mode, the -3 dB frequency at a 96 kHz sample rate
will be equal to 96/44.1 times that at a sample rate
of 44.1 kHz.
The high pass filters can be disabled by setting the
HPF bit in the ADC Control register. When asserted, any DC present at the analog inputs will be represented in the ADC outputs. The high pass filter
may also be “frozen” using the HPFZ bit in the
ADC Control register. In this condition, it will remember the DC offset present at the ADC inputs at
the moment the HPFZ bit was asserted, and will
continue to remove this DC level from the ADC
outputs. This is useful in cases where it is desirable
to eliminate a fixed DC offset while still maintaining full frequency response down to DC.
Analog Outputs
Line Level Outputs
The CS4228 contains on-chip buffer amplifiers capable of producing line level outputs. These amplifiers are biased to a quiescent DC level of
approximately 2.3 V. This bias, as well as variations in offset voltage, are removed using off-chip
AC load coupling.
DS307PP1
CS4228
High frequency noise beyond the audio passband,
resulting from the delta-sigma conversion process
produces high frequency noise beyond the audio
passband, most of which is removed by the on-chip
analog filters. The remaining out-of-band noise can
be attenuated using an off-chip low pass filter. For
most applications, a simple passive filter as show in
Figure 7 can be used. Note that this circuit also
serves to block the DC present at the outputs. Figure 8 gives an example of a filter which can be used
in applications where greater out of band attenuation is desired. The 2-pole Butterworth filter has a
-3 dB frequency of 50 kHz, a passband attenuation
of 0.1 dB at 20 kHz providing optimal out-of-band
filtering for sample rates from 44.1 kHz to 96 kHz.
The filter has and a gain of 1.56 providing a 2 Vrms
output signal.
10 k
MUTEC
AOUT
MUTEDRV
560
Line Out
C
100 k
2SC2878
2.2 k
C=142µF
Fs
Each DAC’s output level is controlled via the Digital Volume Control register operating over the
range of 0 to 90.5 dB attenuation with 0.5 dB resolution. Volume control changes do not occur instantaneously. Instead they ramp in increments of
0.125 dB at a variable rate controlled by the
RMP1:0 bits in the Digital Volume Control register.
Each output can be independently muted via mute
control bits MUT6-1 in the DAC Mute1 Control
register. When asserted, MUT attenuates the corresponding DAC to its maximum value (90.5 dB).
When MUT is deasserted, the corresponding DAC
returns to the attenuation level set in the Digital
Volume Control register. The attenuation is
ramped up and down at the rate specified by the
RMP1:0 bits.
To achieve complete digital attenutation of an incoming signal, Hard Mute controls are provided.
When asserted, Hard Mute will send zero data to a
corresponding pair of DACs. Hard Mute is not
ramped, so it should only be asserted after setting
the two corresponding MUT bits to prevent high
frequency noise from appearing on the DAC outputs. Hard Mute is controlled by the
HMUTE56/34/12 bits in the DAC Mute2 Control
register.
MUN2IIIT1
10 k
22 µ F
+
Digital Volume Control
Figure 7. Passive Output Filter with Mute
Mute Control
1 nf
3.16 k
+12
3.16 k
5
AOUT
1 nf
GND
3.16 k
6
+
7
_
MC33078
-12
+
MUTE
10 µf
MUTE DRV
1.78 k
100 pf
Figure 8. Butterworth Output Filter with Mute
DS307PP1
Line
Out
The Mute Control pin is typically connected to an
external mute control circuit as shown in Figure 7
and Figure 8. Mute Control is asserted during power up, power down, and when serial port clock errors are present. The pin can also be controlled by
the user via the control port, or automatically asserted when zero data is present on all six DAC inputs. To prevent large transients on the output, it is
desirable to mute the DAC outputs before the Mute
Control pin is asserted. Please see the MUTEC pin
in the Pin Descriptions section for more information.
13
CS4228
Clock Generation
The master clock, MCLK, is supplied to the
CS4228 from an external clock source. If MCLK
stops for 10µs, the CS4228 will enter Power Down
Mode in which the supply current is reduced as
specified under “Power Supply” on page 6. In all
modes it is required that the number of MCLK periods per SCLK and LRCK period be constant.
Clock Source
The CS4228 internal logic requires an external
master clock, MCLK, that operates at multiples of
the sample rate frequency, Fs. The MCLK/Fs ratio
is determined by the CI1:0 bits in the CODEC
Clock Mode register.
Synchronization
The serial port is internally synchronized with
MCLK. If from one LRCK cycle to the next, the
number of MCLK cycles per LRCK cycle changes
by more than 32, the CS4228 will undergo an internal reset of its data paths in an attempt to resynchronize. Consequently, it is advisable to mute the
DACs when changing from one clock source to another to avoid the output of undesirable audio signals as the device resynchronizes.
Digital Interfaces
Serial Audio Interface Signals
The serial audio data is presented in 2's complement binary form with the MSB first in all formats.
The serial interface clock, SCLK, is used for both
transmitting and receiving audio data. SCLK can
be generated by the CS4228 (master mode) or it
can be input from an external source (slave mode).
Mode selection is made with the DMS1:0 bits in
the Serial Port Mode register. The number of
SCLK cycles in one sample period can be set using
the DCK1:0 bits as detailed in the Serial Port Mode
register.
14
The Left/Right clock (LRCK) is used to indicate
left and right data frames and the start of a new
sample period. It may be an output of the CS4228
(master mode), or it may be generated by an external source (slave mode). The frequency of LRCK is
the same as the system sample rate, Fs.
SDIN1, SDIN2, and SDIN3 are the data input pins.
SDOUT, the data output pin, carries data from the
two 24-bit ADC's. The serial audio port may also
be operated in One Line Data Mode in which all 6
channels of DAC data is input on SDIN1 and the
stereo ADC data is output on SDOUT. Table 1 outlines the serial port input to DAC channel allocations.
DAC Inputs
SDIN1
left channel
right channel
single line
SDIN2
left channel
right channel
SDIN3
left channel
right channel
DAC #1
DAC #2
All 6 DAC channels
DAC #3
DAC #4
DAC #5
DAC #6
Table 1. Serial Audio Port Input Channel Allocations
Serial Audio Interface Formats
The digital audio port supports 6 formats, shown in
Figures 9, 10, 11 and 12. These formats are selected
using the DDF2:0 bits in the Serial Port Mode register.
In One Line Data Mode, all 6 DAC channels are input on SDIN1. One Line Data Mode is only available in BRM. See Figure 12 for channel
allocations.
Control Port Signals
Internal registers are accessed through the control
port. The control port may be operated asynchronously with respect to audio sample rate. However,
to avoid potential interference problems, the control port pins should remain static if no register access is required.
DS307PP1
CS4228
LRCK
Right Channel
Left Channel
SCLK
SDIN1/2/3
SDOUT
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Right Justified Mode, Data Valid on Rising Edge of SCLK
Bits/Sample
SCLK Rate(s)
Notes
16
32, 48, 64, 128 Fs
48 Fs Slave only
20
48, 64, 128 Fs
48 Fs Slave only
24
48, 64, 128 Fs
48 Fs Slave only
Figure 9. Right Justified Serial Audio Formats
Left Channel
LRCK
Right Channel
SCLK
SDIN1/2/3
SDOUT
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4 -5
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
Left Justified Mode, Data Valid on Rising Edge of SCLK
Bits/Sample
SCLK Rate(s)
Notes
16
32, 48, 64, 128 Fs
48 Fs Slave only
18 to 24
48, 64, 128 Fs
48 Fs Slave only
Figure 10. Left Justified Serial Audio Formats
Left Channel
LRCK
Right Channel
SCLK
SDIN1/2/3
SDOUT
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
I2S Mode, Data Valid on Rising Edge of SCLK
Bits/Sample
SCLK Rate(s)
Notes
16
32, 48, 64, 128 Fs
48 Fs Slave only
18 to 24
48, 64, 128 Fs
48 Fs Slave only
Figure 11. I2S Serial Audio Formats
DS307PP1
15
CS4228
LRCK
64 clks
64 clks
Left Channel
Right Channel
SCLK
SDIN1/2/3
SDOUT
MSB
LSB MSB
LSB MSB
LSB
MSB
LSB MSB
LSB MSB
DAC1
DAC3
DAC5
DAC2
DAC4
DAC6
20 clks
20 clks
20 clks
20 clks
20 clks
20 clks
ADCL
ADCR
20 clks
20 clks
LSB
MSB
One Line Data Mode, Data Valid on Rising Edge of SCLK
Bits/Sample
SCLK Rate(s)
Notes
20
128 Fs
6 inputs, 2 outputs, BRM only
Figure 12. One Line Data Serial Audio Format
The control port has 2 operating modes: SPI and
I2C compatible. In both modes the CS4228 operates as a slave device. Mode selection is determined by the state of the SDOUT pin when RST
transitions from low to high: high for SPI, low for
I2C. SDOUT is internally pulled high to VL. A resistive load from SDOUT to DGND of less than 47
kΩ will enable I2C Mode after a reset.
SPI Mode
In SPI mode, CS is the CS4228 chip select signal,
CCLK is the control port bit clock input, and CDIN
is the input data line. There is no data output line,
therefore all registers are write-only in SPI mode.
Data is clocked in on the rising edge of CCLK.
Figure 13 shows the operation of the control port in
SPI mode. The first 7 bits on CDIN, after CS goes
low, form the chip address (0010000). The eighth
bit is a read/write indicator (R/W), which should be
low to write. The next 8 bits set the Memory Address Pointer (MAP) which is the address of the
register that is to be written. The following bytes
contain the data which will be placed into the registers designated by the MAP.
16
The CS4228 has a MAP auto increment capability,
enabled by the INCR bit in the MAP register. If
INCR is zero, then the MAP will stay constant for
successive reads or writes. If INCR is 1, then MAP
will increment after each byte is read or written, allowing block reads or writes of successive registers.
I2C Mode
In I2C mode, SDA is a bidirectional data line. Data
is clocked into and out of the port by the SCL clock.
The signal timing is shown in Figure 14. The AD0
pin forms the LSB of the chip address. The upper 6
bits of the 7 bit address field must be 001000. To
communicate with a CS4228, the LSB of the chip
address field, which is the first byte sent to the
CS4228 after a Start condition, should match the
setting of the AD0 pin. The eighth bit of the address
bit is the R/W bit (high for a read, low for a write).
When writing, the next byte is the Memory Address Pointer (MAP) which selects the register to
be read or written. If the operation is a read, the
contents of the register pointed to by the MAP will
be output. Setting the auto increment bit in the
DS307PP1
CS4228
mode in which the control port is inactive. The part
may be held in a low power reset state by clearing
the DIGPDN bit in the Chip Control register. In this
state, the digital portions of the CODEC are in reset, but the control port is active and the desired
register settings can be loaded. Normal operation is
achieved by setting the DIGPDN bit to 1, at which
time the CODEC powers up and normal operation
begins.
MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit.
Control Port Bit Definitions
All registers are read/write, except the Chip Status
register which is read-only. For more detailed information, see the bit definition tables starting on
page 19.
The CS4228 will enter a stand-by mode if the master clock source stops for approximately 10 µs or if
the number of MCLK cycles per LRCK period varies by more than 32. Should this occur, the control
registers retain their settings.
Power-up/Reset/Power Down Mode
Upon power up, the user should hold RST = 0 until
the power supplies and clocks stabilize. In this
state, the control registers are reset to their default
settings, and the device remains in a low power
CS
CCLK
CHIP
ADDRESS
CDIN
0010000
MAP
MSB
R/W
CHIP
ADDRESS
DATA
byte 1
LSB
0010000
R/W
byte n
MAP = Memory Address Pointer
Figure 13. Control Port Timing, SPI mode
Note 1
001000 AD 0
SDA
R/W
ACK
D7:0
ACK
D7:0
ACK
SCL
Start
Stop
Note 1: If operation is a write, this byte contains the Memory Address Pointer, MAP.
Figure 14. Control Port Timing, I2C Mode
DS307PP1
17
CS4228
The CS4228 will mute the analog outputs, assert
the MUTEC pin and enter the Power Down Mode
if the supply drops below approximately 4 volts.
Power Supply, Layout, and Grounding
The CS4228 requires careful attention to power
supply and grounding details. VA is normally supplied from the system analog supply. VD is from a
3.3VDC supply, and VL should be from the supply
used for the devices digitally interfacing with the
CS4228. The power up sequence of these three
supply pins is not important.
AGND and DGND pins should both be tied to a
solid ground plane surrounding the CS4228. If the
system analog and digital ground planes are separate, they should be connected at a point near where
18
the supply currents enter the board. A solid ground
plane underneath the part is recommended.
Decoupling capacitors should be mounted in such a
way as to minimize the circuit path length from the
CS4228 supply pin, through the capacitor, to the
applicable CS4228 AGND or DGND pin. The
small value ceramic capacitors should be closest to
the part. In some cases, ferrite beads in the VL, VD
and VA supply lines, and low-value resistances
(~ 50 Ω) in series with the LRCK, SCLK, and SDOUT lines can help reduce coupling of digital signals into the analog.
The capacitor on the FILT pin should be as close to
the CS4228 as possible. See Crystal’s layout Applications Note, and the CDB4228 evaluation board
data sheet for recommended layout of the decoupling components.
DS307PP1
CS4228
REGISTER DESCRIPTION
All registers are read/write except for Chip Status, which is read only. See the following bit definition tables for bit
assignment information. The default bit state after power-up sequence or reset is listed underneath the bit definition
for that field. Default values are also marked with an asterick.
Memory Address Pointer (MAP) - not a register
7
6
INCR
1
5
RESERVED
0
0
4
3
2
1
0
MAP4
MAP3
MAP2
MAP1
MAP0
0
0
0
0
1
INCR
memory address pointer auto increment control
0MAP is not incremented automatically.
*1 - internal MAP is automatically incremented after each read or write.
MAP4:0
Memory address pointer (MAP). Sets the register address that will be read or written by the control port.
CODEC Clock Mode
Address 0x01
7
6
5
HRM
0
4
RESERVED
0
0
0
3
2
CI1
CI0
0
1
1
0
RESERVED
0
0
HRM
Sets the sample rate mode for the ADCs and DACs
*0 - Base Rate Mode (BRM) supports sample rates up to 50kHz
1High Rate Mode (HRM) supports sample rates up to 100 kHz. Typically used for
96 kHz sample rate.
CI1:0
Specifies the ratio of MCLK to the sample rate of the ADCs and DACs (Fs)
DS307PP1
CI1:0
BRM (Fs)
HRM (Fs)
0
128
64
*1
256
128
2
384
192
3
512
256
19
CS4228
Chip Control
Address 0x02
7
6
DIGPDN
5
RESERVED
1
0
4
3
2
1
0
ADCPDN
DACPDN56
DACPDN34
DACPDN12
RESERVED
0
0
0
0
0
0
DIGPDN
Power down the digital portions of the CODEC
0Digital power down.
*1 - Normal operation
ADCPDN
Power down the analog section of the ADC
*0 - Normal
1ADC power down.
DACPDN12
Power down the analog section of DAC 1&2
*0 - Normal
1Power down DAC 1&2.
DACPDN34
Power down the analog section of DAC 3&4
*0 - Normal
1Power down DAC 3&4.
DACPDN56
Power down the analog section of DAC 5&6
*0 - Normal
1Power down DAC 5&6.
ADC Control
Address 0x03
7
6
5
4
MUTL
MUTR
HPF
HPFZ
0
0
0
0
3
2
0
0
1
0
0
0
RESERVED
MUTL, MUTR
ADC left and right channel mute control
*0 - Normal
1Selected ADC output muted
HPF
ADC DC offset removal. See “High Pass Filter” on page 12 for more information
*0 - Enabled
1Disabled
HPFZ
ADC DC offset averaging freeze. See “High Pass Filter” on page 12 for more information
*0 - Normal. The DC offset average is dynamically calculated and subtracted from incoming
ADC data.
1Freeze. The DC offset average is frozen at the current value and subtracted from
incoming ADC data. Allows passthru of DC information.
20
DS307PP1
CS4228
DAC Mute1 Control
Address 0x04
7
6
5
4
3
2
1
0
MUT6
MUT5
MUT4
MUT3
MUT2
MUT1
RMP1
RMP0
1
1
1
1
1
1
0
0
MUT6 - MUT1
Mute control for DAC6 - DAC1 respectively. When asserted, the corresponding DAC is digitally
attenuated to its maximum value (90.5 dB). When deasserted, the corresponding DAC attenutation value returns to the value stored in the corresponding Digital Volume Control register. The
attenuation value is ramped up and down at the rate specified by RMP1:0.
0Normal output level
*1 - Selected DAC output fully attenuated.
RMP1:0
Attenuation ramp rate.
*0 - 0.5dB change per 4 LRCKs
10.5dB change per 8 LRCKs
20.5dB change per 16 LRCKs
30.5dB change per 32 LRCKs
DAC Mute2 Control
Address 0x05
7
6
MUTEC
MUTCZ
0
0
5
4
RESERVED
0
0
3
2
1
0
HMUTE56
HMUTE34
HMUTE12
RESERVED
0
0
0
0
MUTEC
Controls the MUTEC pin
*0 - Normal operation
1MUTEC pin asserted low
MUTCZ
Automatically asserts the MUTEC pin on consecutive zeros. When enabled, 512 consecutive
zeros on all six DAC inputs will cause the MUTEC pin to be asserted low. A single non-zero
value on any DAC input will cause the MUTEC pin to deassert.
*0 - Disabled
1Enabled
HMUTE56/34/12
Hard mute the corresponding DAC pair. When asserted, zero data is sent to the corresponding
DAC pair causing an instantaneous mute. To prevent high frequency transients on the outputs,
a DAC pair should be fully attenuated by asserting the corresponding MUT6-MUT1 bits in the
DAC Mute Control register or by writing 0xFF to the corresponding Digital Volume Control registers before asserting HMUTE.
*0 - Normal operation
1DAC pair is muted
DS307PP1
21
CS4228
DAC De-emphasis Control
Address 0x06
7
6
5
4
3
2
1
0
DEMS1
DEMS0
DEM6
DEM5
DEM4
DEM3
DEM2
DEM1
1
0
0
0
0
0
0
0
3
2
1
0
0
0
0
0
DEMS1:0
Selects the DAC de-emphasis response curve.
0Reserved
1De-emphasis for 48 kHz
*2 - De-emphasis for 44.1 kHz
3De-emphasis for 32 kHz
DEM6 - DEM1
De-emphasis control for DAC6 - DAC1 respectively
*0 - De-emphasis off
1De-emphasis on
Digital Volume Control
Addresses 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C
7
6
5
4
0
0
0
0
VOLn
VOL6 - VOL1
22
Address 0x0C - 0x07 sets the attenuation level for DAC 6 - DAC1 respectively. The attenutation
level is ramped up and down at the rate specified by RMP1:0 in the DAC Volume Control Setup
register.
0 - 181 represents 0 to 90.5 dB of attenuation in 0.5 dB steps.
DS307PP1
CS4228
Serial Port Mode
Address 0x0D
7
6
5
4
3
2
1
0
DCK1
DCK0
DMS1
DMS0
RESERVED
DDF2
DDF1
DFF0
1
0
0
0
0
1
0
0
DCK1:0
Sets the number of Serial Clocks (SCLK) per Fs period (LRCLK)
DCK1:0
BRM (Fs)
HRM (Fs)
0
32 (1)
16 (3)
1
48 (2)
24 (4)
2
*64
32 (1)
3
128
Notes: 1.
2.
3.
4.
64
All formats will default to 16 bits
External Slave mode only
Only valid for left justified and I2S modes
Only valid for left justified and I2S, External Slave mode only
DMS1:0
Sets the master/slave mode of the serial audio port
*0 - Slave (External LRCLK, SCLK)
1Reserved
2Reserved
3Master (No 48 Fs SCLK in BRM, no 24 Fs SCLK in HRM)
DDF2:0
Serial Port Data Format
0Right Justified, 24-bit
1Right Justified, 20-bit
2Right Justified, 16-bit
3Left Justified, maximum 24-bit
*4 - I2S compatible, maximum 24-bit
5One-line Data Mode, available in BRM only
6Reserved
7Reserved
Chip Status
Address 0x0E
7
6
CLKERR
ADCOVL
X
X
5
4
3
2
1
0
0
0
0
RESERVED
0
0
0
CLKERR
Clocking system status, read only
0No Error
1No MCLK is present, or a request for clock change is in progress
ADCOVL
ADC overflow bit, read only
0No overflow
1ADC overflow has occurred
DS307PP1
23
CS4228
PIN DESCRIPTION
Serial Audio Data In 3
Serial Audio Data In 2
Serial Audio Data In 1
Serial Audio Data Out
Serial Clock
Left/Right Clock
Digital Ground
Digital Power
Digital Interface Power
Master Clock
SCL/CCLK
SDA/CDIN
AD0/CS
Reset
SDIN3
SDIN2
SDIN1
SDOUT
SCLK
LRCK
DGND
VD
VL
MCLK
SCL/CCLK
SDA/CDIN
AD0/CS
RST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AOUT6
AOUT5
AOUT4
AOUT3
AOUT2
AOUT1
AGND
VA
AINL+
AINLFILT
AINRAINR+
MUTEC
Analog Output 6
Analog Output 5
Analog Output 4
Analog Output 3
Analog Output 2
Analog Output 1
Analog Ground
Analog Power
Left Channel Analog Input+
Left Channel Analog InputInternal Voltage Filter
Right Channel Analog InputRight Channel Analog Input+
Mute Control
Serial Audio Data In - SDIN3, SDIN2, SDIN1
Pin 1, 2, 3, Input
Function:
Two’s complement MSB-first serial audio data is input on this pin. The data is clocked into SDIN1, SDIN2,
SDIN3 via the serial clock and the channel is determined by the Left/Right clock. The required relationship
between the Left/Right clock, serial clock and serial data is defined by the Serial Mode Register. The options are detailed in Figures 9, 10, 11 and 12.
Serial Audio Data Out - SDOUT
Pin 4, Output
Function:
Two’s complement MSB-first serial data is output on this pin. The data is clocked out of SDOUT via the
serial clock and the channel is determined by the Left/Right clock. The required relationship between the
Left/Right clock, serial clock and serial data is defined by the Serial Mode Register. The options are detailed in Figures 9, 10, 11 and 12.
The state of the SDOUT pin during reset is used to set the Control Port Mode (I2C or SPI). When RST is
low, SDOUT is configured as an input, and the rising edge of RST latches the state of the pin. A weak
internal pull up is present such that a resistive load less than 47 kΩ will pull the pin low, and the control
port mode is I2C. When the resistive load on SDOUT is greater than 47 kΩ during reset, the control port
mode is SPI.
24
DS307PP1
CS4228
Serial Clock — SCLK
Pin 5, Bidirectional
Function:
Clocks serial data into the SDIN1, SDIN2, and SDIN3 pins, and out of the SDOUT pin. The pin is an output
in master mode, and an input in slave mode.
In master mode, SCLK is configured as an output. MCLK is divided internally to generate SCLK at the
desired multiple of the sample rate.
In slave mode, SCLK is configured as an input. The serial clock can be provided externally, or the pin can
be grounded and the serial clock derived internally from MCLK.
The required relationship between the Left/Right clock, serial clock and serial audio data is defined by the
Serial Port Mode register. The options are detailed in Figures 9, 10, 11 and 12.
Left/Right Clock — LRCK
Pin 6, Bidirectional
Function:
The Left/Right clock determines which channel is currently being input or output on the serial audio data
output, SDOUT. The frequency of the Left/Right clock must be at the output sample rate, Fs. In Master
mode, LRCK is an output, in Slave Mode, LRCK is an input whose frequency must be equal to Fs and
synchronous to the Master clock.
Audio samples in Left/Right pairs represent simultaneously sampled analog inputs whereas Right/Left
pairs will exhibit a one sample period difference. The required relationship between the Left/Right clock,
serial clock and serial data is defined by the Serial Port Mode register. The options are detailed in Figures
9, 10, 11 and 12.
Digital Ground - DGND
Pin 7, Inputs
Function:
Digital ground reference.
Digital Power - VD
Pin 8, Input
Function:
Digital power supply. Typically 3.3 VDC.
Digital Interface Power - VL
Pin 9, Input
Function:
Digital interface power supply. Typically 3.3 or 5.0 VDC. All digital output voltages and input thresholds
scale with VL.
DS307PP1
25
CS4228
Master Clock - MCLK
Pin 10, Input
Function:
The master clock frequency must be either 128x, 256x, 384x or 512x the input sample rate in Base Rate
Mode (BRM) and either 64x, 128x, 192x, or 256x the input sample rate in High Rate Mode (HRM). Table
2 illustrates several standard audio sample rates and the required master clock frequencies. The
MCLK/Fs ration is set by the CI1:0 bits in the CODEC Clock Mode register
Sample
Rate
(kHz)
32
44.1
48
64
88.2
96
MCLK (MHz)
HRM
64x
4.0960
5.6448
6.1440
128x
8.1920
11.2896
12.2880
192x
12.2880
16.9344
18.4320
256x
16.3840
22.5792
24.5760
128x
4.0960
5.6448
6.1440
-
BRM
256x
384x
8.1920
12.2880
11.2896
16.9344
12.2880
18.4320
-
512x
16.3840
22.5792
24.5760
-
Table 2. Common Master Clock Frequencies
Serial Control Interface Clock - SCL/CCLK
Pin 11, Input
Function:
Clocks serial control data into or out of SDA/CDIN.
Serial Control Data I/O - SDA/CDIN
Pin 12, Bidirectional/Input
Function:
In I2C mode, SDA is a bidirectional control port data line. A pull up resistor must be provided for proper
open drain output operation. In SPI mode, CDIN is the control port data input line. The state of the SDOUT
pin during reset is used to set the control port mode.
Address Bit 0 / Chip Select - ADO/CS
Pin 13, Input
Function:
In I2C mode, AD0 is the LSB of the chip address. In SPI mode, CS is used as a enable for the control port
interface.
Reset - RST
Pin 14, Input
Function:
When low, the device enters a low power mode and all internal registers are reset to the default settings,
including the control port. The control port can not be accessed when reset is low.
When high, the control port and the CODEC become operational.
26
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CS4228
Mute Control - MUTEC
Pin 15, Output
Function:
The Mute Control pin goes low during the following conditions: power-up initialization, power-down, reset,
no master clock present, or if the master clock to left/right clock frequency ratio is incorrect. The Mute Control pin can also be user controlled by the MUTEC bit in the DAC Mute2 Control register. Mute Control can
be automatically asserted when 512 consecutive zeros are detected on all six DAC inputs, and automatically deasserted when a single non-zero value is sent to any of the six DACs. The mute on zero function
is controlled by the MUTCZ bit in the DAC Mute2 Control register. The MUTEC pin is intended to be used
as a control for an external mute circuit to achieve a very low noise floor during periods when no audio is
present on the DAC outputs, and to prevent the clicks and pops that can occur in any single supply system. Use of the Mute Control pin is not mandatory but recommended.
Differential Analog Inputs — AINR+, AINR- and AINL+, AINL-
Pins 16, 17 and 19, 20, Inputs
Function:
The analog signal inputs are presented deferentially to the modulators via the AINR+/- and AINL+/- pins.
The + and - input signals are 180° out of phase resulting in a nominal differential input voltage of twice the
input pin voltage. These pins are biased to the internal reference voltage of approximately 2.3 V. A passive anti-aliasing filter is required for best performance, as shown in Figure 5. The inputs can be driven at
-1dB FS single-ended if the unused input is connected to ground through a large value capacitor. A single
ended to differential converter circuit can also be used for slightly better performance.
Internal Voltage Filter - FILT
Pin 18, Output
Function:
Filter for internal circuits. An external capacitor is required from FILT to analog ground, as shown in Figure
5. FILT is not intended to supply external current. FILT+ has a typical source impedance of 250 kΩ and
any current drawn from this pin will alter device performance. Care should be taken during board layout
to keep dynamic signal traces away from this pin.
Analog Power - VA
Pin 21, Input
Function:
Power for the analog and reference circuits. Typically 5.0 VDC.
Analog Ground - AGND
Pin 22, Input
Function:
Analog ground reference.
Analog Output - AOUT1, AOUT2, AOUT3, AOUT4, AOUT5 and AOUT6
Pins 23, 24, 25, 26, 27, 28, Outputs
Function:
Analog outputs from the DACs. The full scale analog output level is specified in the Analog Characteristics
specifications table. The amplitude of the outputs is controlled by the Digital Volume Control registers
VOL6 - VOL1.
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27
CS4228
PARAMETER DEFINITIONS
Dynamic Range
The ratio of the full scale RMS value of the signal to the RMS sum of all other spectral
components over the specified bandwidth. Dynamic range is a signal-to-noise measurement
over the specified bandwidth made with a -60 dbFs signal. 60 dB is then added to the resulting
measurement to refer the measurement to full scale. This technique ensures that the distortion
components are below the noise level and do not effect the measurement. This measurement
technique has been accepted by the Audio Engineering Society, AES17-1991, and the
Electronic Industries Association of Japan, EIAJ CP-307.
Total Harmonic Distortion + Noise
The ratio of the RMS value of the signal to the RMS sum of all other spectral components over
the specified bandwidth (typically 20 Hz to 20 kHz), including distortion components.
Expressed in decibels. ADCs are measured at -1dBFs as suggested in AES 17-1991 Annex A.
Idle Channel Noise / Signal-to-Noise-Ratio
The ratio of the RMS analog output level with 1 kHz full scale digital input to the RMS analog
output level with all zeros into the digital input. Measured A-weighted over a 10 Hz to 20 kHz
bandwidth. Units in decibels. This specification has been standardized by the Audio
Engineering Society, AES17-1991, and referred to as Idle Channel Noise. This specification has
also been standardized by the Electronic Industries Association of Japan, EIAJ CP-307, and
referred to as Signal-to-Noise-Ratio.
Total Harmonic Distortion (THD)
THD is the ratio of the test signal amplitude to the RMS sum of all the in-band harmonics of
the test signal. Units in decibels.
Interchannel Isolation
A measure of crosstalk between channels. Measured for each channel at the converter’s output with
no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels.
Frequency Response
A measure of the amplitude response variation from 20Hz to 20 kHz relative to the amplitude
response at 1 kHz. Units in decibels.
Interchannel Gain Mismatch
For the ADCs, the difference in input voltage that generates the full scale code for each
channel. For the DACs, the difference in output voltages for each channel with a full scale
digital input. Units are in decibels.
Gain Error
The deviation from the nominal full scale output for a full scale input.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
Offset Error
For the ADCs, the deviation in LSBs of the output from mid-scale with the selected input
grounded. For the DACs, the deviation of the output from zero (relative to CMOUT) with midscale input code. Units are in volts.
28
DS307PP1
CS4228
PACKAGE DIMENSIONS
28L SSOP PACKAGE DRAWING
N
D
E11
A2
E
e
b2
SIDE VIEW
A
A1
L
END VIEW
SEATING
PLANE
1 2 3
TOP VIEW
INCHES
MILLIMETERS
NOTE
DIM
A
A1
A2
b
D
E
E1
e
L
MIN
MAX
MIN
MAX
-0.084
-2.13
0.002
0.010
0.05
0.25
0.064
0.074
1.62
1.88
0.009
0.015
0.22
0.38
2,3
0.390
0.413
9.90
10.50
1
0.291
0.323
7.40
8.20
0.197
0.220
5.00
5.60
1
0.022
0.030
0.55
0.75
0.025
0.041
0.63
1.03
∝
0°
8°
0°
8°
Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold
mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per
side.
2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be
0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not
reduce dimension “b” by more than 0.07 mm at least material condition.
3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
DS307PP1
29
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