CS5303 Three−Phase Buck Controller with Integrated Gate Drivers The CS5303 is a three−phase step down controller which incorporates all control functions required to power high performance processors and high current power supplies. Proprietary multi−phase architecture guarantees balanced load current distribution and reduces overall solution cost in high current applications. Enhanced V2™ control architecture provides the fastest possible transient response, excellent overall regulation, and ease of use. The CS5303 multi−phase architecture reduces output voltage and input current ripple, allowing for a significant reduction in inductor values and a corresponding increase in inductor current slew rate. This approach allows a considerable reduction in input and output capacitor requirements, as well as reducing overall solution size and cost. http://onsemi.com SO−28L DW SUFFIX CASE 751F 28 1 MARKING DIAGRAM 28 CS5303 AWLYYWW Features • Enhanced V2 Control Method • 5−Bit DAC with 1.0% Accuracy • Adjustable Output Voltage Positioning • 6 On−Board Gate Drivers • 200 kHz to 800 kHz Operation Set by Resistor • Current Sensed through Buck Inductors, Sense Resistors, or V−S Control • Hiccup Mode Current Limit • Individual Current Limits for Each Phase • On−Board Current Sense Amplifiers • 3.3 V, 1.0 mA Reference Output • 5.0 V and/or 12 V Operation • On/Off Control (through COMP Pin) 1 A WL, L YY, Y WW, W = Assembly Location = Wafer Lot = Year = Work Week PIN CONNECTIONS COMP VFB VDRP CS1 CS2 CS3 CSREF VID0 VID1 VID2 VID3 VID4 ILIM REF 1 28 ROSC VCCLL1 Gate(L)1 Gnd1 Gate(H)1 VCCH12 Gate(H)2 GndL2 Gate(L)2 VCCL23 Gate(L)3 Gnd3 Gate(H)3 VCCH3 ORDERING INFORMATION Device © Semiconductor Components Industries, LLC, 2006 July, 2006 − Rev. 14 1 Package Shipping CS5303GDW28 SO−28L 27 Units/Rail CS5303GDWR28 SO−28L 1000 Tape & Reel Publication Order Number: CS5303/D CS5303 +12 V R9 2.8 k R10 10 k C12 1 nF R3 VID0 VID1 VID2 VID3 Q1 2.80 k R2 R5 20 k C1 C7 .01 μF C6 .01 μF C2 470 nH Q7 C26 − 39 14 × 1200 μF, 10 V ROSC VCCLL2 Gate(L)1 Gnd1 Gate(H)1 VCCH12 Gate(H)2 GndL2 Gate(L)2 VCCL23 Gate(L)3 Gnd3 Gate(H)3 VCCH3 Q3 C2 L2 470 nH Q4 Q8 C40 − 51 12 × 10 μF C3 C5 0.1 μF Q5 L3 1k R7 R6 20 k C20 − 24 5 × 820 μF, 16 V L1 R1 VID4 + C1 + COMP VFB VDRP CS1 CS2 CS3 CSREF VID0 VID1 VID2 VID3 VID4 ILIM REF 6.65 k C2 1 μF Q2 56.2 k 1 μF ENABLE L4 300 nH C3 1 μF C1 1 μF C4 C11 1 nF R8 20 k +12 V D1 BAT54S CS5303 D2 BAS16LT1 +5.0 V Q6 VOUT 470 nH Q9 20 k C3 C9 .01 μF Note: Q1 − 9 are Siliconix SUD50N03−10P. C1 0.1 μF Figure 1. Application Diagram, 12 V to 1.5 V, 60 A Converter ABSOLUTE MAXIMUM RATINGS* Rating Operating Junction Temperature Lead Temperature Soldering: : Reflow: (SMD styles only) (Note 1) Storage Temperature Range ESD Susceptibility (Human Body Model) 1. 60 second maximum above 183°C. *The maximum package power dissipation must be observed. Value Unit 150 °C 230 peak, °C −65 to +150 °C 2.0 kV ABSOLUTE MAXIMUM RATINGS Pin Name Pin Symbol VMAX VMIN ISOURCE ISINK Power for logic and Gate(L)1 VCCLL1 16 V −0.3 V N/A 1.5 A, 1.0 μs 200 mA DC Power for Gate(L)2 and Gate(L)3 VCCL23 16 V −0.3 V N/A 1.5 A, 1.0 μs 200 mA DC Power for Gate(H)1 and Gate(H)2 VCCH12 20 V −0.3 V N/A 1.5 A, 1.0 μs 200 mA DC Power Gate(H)3 VCCH3 20 V −0.3 V N/A 1.5 A, 1.0 μs 200 mA DC http://onsemi.com 2 CS5303 ABSOLUTE MAXIMUM RATINGS (continued) Pin Name Pin Symbol VMAX VMIN ISOURCE ISINK Voltage Feedback Compensation Network COMP 6.0 V −0.3 V 1.0 mA 1.0 mA Voltage Feedback Input VFB 6.0 V −0.3 V 1.0 mA 1.0 mA Output for adjusting adaptive voltage positioning VDRP 6.0 V −0.3 V 1.0 mA 1.0 mA Frequency Resistor ROSC 6.0 V −0.3 V 1.0 mA 1.0 mA Reference Output REF 6.0 V −0.3 V 1.0 mA 50 mA High−Side FET Drivers Gate(H)1−3 20 V −0.3 V −2 V for 100 nS 1.5 A, 1.0 μs 200 mA DC 1.5 A, 1 μs 200 mA DC Low−Side FET Drivers Gate(L)1−3 16 V −0.3 V −2 V for 100 nS 1.5 A, 1.0 μs 200 mA DC 1.5 A, 1.0 μs 200 mA DC Return for #1 Driver Gnd1 0.3 V −0.3 V 2 A, 1.0 μs 200 mA DC N/A Return for logic and #2 Driver GndL2 N/A N/A 2.0 A, 1.0 μs 200 mA DC N/A Return for #3 Driver Gnd3 0.3 V −0.3 V 2.0 A, 1.0 μs 200 mA DC N/A Current Sense for phases 1 − 3 CS1−CS3 6.0 V −0.3 V 1.0 mA 1.0 mA Current Limit Set Point ILIM 6.0 V −0.3 V 1.0 mA 1.0 mA Current Sense Reference CSREF 6.0 V −0.3 V 1.0 mA 1.0 mA Voltage ID DAC Inputs VID0−4 6.0 V −0.3 V 1.0 mA 1.0 mA ELECTRICAL CHARACTERISTICS (0°C < TA < 70°C; 0°C < TJ < 125°C; 4.7 V < VCCL < 14 V; 8 V < VCCH < 20 V; CGATE(H) = 3.3 nF, CGATE(L) = 3.3 nF, RR(OSC) = 53.6 k, CCOMP = 0.1 μF, CREF = 0.1μF, DAC Code 10000, CVCC = 1.0 μF, ILIM ≥ 1 V; unless otherwise specified.) Characteristic Test Conditions Min Typ Max Unit ± 1.0 % Voltage Identification DAC (0 = Connected to VSS; 1 = Open or Pull−up to 3.3 V) Accuracy (all codes) Measure VFB = COMP VID4 VID3 VID2 VID1 VID0 1 1 1 1 1 − 1.064 1.075 1.086 V 1 1 1 1 0 − 1.089 1.100 1.111 V 1 1 1 0 1 − 1.114 1.125 1.136 V 1 1 1 0 0 − 1.139 1.150 1.162 V 1 1 0 1 1 − 1.163 1.175 1.187 V 1 1 0 1 0 − 1.188 1.200 1.212 V 1 1 0 0 1 − 1.213 1.225 1.237 V 1 1 0 0 0 − 1.238 1.250 1.263 V 1 0 1 1 1 − 1.262 1.275 1.288 V 1 0 1 1 0 − 1.287 1.300 1.313 V 1 0 1 0 1 − 1.312 1.325 1.338 V 1 0 1 0 0 − 1.337 1.350 1.364 V 1 0 0 1 1 − 1.361 1.375 1.389 V 1 0 0 1 0 − 1.386 1.400 1.414 V 1 0 0 0 1 − 1.411 1.425 1.439 V 1 0 0 0 0 − 1.436 1.450 1.465 V http://onsemi.com 3 CS5303 ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 125°C; 4.7 V < VCCL < 14 V; 8 V < VCCH < 20 V; CGATE(H) = 3.3 nF, CGATE(L) = 3.3 nF, RR(OSC) = 53.6 k, CCOMP = 0.1 μF, CREF = 0.1μF, DAC Code 10000, CVCC = 1.0 μF, ILIM ≥ 1 V; unless otherwise specified.) Characteristic Test Conditions Min Typ Max Unit Voltage Identification DAC (0 = Connected to VSS; 1 = Open or Pull−up to 3.3 V) 0 1 1 1 1 − 1.460 1.475 1.490 V 0 1 1 1 0 − 1.485 1.500 1.515 V 0 1 1 0 1 − 1.510 1.525 1.540 V 0 1 1 0 0 − 1.535 1.550 1.566 V 0 1 0 1 1 − 1.559 1.575 1.591 V 0 1 0 1 0 − 1.584 1.600 1.616 V 0 1 0 0 1 − 1.609 1.625 1.641 V 0 1 0 0 0 − 1.634 1.650 1.667 V 0 0 1 1 1 − 1.658 1.675 1.692 V 0 0 1 1 0 − 1.683 1.700 1.717 V 0 0 1 0 1 − 1.708 1.725 1.742 V 0 0 1 0 0 − 1.733 1.750 1.768 V 0 0 0 1 1 − 1.757 1.775 1.793 V 0 0 0 1 0 − 1.782 1.800 1.818 V 0 0 0 0 1 − 1.807 1.825 1.843 V 0 0 0 0 0 − 1.832 1.850 1.869 V Input Threshold VID4, VID3, VID2, VID1, VID0 1.00 1.25 1.50 V Input Pull−up Resistance VID4, VID3, VID2, VID1, VID0 25 50 100 kΩ 3.15 3.30 3.45 V 16.8 19.0 21.5 μA Pull−up Voltage − Voltage Feedback Error Amplifier VFB Bias Current (Note 2) 1.0 V < VFB < 1.9 V COMP Source Current COMP = 0.5 V to 2.0 V; VFB = 1.8 V; DAC = 00000 15 30 60 μA COMP Sink Current COMP = 0.5 V to 2.0 V; VFB = 1.9 V; DAC = 00000 15 30 60 μA 0.20 0.27 0.34 V − 32 − mmho − 2.5 − MΩ COMP Discharge Threshold Voltage Transconductance − −10 μA < ICOMP < +10 μA Output Impedance − Open Loop DC Gain Note 3 60 90 − − Unity Gain Bandwidth 0.01 μF COMP Capacitor − 400 − kHz − 70 − dB PSRR @ 1 kHz − COMP Max Voltage VFB = 1.8 V; COMP Open; DAC = 00000 2.4 2.7 − V COMP Min Voltage VFB = 1.9 V; COMP Open; DAC = 00000 − 0.1 0.2 V Hiccup Latch Discharge Current − 2.0 5.0 10 μA COMP Discharge Ratio − 4.0 6.0 10 − 2. The VFB Bias Current changes with the value of ROSC per Figure 4. 3. Guaranteed by design. Not tested in production. http://onsemi.com 4 CS5303 ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 125°C; 4.7 V < VCCL < 14 V; 8 V < VCCH < 20 V; CGATE(H) = 3.3 nF, CGATE(L) = 3.3 nF, RR(OSC) = 53.6 k, CCOMP = 0.1 μF, CREF = 0.1μF, DAC Code 10000, CVCC = 1.0 μF, ILIM ≥ 1 V;unless otherwise specified) Characteristic Test Conditions Min Typ Max Unit Minimum Pulse Width Measured from CSx to GATE(H) V(VFB) = V(CSREF) = 1.0 V, V(COMP) = 1.5 V 60 mV step applied between VCSX and VCREF − 350 515 ns Channel Start Up Offset V(CS1) = V(CS2) = V(CS3) = V(VFB) = 0.3 V(CSREF) = 0 V; Measure V(COMP) when GATE1(H), 2(H), 3(H) switch high 0.4 0.5 − V PWM Comparators Gate(H) and Gate(L) High Voltage (AC) Note 4 Measure VCCLX − Gate(L) or VCCHX − Gate(H) − 0 1.0 V Low Voltage (AC) Note 4, Measure Gate(L) or Gate(H) − 0 0.5 V Rise Time Gate(H)x 1.0 V < GATE < 8.0 V; VCCHX = 10 V − 35 80 ns Rise Time Gate(L)x 1.0 V < GATE < 8.0 V; VCCLX = 10 V − 35 80 ns Fall Time Gate(H)x 8.0 V > GATE > 1.0 V; VCCHX = 10 V − 35 80 ns Fall Time Gate(L) 8.0 V > GATE > 1.0 V; VCCLX = 10 V − 35 80 ns Gate(H) to Gate(L) Delay Gate(H) < 2.0 V, Gate(L) > 2 V 30 65 110 ns Gate(L) to Gate(H) Delay Gate(L) < 2.0 V, Gate(H) > 2 V 30 65 110 ns GATE Pull−down Force 100 μA into Gate Driver with no power applied to VCCHX and VCCLX = 2 V. − 1.2 1.6 V Oscillator Switching Frequency Measure any phase (ROSC = 53.6 k) 220 250 280 kHz Switching Frequency Note 4 Measure any phase (ROSC = 32.4 k) 300 400 500 kHz Switching Frequency Note 4 Measure any phase (ROSC = 16.2 k) 600 800 1000 kHz ROSC Voltage − − 1.00 − V Phase Delay − 105 120 135 deg Adaptive Voltage Positioning VDRP Output Voltage to DACOUT Offset CS1 = CS2 = CS3 = CSREF, VFB = COMP Measure VDRP − COMP −20 − 20 mV Maximum VDRP Voltage |(CS1 = CS2 = CS3) − CREF| = 50 mV, VFB = COMP, Measure VDRP − COMP 360 465 570 mV 2.4 3.0 3.8 V/V Current Sense Amp to VDRP Gain − Current Sensing and Sharing − 0.2 2.0 μA CSREF Input Bias Current − − 0.6 6.0 μA Current Sense Amplifiers Gain − 3.8 4.3 4.8 V/V −5.0 − 5.0 mV 0 − VCCLL1 − 2 V CS1−CS3 Input Bias Current V(CSx) = V(CSREF) = 0 V Current Sense Amp Mismatch (The sum of offset and gain errors) Note 4 0 ≤ (CSx − CSREF) ≤ 50 mV Current Sense Amplifiers Input Common Mode Range Limit Note 4 7 V < VCCLL1 < 12 V Current Sense Input to ILIM Gain 0.25 V < ILIM < 1.20 V 5.0 6.5 8.0 V/V Current Limit Filter Slew Rate Note 4 7.5 15.0 40.0 mV/μs 4. Guaranteed by design. Not tested in production. http://onsemi.com 5 CS5303 ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 125°C; 4.7 V < VCCL < 14 V; 8 V < VCCH < 20 V; CGATE(H) = 3.3 nF, CGATE(L) = 3.3 nF, RR(OSC) = 53.6 k, CCOMP = 0.1 μF, CREF = 0.1μF, DAC Code 10000, CVCC = 1.0 μF, ILIM ≥ 1 V;unless otherwise specified) Characteristic Test Conditions Min Typ Max Unit − 0.1 1.0 μA 60 70 90 mV Note 5 1.0 − − mHz 0 mA < I(VREF) < 1.0 mA 3.15 3.25 3.35 V Current Sensing and Sharing ILIM Bias Current 0 < ILIM < 1.0 V Single Phase Pulse by Pulse Current Limit: V(CSx) − V(CSREF) Current Share Amplifier Bandwidth − Reference Output VREF Output Voltage General Electrical Specifications VCCLL1 Operating Current VFB = COMP(no switching) − 23 28 mA VCCL23 Operating Current VFB = COMP(no switching) − 8.0 11 mA VCCH12 Operating Current VFB = COMP(no switching) − 5.5 7.0 mA VCCH3 Operating Current VFB = COMP(no switching) − 2.5 3.5 mA VCCLL1 Start Threshold GATEs switching, COMP charging 4.05 4.40 4.70 V VCCLL1 Stop Threshold GATEs stop switching, COMP discharging 3.75 4.20 4.60 V VCCLL1 Hysteresis GATEs not switching, COMP not charging 100 200 300 mV VCCH12 Start Threshold GATEs switching, COMP charging 1.7 1.9 2.1 V VCCH12 Stop Threshold GATEs stop switching, COMP discharging 1.55 1.75 1.90 V VCCH12 Hysteresis GATEs not switching, COMP not charging 100 200 300 mV 5. Guaranteed by design. Not tested in production. PACKAGE PIN DESCRIPTION PACKAGE PIN # 28 Lead SO Wide PIN SYMBOL 1 COMP 2 VFB Voltage Feedback Pin. To use Adaptive Voltage Positioning (AVP) select an offset voltage at light load and connect a resistor between VFB and VOUT. The input bias current of the VFB pin and the resistor value determine output voltage offset for zero output current. Short VFB to VOUT for no AVP. 3 VDRP Current sense output for AVP. The offset of this pin above the DAC voltage is proportional to the output current. Connect a resistor from this pin to VFB to set amount AVP or leave this pin open for no AVP. 4−6 CS1−CS3 7 CSREF Reference for current sense amplifiers. To balance input offset voltages between the inverting and noninverting inputs of the current sense amplifiers, connect a resistor between CSREF and the output voltage. The value should be 1/3 of the value of the resistors connected to the CSx pins. 8−12 VID4−VID0 Voltage ID DAC inputs. These pins are internally pulled up to 3.3 V if left open. 13 ILIM Sets threshold for current limit. Connect to reference through a resistive divider. FUNCTION Output of the error amplifier and input for the PWM comparators. Current sense amplifier inputs. Connect current sense network for the corresponding phase to each input. http://onsemi.com 6 CS5303 PACKAGE PIN DESCRIPTION (continued) PACKAGE PIN # 28 Lead SO Wide PIN SYMBOL 14 REF 15 VCCH3 Power for Gate(H)3. 16 Gate(H)3 High side driver #3. 17 Gnd3 18 Gate(L)3 19 VCCL23 20 Gate(L)2 21 GndL2 22 Gate(H)2 23 VCCH12 24 Gate(H)1 25 Gnd1 26 Gate(L)1 27 VCCLL1 28 ROSC FUNCTION Reference output. Decouple with 0.1 μF to GndL2 Return for #3 drivers. Low side driver #3. Power for Gate(L)2 and Gate(L)3. Low side driver #2. Return for #2 driver, internal control circuits and IC substrate connection. High side driver #2. Power for Gate(H)1 and Gate(H)2. UVLO Sense for High Side Driver supply connects to this pin. High side driver #1. Return for #1 drivers. Low side driver #1. Power for internal control circuits and Gate(L)1. UVLO Sense for Logic and Low Side Driver supply connects to this pin. A resistor from this pin to ground sets operating frequency and VFB bias current. http://onsemi.com 7 CS5303 VCCLL1 VCCLL1 3.3 V REF − − +Stop +Stop Start − + VID1 DAC VID3 Start 4.4 V 4.2 V VCCH12 PH 1 S 2V 1.8 V − + Reset Dominant DACOUT + VID0 PWMC1 VID4 Gate Nonoverlap Gate(H)1 Gate(L)1 Gnd1 + MAXC1 − CO1 + 1 2 + − + 5 μA CSREF + DACOUT Offset − 2 1 CO3 + FAULT − Gate(H)2 Gate Nonoverlap Gate(L)2 R + MAXC2 − 0.3 V VCCH3 PH 3 FAULT S 0.3 V VCCL23 Gate(L)3 Gnd3 FAULT Current Source Gen PH 1 DACOUT OSC PH 2 PH 3 VFB ROSC COMP Figure 2. Block Diagram http://onsemi.com 8 Gnd2 Gate(H)3 Gate Nonoverlap R EA FAULT VDRP VCCL23 + MAXC3 − ×1.5 AVPA S − PWMC3 + CO3 − CS3 − CO3 +CSA3 VITotal − + CS2 − CO2 CSA2 + CO2 CO2 − − CS1 COMP Discharge Threshold PH 2 Reset Dominant − + VCCH12 PWMC2 + Set Dominant + − R 0.3 V FAULT − S − CO1 +CSA1 + FAULT ILIM VCCLL1 R CO1 Reset Dominant VID2 VCCH3 VCCH12 VCCLL1 − REF VCCH12 VCCL23 BIAS CS5303 TYPICAL PERFORMANCE CHARACTERISTICS 80 900 VFB Bias Current, μA 800 Frequency, kHz 700 600 500 400 300 60 40 20 200 100 10 20 30 40 50 60 0 10 70 20 30 ROSC Value, kΩ 60 70 80 Figure 4. VFB Bias Current vs. ROSC Value 120 120 100 100 80 80 Time, ns Time, ns 50 ROSC Value, kΩ Figure 3. Oscillator Frequency 60 60 40 40 20 20 0 0 0 2 4 6 8 10 12 14 16 0 2 4 6 8 10 12 14 16 Load Capacitance, nF Load Capacitance, nF Figure 5. Gate(H) Rise−time vs. Load Capacitance measured from 1 V to 4 V with VCC at 5 V. Figure 6. Gate(L) Rise−time vs. Load Capacitance measured from 4 V to 1 V with VCC at 5 V. 120 120 100 100 80 80 Time, ns Time, ns 40 60 60 40 40 20 20 0 0 0 2 4 6 8 10 12 14 16 0 Load Capacitance, nF 2 4 6 8 10 12 14 16 Load Capacitance, nF Figure 7. Gate(H) Fall−time vs. Load Capacitance measured from 4 V to 1 V with VCC at 5 V. Figure 8. Gate(L) Fall−time vs. Load Capacitance measured from 4 V to 1 V with VCC at 5 V. http://onsemi.com 9 CS5303 APPLICATIONS INFORMATION FIXED FREQUENCY MULTI−PHASE CONTROL comparator rises and terminates the pwm cycle. If the inductor starts the cycle with a higher current the PWM cycle will terminate earlier providing negative feedback. The CS5303 provides a CX input for each phase, but the CSREF, VFB and COMP inputs are common to all phases. Current sharing is accomplished by referencing all phases to the same VFB and COMP pins, so that a phase with a larger current signal will turn off earlier than phases with a smaller current signal. Including both current and voltage information in the feedback signal allows the open loop output impedance of the power stage to be controlled. If the COMP pin is held steady and the inductor current changes there must also be a change in the output voltage. Or, in a closed loop configuration when the output current changes, the COMP pin must move to keep the same output voltage. The required change in the output voltage or COMP pin depends on the scaling of the current feedback signal and is calculated as In a multi−phase converter, multiple converters are connected in parallel and are switched on at different times. This reduces output current from the individual converters and increases the apparent ripple frequency. Because several converters are connected in parallel, output current can ramp up or down faster than a single converter (with the same value output inductor) and heat is spread among multiple components. The CS5303 uses a three−phase, fixed frequency, enhanced V2 architecture. Each phase is delayed 120° from the previous phase. Normally GATE(H) transitions high at the beginning of each oscillator cycle. Inductor current ramps up until the combination of the current sense signal and the output ripple trip the PWM comparator and bring GATE(H) low. Once GATE(H) goes low, it will remain low until the beginning of the next oscillator cycle. While GATE(H) is high, the enhanced V2 loop will respond to line and load transients. Once GATE(H) is low, the loop will not respond again until the beginning of the next cycle. Therefore, constant frequency enhanced V2 will typically respond within the off−time of the converter. The enhanced V2 architecture measures and adjusts current in each phase. An additional input (CX) for inductor current information has been added to the V2 loop for each phase as shown in Figure 9. SWNODE L RL CX + CSA RS OFFSET CSREF VOUT DACOUT + CSA Gain DI Single Stage Impedance + DVńDI + RS CSA Gain. The multi−phase power stage output impedance is the single−phase output impedance divided by the number of phases. The output impedance of the power stage determines how the converter will respond during the first few μs of a transient before the feedback loop has repositioned the COMP pin. The peak output current of each phase can also be calculated from; + V * VFB * VOFFSET Ipkout (per phase) + COMP RS CSA Gain + + PWMCOMP Figure 10 shows the step response of a single phase with the COMP pin at a fixed level. Before T1 the converter is in normal steady state operation. The inductor current provides the pwm ramp through the Current Share Amplifier. The pwm cycle ends when the sum of the current signal, voltage signal and OFFSET exceed the level of the COMP pin. At T1 the output current increases and the output voltage sags. The next pwm cycle begins and the cycle continues longer than previously while the current signal increases enough to make up for the lower voltage at the VFB pin and the cycle ends at T2. After T2 the output voltage remains lower than at light load and the current signal level is raised so that the sum of the current and voltage signal is the same as with the original load. In a closed loop system the COMP pin would move higher to restore the output voltage to the original level. + VFB + DV + RS The single−phase power stage output impedance is; E.A. + COMP Figure 9. Enhanced V2 Feedback and Current Sense Scheme The inductor current is measured across RS, amplified by CSA and summed with the OFFSET and Output Voltage at the non−inverting input of the PWM comparator. The inductor current provides the PWM ramp and as inductor current increases the voltage on the positive pin of the pwm http://onsemi.com 10 CS5303 considered when setting the ILIM threshold. If a more accurate current sense is required than inductive sensing can provide, current can be sensed through a resistor as shown in Figure 9. SWNODE Current Sharing Accuracy PCB traces that carry inductor current can be used as part of the current sense resistance depending on where the current sense signal is picked off. For accurate current sharing, the current sense inputs should sense the current at the same point for each phase and the connection to the CSREF should be made so that no phase is favored. (In some cases, especially with inductive sensing, resistance of the pcb can be useful for increasing the current sense resistance.) The total current sense resistance used for calculations must include any pcb trace between the CS inputs and the CSREF input that carries inductor current. Current Sense Amplifier Input Mismatch and the value of the current sense element will determine the accuracy of current sharing between phases. The worst case Current Sense Amplifier Input Mismatch is 5 mV and will typically be within 3 mV. The difference in peak currents between phases will be the CSA Input Mismatch divided by the current sense resistance. If all current sense elements are of equal resistance a 3 mV mismatch with a 2 mΩ sense resistance will produce a 1.5 A difference in current between phases. VFB (VOUT) CSA Out COMP − Offset CSA Out + VFB T1 T2 Figure 10. Open Loop Operation Inductive Current Sensing For lossless sensing current can be sensed across the inductor as shown below in Figure 11. In the diagram L is the output inductance and RL is the inherent inductor resistance. To compensate the current sense signal the values of R1 and C1 are chosen so that L/RL = R1 × C1. If this criteria is met the current sense signal will be the same shape as the inductor current, the voltage signal at Cx will represent the instantaneous value of inductor current and the circuit can be analyzed as if a sense resistor of value RL was used as a sense resistor (RS). For operation at duty cycles above 50% Enhanced V2 will exhibit subharmonic oscillation unless a compensation ramp is added to each phase. A circuit like the one on the left side of Figure 12 can be added to each current sense network to implement slope compensation. The value of R1 can be varied to adjust the ramp size. R1 SWNODE CS L C1 RL VOUT Operation at > 50% Duty Cycle CSREF + CSA OFFSET + + + + PWMCOMP Switch Node Gate(L)X VFB DACOUT E.A. + R1 3k COMP 25 k CSX Figure 11. Lossless Inductive Current Sensing with Enhanced V2 1 nF 0.1 μF When choosing or designing inductors for use with inductive sensing, tolerances and temperature effects should be considered. Cores with a low permeability material or a large gap will usually have minimal inductance change with temperature and load. Copper magnet wire has a temperature coefficient of 0.39% per °C. The increase in winding resistance at higher temperatures should be .01 μF CSREF MMBT2222LT1 Slope Comp Circuit Existing Current Sense Circuit Figure 12. External Slope Compensation Circuit http://onsemi.com 11 CS5303 Ramp Size and Current Sensing Because the current ramp is used for both the PWM ramp and to sense current, the inductor and sense resistor values will be constrained. A small ramp will provide a quick transient response by minimizing the difference over which the COMP pin must travel between light and heavy loads, but a steady state ramp of 25 mVP−P or greater is typically required to prevent pulse skipping and minimize pulse width jitter. For resistive current sensing the combination of the inductor and sense resistor values must be chosen to provide a large enough steady state ramp. For large inductor values the sense resistor value must also be increased. For inductive current sensing the RC network must meet the requirement of L/RL = R × C to accurately sense the AC and DC components of the current the signal. Again the values for L and RL will be constrained in order to provide a large enough steady state ramp with a compensated current sense signal. A smaller L, or a larger RL than optimum might be required. But unlike resistive sensing, with inductive sensing small adjustments can be made easily with the values of R and C to increase the ramp size if needed. If RC is chosen to be smaller (faster) than L/RL, the AC portion of the current sensing signal will be scaled larger than the DC portion. This will provide a larger steady state ramp, but circuit performance will be affected and must be evaluated carefully. The current signal will overshoot during transients and settle at the rate determined by R × C. It will eventually settle to the correct DC level, but the error will decay with the time constant of R × C. If this error is excessive it will effect transient response, adaptive positioning and current limit. During transients the COMP pin will be required to overshoot along with the current signal in order to maintain the output voltage. The VDRP pin will also overshoot during transients and possibly slow the response. Single phase overcurrent will trip earlier than it would if compensated correctly and hiccup mode current limit will have a lower threshold for fast rise step loads than for slowly rising output currents. The waveforms in Figure 13 show a simulation of the current sense signal and the actual inductor current during a positive step in load current with values of L = 500 nH, RL = 1.6 mΩ, R1 = 20 k and C1 = .01 μF. For ideal current signal compensation the value of R1 should be 31 kΩ. Due to the faster than ideal RC time constant there is an overshoot of 50% and the overshoot decays with a 200 μs time constant. With this compensation the ILIM pin threshold must be set more than 50% above the full load current to avoid triggering hiccup mode during a large output load step. Figure 13. Inductive Sensing waveform during a Step with Fast RC Time Constant (50 ms/div) Current Limit Two levels of overcurrent protection are provided. Any time the voltage on a Current Sense pin exceeds CSREF by more than the Single Phase Pulse by Pulse Current Limit, the pwm comparator for that phase is turned off. This provides fast peak current protection for individual phases. The outputs of all the currents are also summed and filtered to compare an averaged current signal to the voltage on the ILIM pin. If this voltage is exceeded, the fault latch trips and the SS capacitor is discharged by a 5 μA source until the COMP pin reaches 0.2 V. Then soft−start begins. The converter will continue to operate in this mode until the fault condition is corrected. Overvoltage Protection Overvoltage protection (OVP) is provided as a result of the normal operation of the enhanced V2 control topology with synchronous rectifiers. The control loop responds to an overvoltage condition within 400 ns, causing the top MOSFET’s to shut off, and the synchronous MOSFET’s to turn on. This results in a “crowbar” action to clamp the output voltage and prevents damage to the load. The regulator will remain in this state until the overvoltage condition ceases or the input voltage is pulled low. Transient Response and Adaptive Positioning For applications with fast transient currents the output filter is frequently sized larger than ripple currents require in http://onsemi.com 12 CS5303 through the VDRP resistor (R8). When output current increases the VDRP pin increases proportionally and the VDRP pin current offsets the VFB bias current and causes the output voltage to further decrease. The VFB and VDRP pins take care of the slower and DC voltage positioning. The first few μs are controlled primarily by the ESR and ESL of the output filter. The transition between fast and slow positioning is controlled by the ramp size and the error amp compensation. If the ramp size is too large or the error amp too slow there will be a long transition to the final voltage after a transient. This will be most apparent with lower capacitance output filters. Note: Large levels of adaptive positioning can cause pulse width jitter. order to reduce voltage excursions during transients. Adaptive voltage positioning can reduce peak−peak output voltage deviations during load transients and allow for a smaller output filter. The output voltage can be set higher at light loads to reduce output voltage sag when the load current is stepped up and set lower during heavy loads to reduce overshoot when the load current is stepped up. For low current applications a droop resistor can provide fast accurate adaptive positioning. However at high currents, the loss in a droop resistor becomes excessive. For example; in a 50 A converter a 1 mΩ resistor to provide a 50 mV change in output voltage between no load and full load would dissipate 2.5 Watts. Lossless adaptive positioning is an alternative to using a droop resistor, but must respond quickly to changes in load current. Figure 14 shows how adaptive positioning works. The waveform labeled normal shows a converter without adaptive positioning. On the left, the output voltage sags when the output current is stepped up and later overshoots when current is stepped back down. With fast (ideal) adaptive positioning the peak to peak excursions are cut in half. In the slow adaptive positioning waveform the output voltage is not repositioned quickly enough after current is stepped up and the upper limit is exceeded. Error Amp Compensation The transconductance error amplifier can be configured to provide both a slow soft−start and a fast transient response. C4 in the main applications diagram controls soft−start. A 0.1 μF capacitor with the 30 μA error amplifier output capability will allow the output to ramp up at 0.3 V/ms or 1.5 V in 5 ms. R10 is connected in series with C4 to allow the error amplifier to slew quickly over a narrow range during load transients. Here the 30 μA error amplifier output capability works against 10 kΩ (R10) to limit the window of fast slewing too 300 mV − enough to allow for fast transients, but not enough to interfere with soft−start. This window will be noticeable as a step in the COMP pin voltage at start−up. The size of this step must be kept smaller than the Channel Start−Up Offset (nominally 0.4 V) for proper soft−start operation. If adaptive positioning is used the R9 and R8 form a divider with the VDRP end held at the DAC voltage during start−up, which effectively makes the Channel Start−Up Offset larger. C12 is included for error amp stability. A capacitive load is required on the error amp output. Use of values less than 1 nF may result in error amp oscillation of several MHz. C11 and the parallel resistance of the VFB resistor (R9) and the VDRP resistor (R8) are used to roll off the error amp gain. The gain is rolled off at a high enough frequency to give a quick transient response, but low enough to cross zero dB well below the switching frequency to minimize ripple and noise on the COMP pin. Normal Fast Adaptive Positioning Slow Adaptive Positioning Limits Figure 14. Adaptive Positioning The CS5303 uses two methods to provide fast and accurate adaptive positioning. For low frequency positioning the VFB and VDRP pins are used to adjust the output voltage with varying load currents. For high frequency positioning, the current sense input pins can be used to control the power stage output impedance. The transition between fast and slow positioning is adjusted by the error amp compensation. The CS5303 can be configured to adjust the output voltage based on the output current of the converter. The adaptive positioning circuit is designed to select the DAC setting as the maximum output voltage. (Refer to Application Diagram on page 2.) To set the no−load positioning a resistor (R9) is placed between the output voltage and VFB pin. The VFB bias current will develop a voltage across the resistor to decrease the output voltage. The VFB bias current is dependent on the value of ROSC. See Figure 4 on the datasheet. During no load conditions the VDRP pin is at the same voltage as the VFB pin, so none of the VFB bias current flows UVLO The CS5303 has undervoltage lockout functions connected to two pins. One intended for the logic and low−side drivers with a 4.4 V turn−on threshold is connected to the VCCLL1 pin. A second for the high side drivers has a 2 V threshold and is connected to the VCCH12 pin. The UVLO threshold for the high side drivers was chosen at a low value to allow for flexibility in the part and an input voltage as low as 3.3 V. In many applications this will be http://onsemi.com 13 CS5303 similar points for accurate current sharing. If the current signal is taken from a place other than directly at the inductor any additional resistance between the pick−off point and the inductor appears as part of the inherent inductor resistance and should be considered in design calculations. Capacitors for the current feedback networks should be placed as close to the current sense pins as practical. disabled or will only check that the applicable supply is on − not that it is at a high enough voltage to run the converter. For the 12 VIN converter in the application diagram on page 2 the UVLO pin for the high side driver is pulled up by the 5 V supply (through two diode drops) and the function is not used. The diode between the COMP pin and the 12 V supply holds the COMP pin near Gnd and prevents start−up while the 12 V supply is off. In an application where a higher UVLO threshold is necessary a circuit like the one in Figure 15 will lock out the converter until the 12 V supply exceeds 9 V. DESIGN PROCEDURE Current Sensing, Power Stage and Output Filter Components 1. Choose the output filter components to meet peak transient requirements. The formula below can be used to provide an approximate starting point for capacitor choice, but will be inadequate to calculate actual values. +12 V +5 V 50 k COMP DVPEAK + (DIńDT) ESL ) DI ESR Ideally the output filter should be simulated with models including ESR, ESL, circuit board parasitics and delays due to switching frequency and converter response. Typically both bulk capacitance (electrolytic, Oscon, etc,) and low impedance capacitance (ceramic chip) will be required. The bulk capacitance provides “hold up” during the converter response. The low impedance capacitance reduces steady state ripple and bypasses the bulk capacitance during slewing of output current. 2. For inductive current sensing (only) choose the current sense network RC to provide a 25 mV minimum ramp during steady state operation. 100 k 100 k Figure 15. External UVLO Circuit Layout Guidelines With the fast rise, high output currents of microprocessor applications parasitic inductance and resistance should be considered when laying out the power, filter and feedback signal sections of the board. Typically a multi−layer board with at least one ground plane is recommended. If the layout is such that high currents can exist in the ground plane underneath the controller or control circuitry, the ground plane can be slotted to reroute the currents away from the controller. The slots should typically not be placed between the controller and the output voltage or in the return path of the gate drive. Additional power and ground planes or islands can be added as required for a particular layout. Output filter components should be placed on wide planes connected directly to the load to minimize resistive drops during heavy loads and inductive drops and ringing during transients. If required, the planes for the output voltage and return can be interleaved to minimize inductance between the filter and load. Voltage feedback should be taken from a point of the output or the output filter that doesn’t favor any one phase. If the feedback connection is closer to one inductor than the others the ripple associated with that phase may appear larger than the ripple associated with the other phases and poor current sharing can result. The current sense signal is typically tens of milli−volts. Noise pick−up should be avoided wherever possible. Current feedback traces should be routed away from noisy areas such as switch nodes and gate drive signals. The paths should be matched as well as possible. It is especially important that all current sense signals be picked off at R + (VIN * VOUT) F VOUTńVIN C 25 mV Then choose the inductor value and inherent resistance to satisfy L/RL = R × C. For ideal current sense compensation the ratio of L and RL is fixed, so the values of L and RL will be a compromise typically with the maximum value RL limited by conduction losses or inductor temperature rise and the minimum value of L limited by ripple current. 3. For resistive current sensing choose L and RS to provide a steady state ramp greater than 25 mV. LńRS + (VIN * VOUT) TONń25 mV Again the ratio of L and RL is fixed and the values of L and RS will be a compromise. 4. Calculate the high frequency output impedance (ConverterZ) of the converter during transients. This is the impedance of the Output filter ESR in parallel with the power stage output impedance (PwrstgZ) and will indicate how far from the original level (ΔVR) the output voltage will typically recover to within one switching cycle. For a good transient response ΔVR should be less than the peak output voltage overshoot or undershoot. http://onsemi.com 14 CS5303 DVR + ConverterZ ConverterZ + ESR RV(FB) + NL PositionńVFB Bias Current PwrstgZ ESR PwrstgZ ) ESR See Figure 4 for VFB Bias Current. 8. To set the difference in output voltage between no load and full load, connect a resistor (RV(DRP)) between the VDRP and VFB pins. RV(DRP) can be calculated in two steps. First calculate the difference between the VDRP and VFB pin at full load. (The VFB voltage should be the same as the DAC voltage during closed loop operation.) Then choose the RV(DRP) to source enough current across RV(FB) for the desired change in output voltage. where: PwrstgZ + RS CSA Gainń3 Multiply the converterZ by the output current step size to calculate where the output voltage should recover to within the first switching cycle after a transient. If the ConverterZ is higher than the value required to recover to where the adaptive positioning is set the remainder of the recovery will be controlled by the error amp compensation and will typically recover in 10 − 20 μs. DVR + DIOUT DVV(DRP) + IOUTFL R CS to VDRP Gain where: R = RL or RS for one phase; IOUTFL is the full load output current. ConverterZ Make sure that ΔVR is less than the expected peak transient for a good transient response. 5. Adjust L and RL or RS as required to meet the best combination of transient response, steady state output voltage ripple and pulse width jitter. RV(DRP) + DVDRP RV(FB)ńDVOUT DESIGN EXAMPLE Choose the component values for lossless current sensing, adaptive positioning and current limit for a 60 A converter. The adaptive positioning is chosen 50 mV below the maximum VOUT at no load and 50 mV below the no−load position with 60 A out. The peak output voltage transient is 100 mV max during a 60 A step current. The overcurrent limit is nominally 75 A. Current Limit When the sum of the Current Sense amplifiers (VITOTAL) exceeds the voltage on the ILIM pin the part will enter hiccup mode. For inductive sensing the ILIM pin voltage should be set based on the inductor resistance (or current sense resistor) at max temperature and max current. To set the level of the ILIM pin: 6. VI(LIM) + R IOUT(LIM) CS to ILIM Gain Current Sensing, Power Stage and Output Filter Components 1. Assume 1.5 mΩ of output filter ESR. 2. R + (VIN * VOUT) (VOUTńVIN)ń(F where: R is RL or RS; IOUT(LIM) is the current limit threshold. For the overcurrent to work properly the inductor time constant (L/R) should be ≤ the Current sense RC. If the RC is too fast, during step loads the current waveform will appear larger than it is (typically for a few hundred μs) and may trip the current limit at a level lower than the DC limit. + (12 * 1.5) (1.5ń12)ń(250 k + 21 kW å Choose 20 kW LńRL + .01 mF 20 kW + 200 ms C 25 mV) .01 mF 25 mV) Choose RL + 2 mW L + 2 mW 200 ms + 400 nH 3. n/a 4. PwrstgZ + RL CSA Gainń3 + 1.5 mW 4.2ń3 + 2.1 mW Adaptive Positioning 7. To set the amount of voltage positioning below the DAC setting at no load connect a resistor (RV(FB)) between the output voltage and the VFB pin. Choose RV(FB) as: ConverterZ + PwrstgZ ESR PwrstgZ ) ESR + 2.8 mW 1.5 mW ^ 1 mW 2.8 mW ) 1.5 mW DVR + 1.2 mW 60 A + 60 mV http://onsemi.com 15 CS5303 Adaptive Positioning 5. n/a 7. RV(FB) + NL PositionńVFB Bias Current Current Limit + 50 mVń19 mA + 2.63 kW 6.VI(LIM) + RL IOUT(LIM) CS to ILIM Gain + 1.5 mW 75 A 6.5 + 731 mV 8. DVDRP + RL + 2 mW IOUT Current Sense to VDRP Gain 60 A 3 + 360 mV RV(DRP) + DVDRP + 360 mV http://onsemi.com 16 RV(FB)ńDVOUT 2.63 kWń50 mV + 18.9 kW CS5303 ADDITIONAL APPLICATION DIAGRAMS +5.0 V +5.0 V C1 + + U1 ROSC VCCLL2 Gate(L)1 Gnd1 Gate(H)1 VCCH12 Gate(H)2 GndL2 Gate(L)2 VCCL23 Gate(L)3 Gnd3 Gate(H)3 VCCH3 COMP VFB VDRP CS1 CS2 CS3 CSREF VID0 VID1 VID2 VID3 VID4 ILIM REF C2 CS5303 ENABLE VID0 VID1 VID2 VID3 C3 VID4 VOUT C1 C3 C2 Figure 16. 5 V only to 1.2 V +12 V +5.0 V +12 V +12 V C1 + U1 COMP VFB VDRP CS1 CS2 CS3 CSREF VID0 VID1 VID2 VID3 VID4 ILIM REF ROSC VCCLL2 Gate(L)1 Gnd1 Gate(H)1 VCCH12 Gate(H)2 GndL2 Gate(L)2 VCCL23 Gate(L)3 Gnd3 Gate(H)3 VCCH3 CS5303 ENABLE VID0 VID1 VID2 + VID3 C2 C3 VID4 VOUT C1 C2 C3 Figure 17. 5 V to 1.2 V with 12 V Bias http://onsemi.com 17 CS5303 ADDITIONAL APPLICATION DIAGRAMS +5 V +5 V C1 + U1 CS5303 + COMP VFB VDRP CS1 CS2 CS3 CSREF VID0 VID1 VID2 VID3 VID4 ILIM REF ENABLE ROSC VCCLL1 Gate(L)1 Gnd1 Gate(H)1 VCCH12 Gate(H)2 GndL2 Gate(L)2 VCCL23 Gate(L)3 Gnd3 Gate(H)3 VCCH3 C2 C3 VOUT C3 C1 C2 Figure 18. 5 V only to 2.5 V http://onsemi.com 18 CS5303 PACKAGE DIMENSIONS SO−28L DW SUFFIX CASE 751F−05 ISSUE F D A NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. 4. MAXIMUM MOLD PROTRUSION 0.015 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. 15 M 0.25 E H B M 28 1 14 PIN 1 IDENT A B A1 e B 0.025 M C A S B L 0.10 C S C SEATING PLANE q DIM A A1 B C D E e H L q MILLIMETERS MIN MAX 2.35 2.65 0.13 0.29 0.35 0.49 0.23 0.32 17.80 18.05 7.40 7.60 1.27 BSC 10.05 10.55 0.41 0.90 0 8 PACKAGE THERMAL DATA Parameter 28 Lead SO Wide Unit RΘJC Typical 15 °C/W RΘJA Typical 75 °C/W V2 is a trademark of Switch Power, Inc. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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