Intersil CS82C54-10 Cmos programmable intervel timer Datasheet

82C54
®
Data Sheet
July 11, 2005
FN2970.4
CMOS Programmable Intervel Timer
Features
The Intersil 82C54 is a high performance CMOS
Programmable Interval Timer manufactured using an
advanced 2 micron CMOS process.
• 8MHz to 12MHz Clock Input Frequency
• Compatible with NMOS 8254
- Enhanced Version of NMOS 8253
The 82C54 has three independently programmable and
functional 16-bit counters, each capable of handling clock
input frequencies of up to 8MHz (82C54) or 10MHz
(82C54-10) or 12MHz (82C54-12).
The high speed and industry standard configuration of the
82C54 make it compatible with the Intersil 80C86, 80C88,
and 80C286 CMOS microprocessors along with many
other industry standard processors. Six programmable
timer modes allow the 82C54 to be used as an event
counter, elapsed time indicator, programmable one-shot,
and many other applications. Static CMOS circuit design
insures low power operation.
The Intersil advanced CMOS process results in a significant
reduction in power with performance equal to or greater than
existing equivalent products.
• Three Independent 16-Bit Counters
• Six Programmable Counter Modes
• Status Read Back Command
• Binary or BCD Counting
• Fully TTL Compatible
• Single 5V Power Supply
• Low Power
- ICCSB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10µA
- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA at 8MHz
• Operating Temperature Ranges
- CX82C54 . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to +70oC
- IX82C54 . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
- MD82C54 . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
• Pb-Free Plus Anneal Available (RoHS Compliant)
21 CS
20 A1
D3 5
19 A0
D2 6
18 CLK 2
D1 7
17 OUT 2
D0 8
16 GATE 2
CLK 0 9
15 CLK 1
OUT 0 10
2
1
28 27 26
RD
D4 4
VCC
22 RD
3
WR
D5 3
4
NC
23 WR
D6
24 VCC
D6 2
D7
D7 1
82C54 (PLCC/CLCC)
TOP VIEW
D5
82C54 (PDIP, CERDIP)
TOP VIEW
D4 5
25 NC
D3 6
24 CS
D2 7
23 A1
D1 8
22 A0
D0 9
21 CLK2
CLK 0 10
20 OUT 2
NC 11
19 GATE 2
14 GATE 1
1
CLK 1
GATE 1
NC
13 14 15 16 17 18
OUT 1
12
GND
13 OUT 1
GND 12
OUT 0
GATE 0 11
GATE 0
Pinouts
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003, 2005. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
82C54
Ordering Information
PART NUMBERS
8MHz
10MHz
12MHz
TEMPERATURE
RANGE
PACKAGE
PKG.
DWG. #
0oC to +70oC
24 Lead PDIP
CP82C54-10Z (See Note) CP82C54-12Z (See Note)
0oC to +70oC
24 Lead PDIP** (Pb-free) E24.6
CS82C54*
CS82C54-10*
0oC to +70oC
28 Lead PLCC
CS82C54Z* (See Note)
CS82C54-10Z* (See Note) CS82C54-12Z* (See Note)
0oC to +70oC
28 Lead PLCC (Pb-free) N28.45
CP82C54
CP82C54-10
CP82C54Z (See Note)
ID82C54
IP82C54
CP82C54-12
CS82C54-12
IP82C54-10
E24.6
N28.45
-
-40oC to +85oC
24 Lead CERDIP
F24.6
-
-40oC to +85oC
24 Lead PDIP
E24.6
24 Lead PDIP** (Pb-free) E24.6
IP82C54Z (See Note)
IP82C54-10Z (See Note)
-
-40oC to +85oC
IS82C54*
IS82C54-10*
-
-40oC to +85oC
28 Lead PLCC
-
-40oC to +85oC
28 Lead PLCC (Pb-free) N28.45
-
-55oC to +125oC
24 Lead CERDIP
-
-55oC to +125oC
24 Lead CERDIP
F24.6
-55oC to +125oC
28 Lead CLCC
J28.A
IS82C54Z (See Note)
IS82C54-10Z (See Note)
MD82C54/B
-
SMD # 8406501JA
-
SMD# 84065013A
-
84065023A
N28.45
F24.6
Contact factory for availability.
*Add “96” suffix for tape and reel.
**Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2
82C54
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V
Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.5V to VCC +0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance (Typical)
θJA (oC/W) θJC (oC/W)
CERDIP Package. . . . . . . . . . . . . . . . .
55
12
CLCC Package. . . . . . . . . . . . . . . . . . .
65
14
PDIP Package*. . . . . . . . . . . . . . . . . . .
55
N/A
PLCC Package. . . . . . . . . . . . . . . . . . .
60
N/A
Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC
Maximum Junction Temperature Ceramic Package. . . . . . . .+175oC
Maximum Junction Temperature Plastic Package . . . . . . . . .+150oC
Maximum Lead Temperature Package (Soldering 10s). . . . .+300oC
(PLCC - Lead Tips Only)
Operating Conditions
Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range
CX82C54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to +70oC
IX82C54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
MD82C54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2250 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications
SYMBOL
VIH
VCC = +5.0V ± 10%, Includes all Temperature Ranges
PARAMETER
Logical One Input Voltage
VIL
Logical Zero Input Voltage
VOH
Output HIGH Voltage
MIN
MAX
UNITS
TEST CONDITIONS
2.0
-
V
CX82C54, IX82C54
2.2
-
V
MD82C54
-
0.8
V
-
3.0
-
V
IOH = -2.5mA
VCC -0.4
-
V
IOH = -100µA
VOL
Output LOW Voltage
-
0.4
V
IOL = +2.5mA
II
Input Leakage Current
-1
+1
µA
VIN = GND or VCC
DIP Pins 9,11,14-16,18-23
IO
Output Leakage Current
-10
+10
µA
VOUT = GND or VCC
DIP Pins 1-8
ICCSB
Standby Power Supply Current
-
10
µA
VCC = 5.5V, VIN = GND or VCC,
Outputs Open, Counters
Programmed
ICCOP
Operating Power Supply Current
-
10
mA
VCC = 5.5V,
CLK0 = CLK1 = CLK2 = 8MHz,
VIN = GND or VCC,
Outputs Open
Capacitance
TA = +25oC; All Measurements Referenced to Device GND, Note 1
SYMBOL
CIN
COUT
CI/O
PARAMETER
TYP
UNITS
Input Capacitance
20
pF
FREQ = 1MHz
Output Capacitance
20
pF
FREQ = 1MHz
I/O Capacitance
20
pF
FREQ = 1MHz
NOTE:
1. Not tested, but characterized at initial design and at major process/design changes.
3
TEST CONDITIONS
82C54
AC Electrical SpecificationsVCC = +5.0V ± 10%, Includes all Temperature Ranges
82C54
SYMBOL
PARAMETER
82C54-10
82C54-12
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
TEST
CONDITIONS
READ CYCLE
(1)
TAR
Address Stable Before RD
30
-
25
-
25
-
ns
1
(2)
TSR
CS Stable Before RD
0
-
0
-
0
-
ns
1
(3)
TRA
Address Hold Time After RD
0
-
0
-
0
-
ns
1
(4)
TRR
RD Pulse Width
150
-
95
-
95
-
ns
1
(5)
TRD
Data Delay from RD
-
120
-
85
-
85
ns
1
(6)
TAD
Data Delay from Address
-
210
-
185
-
185
ns
1
(7)
TDF
RD to Data Floating
5
85
5
65
5
65
ns
2, Note 1
(8)
TRV
Command Recovery Time
200
-
165
-
165
-
ns
WRITE CYCLE
(9)
TAW
Address Stable Before WR
0
-
0
-
0
-
ns
(10)
TSW
CS Stable Before WR
0
-
0
-
0
-
ns
(11)
TWA
Address Hold Time After WR
0
-
0
-
0
-
ns
(12)
TWW
WR Pulse Width
95
-
95
-
95
-
ns
(13)
TDW
Data Setup Time Before WR
140
-
95
-
95
-
ns
(14)
TWD
Data Hold Time After WR
25
-
0
-
0
-
ns
(15)
TRV
Command Recovery Time
200
-
165
-
165
-
ns
CLOCK AND GATE
(16)
TCLK
Clock Period
125
DC
100
DC
80
DC
ns
1
(17)
TPWH
High Pulse Width
60
-
30
-
30
-
ns
1
(18)
TPWL
Low Pulse Width
60
-
40
-
30
-
ns
1
(19)
TR
Clock Rise Time
-
25
-
25
-
25
ns
(20)
TF
Clock Fall Time
-
25
-
25
-
25
ns
(21)
TGW
Gate Width High
50
-
50
-
50
-
ns
1
(22)
TGL
Gate Width Low
50
-
50
-
50
-
ns
1
(23)
TGS
Gate Setup Time to CLK
50
-
40
-
40
-
ns
1
(24)
TGH
Gate Hold Time After CLK
50
-
50
-
50
-
ns
1
(25)
TOD
Output Delay from CLK
-
150
-
100
-
100
ns
1
(26)
TODG
Output Delay from Gate
-
120
-
100
-
100
ns
1
(27)
TWO
OUT Delay from Mode Write
-
260
-
240
-
240
ns
1
(28)
TWC
CLK Delay for Loading
0
55
0
55
0
55
ns
1
(29)
TWG
Gate Delay for Sampling
-5
40
-5
40
-5
40
ns
1
(30)
TCL
CLK Setup for Count Latch
-40
40
-40
40
-40
40
ns
1
NOTE:
1. Not tested, but characterized at initial design and at major process/design changes.
4
82C54
Functional Diagram
D7 - D 0
8
CLK 0
DATA/
BUS
BUFFER
COUNTER
0
GATE 0
INTERNAL BUS
OUT 0
CONTROL
WORD
REGISTER
WR
A0
INTERNAL BUS
RD
READ/
WRITE
LOGIC
A1
CS
STATUS
LATCH
CRM
CLK 1
COUNTER
1
GATE 1
OUT 1
CE
CONTROL
LOGIC
CLK 2
CONTROL
WORD
REGISTER
CRL
STATUS
REGISTER
COUNTER
2
OLM
GATE 2
OLL
OUT 2
GATE n
CLK n
OUT n
COUNTER INTERNAL BLOCK DIAGRAM
Pin Description
SYMBOL
DIP PIN
NUMBER
TYPE
D7 - D0
1-8
I/O
CLK 0
9
I
CLOCK 0: Clock input of Counter 0.
OUT 0
10
O
OUT 0: Output of Counter 0.
GATE 0
11
I
GATE 0: Gate input of Counter 0.
DEFINITION
DATA: Bi-directional three-state data bus lines, connected to system data bus.
GND
12
OUT 1
13
O
GROUND: Power supply connection.
OUT 1: Output of Counter 1.
GATE 1
14
I
GATE 1: Gate input of Counter 1.
CLK 1
15
I
CLOCK 1: Clock input of Counter 1.
GATE 2
16
I
GATE 2: Gate input of Counter 2.
OUT 2
17
O
OUT 2: Output of Counter 2.
CLK 2
18
I
CLOCK 2: Clock input of Counter 2.
A0, A1
19 - 20
I
ADDRESS: Select inputs for one of the three counters or Control Word Register for read/write
operations. Normally connected to the system address bus.
A1
A0
SELECTS
0
0
Counter 0
0
1
Counter 1
1
0
Counter 2
1
1
Control Word Register
CS
21
I
CHIP SELECT: A low on this input enables the 82C54 to respond to RD and WR signals. RD and WR
are ignored otherwise.
RD
22
I
READ: This input is low during CPU read operations.
WR
23
I
WRITE: This input is low during CPU write operations.
VCC
24
-
VCC: The +5V power supply pin. A 0.1µF capacitor between pins VCC and GND is recommended for
decoupling.
5
82C54
Functional Description
Read/Write Logic
General
The 82C54 is a programmable interval timer/counter
designed for use with microcomputer systems. It is a general
purpose, multi-timing element that can be treated as an
array of I/O ports in the system software.
The 82C54 solves one of the most common problems in any
microcomputer system, the generation of accurate time
delays under software control. Instead of setting up timing
loops in software, the programmer configures the 82C54 to
match his requirements and programs one of the counters
for the desired delay. After the desired delay, the 82C54 will
interrupt the CPU. Software overhead is minimal and
variable length delays can easily be accommodated.
Some of the other computer/timer functions common to
microcomputers which can be implemented with the 82C54
are:
The Read/Write Logic accepts inputs from the system bus and
generates control signals for the other functional blocks of the
82C54. A1 and A0 select one of the three counters or the
Control Word Register to be read from/written into. A “low” on
the RD input tells the 82C54 that the CPU is reading one of the
counters. A “low” on the WR input tells the 82C54 that the CPU
is writing either a Control Word or an initial count. Both RD and
WR are qualified by CS; RD and WR are ignored unless the
82C54 has been selected by holding CS low.
Control Word Register
The Control Word Register (Figure 2) is selected by the
Read/Write Logic when A1, A0 = 11. If the CPU then does a
write operation to the 82C54, the data is stored in the
Control Word Register and is interpreted as a Control Word
used to define the Counter operation.
The Control Word Register can only be written to; status
information is available with the Read-Back Command.
• Real time clock
• Event counter
• Digital one-shot
D7 - D 0
• Programmable rate generator
8
CLK 0
DATA/
BUS
BUFFER
COUNTER
0
GATE 0
OUT 0
• Square wave generator
• Binary rate multiplier
• Complex motor controller
RD
Data Bus Buffer
WR
A0
This three-state, bi-directional, 8-bit buffer is used to
interface the 82C54 to the system bus (see Figure 1).
READ/
WRITE
LOGIC
A1
INTERNAL BUS
• Complex waveform generator
CLK 1
COUNTER
1
GATE 1
OUT 1
CS
D7 - D0
8
CLK 0
DATA/
BUS
BUFFER
COUNTER
0
GATE 0
OUT 0
A0
READ/
WRITE
LOGIC
A1
INTERNAL BUS
RD
WR
COUNTER
2
GATE 2
OUT 2
CLK 1
COUNTER
1
GATE 1
FIGURE 2. CONTROL WORD REGISTER AND COUNTER
FUNCTIONS
OUT 1
Counter 0, Counter 1, Counter 2
CS
CLK 2
CONTROL
WORD
REGISTER
CLK 2
CONTROL
WORD
REGISTER
COUNTER
2
GATE 2
OUT 2
These three functional blocks are identical in operation, so
only a single Counter will be described. The internal block
diagram of a signal counter is shown in Figure 3. The
counters are fully independent. Each Counter may operate in
a different Mode.
The Control Word Register is shown in the figure; it is not
part of the Counter itself, but its contents determine how the
Counter operates.
FIGURE 1. DATA BUS BUFFER AND READ/WRITE LOGIC
FUNCTIONS
6
82C54
The status register, shown in the figure, when latched,
contains the current contents of the Control Word Register
and status of the output and null count flag. (See detailed
explanation of the Read-Back command.)
82C54 System Interface
The actual counter is labeled CE (for Counting Element). It is
a 16-bit presettable synchronous down counter.
Basically, the select inputs A0, A1 connect to the A0, A1
address bus signals of the CPU. The CS can be derived
directly from the address bus using a linear select method or
it can be connected to the output of a decoder.
INTERNAL BUS
CONTROL
WORD
REGISTER
The 82C54 is treated by the system software as an array of
peripheral I/O ports; three are counters and the fourth is a
control register for MODE programming.
Operational Description
STATUS
LATCH
CRM
CRL
STATUS
REGISTER
After power-up, the state of the 82C54 is undefined. The
Mode, count value, and output of all Counters are undefined.
How each Counter operates is determined when it is
programmed. Each Counter must be programmed before it
can be used. Unused counters need not be programmed.
CE
CONTROL
LOGIC
General
Programming the 82C54
OLM
OLL
All Control Words are written into the Control Word Register,
which is selected when A1, A0 = 11. The Control Word
specifies which Counter is being programmed.
GATE n
CLK n
Counters are programmed by writing a Control Word and
then an initial count.
OUT n
FIGURE 3. COUNTER INTERNAL BLOCK DIAGRAM
OLM and OLL are two 8-bit latches. OL stands for “Output
Latch”; the subscripts M and L for “Most significant byte” and
“Least significant byte”, respectively. Both are normally referred
to as one unit and called just OL. These latches normally
“follow” the CE, but if a suitable Counter Latch Command is
sent to the 82C54, the latches “latch” the present count until
read by the CPU and then return to “following” the CE. One
latch at a time is enabled by the counter’s Control Logic to drive
the internal bus. This is how the 16-bit Counter communicates
over the 8-bit internal bus. Note that the CE itself cannot be
read; whenever you read the count, it is the OL that is being
read.
Similarly, there are two 8-bit registers called CRM and CRL (for
“Count Register”). Both are normally referred to as one unit and
called just CR. When a new count is written to the Counter, the
count is stored in the CR and later transferred to the CE. The
Control Logic allows one register at a time to be loaded from
the internal bus. Both bytes are transferred to the CE
simultaneously. CRM and CRL are cleared when the Counter is
programmed for one byte counts (either most significant byte
only or least significant byte only) the other byte will be zero.
Note that the CE cannot be written into; whenever a count is
written, it is written into the CR.
The Control Logic is also shown in the diagram. CLK n,
GATE n, and OUT n are all connected to the outside world
through the Control Logic.
7
By contrast, initial counts are written into the Counters, not
the Control Word Register. The A1, A0 inputs are used to
select the Counter to be written into. The format of the initial
count is determined by the Control Word used.
ADDRESS BUS (16)
A1
A0
CONTROL BUS
I/OR I/OW
DATA BUS (8)
8
D0 - D7
82C54
RD
COUNTER
0
COUNTER
1
COUNTER
2
OUT GATE CLK
OUT GATE CLK
OUT GATE CLK
A1
A0
CS
WR
FIGURE 4. COUNTER INTERNAL BLOCK DIAGRAM
Write Operations
The programming procedure for the 82C54 is very flexible.
Only two conventions need to be remembered:
1. For Each Counter, the Control Word must be written
before the initial count is written.
2. The initial count must follow the count format specified in the
Control Word (least significant byte only, most significant
byte only, or least significant byte and then most significant
byte).
82C54
Since the Control Word Register and the three Counters have
separate addresses (selected by the A1, A0 inputs), and each
Control Word specifies the Counter it applies to (SC0, SC1
bits), no special instruction sequence is required. Any
programming sequence that follows the conventions above is
acceptable.
CONTROL WORD FORMAT
A1, A0 = 11; CS = 0; RD = 1; WR = 0
POSSIBLE PROGRAMMING SEQUENCE
A1
A0
Control Word - Counter 0
1
1
LSB of Count - Counter 0
0
0
MSB of Count - Counter 0
0
0
Control Word - Counter 1
1
1
LSB of Count - Counter 1
0
1
D7
D6
D5
D4
D3
D2
D1
D0
MSB of Count - Counter 1
0
1
SC1
SC0
RW1
RW0
M2
M1
M0
BCD
Control Word - Counter 2
1
1
LSB of Count - Counter 2
1
0
MSB of Count - Counter 2
1
0
SC - SELECT COUNTER
SC1
SC0
0
0
Select Counter 0
0
1
Select Counter 1
1
0
Select Counter 2
1
1
Read-Back Command (See Read Operations)
RW - READ/WRITE
RW1 RW0
POSSIBLE PROGRAMMING SEQUENCE
A1
A0
Control Word - Counter 0
1
1
Control Word - Counter 1
1
1
Control Word - Counter 2
1
1
LSB of Count - Counter 2
1
0
0
0
Counter Latch Command (See Read Operations)
LSB of Count - Counter 1
0
1
0
1
Read/Write least significant byte only.
LSB of Count - Counter 0
0
0
1
0
Read/Write most significant byte only.
MSB of Count - Counter 0
0
0
1
1
Read/Write least significant byte first, then most
significant byte.
MSB of Count - Counter 1
0
1
MSB of Count - Counter 2
1
0
M - MODE
M2
M1
M0
0
0
0
Mode 0
0
0
1
Mode 1
X
1
0
Mode 2
X
1
1
Mode 3
1
0
0
Mode 4
1
0
1
Mode 5
BCD - BINARY CODED DECIMAL
POSSIBLE PROGRAMMING SEQUENCE
A1
A0
Control Word - Counter 2
1
1
Control Word - Counter 1
1
1
Control Word - Counter 0
1
1
LSB of Count - Counter 2
1
0
MSB of Count - Counter 2
1
0
LSB of Count - Counter 1
0
1
MSB of Count - Counter 1
0
1
0
Binary Counter 16-bit
LSB of Count - Counter 0
0
0
1
Binary Coded Decimal (BCD) Counter (4 Decades)
MSB of Count - Counter 0
0
0
NOTE: Don’t Care bits (X) should be 0 to insure compatibility with
future products.
8
82C54
SC1, SC0 - specify counter to be latched
POSSIBLE PROGRAMMING SEQUENCE
A1
A0
SC1
SC0
COUNTER
Control Word - Counter 1
1
1
0
0
0
Control Word - Counter 0
1
1
0
1
1
LSB of Count - Counter 1
0
1
1
0
2
Control Word - Counter 2
1
1
1
1
Read-Back Command
LSB of Count - Counter 0
0
0
MSB of Count - Counter 1
0
1
LSB of Count - Counter 2
1
0
MSB of Count - Counter 0
0
0
MSB of Count - Counter 2
1
0
NOTE: In all four examples, all counters are programmed to
Read/Write two-byte counts. These are only four of many
programming sequences.
A new initial count may be written to a Counter at any time
without affecting the Counter’s programmed Mode in any way.
Counting will be affected as described in the Mode definitions.
The new count must follow the programmed count format.
If a Counter is programmed to read/write two-byte counts,
the following precaution applies. A program must not transfer
control between writing the first and second byte to another
routine which also writes into that same Counter. Otherwise,
the Counter will be loaded with an incorrect count.
READ OPERATIONS
It is often desirable to read the value of a Counter without
disturbing the count in progress. This is easily done in the
82C54.
There are three possible methods for reading the Counters.
The first is through the Read-Back command, which is
explained later. The second is a simple read operation of the
Counter, which is selected with the A1, A0 inputs. The only
requirement is that the CLK input of the selected Counter
must be inhibited by using either the GATE input or external
logic. Otherwise, the count may be in process of changing
when it is read, giving an undefined result.
The selected Counter’s output latch (OL) latches the count
when the Counter Latch Command is received. This count is
held in the latch until it is read by the CPU (or until the Counter
is reprogrammed). The count is then unlatched automatically
and the OL returns to “following” the counting element (CE).
This allows reading the contents of the Counters “on the fly”
without affecting counting in progress. Multiple Counter Latch
Commands may be used to latch more than one Counter.
Each latched Counter’s OL holds its count until read. Counter
Latch Commands do not affect the programmed Mode of the
Counter in any way.
If a Counter is latched and then, some time later, latched
again before the count is read, the second Counter Latch
Command is ignored. The count read will be the count at the
time the first Counter Latch Command was issued.
With either method, the count must be read according to the
programmed format; specifically, if the Counter is
programmed for two byte counts, two bytes must be read.
The two bytes do not have to be read one right after the
other; read or write or programming operations of other
Counters may be inserted between them.
Another feature of the 82C54 is that reads and writes of the
same Counter may be interleaved; for example, if the
Counter is programmed for two byte counts, the following
sequence is valid.
1. Read least significant byte.
2. Write new least significant byte.
3. Read most significant byte.
COUNTER LATCH COMMAND
The other method for reading the Counters involves a
special software command called the “Counter Latch
Command”. Like a Control Word, this command is written to
the Control Word Register, which is selected when A1, A0 =
11. Also, like a Control Word, the SC0, SC1 bits select one of
the three Counters, but two other bits, D5 and D4,
distinguish this command from a Control Word.
.
A1, A0 = 11; CS = 0; RD = 1; WR = 0
D7
D6
D5
D4
D3
D2
D1
D0
SC1
SC0
0
0
X
X
X
X
9
D5, D4 - 00 designates Counter Latch Command, X - Don’t Care.
NOTE: Don’t Care bits (X) should be 0 to insure compatibility
with future products.
4. Write new most significant byte.
If a counter is programmed to read or write two-byte counts,
the following precaution applies: A program MUST NOT
transfer control between reading the first and second byte to
another routine which also reads from that same Counter.
Otherwise, an incorrect count will be read.
READ-BACK COMMAND
The read-back command allows the user to check the count
value, programmed Mode, and current state of the OUT pin
and Null Count flag of the selected counter(s).
The command is written into the Control Word Register and
has the format shown in Figure 5. The command applies to
82C54
the counters selected by setting their corresponding bits D3,
D2, D1 = 1.
A0, A1 = 11; CS = 0; RD = 1; WR = 0
D7
D6
D5
D4
D3
1
1
COUNT
STATUS
D2
D1
CNT 2 CNT 1 CNT 0
D0
0
D5:0=Latch count of selected Counter (s)
D4:0=Latch status of selected Counter(s)
D3:1=Select Counter 2
D2:1=Select Counter 1
D1:1=Select Counter 0
D0:Reserved for future expansion; Must be 0
THIS ACTION:
CAUSES:
A. Write to the control word register:(1) . . . . Null Count = 1
B. Write to the count register (CR):(2) . . . . . Null Count = 1
FIGURE 5. READ-BACK COMMAND FORMAT
C. New count is loaded into CE (CR - CE) . . Null Count = 0
The read-back command may be used to latch multiple
counter output latches (OL) by setting the COUNT bit D5 = 0
and selecting the desired counter(s). This signal command is
functionally equivalent to several counter latch commands,
one for each counter latched. Each counter’s latched count
is held until it is read (or the counter is reprogrammed). That
counter is automatically unlatched when read, but other
counters remain latched until they are read. If multiple count
read-back commands are issued to the same counter
without reading the count, all but the first are ignored; i.e.,
the count which will be read is the count at the time the first
read-back command was issued.
The read-back command may also be used to latch status
information of selected counter(s) by setting STATUS bit D4
= 0. Status must be latched to be read; status of a counter is
accessed by a read from that counter.
The counter status format is shown in Figure 6. Bits D5
through D0 contain the counter’s programmed Mode exactly
as written in the last Mode Control Word. OUTPUT bit D7
contains the current state of the OUT pin. This allows the
user to monitor the counter’s output via software, possibly
eliminating some hardware from a system.
D7
D6
D5
OUTPUT
NULL
COUNT
D4
RW1 RW0
D3
D2
D1
D0
M2
M1
M0
BCD
D7:1=Out pin is 1
0=Out pin is 0
D6:1=Null count
0=Count available for reading
D5-D0=Counter programmed mode (See Control Word Formats)
FIGURE 6. STATUS BYTE
10
NULL COUNT bit D6 indicates when the last count written to
the counter register (CR) has been loaded into the counting
element (CE). The exact time this happens depends on the
Mode of the counter and is described in the Mode Definitions,
but until the counter is loaded into the counting element (CE),
it can’t be read from the counter. If the count is latched or read
before this time, the count value will not reflect the new count
just written. The operation of Null Count is shown below.
1. Only the counter specified by the control word will have its
null count set to 1. Null count bits of other counters are
unaffected.
2. If the counter is programmed for two-byte counts (least
significant byte then most significant byte) null count goes
to 1 when the second byte is written.
If multiple status latch operations of the counter(s) are
performed without reading the status, all but the first are
ignored; i.e., the status that will be read is the status of the
counter at the time the first status read-back command was
issued.
Both count and status of the selected counter(s) may be
latched simultaneously by setting both COUNT and STATUS
bits D5, D4 = 0. This is functionally the same as issuing two
separate read-back commands at once, and the above
discussions apply here also. Specifically, if multiple count
and/or status read-back commands are issued to the same
counter(s) without any intervening reads, all but the first are
ignored. This is illustrated in Figure 7.
If both count and status of a counter are latched, the first
read operation of that counter will return latched status,
regardless of which was latched first. The next one or two
reads (depending on whether the counter is programmed for
one or two type counts) return latched count. Subsequent
reads return unlatched count.
82C54
COMMANDS
D7
D6
D5
D4
D3
D2
D1
D0
DESCRIPTION
RESULT
1
1
0
0
0
0
1
0
Read-Back Count and Status of Counter 0
Count and Status Latched for Counter 0
1
1
1
0
0
1
0
0
Read-Back Status of Counter 1
Status Latched for Counter 1
1
1
1
0
1
1
0
0
Read-Back Status of Counters 2, 1
Status Latched for Counter 2,
But Not Counter 1
1
1
0
1
1
0
0
0
Read-Back Count of Counter 2
Count Latched for Counter 2
1
1
0
0
0
1
0
0
Read-Back Count and Status of Counter 1
Count Latched for Counter 1,
But Not Status
1
1
1
0
0
0
1
0
Read-Back Status of Counter 1
Command Ignored, Status Already
Latched for Counter 1
FIGURE 7. READ-BACK COMMAND EXAMPLE
MODE 0: INTERRUPT ON TERMINAL COUNT
CS
RD
WR
A1
A0
0
1
0
0
0
Write into Counter 0
0
1
0
0
1
Write into Counter 1
0
1
0
1
0
Write into Counter 2
0
1
0
1
1
Write Control Word
0
0
1
0
0
Read from Counter 0
0
0
1
0
1
Read from Counter 1
0
0
1
1
0
Read from Counter 2
0
0
1
1
1
No-Operation (Three-State)
1
X
X
X
X
No-Operation (Three-State)
0
1
1
X
X
No-Operation (Three-State)
FIGURE 8. READ/WRITE OPERATIONS SUMMARY
MODE DEFINITIONS
The following are defined for use in describing the operation
of the 82C54.
CLK PULSE - A rising edge, then a falling edge, in that
order, of a Counter’s CLK input.
TRIGGER - A rising edge of a Counter’s Gate input.
COUNTER LOADING - The transfer of a count from the CR
to the CE (See “Functional Description”)
11
Mode 0 is typically used for event counting. After the Control
Word is written, OUT is initially low, and will remain low until
the Counter reaches zero. OUT then goes high and remains
high until a new count or a new Mode 0 Control Word is
written to the Counter.
GATE = 1 enables counting; GATE = 0 disables counting.
GATE has no effect on OUT.
After the Control Word and initial count are written to a
Counter, the initial count will be loaded on the next CLK
pulse. This CLK pulse does not decrement the count, so for
an initial count of N, OUT does not go high until N + 1 CLK
pulses after the initial count is written.
If a new count is written to the Counter it will be loaded on
the next CLK pulse and counting will continue from the new
count. If a two-byte count is written, the following happens:
1. Writing the first byte disables counting. Out is set low
immediately (no clock pulse required).
2. Writing the second byte allows the new count to be
loaded on the next CLK pulse.
This allows the counting sequence to be synchronized by
software. Again OUT does not go high until N + 1 CLK
pulses after the new count of N is written.
82C54
If an initial count is written while GATE = 0, it will still be
loaded on the next CLK pulse. When GATE goes high, OUT
will go high N CLK pulses later; no CLK pulse is needed to
load the counter as this has already been done.
CW = 10
LSB = 4
WR
CLK
GATE
OUT
N
N
CW = 10
N
N
0
4
0
3
0
2
0
1
0
0
FF
FF
FF
FE
MODE 1: HARDWARE RETRIGGERABLE ONE-SHOT
OUT will be initially high. OUT will go low on the CLK pulse
following a trigger to begin the one-shot pulse, and will remain
low until the Counter reaches zero. OUT will then go high and
remain high until the CLK pulse after the next trigger.
After writing the Control Word and initial count, the Counter is
armed. A trigger results in loading the Counter and setting
OUT low on the next CLK pulse, thus starting the one-shot
pulse N CLK cycles in duration. The one-shot is retriggerable,
hence OUT will remain low for N CLK pulses after any trigger.
The one-shot pulse can be repeated without rewriting the
same count into the counter. GATE has no effect on OUT.
If a new count is written to the Counter during a one-shot
pulse, the current one-shot is not affected unless the
Counter is retriggerable. In that case, the Counter is loaded
with the new count and the one-shot pulse continues until
the new count expires.
LSB = 3
WR
CLK
GATE
CW = 12
LSB = 3
WR
OUT
N
N
CW = 10
N
N
0
3
LSB = 3
0
2
0
2
0
2
0
1
0
0
FF
FF
CLK
LSB = 2
GATE
WR
OUT
CLK
N
GATE
N
N
N
N
0
3
0
2
0
1
0
0
FF
FF
0
3
0
2
N
0
3
0
2
0
1
0
3
0
2
0
1
0
0
0
0
FF
FF
FF
FE
0
4
0
3
OUT
N
N
N
N
0
3
0
2
0
1
0
2
0
1
0
0
CW = 12
FF
FF
LSB = 3
WR
FIGURE 9. MODE 0
NOTES: The following conventions apply to all mode timing diagrams.
1. Counters are programmed for binary (not BCD) counting and for
reading/writing least significant byte (LSB) only.
CLK
GATE
2. The counter is always selected (CS always low).
3. CW stands for “Control Word”; CW = 10 means a control word of
10, Hex is written to the counter.
OUT
N
4. LSB stands for Least significant “byte” of count.
5. Numbers below diagrams are count values. The lower number is
the least significant byte. The upper number is the most
significant byte. Since the counter is programmed to read/write
LSB only, the most significant byte cannot be read.
N
CW = 12
N
N
LSB = 2
LSB = 4
WR
6. N stands for an undefined count.
7. Vertical lines show transitions between count values.
CLK
GATE
OUT
N
N
N
N
N
0
2
0
1
FIGURE 10. MODE 1
12
82C54
MODE 2: RATE GENERATOR
MODE 3: SQUARE WAVE MODE
This Mode functions like a divide-by-N counter. It is typically
used to generate a Real Time Clock Interrupt. OUT will
initially be high. When the initial count has decremented to 1,
OUT goes low for one CLK pulse. OUT then goes high
again, the Counter reloads the initial count and the process
is repeated. Mode 2 is periodic; the same sequence is
repeated indefinitely. For an initial count of N, the sequence
repeats every N CLK cycles.
Mode 3 is typically used for Baud rate generation. Mode 3 is
similar to Mode 2 except for the duty cycle of OUT. OUT will
initially be high. When half the initial count has expired, OUT
goes low for the remainder of the count. Mode 3 is periodic;
the sequence above is repeated indefinitely. An initial count
of N results in a square wave with a period of N CLK cycles.
GATE = 1 enables counting; GATE = 0 disables counting. If
GATE goes low during an output pulse, OUT is set high
immediately. A trigger reloads the Counter with the initial
count on the next CLK pulse; OUT goes low N CLK pulses
after the trigger. Thus the GATE input can be used to
synchronize the Counter.
After writing a Control Word and initial count, the Counter will
be loaded on the next CLK pulse. OUT goes low N CLK
pulses after the initial count is written. This allows the
Counter to be synchronized by software also.
Writing a new count while counting does not affect the current
counting sequence. If a trigger is received after writing a new
count but before the end of the current period, the Counter will
be loaded with the new count on the next CLK pulse and
counting will continue from the end of the current counting
cycle.
CW = 14
LSB = 3
GATE = 1 enables counting; GATE = 0 disables counting. If
GATE goes low while OUT is low, OUT is set high
immediately; no CLK pulse is required. A trigger reloads the
Counter with the initial count on the next CLK pulse. Thus
the GATE input can be used to synchronize the Counter.
After writing a Control Word and initial count, the Counter will
be loaded on the next CLK pulse. This allows the Counter to
be synchronized by software also.
Writing a new count while counting does not affect the
current counting sequence. If a trigger is received after
writing a new count but before the end of the current halfcycle of the square wave, the Counter will be loaded with the
new count on the next CLK pulse and counting will continue
from the new count. Otherwise, the new count will be loaded
at the end of the current half-cycle.
CW = 16 LSB = 4
WR
WR
CLK
CLK
GATE
GATE
OUT
OUT
N
N
N
N
0
3
0
2
0
1
0
3
0
2
0
1
N
0
3
N
N
0
4
0
2
0
4
0
2
0
4
0
2
0
4
0
2
0
4
0
2
0
5
0
4
0
2
0
5
0
2
0
5
0
4
0
2
0
5
0
2
0
4
0
2
0
4
0
2
0
2
0
2
0
4
0
2
0
4
0
2
N
CW = 16 LSB = 5
CW = 14
LSB = 3
WR
WR
CLK
CLK
GATE
GATE
OUT
OUT
N
N
N
CW = 14
N
N
0
3
LSB = 4
0
2
0
2
0
3
0
2
0
1
0
3
N
N
N
CW = 16 LSB = 4
WR
LSB = 5
WR
CLK
CLK
GATE
GATE
OUT
OUT
N
N
N
N
0
4
0
3
0
2
FIGURE 11. MODE 2
13
0
1
0
5
0
4
0
3
N
N
N
N
FIGURE 12. MODE 3
82C54
Mode 3 Is Implemented As Follows
EVEN COUNTS - OUT is initially high. The initial count is
loaded on one CLK pulse and then is decremented by two
on succeeding CLK pulses. When the count expires, OUT
changes value and the Counter is reloaded with the initial
count. The above process is repeated indefinitely.
ODD COUNTS - OUT is initially high. The initial count is loaded
on one CLK pulse, decremented by one on the next CLK pulse,
and then decremented by two on succeeding CLK pulses.
When the count expires, OUT goes low and the Counter is
reloaded with the initial count. The count is decremented by
three on the next CLK pulse, and then by two on succeeding
CLK pulses. When the count expires, OUT goes high again and
the Counter is reloaded with the initial count. The above
process is repeated indefinitely. So for odd counts, OUT will be
high for (N + 1)/2 counts and low for (N - 1)/2 counts.
MODE 4: SOFTWARE TRIGGERED MODE
CW = 18
CLK
GATE
OUT
N
After writing a Control Word and initial count, the Counter will
be loaded on the next CLK pulse. This CLK pulse does not
decrement the count, so for an initial count of N, OUT does not
strobe low until N + 1 CLK pulses after the initial count is
written.
If a new count is written during counting, it will be loaded on
the next CLK pulse and counting will continue from the new
count. If a two-byte count is written, the following happens:
1. Writing the first byte has no effect on counting.
2. Writing the second byte allows the new count to be
loaded on the next CLK pulse.
This allows the sequence to be “retriggered” by software. OUT
strobes low N + 1 CLK pulses after the new count of N is
written.
N
CW = 18
N
N
0
3
0
2
0
1
0
0
FF
FF
FF
FE
FF
FD
0
3
0
2
0
1
0
0
FF
FF
0
2
0
1
0
0
FF
FF
LSB = 3
WR
CLK
GATE
OUT
OUT will be initially high. When the initial count expires, OUT
will go low for one CLK pulse then go high again. The
counting sequence is “Triggered” by writing the initial count.
GATE = 1 enables counting; GATE = 0 disables counting.
GATE has no effect on OUT.
LSB = 3
WR
N
N
CW = 18
N
N
0
3
LSB = 3
0
3
LSB = 2
WR
CLK
GATE
OUT
N
N
N
N
0
3
0
2
0
1
FIGURE 13. MODE 4
MODE 5: HARDWARE TRIGGERED STROBE
(RETRIGGERABLE)
OUT will initially be high. Counting is triggered by a rising
edge of GATE. When the initial count has expired, OUT will
go low for one CLK pulse and then go high again.
After writing the Control Word and initial count, the counter
will not be loaded until the CLK pulse after a trigger. This
CLK pulse does not decrement the count, so for an initial
count of N, OUT does not strobe low until N + 1 CLK pulses
after trigger.
A trigger results in the Counter being loaded with the initial
count on the next CLK pulse. The counting sequence is
triggerable. OUT will not strobe low for N + 1 CLK pulses
after any trigger GATE has no effect on OUT.
If a new count is written during counting, the current counting
sequence will not be affected. If a trigger occurs after the
new count is written but before the current count expires, the
14
82C54
Counter will be loaded with new count on the next CLK pulse
and counting will continue from there.
CW = 1A LSB = 3
WR
Counter
New counts are loaded and Counters are decremented on
the falling edge of CLK.
The largest possible initial count is 0; this is equivalent to 216
for binary counting and 104 for BCD counting.
CLK
The counter does not stop when it reaches zero. In Modes 0,
1, 4, and 5 the Counter “wraps around” to the highest count,
either FFFF hex for binary counting or 9999 for BCD
counting, and continues counting. Modes 2 and 3 are
periodic; the Counter reloads itself with the initial count and
continues counting from there.
GATE
OUT
N
N
N
N
N
0
3
0
2
0
1
0
0
FF
FF
0
3
CW = 1A LSB = 3
WR
CLK
SIGNAL
STATUS
MODES
LOW OR
GOING LOW
RISING
HIGH
0
Disables Counting
-
Enables Counting
1
-
1) Initiates
Counting
2) Resets output
after next clock
-
GATE
OUT
N
N
N
N
N
CW = 1A LSB = 3
N
0
3
0
2
0
3
0
2
0
1
0
0
FF
FF
2
Initiates Counting Enables Counting
1) Disables
counting
2) Sets output
immediately high
3
Initiates Counting Enables Counting
1) Disables
counting
2) Sets output
immediately high
4
1) Disables
Counting
LSB = 5
WR
CLK
GATE
OUT
5
N
N
N
N
N
0
3
0
2
0
1
0
0
FF
FF
FF
FE
0
5
0
4
FIGURE 14. MODE 5
Operation Common To All Modes
Programming
When a Control Word is written to a Counter, all Control
Logic, is immediately reset and OUT goes to a known initial
state; no CLK pulses are required for this.
Gate
The GATE input is always sampled on the rising edge of
CLK. In Modes 0, 2, 3 and 4 the GATE input is level
sensitive, and logic level is sampled on the rising edge of
CLK. In modes 1, 2, 3 and 5 the GATE input is rising-edge
sensitive. In these Modes, a rising edge of Gate (trigger)
sets an edge-sensitive flip-flop in the Counter. This flip-flop is
then sampled on the next rising edge of CLK. The flip-flop is
reset immediately after it is sampled. In this way, a trigger will
be detected no matter when it occurs - a high logic level
does not have to be maintained until the next rising edge of
CLK. Note that in Modes 2 and 3, the GATE input is both
edge-and level-sensitive.
15
-
-
Enables Counting
Initiates Counting
-
FIGURE 15. GATE PIN OPERATIONS SUMMARY
MODE
MIN COUNT
MAX COUNT
0
1
0
1
1
0
2
2
0
3
2
0
4
1
0
5
1
0
NOTE: 0 is equivalent to 216 for binary counting and 104 for BCD
counting.
FIGURE 16. MINIMUM AND MAXIMUM INITIAL COUNTS
82C54
Timing Waveforms
A0 - A1
(9)
tAW
tWA (11)
CS
(10)
tSW
VALID
DATA BUS
(13)
tDW
tWD
(14)
WR
(12)
tWW
FIGURE 17. WRITE
A0 - A1
tRA (3)
tAR (1)
CS
(2)
tSR
(4)
tRR
RD
DATA BUS
(6)
tAD
(5)
tRD
(7)
tDF
VALID
FIGURE 18. READ
(8) (15)
tRV
RD, WR
FIGURE 19. RECOVERY
16
82C54
Timing Waveforms (Continued)
COUNT
(SEE NOTE)
MODE
WR
tWC (28)
(17)
tPWH
(23)
tGS
(16)
tCLK
tCL (30)
(18)
tPWL
CLK
(19)
tR
tF (20)
tGS
(23)
GATE
tGH (24)
(21)
tGW
(24)
(22)
tGL
tGH
tOD (25)
OUT
(27)
tWO
tODG (26)
NOTE: LAST BYTE OF COUNT BEING WRITTEN
FIGURE 20. CLOCK AND GATE
Burn-In Circuits
MD82C54 (CERDIP)
VCC
Q1
Q2
VCC
GND
F9
F10
F11
F12
F0
A
Q6
GND
R1
R1
R1
R1
R1
R1
R1
R1
R2
R1
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
R1
R1
R1
R1
R1
R2
MR82C54 (CLCC)
VCC
VCC Q2 Q1 OPEN
Q3
R2
R1
R1 R1
Q3 VCC
R1
R1 R1
VCC
GND
VCC
Q5
GND
Q4
R3
F9
F10
A
Q8
F1
R4
F11
F12
Q7
A
R1
R1
F2
A
R1
C1
C1
F0
R1
R1
R1
R2
OPEN
4
3
2
1
28
27
26
25
5
6
24
7
23
8
22
21
9
10
20
11
19
12
13
14
R5 R1
15
16
17
R5
18
R1 R2
VCC/2 Q6 GND
VCC/2 Q7 F1
OPEN
NOTES:
1. VCC = 5.5V ± 0.5V
2. GND = 0V
3. VIH = 4.5V ±10%
4. VIL = -0.2V to 0.4V
5. R1 = 47kΩ ±5%
6. R2 = 1.0kΩ ±5%
7. R3 = 2.7kΩ ±5%
8. R4 = 1.8kΩ ±5%
9. R5 = 1.2kΩ ±5%
10. C1 = 0.01µF Min
11. F0 = 100kHz ±10%
12. F1 = F0/2, F2 = F1/2, ...F12 = F11/2
17
OPEN
R1
GND
R1
R1
R2
R5
R1
Q5
Q4
F2
VCC/2
Q8
82C54
Die Characteristics
METALLIZATION:
Type: Si-Al-Cu
Thickness: Metal 1: 8kÅ ± 0.75kÅ
Metal 2: 12kÅ ± 1.0kÅ
DIE DIMENSIONS:
129mils x 155mils x 19mils
(3270µm x 3940µm x 483µm)
GLASSIVATION:
Type: Nitrox
Thickness: 10kÅ ± 3.0kÅ
Metallization Mask Layout
82C54
D5
D6
D7
VCC
WR
RD
D4
CS
D3
A1
D2
A0
D1
CLK2
D0
OUT2
GATE2
CLK0
OUT0
18
GATE0
GND
OUT1
GATE1
CLK1
82C54
Dual-In-Line Plastic Packages (PDIP)
E24.6 (JEDEC MS-011-AA ISSUE B)
N
24 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
1 2 3
INCHES
N/2
SYMBOL
-B-
-C-
A2
SEATING
PLANE
e
B1
D1
A1
eC
B
0.010 (0.25) M
C A B S
0.250
-
-
0.39
A2
0.125
0.195
3.18
4.95
-
B
0.014
0.022
0.356
0.558
-
C
L
B1
0.030
0.070
0.77
1.77
8
eA
C
0.008
0.015
0.204
0.381
-
D
1.150
1.290
D1
0.005
-
C
eB
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
7. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
6.35
NOTES
-
NOTES:
19
MAX
0.015
A
L
D1
MIN
A
E
BASE
PLANE
MAX
A1
-AD
MILLIMETERS
MIN
29.3
-
4
4
32.7
5
-
5
0.13
E
0.600
0.625
15.24
15.87
6
E1
0.485
0.580
12.32
14.73
5
e
0.100 BSC
2.54 BSC
-
eA
0.600 BSC
15.24 BSC
6
eB
-
0.700
-
17.78
7
L
0.115
0.200
2.93
5.08
4
N
24
24
9
Rev. 0 12/93
82C54
Plastic Leaded Chip Carrier Packages (PLCC)
0.042 (1.07)
0.048 (1.22)
PIN (1) IDENTIFIER
N28.45 (JEDEC MS-018AB ISSUE A)
0.042 (1.07)
0.056 (1.42)
0.004 (0.10)
C
0.025 (0.64)
R
0.045 (1.14)
0.050 (1.27) TP
C
L
D2/E2
C
L
E1 E
D2/E2
VIEW “A”
0.020 (0.51)
MIN
A1
A
D1
D
0.026 (0.66)
0.032 (0.81)
0.013 (0.33)
0.021 (0.53)
0.025 (0.64)
MIN
0.045 (1.14)
MIN
VIEW “A” TYP.
NOTES:
1. Controlling dimension: INCH. Converted millimeter dimensions are
not necessarily exact.
2. Dimensions and tolerancing per ANSI Y14.5M-1982.
3. Dimensions D1 and E1 do not include mold protrusions. Allowable
mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1
and E1 include mold mismatch and are measured at the extreme
material condition at the body parting line.
4. To be measured at seating plane -C- contact point.
5. Centerline to be determined where center leads exit plastic body.
6. “N” is the number of terminal positions.
20
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.165
0.180
4.20
4.57
-
A1
0.090
0.120
2.29
3.04
-
D
0.485
0.495
12.32
12.57
-
D1
0.450
0.456
11.43
11.58
3
D2
0.191
0.219
4.86
5.56
4, 5
E
0.485
0.495
12.32
12.57
-
E1
0.450
0.456
11.43
11.58
3
E2
0.191
0.219
4.86
5.56
4, 5
N
28
28
6
Rev. 2 11/97
SEATING
-C- PLANE
0.020 (0.51) MAX
3 PLCS
28 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE
82C54
Ceramic Leadless Chip Carrier Packages (CLCC)
J28.A
MIL-STD-1835 CQCC1-N28 (C-4)
28 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE
0.010 S E H S
D
INCHES
D3
SYMBOL
j x 45o
E3
B
E
h x 45o
0.010 S E F S
A
A1
PLANE 2
PLANE 1
-E-
B1
e
L
-H-
L3
MILLIMETERS
MAX
MAX
NOTES
A
0.060
0.100
1.52
2.54
6, 7
0.050
0.088
1.27
2.23
-
B
-
-
-
-
-
B1
0.022
0.028
0.56
0.71
2, 4
B2
0.072 REF
1.83 REF
-
B3
0.006
0.022
0.15
0.56
-
D
0.442
0.460
11.23
11.68
-
D1
0.300 BSC
7.62 BSC
-
D2
0.150 BSC
3.81 BSC
-
D3
-
0.460
E
0.442
0.460
11.23
11.68
2
11.68
-
E1
0.300 BSC
7.62 BSC
-
E2
0.150 BSC
3.81 BSC
-
E3
e
-
0.460
0.050 BSC
0.015
-
-
11.68
1.27 BSC
0.38
2
-
-
2
h
0.040 REF
1.02 REF
5
j
0.020 REF
0.51 REF
5
L
0.045
0.055
1.14
1.40
-
L1
0.045
0.055
1.14
1.40
-
L2
0.075
0.095
1.90
2.41
-
L3
0.003
0.015
0.08
0.038
-
ND
7
7
3
NE
7
7
3
N
28
28
-F-
3
Rev. 0 5/18/94
B3
E1
E2
MIN
A1
e1
0.007 M E F S H S
MIN
1. Metallized castellations shall be connected to plane 1 terminals
and extend toward plane 2 across at least two layers of ceramic
or completely across all of the ceramic layers to make electrical
connection with the optional plane 2 terminals.
L2
B2
L1
D2
e1
D1
NOTES:
2. Unless otherwise specified, a minimum clearance of 0.015 inch
(0.38mm) shall be maintained between all metallized features
(e.g., lid, castellations, terminals, thermal pads, etc.)
3. Symbol “N” is the maximum number of terminals. Symbols “ND”
and “NE” are the number of terminals along the sides of length
“D” and “E”, respectively.
4. The required plane 1 terminals and optional plane 2 terminals (if
used) shall be electrically connected.
5. The corner shape (square, notch, radius, etc.) may vary at the
manufacturer’s option, from that shown on the drawing.
6. Chip carriers shall be constructed of a minimum of two ceramic
layers.
7. Dimension “A” controls the overall package thickness. The maximum “A” dimension is package height before being solder dipped.
8. Dimensioning and tolerancing per ANSI Y14.5M-1982.
9. Controlling dimension: INCH.
21
82C54
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
F24.6 MIL-STD-1835 GDIP1-T24 (D-3, CONFIGURATION A)
24 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
LEAD FINISH
c1
-D-
-A-
BASE
METAL
E
M
-Bbbb S
C A-B S
-C-
S1
0.225
-
5.72
-
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
-
1.290
-
32.77
5
E
0.500
0.610
15.49
5
eA
e
ccc M
C A-B S
eA/2
c
aaa M C A - B S D S
D S
NOTES
-
b2
b
MAX
0.014
α
A A
MIN
b
A
L
MILLIMETERS
MAX
A
Q
SEATING
PLANE
MIN
M
(b)
D
BASE
PLANE
SYMBOL
b1
SECTION A-A
D S
INCHES
(c)
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
12.70
e
0.100 BSC
2.54 BSC
-
eA
0.600 BSC
15.24 BSC
-
eA/2
0.300 BSC
7.62 BSC
-
L
0.120
0.200
3.05
5.08
-
Q
0.015
0.075
0.38
1.91
6
S1
0.005
-
0.13
-
7
105o
90o
105o
-
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
α
90o
aaa
-
0.015
-
0.38
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
bbb
-
0.030
-
0.76
-
ccc
-
0.010
-
0.25
-
M
-
0.0015
-
0.038
2, 3
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
N
24
24
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
8
Rev. 0 4/94
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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22
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