CXA1998AQ Recording/Playback Equalizer Amplifier For the availability of this product, please contact the sales office. Description The CXA1998AQ is an IC developed for analog signal processing in tape recorders. Processing for both the recording and playback systems is achieved on one chip. Features • 11-bit serial data interface • Recording/playback mute function • Recording equalizer Gp and Fp can be adjusted externally. • AGC (Automatic Gain Control) • Comparator for AMS (Automatic Music Sensor) • Recording/playback equalizer amplifier with 1.7 times speed switching Absolute Maximum Ratings (Ta = 25°C) • Supply voltage VCC, VDD 12 V • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –65 to +150 °C • Allowable power dissipation PD 645 mW Operating Conditions Supply voltage VCC VDD 6.5 to 10.0 4.5 to 5.5 48 pin QFP (Plastic) Structure Bipolar silicon monolithic IC Applications All analog signal processing in the cassette decks of tape recorders and compact music centers Applicable Head Applicable to MITSUMI ELECTRIC Co., Ltd. Playback head: BP-7442-CP-6973 Recording/playback head: BC-9242-CB-9267 V V Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E96802A78 CXA1998AQ RFC Vcc VG GND AGC IN2 REC IN2 AGC OUT2 REC OUT2 DGND XRESET DATA CLK Block Diagram and Pin Configuration (Top View) 36 35 34 33 32 31 30 29 28 27 26 25 RECEQ 22 M2 GND D2 21 M1 GND D3 20 PL2 GND D4 19 PL1 GND D5 18 GND D6 17 BPA GND D9 16 SPEED 20k 20k GND VDD 5 6 7 8 9 GP CAL A EQ B EQ AGC TC AGC IN1 REC IN1 AGC OUT1 REC OUT1 AMS GAIN GND 10 11 12 AMS OUT 4 20k AMS TC 3 20k AMS GND 2 GND 1 –2– D9 D11 D7 VDD 10k FP CAL 48 D11 GND GND LATCHES SHIFT REGISTERS SPEED GND AMS GND PB OUT1 47 D10 RECEQ 40k AGC GAIN 19.5dB MUTE PB FB21 46 2.8V D1 D8 210k PB FB11 45 210k GND PB INA1 43 PB INB1 44 PBEQ CTL RECEQ CTL PB INA2 42 23 VDD DECK A/B AGC PB INB2 41 VDD B EQ AGC OFF A EQ GND 210k PB FB12 40 24 LATCH GND 40k AGC GAIN 19.5dB 210k IREF PB OUT2 38 PB FB22 39 10k GND 2.8V IREF 37 GND RFS BPB 15 RMUTE 14 RMUTEI 13 PBMUTE CXA1998AQ (Ta = 25°C, VCC = 8V, VDD = 5V, no signal, RESET ON) Pin Description Pin No. Symbol DC voltage I/O I/O resistance Equivalent circuit Vcc 1 GP CAL 1.2V — Description Vcc — Connects a resistor for determining the high-band peak gain of recording equalizer. Reference setting resistance is 27kΩ. ×2 1 30k 147 GND GND VCC VCC Deck A equalizer switch. Low: 120µs EQ High: 70µs EQ 147 2 A EQ — I 2 — GND GND VCC VCC 3 B EQ 2.5V (OPEN) 5k 147 50k I 53kΩ Deck B equalizer switch. Low: NORMAL TAPE, 120µs EQ Medium: Cro2 TAPE, 70µs EQ High: METAL TAPE, 70µs EQ 3 5k GND GND VCC VCC ×2 ×2 200 4 AGC TC 0.0V — — 500 4 147 ×2 500 5k 100k GND –3– GND ×4 200 Connects a resistor and capacitor for determining AGC attack/recovery time constants. CXA1998AQ Pin No. Symbol DC voltage I/O I/O resistance Equivalent circuit Description VCC 5 32 AGC IN1 AGC IN2 AGC signal input. Input resistance changes between 50kΩ and 100kΩ. AGC functions when the signal of –30dBm or more is input to AGC for AGC ON. (External 47µF//300kΩ for Pin 4) VCC 147 10k 4.0V I 50kΩ 5 32 40k ×4 VGS GND VCC VCC 23186 147 6 31 REC IN1 REC IN2 4.0V I 6 50kΩ 31 Recording equalizer input. 50k 1759 VGS VGS GND GND VCC VCC ×2 147 7 30 AGC OUT1 AGC OUT2 4.0V O 147Ω 18752 500 500 7 AGC output. 30 ×4 VGS 107423 9945 GND GND VGS VCC VCC ×3 40k 500 8 29 REC OUT1 REC OUT2 4.0V O 147Ω ×2 8 29 147 500 × 10 GND GND –4– 5p Recording equalizer output. CXA1998AQ Pin No. Symbol DC voltage I/O I/O resistance Equivalent circuit Description VCC VCC 10µ 9 AMS GAIN 3.5V — — Connects a resistor for determining AMS signal detection level and a capacitor for determining HPF cutoff frequency. 100k 9 147 GND 10 AMS GND 0.0V — GND 10 — AMS block ground. GND Vcc Vcc Vcc 11 147 11 AMS TC 8.0V — Connects time constant for AMS detection. 1k — GND GND Vcc Vcc 12 AMS OUT 8.0V O Vcc — 12 10k GND GND –5– AMS output. No signal detection: High Signal detection: Low CXA1998AQ Pin No. Symbol DC voltage I/O I/O resistance Equivalent circuit VDD VDD ×4 13 Description Connects a capacitor for setting time constant for playback mute ON/OFF switching. 20k PBMUTE 20k 5.0V — — GND 13 14 147 14 RMUTE1 GND GND 15 VDD RMUTE VDD Connects a capacitor for setting time constant for recording mute ON/OFF switching. Output for recording mute ON/OFF switch control signal. Outputs D11 from Pin 26 (DATA). ×4 5k 5.0V O — 15 Output for recording/playback equalizer speed switch control signal. Outputs D9 from Pin 26 (DATA). Low: Normal Speed High: High Speed (1.7 times) 5k 16 16 ×4 SPEED 20k GND GND 17 BPA 18 BPB 19 PL1 VDD VDD Outputs D5 from Pin 26 (DATA). ×4 O — 17 18 PL2 ×4 19 21 M1 22 M2 23 VDD Outputs D4 from Pin 26 (DATA). 10k 5.0V 20 Outputs D6 from Pin 26 (DATA). 20 Outputs D3 from Pin 26 (DATA). 20k Outputs D2 from Pin 26 (DATA). GND 21 GND 22 5.0V — — 23 –6– Outputs D1 from Pin 26 (DATA). VDD Power supply of serial data interface block. CXA1998AQ Pin No. 24 Symbol DC voltage I/O I/O resistance Equivalent circuit Description LATCH VDD 25µA 30k 2k Serial data interface reset input. Low: Reset. At this time serial data outputs (Pins 15 to 22) are all open (high). 24 — 27 I — 27 ×4 XRESET 30k 5p 10.5k GND Serial data interface latch input. GND VDD 25 25µA CLK Serial data interface clock input. 30k 4k 25 — I — 26 ×4 30k 10.5k GND 26 Serial data interface serial data input. DATA GND 28 DGND 0.0V — Serial data interface block ground. 28 — GND 33 GND 0.0V — 33 — Ground. GND VCC VCC ×2 ×2 34 VG 4.0V — 60kΩ 500 147 34 500 ×4 45k To each VGS 30k Signal reference voltage. Connects a capacitor for ripple rejection. 30k GND 35 VCC 8.0V — — GND VCC 35 –7– Power supply. CXA1998AQ Pin No. Symbol DC voltage I/O I/O resistance Equivalent circuit VCC Description VCC ×3 36 RFC 8.0V — Connects a resistor and capacitor for obtaining stable voltage with power supply ripple rejected. ×3 — 36 × 250 147 To each RFS GND Vcc Vcc 37 IREF ×2 1.2V — — Connects a resistor for determining the highband peak frequency of recording equalizer. Reference setting resistance is 27kΩ. 37 147 5p 48 48 FP CAL Connects a resistor (12kΩ) for determining equalizer gains. GND GND Vcc Vcc ×3 500 38 47 PB OUT2 PB OUT1 38 2.8V O 147Ω Playback equalizer output. 147 500 47 ×6 15p GND GND RFS VCC 39 46 PB FB22 PB FB21 147 2.8V — — 39 7k ×3 2k 2k ×4 ×4 ×3 46 GND GND –8– GND Connects a capacitor for determining playback equalizer time constants, such as 120µs and 70µs. CXA1998AQ Pin No. Symbol DC voltage I/O I/O resistance Equivalent circuit VCC 40 45 PB FB12 PB FB11 1.4V — 105kΩ Description VCC RFS 10k 5k VCC Playback equalizer negative feedback. VCC 1k 41 42 41 42 43 44 PB INB2 PB INA2 PB INA1 PB INB1 147 43 44 0.0V I 1k ×6 30p ×2 210k 10p 147 ×6 70k Playback equalizer input. 210k 70kΩ GND 40 45 GND GND Note) • AMS GND (Pin 10), DGND (Pin 28) and GND (Pin 33) are each independent in the IC and are not connected. Be sure tp ground each of the ground pins listed above. • The resistance of open collector outputs (Pins 15 to 22) can be connected Vcc. –9– CXA1998AQ Electrical Characteristics (Ta = 25°C, VCC = 8.0V, VDD = 5.0V, refer to Electrical Characteristics Measurement Circuit) Item Min. Typ. Max. Unit VCC 6.5 8.0 10.0 V VDD 4.5 5.0 5.5 V Current consumption Sum of VCC and VDD pin currents NORM – NS, no signal 13.5 19.7 25.0 mA AGC ON output level Pin 4 external R300kΩ//C47µF f = 1kHz, Vin = –25dBm –13.0 –11.0 –9.0 dBm AGC ON channel balance Pin 4 external R300kΩ//C47µF f = 1kHz, Vin = –25dBm –2.0 0.0 2.0 dB AGC ON distortion Pin 4 external R300kΩ//C47µF f = 1kHz, Vin = 0dBm — 0.3 1.5 % AGC OFF output level Pin 4 external R300kΩ//C 47µF f = 1kHz, Vin = –25dBm –7.5 –5.5 –3.5 dBm No signal detection threshold level Pin 9 external R9.1kΩ, C0.015µF Pin 11 external R100kΩ//C0.1µF f = 5kHz, 0dB = –21dBm (at PBEQ reference output level) –11.5 –8.2 — dB 120µs – NS frequency response f = 315Hz, Vin = –70dBm Reference for frequency response –23.0 –21.0 –19.0 dBm 120µs – NS frequency response f = 2.7kHz, Vin = –58.5dBm at 120µs – NS, 315Hz –0.1 1.3 2.9 70µs – NS frequency response f = 4.5kHz, Vin = –53.8dBm at 120µs – NS, 315Hz –0.1 1.7 2.9 120µs – HS frequency response f = 5.3kHz, Vin = –52.5dBm at 120µs – NS, 315Hz 1.8 3.0 4.8 70µs – HS frequency response f = 9.1kHz, Vin = –47.8dBm at 120µs – NS, 315Hz 2.1 3.6 5.1 Signal handling 120µs – NS, RL = 2.7kΩ f = 1kHz, THD + N = 1% –10.0 –6.0 — dBm Total harmonic distortion 120µs – NS, RL = 2.7kΩ f = 1kHz, Vin = –56.4dBm — 0.3 0.7 % S/N ratio 120µs – NS, Rg = 470Ω “A” weighting filter 55.0 62.0 — dB Output offset voltage 120µs – NS, Rg = 470Ω, playback mute OFF 2.4 2.7 3.2 V Playback mute characteristics 120µs – NS, f = 1kHz, Vin = –51.4dBm — –100 –80 dB Playback equalizer amplifier block AMS AGC Operating voltage Measurement conditions – 10 – dB CXA1998AQ Recording equalizer amplifier block Item Measurement conditions Min. Typ. Max. Reference input level NORM – NS, 315Hz, input level at which reference output can be obtained –28.2 –26.7 –25.2 Reference output level NORM – NS, 315Hz — –10.0 — Channel balance NORM – NS, 315Hz, output level difference 1ch-2ch for –26.7dBm input –1.5 0.0 1.5 NORM – NS frequency response f = 3kHz at NORM – NS, 315Hz, reference output –20dB –1.8 –0.6 0.6 NORM – NS frequency response f = 8kHz at NORM – NS, 315Hz, reference output –20dB 3.4 5.2 7.0 NORM – NS frequency response f = 12kHz at NORM – NS, 315Hz, reference output –20dB 8.7 11.7 14.7 CrO2 – NS frequency response f = 3kHz at NORM – NS, 315Hz, reference output –20dB 3.7 4.9 6.1 CrO2 – NS frequency response f = 8kHz at NORM – NS, 315Hz, reference output –20dB 9.9 11.4 12.9 CrO2 – NS frequency response f = 12kHz at NORM – NS, 315Hz, reference output –20dB 14.8 17.6 20.4 METAL – NS frequency response f = 3kHz at NORM – NS, 315Hz, reference output –20dB 4.7 5.9 7.1 METAL – NS frequency response f = 8kHz at NORM – NS, 315Hz, reference output –20dB 8.7 10.2 11.7 METAL – NS frequency response f = 12kHz at NORM – NS, 315Hz, reference output –20dB 12.9 15.2 17.5 NORM – HS frequency response f = 5kHz at NORM – NS, 315Hz, reference output –20dB –1.6 0.2 2.2 NORM – HS frequency response f = 15kHz at NORM – NS, 315Hz, reference output –20dB 7.6 9.7 11.8 NORM – HS frequency response f = 20kHz at NORM – NS, 315Hz, reference output –20dB 11.9 14.9 17.4 CrO2 – HS frequency response f = 5kHz at NORM – NS, 315Hz, reference output –20dB 5.2 6.4 7.6 CrO2 – HS frequency response f = 15kHz at NORM – NS, 315Hz, reference output –20dB 14.1 16.2 18.3 CrO2 – HS frequency response f = 20kHz at NORM – NS, 315Hz, reference output –20dB 16.7 19.7 22.7 METAL – HS frequency response f = 5kHz at NORM – NS, 315Hz, reference output –20dB 6.8 8.0 9.2 METAL – HS frequency response f = 15kHz at NORM – NS, 315Hz, reference output –20dB 13.7 15.5 17.3 METAL – HS frequency response f = 20kHz at NORM – NS, 315Hz, reference output –20dB 16.9 19.4 21.9 – 11 – Unit dBm dB CXA1998AQ Recording equalizer amplifier block Item Measurement conditions Min. Typ. Max. Unit Signal handling NORM – NS, RL = 2.7kΩ f = 1kHz, THD + N = 1% 8.0 8.8 — dB Total harmonic distortion NORM – NS, RL = 2.7kΩ f = 1kHz, 0dB — 0.2 0.5 % S/N ratio NORM – NS, Rg = 5.1kΩ “A” weighting filter 57.0 60.6 — dB Output offset voltage NORM – NS 3.6 4.0 4.4 V Recording mute characteristics NORM – NS, f = 1kHz 8dB — –100 –80 dB Control voltage low level 1 A-EQ (Pin 2) 0.0 — 0.5 Control voltage high level 1 A-EQ (Pin 2) 2.5 — VCC Control voltage low level 2 B-EQ (Pin 3) 0.0 — 0.5 Control voltage medium level 1 B-EQ (Pin 3) 2.2 — 2.8 Control voltage high level 2 B-EQ (Pin 3) 4.2 — VCC Note) NORM – NS: NORMAL TAPE – NORMAL SPEED NORM – HS: NORMAL TAPE – HIGH SPEED CrO2 – NS: CrO2 TAPE – NORMAL SPEED CrO2 – HS: CrO2 TAPE – HIGH SPEED METAL – NS: METAL TAPE – NORMAL SPEED METAL – HS: METAL TAPE – HIGH SPEED 120µs – NS: EQ = 120µs – NORMAL SPEED 120µs – HS: EQ = 120µs – HIGH SPEED 70µs – NS: EQ = 70µs – NORMAL SPEED 70µs – HS: EQ = 70µs – HIGH SPEED – 12 – V CXA1998AQ 11-bit serial data interface block Item Measurement conditions Min. Typ. Max. Unit Low level input voltage VIL (LATCH/CLK/DATA/XRESET) (Pins 24, 25, 26, 27) 0.0 — 1.5 High level input voltage VIH (LATCH/CLK/DATA/XRESET) (Pins 24, 25, 26, 27) 3.5 — VDD Low level output voltage VOL, IOL = 2mA (max) (Pins 15, 16, 17, 18, 19, 20, 21, 22) 0.0 — 0.5 High level output off leak current IOZ Leak current which flows to the output pin when IOZ output is open; applied voltage is 10V. (Pins 15 to 22) — — 1.0 µA Maximum clock frequency (1) fCK 500 — — kHz Minimum clock pulse width (2) tWC — — 1.0 Minimum reset pulse width (3) tWR — — 1.0 Minimum data setup time (4) tSDK (DATA → CLK) — — 1.0 Minimum data hold time (5) tHCD (CLK → DATA) — — 1.0 Minimum data pulse width (6) tWD — — 2.0 Minimum latch setup time (7) tSLD (LATCH → DATA) — — 1.0 Minimum latch hold time (8) tHCL (CLK → LATCH) — — 1.0 Minimum clock hold time (9) tHLC (LATCH → CLK) — — 1.0 V µs Note) • VDD is CPU supply voltage of 5.0V. • VCC is 10.0V for high level output off-leak current. • The threshold levels of low level input voltage and high level input voltage depend on VDD. Input level detection is done by comparison with VDD/2. (Refer to “Equivalent circuit” of Pin Description.) – 13 – CXA1998AQ Timing Chart for 11-bit Serial Data Interface (VDD = 5.0V) tWC 3.5V CLK 1.5V tSDK tHCD tWD 3.5V DATA D1 D2 1.5V tSLD LATCH 1.5V 3.5V CLK tHLC tHCL DATA D10 D11 3.5V LATCH 1.5V XRESET 1.5V tWR – 14 – tWC AC OUTPUT AC INPUT S505 S504 S503 S502 S501 ATT BUF S5B S4B S3B "A" Weighting Filter 30dB AMP –6dB ATT –9dB ATT –17dB ATT –29dB S2B 600 1kHz Band Pass Filter (20dB) + – TL072 Audio (22.2Hz – 22.2kHz) Filter S5A S4A S3A S2A ATT –40dB R30 100k GND C2 4.7µ/25V C1 4.7µ/25V 82k R32 82k 4.7k R36 4.7µ/25V 82k C3 4.7µ/25V C4 R33 R34 82k R35 R37 4.7k S11A S11B 27k R42 C11 2.2µ/25V R38 2.7k 100 47µ/25V S12B R43 100 R44 2.2µ/25V C12 12k C5 1µ C6 1µ C7 1µ C8 1µ C9 47µ/25V C10 2.7k S12A R39 R41 S10A R40 S1B R536 100 100 10k C14 S14 S9 470 S8 R47 470 S7 R48 470 S6 R49 470 S13 R50 PB FB22 39 PB OUT1 FP CAL 48 PB FB11 45 47 PB INB1 44 PB FB21 PB INA1 43 46 PB INA2 PB INB2 42 41 PB FB12 PB OUT2 38 40 IREF 37 1 2 0.5V 3 2.5V 4.2V 4 5 6 7 8 9 10 11 PBMUTE 12 13 RMUTEI 14 RMUTE 15 SPEED 16 BPA 17 BPB 18 PL1 19 PL2 20 M1 21 M2 22 VDD 23 LATCH 24 25 26 27 28 29 30 31 32 33 34 C15 35 S15 GP CAL 27k A EQ C16 S37 0.1µ R59 S17 AGC IN1 R52 S10B R51 C17 A EQ B EQ 10k C19 70µs B EQ 120µs AGC TC R66 300k R68 0.018µ 0.018µ 47µ/25V 0.1µ R63 S18 S19 S20 NORM CrO2 METAL C13 10k C18 10k S16 S55 36 S22A REC IN1 C23 0.1µ S1A 10k 47µ/25V RFC 5.1k Vcc S25B VG R71 47k R45 R56 R72 47k 5.1k GND S24 AGC OUT1 AGC IN2 10k REC IN2 S22B R80 100 10k 100 S21B R78 AGC OUT2 R61 R64 47µ/25V C20 C24 0.1µ 5.1k S21A 0.47µ/50V R81 R76 390k S25A 5.1k R73 390k 47µ/25V 1k R84 REC OUT2 R83 REC OUT1 S12C R88 R85 100 S26A 2.7k DGND AMS GAIN R90 C31 CHARGE2 C22 C21 R69 0.47µ/50V R74 S23 C26 C25 R75 0.47µ/50V 0.47µ/25V R79 C28 C27 10k 4.7µ/25V 4.7µ/25V 100 S27A S12D R86 C30 C29 R89 2.7k 2.2µ/25V 2.2µ/25V R5B 10k S27B 10k S26B 9.1k 0.015µ AMS GND R54 XRESET XRESET AMS TC C32 AMS OUT 4.7k R92 DATA 0.1µ R93 CHARGE1 10k 8V DATA CLK 100k CLK 100k R94 – 15 – S28 Electrical Characteristics Measurement Circuit S56B S56A S58H S58G S58F S58E S58D S58C S58B S58A 5V S30A S31A S32A S33A S34A S35A S36A 10k R105 10k S54 S53 10k S29A R106 R107 10k R108 10k R109 10k R110 10k R111 10k R112 10k R113 10k R114 GND 0.1µ C33 0.1µ C34 2.2k R96 2.2k R97 2.2k R98 2.2k R99 2.2k R100 2.2k R101 2.2k R102 2.2k R103 5V S57B S57A S29B S30B S31B S32B S33B S34B S35B S36B DC OUTPUT LATCH CXA1998AQ CXA1998AQ Application Circuit GND VCC GND 100k CLK 100k 2.2µ LATCHES 19 GND D5 18 GND D6 17 GND D9 16 GND D11 GND GND 47k PL2 47k PL1 47k BPB 47k BPA 47k SPEED 47k VDD VDD VDD VDD VDD VDD RMUTE 47k 15 VDD RMUTEI 47k GND 14 PBMUTE 20k 13 GND GND 22µ 12 100k AMS OUT VCC 0.1µ GND GND VDD M1 0.1µ 11 AMS TC 2.2µ AMS GAIN 10 100k 4.7µ 9 8 7 10k REC OUT1 AGC OUT1 0.1µ 2.7k 0.47µ REC IN1 47µ AGC IN1 AGC TC 3.3meg 6 5 4 3 B EQ A EQ 2 27k 10k 820p GP CAL 1 150p GND D4 20k 10k 48 20 20k 20k GND VDD 27k GND SHIFT REGISTERS DECK A/B VDD 2.2k FP CAL GND 21 GND D3 D7 AMS GND 2.2µ 2.8V 10k GND 47 GND RECEQ 46 PB OUT1 22 GND D2 D8 D10 D9 GND D11 40k AGC GAIN 19.5dB 45 PB FB21 MUTE 100 210k 47µ 0.018µ GND 210k 44 GND PB INB1 GND 12mH 100k 43 PB FB11 180p 2.2µ RECEQ CTL 42 VDD M2 PB INA1 PB GND AGC PB INA2 DECK-A PB-HEAD Bias OSC R/P-HEAD DECK-B PB REC REC OUT2 AGC OUT2 41 REC 100k 23 SPEED PB INB2 40k IREF GND 100 210k 40 47µ VDD VDD VDD 0.1µ PB FB12 24 D1 AGC OFF A EQ GND 210k 0.018µ GND 39 25 LATCH 2.2µ PB FB22 GND GND PBEQ CTL 38 10k GND 26 27 28 29 AMS GND 30 GND RECEQ PB OUT2 31 GND 37 GND REC IN2 AGC IN2 GND IREF 2.8V 12mH 180p 12k 10k 10k VG GND 32 33 34 RFS 150p GND VDD DGND 0.47µ 47µ 100µ 47µ Vcc RFC 35 36 GND 2.7k 4.7µ 1k 10k 820p 0.1µ DATA GND XRESET GND GND B EQ VCC AGC GAIN 19.5dB GND VCC GND Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 16 – CXA1998AQ 1. System control mode Playback and recording equalizer (1) Playback equalizer (120µs/70µs) A-EQ (Pin 2) L DECK-AB (serial data D10 (Pin 25)) L H 120µs (DECK A) B-EQ (Pin 3) H L 70µs (DECK A) M/H According to A-EQ control 120µs (DECK B) According to B-EQ control 70µs (DECK B) (2) Playback mute (Pin 13) ON/OFF control is performed by 11-bit serial data interface D7 (Pin 26). A capacitor for setting the switching time constant is connected. Time constant = 20kΩ × C (3) Recording equalizer (Normal, CrO2, Metal) B-EQ (Pin 3) REC MODE L M H NORMAL (TYPE I) CrO2 (TYPE II) METAL (TYPE IV) (4) Recording mute (Pin 14) ON/OFF control is performed by 11-bit serial data interface D11 (Pin 26). A fader function is achieved using a time constant circuit formed with the external capacitor and incorporated 20kΩ resistor. (5) FP CAL (Pin 48) The standard resistor setting is 27kΩ, but when resistance value is larger, fo (Hz) is lower, and when resistance value is smaller, fo (Hz) is higher. (fo: high-band peak frequency) (6) GP CAL (Pin 1) The standard resistor setting is 27kΩ, but when resistance value is larger, high-band peak gain is larger, and when resistance value is smaller, high-band peak gain is smaller. – 17 – CXA1998AQ 2. 11-bit serial data interface CLK (Pin 25) DATA (Pin 26) D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 LATCH (Pin 24) XRESET (Pin 27) • The DATA signal is taken in at the rising edge of the CLK signal. • The DATA signal is taken into the internal shift register when the LATCH signal is low. (Outputs (Pins 15 to 22) hold the previous value while the LATCH signal is low.) • The internal shift register data is latched and output in parallel at the rising edge of the LATCH signal. (Internal shift register data is loaded while the LATCH signal is high.) • The CLK signal of the 11th bit should fall after the LATCH signal rises. • Reset is done when the XRESET pin is low. (asynchronous method) Outputs (Pins 15 to 22) are all high (open) during reset. DATA (Pin 26) Output Control signal Output pin Input set at low Input set at high D1 M2 Pin 22 Low High (OPEN) D2 M1 Pin 21 Low High (OPEN) D3 PL2 Pin 20 Low High (OPEN) D4 PL1 Pin 19 Low High (OPEN) D5 BPB Pin 18 Low High (OPEN) D6 BPA Pin 17 Low High (OPEN) D7 PB MUTE — Low mute OFF High mute ON D8 AGC OFF — AGC function stops AGC function operates D9 SPEED Pin 16 Low, normal speed High (open) 1.7 D10 DECK AB — DECK A selected DECK B selected D11 REC MUTE Pin 15 Low mute OFF High (open) mute ON – 18 – CXA1998AQ • Make sure that VDD is 4.0V or more and XRESET is 1.5V or less, and 1µs or more when resetting by applying CR time constant to XRESET (Pin 27) and turning power ON. 4.0V or more VDD (Pin 23) 1.5V or less XRESET (Pin 27) 1µs or more A • XRESET (Pin 27) input level detection is done by comparison with VDD/2. The level should be VDD/2 > XRESET during the interval A. • For resetting with CPU when power is turned ON 4.0V or more VDD (Pin 23) 5.0V XRESET (Pin 27) 0V 1µs or more • Examples of AGC control during timer recording (1) Resets when power is turned ON (AGC function operates). (2) AGC is turned OFF after AGC inputs (Pins 5 and 32) rise. (External capacitor charge of AGC TC is discharged.) (3) AGC is turned ON and timer recording begins. – 19 – CXA1998AQ Circuit Diagram for 11-bit Serial Data Transfer Evaluation Tool XR1 D1 CLK1 XPR1 18 100 R16 B3 A3 Y3 Y1 A2 B2 Y2 VSS A4 VDD B4 A4 Y4 B3 A3 Y3 VDD B4 A4 Y4 B3 A3 Y3 C19 0.1µ 74HC08 (2) Y4 C12 0.1µ A4 Y1 A2 B2 Y2 VSS B2 B1 A2 A1 Y1 Y2 B1 VSS A1 C9 0.1µ Y1 A2 Y2 A3 Y3 VSS C8 0.1µ A1 100 R18 R15 220 R14 220 R9 220 R4 220 A = BIN A > BIN A1 A > BOUT B1 A = BOUT A0 A < BOUT VSS B0 B3 A < BIN A2 A3 B2 VDD C1 Q1 XQ2 XRES2 B2 XA2 C18 0.1µ R/C1 Q7 Q4 Q3 Q2 VSS XA1 B1 XRES1 Q2 Q1 Q5 XQ1 CLOCK Q6 Q10 Q8 Q9 C11 0.1µ RESET Q12 Q11 R8 220 R7 220 500kHz 10 250kHz D4 D5 D6 D14 D13 15 R19 100 H SERIAL XQH IN VSS QH G A F B E C D S/XL CLK2 CLK1 VDD C17 0.1µ VSS H SERIAL XQH IN QH G A F B E C D Q11 CLOCK Q10 DA D3 D2 D1 D11 D10 D9 D8 L D7 L H L D15 LH D12 S/XL CLK2 CLK1 VDD VSS C10 0.1µ XLOAD DD ENA 1 ENA P RESET DB Q9 DC Q8 VDD XRESET LH 1 2 4 8 VSS VDD C2 8 R/C2 7 VDD C 0.1µ L H H Y4 B1 D1 A1 B4 XR1 R12 10k R11 10k R10 9 100 Y6 Y5 A6 A5 VDD 8 7 VDD XQ2 C20 0.1µ Q2 VSS VSS XPR2 XQ1 XQ1 CLK2 Q1 Q1 D2 XQ2 XPR1 CLK1 XR2 Q2 CLK1 XPR1 VDD XPR2 C13 0.1µ CLK2 D1 7 14 8 16 C15 1000P CLK 100µ/25V LATCH VSS D2 XR1 7 6 6 DATA XQ2 XR2 6 5 5 XRESET Q2 XPR1 VDD 5 4 8 5V XPR2 XPR2 CLK1 XQ1 VSS CLK2 CLK2 D1 START XQ1 ON XQ2 D2 D2 XR1 Q1 Q2 XR2 XR2 OFF Q1 VDD VDD 4 3 7 4 C2 0.1µ 3 2 6 9 C3 0.1µ 2 8 1 8 5 – 20 – 1 74HC165 (2) 4 L H L 9 3 LH 10 2 L H 11 14 1 H 12 15 L H H L L L L H H H H 13 16 9 74HC165 (1) 3 3 10 74HC161 2 2 11 9 1 7 8 6 1 5 8 4 7 12 10 9 6 L H L H L 10 5 L H H 11 4 R17 C16 4.7µ 12 3 10 8 13 2 74HC123 11 9 74HC85 1 13 14 11 14 11 R13 2.2k 12 10 14 9 13 11 15 9 10 14 12 16 10 11 7 C4 0.1µ 7 11 12 7 6 12 13 6 5 13 14 5 4 14 15 4 3 15 16 3 5 2 4 1 3 7 2 2 2 6 1 1 6 8 8 8 74HC08 (1) 74HC04 5 9 9 9 13 8 4 2 3 1 2 7 1 6 7 5 6 4 5 3 4 2 3 1 10 10 10 12 17 74HC00 74HC74 (4) 74HC74 (3) 11 12 11 11 68k DGND 13 3 13 12 12 15 12 15 4 14 13 13 C14 0.1µ 8 14 14 8 9 16 13 16 3 6 2 4 9 10 16 74HC4040 1 EXCLK EXCLK OFF ON R5 7 10 11 DGND SW GND RESET 10k 6 11 12 C5 0.1µ R2 220 4.4MHz R1 1M 74HC74 (2) 74HC74 (1) 5 1 4 7 3 6 2 5 1 12 5 13 13 14 9 12 10 13 11 14 19 C7 15P C6 15P R6 10k 14 14 C21 GND R3 10k – 21 – Dummy D1 D2 D3 D4 D5 D6 The numbers (1) to (19) correspond to those of test pins for the 11-bit serial data transfer evaluation tool circuit. (19) LATCH (18) (17) = (8) (16) CLK (15) DATA HC165 (14) RESET/CLOCK STOP and COUNT RESET (13) (12) (11) HC123 (10) H when A = B (9) (8) CLK GATE CONT. (7) S/L (6) = (4) (5) (4) (3) START PULSE (2) CLK (1) CLK Timing Chart for 11-bit Serial Data Transfer Evaluation Tool D7 D8 D9 D10 D11 2µs COUNT RESET CLOCK STOP CXA1998AQ CXA1998AQ 3. AMS (1) AMS output logic Detection status Signal detection No signal detection Low High AMS OUT (Pin 12) AMS OUT (Pin 12) is an open collector output pin. When a 3.9 kΩ resistor is connected to VCC = 8V: Low: approximately 0.5V (IOL = 2mA (max.)) High: 8V Fig. 1 shows the AMS block diagram. PB OUT1 20k Inside IC SA HPF 20k LPF DET 25kHz AMS GAIN PB OUT2 AMS OUT 100k 11 AMS TC 12 10 AMS GND C2 C1 R2 R3 R1 9 VCC VCC GND VCC GND Fig. 1. AMS Block Diagram Fig. 2 shows the frequency response of the signal output from HPF. fC G GAIN (dB) 10 1kHz 25kHz f (Hz) Fig. 2. Frequency Response – 22 – 100kHz CXA1998AQ (2) AMS level setting The AMS level is set by adjusting HPF gain and cut-off frequency with the external resistor and capacitor at Pin 9. G and fc in Fig. 2 are obtained from the following formula. G = 20log (1 + 100k/R1) [dB] (1) fc = 1 / (2 · π · C1 · R1) [Hz] Full-wave rectifier is applied for the signal at DET. Signal detection time is set by the time constant of Pin 11 external resistor and capacitor. DET signal detection level: = –7.5dBm (typ.) = playback equalizer reference output level + AMS level + HPF gain (2) Playback equalizer reference output level of –21dBm is 0dB. Ex.) To set AMS level at –25dB, determine and set the constant for Pin 9 external resistor. (Calculate assuming PBOUT1 = PBOUT2) First, get the required HPF gain from formula (2). –7.5dBm = –21dBm + (–25dB) + HPFgain, so HPF gain = 38.5dB. Next, get Pin 9 external resistance from formula (1). 38.5dB = 20log (1 + 100k / R1), so R1 ≈ 1.2kΩ, and external resistance is 1.2kΩ. – 23 – CXA1998AQ Example of Representative Characteristics Quiescent current consumption vs. Supply voltage Quiescent current consumption [mA] 25 ICC is the sum of the VCC and VDD currents. VDD = 5.0V 24 23 22 21 20 19 18 17 16 15 6 7 8 9 10 11 VCC – Supply voltage [V] PB OUT PB FB1 PB IN Playback equalizer frequency response PB FB2 VCC = 8V GAIN [dB] 470 55 50 45 40 120µs – NS 35 120µs – HS 70µs – NS 30 70µs – HS 25 20 50 100 200 500 1k 2k 5k 10k 20k Frequency [Hz] – 24 – 50k 0.018µ 47µ 100 10µF 60 2.2µ 65 M CXA1998AQ Output response [dB] Recording equalizer frequency response 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 20 VCC = 8V 0dB = NORM – NS, 315Hz, –30dBm (TAPE) (SPEED) NORM – NS CrO2 – NS METAL– NS 50 100 200 500 1k 2k 5k 10k 20k 50k 20k 50k Frequency [Hz] Output response [dB] Recording equalizer frequency response 28 26 VCC = 8V 0dB = NORM – NS, 315Hz, –30dBm 24 (TAPE) (SPEED) 22 NORM – NS CrO2 – NS 20 METAL– NS 18 16 14 12 10 8 6 4 2 0 20 50 100 200 500 1k 2k Frequency [Hz] – 25 – 5k 10k CXA1998AQ AMS quiescent detection level frequency response AMS OUT 12 B 100k 11 100k 9 0.1µ A AMS TC A: Pin 9 R9.1k C0.015µ B: Pin 9 R1k C0.1µ AMS GAIN A : 0.015µ 9.1k B : 0.1µ 1k to 8V 20 50 100 200 500 1k 2k 5k 10k 20k 50k Frequency [Hz] AGC output characteristics AGC TC 30 25 20 15 10 5 0 –5 –10 –15 –20 –25 –30 –35 –40 10 5 Output level [dBm] AMS input level (playback equalizer output level) [dB] VCC = 8V 120µs – NS AMS OUT 8V 0dB = –21dBm, 315Hz (playback equalizer reference output level) VCC = 8V 1kHz 4 AGC OFF 0 300k 47µ –5 –10 AGC ON –15 –35 –30 –25 –20 –15 Input level [dBm] – 26 – –10 –5 CXA1998AQ Recording equalizer total harmonic distortion T.H.D + Noise [%] 2.0 VCC = 8V NORM – NS RL = 2.7kΩ 1kHz 0dB = –10dBm 1.0 0.5 0.2 0.1 –15 –10 –5 0 5 10 Output level [dBm] Playback equalizer total harmonic distortion T.H.D + Noise [%] 2.0 VCC = 8V 120µs – NS RL = 2.7kΩ 1kHz 1.0 0.5 0.2 0.1 –30 –25 –20 –15 –10 Output level [dBm] – 27 – –5 CXA1998AQ Package Outline Unit: mm 48PIN QFP (PLASTIC) 15.3 ± 0.4 + 0.1 0.15 – 0.05 + 0.4 12.0 – 0.1 36 25 0.15 24 13.5 37 48 + 0.2 0.1 – 0.1 13 12 0.8 + 0.15 0.3 – 0.1 ± 0.12 M 0.9 ± 0.2 1 + 0.35 2.2 – 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE QFP-48P-L04 LEAD TREATMENT SOLDER / PALLADIUM PLATING EIAJ CODE ∗QFP048-P-1212-B LEAD MATERIAL COPPER / 42 ALLOY PACKAGE WEIGHT 0.7g JEDEC CODE NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). – 28 –