CXL5513M/P CMOS-CCD 1H Delay Line for NTSC Description The CXL5513M/P are CMOS-CCD delay line ICs designed for processing video signals. This ICs provide a 1 H delay time for NTSC chroma signals including the external lowpass filter. Features • Single 5 V power supply • Low power consumption • Built-in peripheral circuit • Built-in tripling PLL circuit • Center bias mode CXL5513M 8 pin SOP (Plastic) CXL5513P 8 pin DIP (Plastic) Input Signal Amplitude VSIG 500 mVp-p (typ.), 572 mVP-P (max.) Absolute Maximum Ratings (Ta=25 °C) • Supply voltage VDD +6 V °C °C • Operating temperature Topr –10 to +60 • Storage temperature Tstg –55 to +150 • Allowable power dissipation PD CXL5513M 350 mW CXL5513P 480 mW Functions • 680-bit CCD register • Clock driver • Auto bias circuit • Input center bias circuit. • Sample and hold circuit • Tripling PLL circuit • Inverted output Structure CMOS-CCD Recommended Operating Range (Ta=25 ˚C) VDD 5 V±5 % Recommended Clock Conditions (Ta=25 ˚C) • Input clock amplitude VCLK 400 mVp-p (Typ.) • Clock frequency fCLK 3.579545 MHz • Input clock waveform Sine wave Block Diagram and Pin Configuration (Top View) VDD VCO OUT VCO IN CLK 8 7 6 5 PLL Auto-bias circuit Timing circuit Bias circuit CCD (680bit) Clock driver Output circuit (S/H 1 bit) Bias circuit A Bias circuit B 1 2 3 4 IN AB OUT VSS Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. —1— E93Y20-TE CXL5513M/P Pin Description Pin No. Symbol I/O Description 1 2 3 4 5 6 7 IN AB OUT VSS CLK VCO IN VCO OUT I O O – I I O Signal input Auto-bias DC output Signal output GND Clock input (fsc) VCO input VCO output (3fsc) 8 VDD – 5 V power supply Impedance >10 KΩ 40 to 500 Ω >10 KΩ Electrical Characteristics (Ta=25 °C, VDD=5 V, fCLK=3.579545 MHz, VCLK=400mVp-p, sine wave) See “Electrical Characteristics Test Circuit”. Item Supply current Symbol SW conditions Min. 1 2 Conditions Typ. Max. Unit Note IDD ——— a – 6 12 20 mA 1 Low frequency gain GL 200 kHz 500mVp-p Sine wave a b -2 0 2 dB 2 Frequency response fR b –2.5 –1.5 –0.5 dB 3 Differential gain DG 5-staircase wave (See Note 4.) d c 0 3 5 % 4 Differential phase DP 5-staircase wave (See Note 4.) d c 0 3 5 degree 4 S/H pulse coupling CP No signal input f a — — 350 mVp-p 5 SN 50 % white video signal (See Note 6.) e d 52 56 — dB 6 S/N ratio 200 kz ↔ 3.57 MHz b↔c 150mVp-p Sine wave —2— CXL5513M/P NOTE 1 This is the IC supply current value during clock and signal input. 2 GL is the output gain of OUT pin when a 500 mVp-p, 200 kHz sine wave is fed to IN pin. GL = 20 log OUT pin output voltage [mVp-p] [dB] 500 [mVp-p] 3 Indicates the dissipation at 3.58 MHz in relation to 200 kHz. From the output voltage at OUT pin when a 150 mVp-p, 200 kHz sine wave is fed to IN pin, and from the output voltage at OUT pin when a 150 mVp-p, 3.58 MHz sine wave is fed to the same, calculation is made according to the following formula. fR = 20 log OUT pin output voltage (3.58 MHz) [mVp-p] [dB] OUT pin output voltage (200 kHz) [mVp-p] 4 In Fig. below, the differential gain (DG) and the differential phase (DP), are tested with a vector scope when the 5-staircase wave is fed. 143mV 357mV 500mV 143mV 1H 63.56µS 5 Leakage of internal clock components and related high frequency component to the output signal, during no signal input, is tested. Test value (mVp-p) —3— CXL5513M/P 6 S/N ratio during a 50 % white video signal input shown in Fig. below is tested at the video noise meter, in BPF 100 kHz to 4 MHz, Sub Carrier Trap mode. 178mV 321mV 143mV 1H 63.56µS CLOCK fSC (3.579545MHz) Sine wave 400mVp-p (Typ.) —4— —5— 50 % white video signal 5-staircase wave 3.57MHz 150mVp-p Sine wave 200kHz 150mVp-p Sine wave 200kHz 500mVp-p Sine wave f e d c SW1 b a 1µ Electrical Characteristics Test Circuit A 5V 6 0.1µ 2 1 0.1µ 3 OUT 4 VSS CLK 5 0.1µ 0 –3 –50 –50 10.7M [Hz] d c SW2 b a BPF Note 2) LPF Note 1) 50 200 ×3 ×3 4.1M 10.7M Frequency [Hz] Note 2) BPF frequency response [dB] 2.2k +15V 0 –3 5.8M Frequency Note 1) LPF frequency response [dB] AB CXL5513M/P VCO OUT VCO IN 7 IN VDD 8 2200p 6.8µ fsc (3.579545MHz) 400mVp-p Sine wave Noise meter Vector scope Spectrum analyzer Oscilloscop e CXL5513M/P Input —6— 7 8 1.8k 2 0.1µ 3fSC OUT 5V AB 1 3 OUT CXL5513M/P 5 1µ 4 VSS CLK 0.1µ fsc (3.579545MHz) 400mVp-p Sine wave 1k 470 Transistor used PNP: 2SA1175 56k 33k LPF 2.2k Transistor used NPN: 2SC403 Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party and other right due to same. 2.2k 2SC403 6 0.1µ VCO OUT VCO IN 7 6.8µ IN VDD When VCO OUT (7 Pin) in use 0.1µ 2200p 5V Application Circuit Output 5V CXL5513M/P CXL5513M/P Supply current vs. Ambient temperature Low frequency gain vs. Ambient temperature 20 1 Low frequency gain (dB) Supply current (mA) 18 16 14 0 –1 –2 12 10 –20 0 20 40 60 –3 –20 80 0 20 40 60 80 Ambient temperature (°C) Ambient temperature (°C) Frequency response vs. Ambient temperature Supply current vs. Supply voltage 0 20 Supply current (mA) Frequency response (dB) 18 –1 –2 16 14 12 –3 –20 0 20 40 60 10 4.7 5 80 Ambient temperature (°C) —7— 5 Supply voltage (V) 5.25 CXL5513M/P Low frequency gain vs. Supply voltage Frequency response vs. Supply voltage 0 Frequency response (dB) 0 –1 –2 –3 –1 –2 –3 4.7 5 5 5.25 Supply voltage (V) 4.7 5 5 5.25 Supply voltage (V) Frequency response 0 –2 Gain (dB) Low frequency gain (dB) 1 –4 –6 –8 –10 10k 100k 1M Frequency (Hz) —8— 10 M CXL5513M/P Package Outline Unit : mm CXL5513M 8PIN SOP (PLASTIC) + 0.4 1.25 – 0.15 + 0.4 5.0 – 0.1 0.10 8 5 + 0.3 4.4 – 0.1 6.4 ± 0.4 A 4 1 + 0.1 0.15 – 0.05 1.27 + 0.1 0.4 – 0.05 0.5 ± 0.2 + 0.15 0.1 – 0.1 ± 0.12 M 0° to 10° DETAILA PACKAGE STRUCTURE SONY CODE SOP-8P-L03 EIAJ CODE ∗SOP008-P-0225-A JEDEC CODE CXL5513P MOLDING COMPOUND EPOXY / PHENOL RESIN LEAD TREATMENT SOLDER PLATING LEAD MATERIAL 42 ALLOY PACKAGE WEIGHT 0.1g + 0.3 6.4 – 0.1 + 0.4 9.4 – 0.1 5 7.62 8 + 0.1 0.05 0.25 – 8PIN DIP (PLASTIC) 300mil 0° to 15° 4 1 + 0.4 3.7 – 0.1 3.0 MIN 0.5 MIN 2.54 0.5 ± 0.1 1.2 ± 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE DIP-8P-01 LEAD TREATMENT SOLDER PLATING EIAJ CODE ∗DIP008-P-0300-A LEAD MATERIAL COPPER ALLOY PACKAGE WEIGHT 0.5g JEDEC CODE —9—